1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 25 /* ------------------------- System Includes -------------------------------- */ 26 #include "gpu/gpu.h" 27 #include "gpu/bif/kernel_bif.h" 28 #include "platform/chipset/chipset.h" 29 #include "nvdevid.h" 30 31 #include "published/maxwell/gm107/dev_nv_xve.h" 32 33 // Defines for C73 chipset registers 34 #ifndef NV_XVR_VEND_XP1 35 #define NV_XVR_VEND_XP1 0x00000F04 /* RW-4R */ 36 37 #define NV_XVR_VEND_XP1_IGNORE_L0S 23:23 /* RWIVF */ 38 #define NV_XVR_VEND_XP1_IGNORE_L0S_INIT 0x00000000 /* RWI-V */ 39 #define NV_XVR_VEND_XP1_IGNORE_L0S__PROD 0x00000000 /* RW--V */ 40 #define NV_XVR_VEND_XP1_IGNORE_L0S_EN 0x00000001 /* RW--V */ 41 #endif 42 43 44 /* ------------------------ Public Functions -------------------------------- */ 45 46 /*! 47 * @brief Get PCIe config test registers 48 * 49 * @param[in] pGpu GPU object pointer 50 * @param[in] pKernelBif BIF object pointer 51 */ 52 void 53 kbifGetPcieConfigAccessTestRegisters_GM107 54 ( 55 OBJGPU *pGpu, 56 KernelBif *pKernelBif, 57 NvU32 *pciStart, 58 NvU32 *pcieStart 59 ) 60 { 61 *pciStart = NV_XVE_ID; 62 *pcieStart = NV_XVE_VCCAP_HDR; 63 } 64 65 /*! 66 * @brief Verify PCIe config test registers 67 * 68 * @param[in] pGpu GPU object pointer 69 * @param[in] pKernelBif BIF object pointer 70 * 71 * @return NV_OK 72 */ 73 NV_STATUS 74 kbifVerifyPcieConfigAccessTestRegisters_GM107 75 ( 76 OBJGPU *pGpu, 77 KernelBif *pKernelBif, 78 NvU32 nvXveId, 79 NvU32 nvXveVccapHdr 80 ) 81 { 82 NvU32 data; 83 84 GPU_BUS_CFG_RD32(pGpu, NV_XVE_ID, &data); 85 86 if (FLD_TEST_DRF(_XVE, _ID, _VENDOR, _NVIDIA, data)) 87 { 88 if (data != nvXveId) 89 return NV_ERR_NOT_SUPPORTED; 90 91 GPU_BUS_CFG_RD32(pGpu, NV_XVE_VCCAP_HDR, &data); 92 93 if (FLD_TEST_DRF(_XVE, _VCCAP_HDR, _ID, _VC, data) && 94 FLD_TEST_DRF(_XVE, _VCCAP_HDR, _VER, _1, data)) 95 { 96 if (data != nvXveVccapHdr) 97 return NV_ERR_NOT_SUPPORTED; 98 return NV_OK; 99 } 100 } 101 return NV_ERR_NOT_SUPPORTED; 102 } 103 104 /*! 105 * @brief Re-arm MSI 106 * 107 * @param[in] pGpu GPU object pointer 108 * @param[in] pKernelBif Kernel BIF object pointer 109 */ 110 void 111 kbifRearmMSI_GM107 112 ( 113 OBJGPU *pGpu, 114 KernelBif *pKernelBif 115 ) 116 { 117 NV_STATUS status = gpuSanityCheckRegisterAccess(pGpu, 0, NULL); 118 119 if (status != NV_OK) 120 { 121 return; 122 } 123 124 // The 32 byte value doesn't matter, HW only looks at the offset. 125 osGpuWriteReg032(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_CYA_2, 0); 126 } 127 128 /*! 129 * @brief Check if MSI is enabled in HW 130 * 131 * @param[in] pGpu GPU object pointer 132 * @param[in] pKernelBif BIF object pointer 133 * 134 * @return True if MSI enabled else False 135 */ 136 NvBool 137 kbifIsMSIEnabledInHW_GM107 138 ( 139 OBJGPU *pGpu, 140 KernelBif *pKernelBif 141 ) 142 { 143 NvU32 data32; 144 if (NV_OK != GPU_BUS_CFG_RD32(pGpu, NV_XVE_MSI_CTRL, &data32)) 145 { 146 NV_PRINTF(LEVEL_ERROR, "unable to read NV_XVE_MSI_CTRL\n"); 147 } 148 149 return FLD_TEST_DRF(_XVE, _MSI_CTRL, _MSI, _ENABLE, data32); 150 } 151 152 /*! 153 * @brief Check if access to PCI config space is enabled 154 * 155 * @param[in] pGpu GPU object pointer 156 * @param[in] pKernelBif Kernel BIF object pointer 157 * 158 * @return True if access to PCI config space is enabled 159 */ 160 NvBool 161 kbifIsPciIoAccessEnabled_GM107 162 ( 163 OBJGPU *pGpu, 164 KernelBif *pKernelBif 165 ) 166 { 167 NvU32 data = 0; 168 169 if (NV_OK == GPU_BUS_CFG_RD32(pGpu, NV_XVE_DEV_CTRL, &data)) 170 { 171 if (FLD_TEST_DRF(_XVE, _DEV_CTRL, _CMD_IO_SPACE, _ENABLED, data)) 172 { 173 return NV_TRUE; 174 } 175 } 176 177 return NV_FALSE; 178 } 179 180 /*! 181 * @brief Check if device is a 3D controller 182 * 183 * @param[in] pGpu GPU object pointer 184 * @param[in] pKernelBif Kernel BIF object pointer 185 * 186 * @return True if device is a 3D controller 187 */ 188 NvBool 189 kbifIs3dController_GM107 190 ( 191 OBJGPU *pGpu, 192 KernelBif *pKernelBif 193 ) 194 { 195 NvU32 data = 0; 196 197 if (NV_OK == GPU_BUS_CFG_RD32(pGpu, NV_XVE_REV_ID, &data)) 198 { 199 if (FLD_TEST_DRF(_XVE, _REV_ID, _CLASS_CODE, _3D, data)) 200 { 201 return NV_TRUE; 202 } 203 } 204 205 return NV_FALSE; 206 } 207 208 /*! 209 * @brief Enable/disable no snoop for GPU 210 * 211 * @param[in] pGpu GPU object pointer 212 * @param[in] pKernelBif Kernel BIF object pointer 213 * @param[in] bEnable True if No snoop needs to be enabled 214 * 215 * @return NV_OK If no snoop modified as requested 216 */ 217 NV_STATUS 218 kbifEnableNoSnoop_GM107 219 ( 220 OBJGPU *pGpu, 221 KernelBif *pKernelBif, 222 NvBool bEnable 223 ) 224 { 225 NvU8 fieldVal; 226 NvU32 regVal; 227 228 regVal = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_DEVICE_CONTROL_STATUS); 229 230 fieldVal = bEnable ? 1 : 0; 231 regVal = FLD_SET_DRF_NUM(_XVE, _DEVICE_CONTROL_STATUS, 232 _ENABLE_NO_SNOOP, fieldVal, regVal); 233 234 GPU_REG_WR32(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_DEVICE_CONTROL_STATUS, regVal); 235 236 return NV_OK; 237 } 238 239 /*! 240 * @brief Enables Relaxed Ordering PCI-E Capability in the PCI Config Space 241 * 242 * @param[in] pGpu GPU object pointer 243 * @param[in] pKernelBif Kernel BIF object pointer 244 */ 245 void 246 kbifPcieConfigEnableRelaxedOrdering_GM107 247 ( 248 OBJGPU *pGpu, 249 KernelBif *pKernelBif 250 ) 251 { 252 NvU32 xveDevCtrlStatus; 253 254 if(NV_ERR_GENERIC == GPU_BUS_CFG_RD32(pGpu, NV_XVE_DEVICE_CONTROL_STATUS, &xveDevCtrlStatus)) 255 { 256 NV_PRINTF(LEVEL_ERROR, 257 "Unable to read NV_XVE_DEVICE_CONTROL_STATUS!\n"); 258 DBG_BREAKPOINT(); 259 } 260 else 261 { 262 GPU_BUS_CFG_FLD_WR_DRF_DEF(pGpu, xveDevCtrlStatus, _XVE, _DEVICE_CONTROL_STATUS, 263 _ENABLE_RELAXED_ORDERING, _INIT); 264 } 265 } 266 267 /*! 268 * @brief Disables Relaxed Ordering PCI-E Capability in the PCI Config Space 269 * 270 * @param[in] pGpu GPU object pointer 271 * @param[in] pKernelBif Kernel BIF object pointer 272 */ 273 void 274 kbifPcieConfigDisableRelaxedOrdering_GM107 275 ( 276 OBJGPU *pGpu, 277 KernelBif *pKernelBif 278 ) 279 { 280 NvU32 xveDevCtrlStatus; 281 282 if(NV_ERR_GENERIC == GPU_BUS_CFG_RD32(pGpu, NV_XVE_DEVICE_CONTROL_STATUS, &xveDevCtrlStatus)) 283 { 284 NV_PRINTF(LEVEL_ERROR, 285 "Unable to read NV_XVE_DEVICE_CONTROL_STATUS!\n"); 286 DBG_BREAKPOINT(); 287 } 288 else 289 { 290 xveDevCtrlStatus = FLD_SET_DRF_NUM(_XVE, _DEVICE_CONTROL_STATUS, 291 _ENABLE_RELAXED_ORDERING, 0, xveDevCtrlStatus); 292 GPU_BUS_CFG_WR32(pGpu, NV_XVE_DEVICE_CONTROL_STATUS, xveDevCtrlStatus); 293 } 294 } 295 296 /*! 297 * @brief Get XVE status bits 298 * 299 * @param[in] pGpu GPU object pointer 300 * @param[in] pKernelBif BIF object pointer 301 * @param[out] pBits PCIe error status values 302 * @param[out] pStatus Full XVE status 303 * 304 * @return NV_OK 305 */ 306 NV_STATUS 307 kbifGetXveStatusBits_GM107 308 ( 309 OBJGPU *pGpu, 310 KernelBif *pKernelBif, 311 NvU32 *pBits, 312 NvU32 *pStatus 313 ) 314 { 315 // control/status reg 316 NvU32 xveDevCtrlStatus; 317 318 if (NV_OK != GPU_BUS_CFG_RD32(pGpu, NV_XVE_DEVICE_CONTROL_STATUS, &xveDevCtrlStatus)) 319 { 320 NV_PRINTF(LEVEL_ERROR, 321 "Unable to read NV_XVE_DEVICE_CONTROL_STATUS!\n"); 322 } 323 if ( pBits == NULL ) 324 return NV_ERR_GENERIC; 325 326 *pBits = 0; 327 328 // The register read above returns garbage on fmodel, so just return. 329 if (IS_FMODEL(pGpu)) 330 { 331 if (pStatus) 332 { 333 *pStatus = 0; 334 } 335 return NV_OK; 336 } 337 338 if (pStatus) 339 *pStatus = xveDevCtrlStatus; 340 341 if (xveDevCtrlStatus & DRF_NUM(_XVE, _DEVICE_CONTROL_STATUS, _CORR_ERROR_DETECTED, 1)) 342 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR; 343 if (xveDevCtrlStatus & DRF_NUM(_XVE, _DEVICE_CONTROL_STATUS, _NON_FATAL_ERROR_DETECTED, 1)) 344 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR; 345 if (xveDevCtrlStatus & DRF_NUM(_XVE, _DEVICE_CONTROL_STATUS, _FATAL_ERROR_DETECTED, 1)) 346 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR; 347 if (xveDevCtrlStatus & DRF_NUM(_XVE, _DEVICE_CONTROL_STATUS, _UNSUPP_REQUEST_DETECTED, 1)) 348 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST; 349 350 if (pKernelBif->EnteredRecoverySinceErrorsLastChecked) 351 { 352 pKernelBif->EnteredRecoverySinceErrorsLastChecked = NV_FALSE; 353 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY; 354 } 355 356 return NV_OK; 357 } 358 359 /*! 360 * @brief Clear the XVE status bits 361 * 362 * @param[in] pGpu GPU object pointer 363 * @param[in] pKernelBif BIF object pointer 364 * @param[out] pStatus Full XVE status 365 * 366 * @return NV_OK 367 */ 368 NV_STATUS 369 kbifClearXveStatus_GM107 370 ( 371 OBJGPU *pGpu, 372 KernelBif *pKernelBif, 373 NvU32 *pStatus 374 ) 375 { 376 NvU32 xveDevCtrlStatus; 377 378 if (pStatus) 379 { 380 xveDevCtrlStatus = *pStatus; 381 if (xveDevCtrlStatus == 0) 382 { 383 return NV_OK; 384 } 385 } 386 else 387 { 388 if (NV_OK != GPU_BUS_CFG_RD32(pGpu, NV_XVE_DEVICE_CONTROL_STATUS, &xveDevCtrlStatus)) 389 { 390 NV_PRINTF(LEVEL_ERROR, 391 "Unable to read NV_XVE_DEVICE_CONTROL_STATUS!\n"); 392 } 393 } 394 395 GPU_BUS_CFG_WR32(pGpu, NV_XVE_DEVICE_CONTROL_STATUS, xveDevCtrlStatus); 396 397 return NV_OK; 398 } 399 400 /*! 401 * @brief Get XVE AER bits 402 * 403 * @param[in] pGpu GPU object pointer 404 * @param[in] pKernelBif BIF object pointer 405 * @param[out] pBits PCIe AER error status values 406 * 407 * @return NV_OK 408 */ 409 NV_STATUS 410 kbifGetXveAerBits_GM107 411 ( 412 OBJGPU *pGpu, 413 KernelBif *pKernelBif, 414 NvU32 *pBits 415 ) 416 { 417 NvU32 xveAerUncorr; 418 NvU32 xveAerCorr; 419 420 if (pBits == NULL) 421 { 422 return NV_ERR_GENERIC; 423 } 424 425 *pBits = 0; 426 427 if (NV_OK != GPU_BUS_CFG_RD32(pGpu, NV_XVE_AER_UNCORR_ERR, &xveAerUncorr)) 428 { 429 NV_PRINTF(LEVEL_ERROR, "Unable to read NV_XVE_AER_UNCORR_ERR\n"); 430 return NV_ERR_GENERIC; 431 } 432 if (NV_OK != GPU_BUS_CFG_RD32(pGpu, NV_XVE_AER_CORR_ERR, &xveAerCorr)) 433 { 434 NV_PRINTF(LEVEL_ERROR, "Unable to read NV_XVE_AER_CORR_ERR\n"); 435 return NV_ERR_GENERIC; 436 } 437 438 // The register read above returns garbage on fmodel, so just return. 439 if (IS_FMODEL(pGpu)) 440 { 441 return NV_OK; 442 } 443 444 if (FLD_TEST_DRF(_XVE, _AER_UNCORR_ERR, _DLINK_PROTO_ERR, _ACTIVE, xveAerUncorr)) 445 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR; 446 if (FLD_TEST_DRF(_XVE, _AER_UNCORR_ERR, _POISONED_TLP, _ACTIVE, xveAerUncorr)) 447 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP; 448 if (FLD_TEST_DRF(_XVE, _AER_UNCORR_ERR, _CPL_TIMEOUT, _ACTIVE, xveAerUncorr)) 449 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT; 450 if (FLD_TEST_DRF(_XVE, _AER_UNCORR_ERR, _UNEXP_CPL, _ACTIVE, xveAerUncorr)) 451 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL; 452 if (FLD_TEST_DRF(_XVE, _AER_UNCORR_ERR, _MALFORMED_TLP, _ACTIVE, xveAerUncorr)) 453 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP; 454 if (FLD_TEST_DRF(_XVE, _AER_UNCORR_ERR, _UNSUPPORTED_REQ, _ACTIVE, xveAerUncorr)) 455 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ; 456 457 if (FLD_TEST_DRF(_XVE, _AER_CORR_ERR, _RCV_ERR, _ACTIVE, xveAerCorr)) 458 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR; 459 if (FLD_TEST_DRF(_XVE, _AER_CORR_ERR, _BAD_TLP, _ACTIVE, xveAerCorr)) 460 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP; 461 if (FLD_TEST_DRF(_XVE, _AER_CORR_ERR, _BAD_DLLP , _ACTIVE, xveAerCorr)) 462 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP; 463 if (FLD_TEST_DRF(_XVE, _AER_CORR_ERR, _RPLY_ROLLOVER, _ACTIVE, xveAerCorr)) 464 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER; 465 if (FLD_TEST_DRF(_XVE, _AER_CORR_ERR, _RPLY_TIMEOUT, _ACTIVE, xveAerCorr)) 466 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT; 467 if (FLD_TEST_DRF(_XVE, _AER_CORR_ERR, _ADVISORY_NONFATAL, _ACTIVE, xveAerCorr)) 468 *pBits |= NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL; 469 470 return NV_OK; 471 } 472 473 /*! 474 * @brief Clear the XVE AER bits 475 * 476 * @param[in] pGpu GPU object pointer 477 * @param[in] pKernelBif BIF object pointer 478 * @param[in] bits PCIe AER error status values 479 * 480 * @return NV_OK 481 */ 482 NV_STATUS 483 kbifClearXveAer_GM107 484 ( 485 OBJGPU *pGpu, 486 KernelBif *pKernelBif, 487 NvU32 bits 488 ) 489 { 490 NvU32 xveAerUncorr = 0; 491 NvU32 xveAerCorr = 0; 492 493 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR) 494 xveAerUncorr = FLD_SET_DRF(_XVE, _AER_UNCORR_ERR, _DLINK_PROTO_ERR, _CLEAR, xveAerUncorr); 495 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP) 496 xveAerUncorr = FLD_SET_DRF(_XVE, _AER_UNCORR_ERR, _POISONED_TLP, _CLEAR, xveAerUncorr); 497 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT) 498 xveAerUncorr = FLD_SET_DRF(_XVE, _AER_UNCORR_ERR, _CPL_TIMEOUT, _CLEAR, xveAerUncorr); 499 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL) 500 xveAerUncorr = FLD_SET_DRF(_XVE, _AER_UNCORR_ERR, _UNEXP_CPL, _CLEAR, xveAerUncorr); 501 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP) 502 xveAerUncorr = FLD_SET_DRF(_XVE, _AER_UNCORR_ERR, _MALFORMED_TLP, _CLEAR, xveAerUncorr); 503 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ) 504 xveAerUncorr = FLD_SET_DRF(_XVE, _AER_UNCORR_ERR, _UNSUPPORTED_REQ, _CLEAR, xveAerUncorr); 505 506 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR) 507 xveAerCorr = FLD_SET_DRF(_XVE, _AER_CORR_ERR, _RCV_ERR, _CLEAR, xveAerCorr); 508 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP) 509 xveAerCorr = FLD_SET_DRF(_XVE, _AER_CORR_ERR, _BAD_TLP, _CLEAR, xveAerCorr); 510 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP) 511 xveAerCorr = FLD_SET_DRF(_XVE, _AER_CORR_ERR, _BAD_DLLP, _CLEAR, xveAerCorr); 512 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER) 513 xveAerCorr = FLD_SET_DRF(_XVE, _AER_CORR_ERR, _RPLY_ROLLOVER, _CLEAR, xveAerCorr); 514 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT) 515 xveAerCorr = FLD_SET_DRF(_XVE, _AER_CORR_ERR, _RPLY_TIMEOUT, _CLEAR, xveAerCorr); 516 if (bits & NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL) 517 xveAerCorr = FLD_SET_DRF(_XVE, _AER_CORR_ERR, _ADVISORY_NONFATAL, _CLEAR, xveAerCorr); 518 519 if (xveAerUncorr != 0) 520 { 521 GPU_BUS_CFG_WR32(pGpu, NV_XVE_AER_UNCORR_ERR, xveAerUncorr); 522 } 523 if (xveAerCorr != 0) 524 { 525 GPU_BUS_CFG_WR32(pGpu, NV_XVE_AER_CORR_ERR, xveAerCorr); 526 } 527 528 return NV_OK; 529 } 530 531 /*! 532 * @brief Returns the BAR0 offset and size of the PCI config space mirror 533 * 534 * @param[in] pGpu GPU object pointer 535 * @param[in] pKernelBif Kernel BIF object pointer 536 * @param[out] pBase BAR0 offset of the PCI config space mirror 537 * @param[out] pSize Size in bytes of the PCI config space mirror 538 * 539 * @returns NV_OK 540 */ 541 NV_STATUS 542 kbifGetPciConfigSpacePriMirror_GM107 543 ( 544 OBJGPU *pGpu, 545 KernelBif *pKernelBif, 546 NvU32 *pBase, 547 NvU32 *pSize 548 ) 549 { 550 *pBase = DEVICE_BASE(NV_PCFG); 551 *pSize = DEVICE_EXTENT(NV_PCFG) - DEVICE_BASE(NV_PCFG) + 1; 552 return NV_OK; 553 } 554 555 /*! 556 * @brief C73 chipset WAR 557 * 558 * @param[in] pGpu GPU object pointer 559 * @param[in] pKernelBif Kernel BIF object pointer 560 */ 561 void 562 kbifExecC73War_GM107 563 ( 564 OBJGPU *pGpu, 565 KernelBif *pKernelBif 566 ) 567 { 568 OBJSYS *pSys = SYS_GET_INSTANCE(); 569 OBJOS *pOS = SYS_GET_OS(pSys); 570 OBJCL *pCl = SYS_GET_CL(pSys); 571 NvU32 val; 572 573 if (CS_NVIDIA_C73 == pCl->Chipset) 574 { 575 // 576 // Turn off L0s on the chipset which are required by the suspend/resume 577 // cycles in Vista. See bug 400044 for more details. 578 // 579 580 // vAddr is a mapped cpu virtual addr into the root ports config space. 581 if (!pOS->getProperty(pOS, PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS) && 582 (pGpu->gpuClData.rootPort.vAddr != 0)) 583 { 584 val = MEM_RD32((NvU8*)pGpu->gpuClData.rootPort.vAddr+NV_XVR_VEND_XP1); 585 val = FLD_SET_DRF(_XVR, _VEND_XP1, _IGNORE_L0S, _EN, val); 586 MEM_WR32((NvU8*)pGpu->gpuClData.rootPort.vAddr+NV_XVR_VEND_XP1, val); 587 } 588 else if (pOS->getProperty(pOS, PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS) && 589 pGpu->gpuClData.rootPort.addr.valid) 590 { 591 val = osPciReadDword(pGpu->gpuClData.rootPort.addr.handle, NV_XVR_VEND_XP1); 592 val = FLD_SET_DRF(_XVR, _VEND_XP1, _IGNORE_L0S, _EN, val); 593 osPciWriteDword(pGpu->gpuClData.rootPort.addr.handle, NV_XVR_VEND_XP1, val); 594 } 595 else 596 { 597 NV_PRINTF(LEVEL_ERROR, 598 "Cannot turn off L0s on C73 chipset, suspend/resume may fail (Bug 400044).\n"); 599 DBG_BREAKPOINT(); 600 } 601 } 602 } 603 604 NV_STATUS 605 kbifGetBusOptionsAddr_GM107 606 ( 607 OBJGPU *pGpu, 608 KernelBif *pKernelBif, 609 BUS_OPTIONS options, 610 NvU32 *addrReg 611 ) 612 { 613 NV_STATUS status = NV_OK; 614 615 switch (options) 616 { 617 case BUS_OPTIONS_DEV_CONTROL_STATUS: 618 *addrReg = NV_XVE_DEVICE_CONTROL_STATUS; 619 break; 620 case BUS_OPTIONS_LINK_CONTROL_STATUS: 621 *addrReg = NV_XVE_LINK_CONTROL_STATUS; 622 break; 623 case BUS_OPTIONS_LINK_CAPABILITIES: 624 *addrReg = NV_XVE_LINK_CAPABILITIES; 625 break; 626 default: 627 NV_PRINTF(LEVEL_ERROR, "Invalid register type passed 0x%x\n", 628 options); 629 status = NV_ERR_GENERIC; 630 break; 631 } 632 return status; 633 } 634 635 NV_STATUS 636 kbifDisableSysmemAccess_GM107 637 ( 638 OBJGPU *pGpu, 639 KernelBif *pKernelBif, 640 NvBool bDisable 641 ) 642 { 643 NV_STATUS status = NV_OK; 644 RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); 645 NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS params = {0}; 646 647 // Only support on Windows 648 NV_ASSERT_OR_RETURN(RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM, NV_ERR_NOT_SUPPORTED); 649 650 params.bDisable = bDisable; 651 status = pRmApi->Control(pRmApi, 652 pGpu->hInternalClient, 653 pGpu->hInternalSubdevice, 654 NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS, 655 ¶ms, 656 sizeof(NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS)); 657 658 // Only set the PDB in kernel if it was set in physical successfully 659 if (status == NV_OK) 660 { 661 pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED, bDisable); 662 } 663 664 return status; 665 } 666