1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "core/locks.h" 25 #include "vgpu/rpc.h" 26 #include "gpu/gpu.h" 27 #include "gpu_mgr/gpu_mgr.h" 28 #include "kernel/gpu/subdevice/subdevice.h" 29 #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" 30 #include "kernel/gpu/fifo/kernel_fifo.h" 31 #include "kernel/gpu/nvlink/kernel_nvlink.h" 32 #include "gpu/bus/kern_bus.h" 33 #include "gpu/ce/kernel_ce.h" 34 #include "gpu/ce/kernel_ce_private.h" 35 36 NvBool ceIsCeGrce(OBJGPU *pGpu, RM_ENGINE_TYPE rmCeEngineType) 37 { 38 NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS partnerParams = {0}; 39 KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); 40 41 if (IsAMODEL(pGpu) || IsT234DorBetter(pGpu)) 42 return NV_FALSE; 43 44 NV_ASSERT_OR_RETURN(RM_ENGINE_TYPE_IS_COPY(rmCeEngineType), NV_FALSE); 45 46 NvU32 i; 47 NV_STATUS status = NV_OK; 48 49 partnerParams.engineType = gpuGetNv2080EngineType(rmCeEngineType); 50 partnerParams.numPartners = 0; 51 52 // See if the hal wants to handle this 53 status = kfifoGetEnginePartnerList_HAL(pGpu, pKernelFifo, &partnerParams); 54 if (status != NV_OK) 55 { 56 // For channels that the hal didnt handle, we should just return 57 // all of the supported engines except for the target engine. 58 // 59 // Update the engine Database 60 status = gpuUpdateEngineTable(pGpu); 61 if (status != NV_OK) 62 { 63 NV_PRINTF(LEVEL_ERROR, 64 "Could not update the engine db. This is fatal\n"); 65 DBG_BREAKPOINT(); 66 return NV_FALSE; 67 } 68 69 // Make sure it all will fit 70 if (pGpu->engineDB.size > NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS) 71 { 72 NV_PRINTF(LEVEL_ERROR, 73 "PartnerList space too small. This is fatal\n"); 74 DBG_BREAKPOINT(); 75 return NV_FALSE; 76 } 77 78 // Copy over all of the engines except the target 79 for (i = 0; i < pGpu->engineDB.size; i++) 80 { 81 // Skip the engine handed in 82 if (pGpu->engineDB.pType[i] != rmCeEngineType ) 83 { 84 partnerParams.partnerList[partnerParams.numPartners++] = 85 gpuGetNv2080EngineType(pGpu->engineDB.pType[i]); 86 } 87 } 88 } 89 90 // check if gr is in the partnerList 91 for (i = 0; i < partnerParams.numPartners; i++) 92 { 93 if (partnerParams.partnerList[i] == NV2080_ENGINE_TYPE_GRAPHICS) 94 { 95 return NV_TRUE; 96 } 97 } 98 99 return NV_FALSE; 100 } 101 102 NvU32 ceCountGrCe(OBJGPU *pGpu) 103 { 104 KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); 105 NvU32 engIdx; 106 NvU32 grCeCount; 107 108 if (pKernelBus == NULL || IsAMODEL(pGpu)) 109 return 0; 110 111 grCeCount = 0; 112 113 // 114 // bug 2188230: Until FIFO reports max instance id for a given engine type, 115 // start by iterating over all CE indices supported by POBJGPU 116 // 117 for (engIdx = 0; engIdx < GPU_MAX_CES; ++engIdx) 118 { 119 if (kbusCheckEngine_HAL(pGpu, pKernelBus, ENG_CE(engIdx)) && 120 ceIsCeGrce(pGpu, RM_ENGINE_TYPE_COPY(engIdx))) 121 { 122 grCeCount++; 123 } 124 } 125 126 return grCeCount; 127 } 128 129 // 130 // Lock Requirements: 131 // Assert that API lock held on entry 132 // 133 NV_STATUS 134 subdeviceCtrlCmdCeGetCapsV2_IMPL 135 ( 136 Subdevice *pSubdevice, 137 NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *pCeCapsParams 138 ) 139 { 140 OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); 141 NvU32 ceNumber; 142 RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(pCeCapsParams->ceEngineType); 143 144 LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); 145 146 NV_PRINTF(LEVEL_INFO, "NV2080_CTRL_CE_GET_CAPS_V2 ceEngineType = %d\n", pCeCapsParams->ceEngineType); 147 148 if (!RM_ENGINE_TYPE_IS_COPY(rmEngineType)) 149 { 150 return NV_ERR_NOT_SUPPORTED; 151 } 152 153 NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, 154 GPU_RES_GET_DEVICE(pSubdevice), 155 rmEngineType, &ceNumber)); 156 157 { 158 KernelCE *pKCe = GPU_GET_KCE(pGpu, ceNumber); 159 160 // Return an unsupported error for not present or stubbed CEs as they are 161 // not supposed to be user visible and cannot be allocated anyway. 162 if (pKCe == NULL) 163 { 164 NV_PRINTF(LEVEL_INFO, "Skipping stubbed CE %d\n", ceNumber); 165 return NV_ERR_NOT_SUPPORTED; 166 } 167 168 // now fill in caps for this CE 169 return kceGetDeviceCaps(pGpu, pKCe, rmEngineType, NvP64_VALUE(pCeCapsParams->capsTbl)); 170 } 171 } 172 173 NV_STATUS 174 subdeviceCtrlCmdCeGetAllCaps_IMPL 175 ( 176 Subdevice *pSubdevice, 177 NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams 178 ) 179 { 180 RM_API *pRmApi; 181 OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); 182 Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); 183 184 ct_assert(NV2080_CTRL_MAX_CES <= sizeof(pCeCapsParams->capsTbl) / sizeof(pCeCapsParams->capsTbl[0])); 185 186 if (!RMCFG_FEATURE_PLATFORM_GSP) 187 { 188 KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); 189 190 // 191 // Since some CE capabilities depend on the nvlink topology, 192 // trigger topology detection before updating the CE caps 193 // 194 if ((pKernelNvlink != NULL) && !knvlinkIsForcedConfig(pGpu, pKernelNvlink) && 195 kmigmgrIsMIGNvlinkP2PSupported(pGpu, GPU_GET_KERNEL_MIG_MANAGER(pGpu))) 196 { 197 knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); 198 } 199 } 200 201 portMemSet(pCeCapsParams, 0, sizeof(*pCeCapsParams)); 202 203 pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); 204 NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, 205 pGpu->hInternalClient, 206 pGpu->hInternalSubdevice, 207 NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS, 208 pCeCapsParams, 209 sizeof(*pCeCapsParams))); 210 211 { 212 KernelCE *pKCe; 213 KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); 214 215 KCE_ITER_DEVICE_BEGIN(pGpu, pKCe, pDevice) 216 if (pKCe->bStubbed) 217 continue; 218 219 pCeCapsParams->present |= BIT64(kceInst); 220 221 NvU8 *pKCeCaps = pCeCapsParams->capsTbl[kceInst]; 222 223 if (pKernelNvlink != NULL) 224 kceGetNvlinkCaps(pGpu, pKCe, pKCeCaps); 225 KCE_ITER_END 226 } 227 228 return NV_OK; 229 } 230