1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "core/core.h"
25 #include "kernel/gpu/intr/intr.h"
26 #include "gpu/gpu.h"
27
28 #include "published/ampere/ga102/dev_vm.h"
29
30 //
31 // Ampere HAL routines that access NV_VIRTUAL_FUNCTION_* registers.
32 // Every function in this file needs to have a GSP equivalent
33 // accessing NV_GSP_INTR_* registers.
34 //
35
36 NvU32
intrReadRegTopEnSet_CPU_GA102(OBJGPU * pGpu,Intr * pIntr,NvU32 regIndex,THREAD_STATE_NODE * pThreadState)37 intrReadRegTopEnSet_CPU_GA102
38 (
39 OBJGPU *pGpu,
40 Intr *pIntr,
41 NvU32 regIndex,
42 THREAD_STATE_NODE *pThreadState
43 )
44 {
45 // SW assumptions that there are two top-levels.
46 ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 <= 2);
47 if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1)
48 {
49 return 0x0;
50 }
51 return GPU_VREG_RD32_EX(pGpu,
52 NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(regIndex),
53 pThreadState);
54 }
55
56 void
intrWriteRegTopEnSet_CPU_GA102(OBJGPU * pGpu,Intr * pIntr,NvU32 regIndex,NvU32 value,THREAD_STATE_NODE * pThreadState)57 intrWriteRegTopEnSet_CPU_GA102
58 (
59 OBJGPU *pGpu,
60 Intr *pIntr,
61 NvU32 regIndex,
62 NvU32 value,
63 THREAD_STATE_NODE *pThreadState
64 )
65 {
66 // SW assumptions that there are two top-levels.
67 ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 <= 2);
68 if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1)
69 {
70 return;
71 }
72 GPU_VREG_WR32_EX(pGpu,
73 NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(regIndex),
74 value,
75 pThreadState);
76 }
77
78 void
intrWriteRegTopEnClear_CPU_GA102(OBJGPU * pGpu,Intr * pIntr,NvU32 regIndex,NvU32 value,THREAD_STATE_NODE * pThreadState)79 intrWriteRegTopEnClear_CPU_GA102
80 (
81 OBJGPU *pGpu,
82 Intr *pIntr,
83 NvU32 regIndex,
84 NvU32 value,
85 THREAD_STATE_NODE *pThreadState
86 )
87 {
88 // SW assumptions that there are two top-levels.
89 ct_assert(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 <= 2);
90 if (regIndex >= NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1)
91 {
92 return;
93 }
94 GPU_VREG_WR32_EX(pGpu,
95 NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(regIndex),
96 value,
97 pThreadState);
98 }
99