1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "core/core.h"
25 #include "kernel/gpu/mc/kernel_mc.h"
26 #include "gpu/gpu.h"
27
28 #include "published/hopper/gh100/dev_pmc.h"
29
30 /*!
31 * @brief Updates PMC_ENABLE register whose pmcEnableMask is passed.
32 *
33 * @param[in] pGpu GPU object pointer
34 * @param[in] pKernelMc
35 * @param[in] pmcEnableMask PMC Mask of engines to be reset.
36 * @param[in] bEnable If True, Enable the engine, else Reset the engines.
37 * @param[in] bIsPmcDeviceEngine NV_TRUE if it is PMC_DEVICE_ENABLE register
38 * else its PMC_ENABLE register.
39 *
40 * @return NV_OK
41 */
42 NV_STATUS
kmcWritePmcEnableReg_GH100(OBJGPU * pGpu,KernelMc * pKernelMc,NvU32 pmcEnableMask,NvBool bEnable,NvBool bIsPmcDeviceEngine)43 kmcWritePmcEnableReg_GH100
44 (
45 OBJGPU *pGpu,
46 KernelMc *pKernelMc,
47 NvU32 pmcEnableMask,
48 NvBool bEnable,
49 NvBool bIsPmcDeviceEngine
50 )
51 {
52 if (bIsPmcDeviceEngine)
53 {
54 NV_ASSERT_FAILED("NV_PMC_DEVICE_ENABLE is not valid on Hopper+\n");
55 return NV_ERR_INVALID_ARGUMENT;
56 }
57
58 // No need for bIsPmcDeviceEngine, so just call GK104
59 return kmcWritePmcEnableReg_GK104(pGpu, pKernelMc, pmcEnableMask, bEnable, NV_FALSE);
60 }
61
62 /*!
63 * @brief Returns NV_PMC_ENABLE or NV_PMC_DEVICE_ENABLE register based on bIsPmcDeviceEngine.
64 * If bIsPmcDeviceEngine is NV_TRUE, then return NV_PMC_DEVICE_ENABLE (available from Ampere),
65 * If bIsPmcDeviceEngine is NV_FALSE, then return NV_PMC_ENABLE.
66 *
67 * @param[in] pGpu GPU object pointer
68 * @param[in] pKernelMc
69 * @param[in] bIsPmcDeviceEngine if true return NV_PMC_DEVICE_ENABLE else return NV_PMC_ENABLE register.
70 *
71 * @return NvU32 containing register data
72 */
73 NvU32
kmcReadPmcEnableReg_GH100(OBJGPU * pGpu,KernelMc * pKernelMc,NvBool bIsPmcDeviceEngine)74 kmcReadPmcEnableReg_GH100
75 (
76 OBJGPU *pGpu,
77 KernelMc *pKernelMc,
78 NvBool bIsPmcDeviceEngine
79 )
80 {
81 if (bIsPmcDeviceEngine)
82 {
83 NV_ASSERT_FAILED("NV_PMC_DEVICE_ENABLE is not valid on Hopper+\n");
84 return 0;
85 }
86
87 // No need for bIsPmcDeviceEngine, so just call GK104
88 return kmcReadPmcEnableReg_GK104(pGpu, pKernelMc, NV_FALSE);
89 }
90