1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gpu/sec2/kernel_sec2.h"
25
26 #include "core/core.h"
27 #include "gpu/falcon/kernel_falcon.h"
28 #include "gpu/gpu.h"
29 #include "os/nv_memory_type.h"
30
31 #include "published/ampere/ga100/dev_fuse.h"
32 #include "published/ampere/ga100/dev_sec_pri.h"
33 #include "published/ampere/ga100/dev_sec_addendum.h"
34
35 NV_STATUS
ksec2ConfigureFalcon_GA100(OBJGPU * pGpu,KernelSec2 * pKernelSec2)36 ksec2ConfigureFalcon_GA100
37 (
38 OBJGPU *pGpu,
39 KernelSec2 *pKernelSec2
40 )
41 {
42 KernelFalconEngineConfig falconConfig;
43
44 portMemSet(&falconConfig, 0, sizeof(falconConfig));
45
46 falconConfig.registerBase = DRF_BASE(NV_PSEC);
47 falconConfig.riscvRegisterBase = 0; // RISC-V unused or unsupported
48 falconConfig.fbifBase = NV_PSEC_FBIF_BASE;
49 falconConfig.bBootFromHs = NV_FALSE;
50 falconConfig.pmcEnableMask = 0;
51 falconConfig.bIsPmcDeviceEngine = NV_FALSE;
52 falconConfig.physEngDesc = ENG_SEC2;
53 falconConfig.ctxAttr = NV_MEMORY_UNCACHED;
54 falconConfig.ctxBufferSize = FLCN_CTX_ENG_BUFFER_SIZE_HW << 4;
55 falconConfig.addrSpaceList = memdescAddrSpaceListToU32(ADDRLIST_FBMEM_PREFERRED);
56
57 kflcnConfigureEngine(pGpu, staticCast(pKernelSec2, KernelFalcon), &falconConfig);
58 return NV_OK;
59 }
60
61 /*!
62 * Returns the SEC2 fuse version of the provided ucode id (1-indexed)
63 *
64 * @param pGpu OBJGPU pointer
65 * @param pKernelSec2 KernelSec2 pointer
66 * @param[in] ucodeId Ucode Id (1-indexed) to read fuse for
67 */
68 NvU32
ksec2ReadUcodeFuseVersion_GA100(OBJGPU * pGpu,KernelSec2 * pKernelSec2,const NvU32 ucodeId)69 ksec2ReadUcodeFuseVersion_GA100
70 (
71 OBJGPU *pGpu,
72 KernelSec2 *pKernelSec2,
73 const NvU32 ucodeId
74 )
75 {
76 NvU32 fuseVal = 0;
77 NvU32 index = ucodeId - 1; // adjust to 0-indexed
78
79 // TODO: Bug 3519329: switch to indexed register once available
80 // if (index < NV_FUSE_OPT_FPF_SEC2_UCODE_VERSION__SIZE_1)
81 if (index < 16)
82 {
83 // fuseVal = GPU_REG_IDX_RD_DRF(pGpu, _FUSE, _OPT_FPF_SEC2_UCODE_VERSION, index, _DATA);
84 fuseVal = GPU_REG_RD32(pGpu, NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION + (4 * index));
85
86 if (fuseVal)
87 {
88 HIGHESTBITIDX_32(fuseVal);
89 fuseVal = fuseVal + 1;
90 }
91 }
92
93 return fuseVal;
94 }
95