1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 25 /***************************** HW State Routines ***************************\ 26 * * 27 * Module: os_stubs.c * 28 * Stubs for all the public stub routines * 29 \***************************************************************************/ 30 31 #include "os/os_stub.h" 32 33 // 34 // Here's a little debugging tool. It is possible that some code is stubbed for 35 // certain OS's that shouldn't be. In debug mode, the stubs below will dump out 36 // a stub 'number' to help you identify any stubs that are getting called. You 37 // can then evaluate whether or not that is correct. 38 // 39 // Highest used STUB_CHECK is 237. 40 // 41 #if defined(DEBUG) 42 #define STUB_CHECK(n) _stubCallCheck(n) 43 44 int enableOsStubCallCheck = 0; 45 46 static void _stubCallCheck(int funcNumber) 47 { 48 if (enableOsStubCallCheck) { 49 NV_PRINTF(LEVEL_INFO, "STUB CALL: %d \r\n", funcNumber); 50 } 51 } 52 53 #else 54 #define STUB_CHECK(n) 55 #endif // DEBUG 56 57 struct OBJCL; 58 59 void stubOsQADbgRegistryInit(OBJOS *pOS) 60 { 61 STUB_CHECK(61); 62 } 63 64 NvU32 stubOsnv_rdcr4(OBJOS *pOS) 65 { 66 STUB_CHECK(76); 67 return 0; 68 } 69 70 NvU64 stubOsnv_rdxcr0(OBJOS *pOs) 71 { 72 STUB_CHECK(237); 73 return 0; 74 } 75 76 int stubOsnv_cpuid(OBJOS *pOS, int arg1, int arg2, NvU32 *arg3, 77 NvU32 *arg4, NvU32 *arg5, NvU32 *arg6) 78 { 79 STUB_CHECK(77); 80 return 0; 81 } 82 83 NvU32 stubOsnv_rdmsr(OBJOS *pOS, NvU32 arg1, NvU32 *arg2, NvU32 *arg3) 84 { 85 STUB_CHECK(122); 86 return 0; 87 } 88 89 NvU32 stubOsnv_wrmsr(OBJOS *pOS, NvU32 arg1, NvU32 arg2, NvU32 arg3) 90 { 91 STUB_CHECK(123); 92 return 0; 93 } 94 95 NvU32 stubOsRobustChannelsDefaultState(OBJOS *pOS) 96 { 97 STUB_CHECK(128); 98 return 0; 99 } 100 101 NV_STATUS stubOsQueueWorkItem(OBJGPU *pGpu, OSWorkItemFunction pFunction, void * pParms) 102 { 103 STUB_CHECK(180); 104 return NV_ERR_NOT_SUPPORTED; 105 } 106 107 NV_STATUS stubOsQueueSystemWorkItem(OSSystemWorkItemFunction pFunction, void *pParms) 108 { 109 STUB_CHECK(181); 110 return NV_ERR_NOT_SUPPORTED; 111 } 112 113 NV_STATUS stubOsQueueWorkItemWithFlags(OBJGPU *pGpu, OSWorkItemFunction pFunction, void * pParms, NvU32 flags) 114 { 115 STUB_CHECK(182); 116 return NV_ERR_NOT_SUPPORTED; 117 } 118 119 NV_STATUS stubOsSimEscapeWrite(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, NvU32 Value) 120 { 121 STUB_CHECK(195); 122 return NV_ERR_GENERIC; 123 } 124 125 NV_STATUS stubOsSimEscapeWriteBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, void* pBuffer) 126 { 127 STUB_CHECK(197); 128 return NV_ERR_GENERIC; 129 } 130 131 NV_STATUS stubOsSimEscapeRead(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value) 132 { 133 STUB_CHECK(196); 134 return NV_ERR_GENERIC; 135 } 136 137 NV_STATUS stubOsSimEscapeReadBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, void* pBuffer) 138 { 139 STUB_CHECK(198); 140 return NV_ERR_GENERIC; 141 } 142 143 NV_STATUS osCallACPI_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU8 *pInOut) 144 { 145 return NV_ERR_NOT_SUPPORTED; 146 } 147 148 NV_STATUS stubOsCallACPI_BCL(OBJGPU *pGpu, NvU32 acpiId, NvU32 *pOut, NvU16 *size) 149 { 150 return NV_ERR_NOT_SUPPORTED; 151 } 152 153 NV_STATUS stubOsCallACPI_ON(OBJGPU *pGpu, NvU32 uAcpiId) 154 { 155 return NV_ERR_NOT_SUPPORTED; 156 } 157 158 NV_STATUS stubOsCallACPI_OFF(OBJGPU *pGpu, NvU32 uAcpiId) 159 { 160 return NV_ERR_NOT_SUPPORTED; 161 } 162 163 NV_STATUS stubOsCallACPI_NBPS(OBJGPU *pGpu, NvU8 *pOut, NvU32 *pOutSize) 164 { 165 *pOutSize = 0; 166 return NV_ERR_NOT_SUPPORTED; 167 } 168 169 NV_STATUS stubOsCallACPI_NBSL(OBJGPU *pGpu, NvU32 val) 170 { 171 return NV_ERR_NOT_SUPPORTED; 172 } 173 174 NV_STATUS stubOsCallWMI_OPTM_GPUON(OBJGPU *pGpu) 175 { 176 return NV_ERR_NOT_SUPPORTED; 177 } 178 179 NV_STATUS stubOsCallWMI_NVHG_GPUON(OBJGPU *pGpu, NvU32 *pInOut) 180 { 181 //STUB_CHECK(225); 182 return NV_ERR_NOT_SUPPORTED; 183 } 184 185 NV_STATUS stubOsCallWMI_NVHG_GPUOFF(OBJGPU *pGpu, NvU32 *pInOut) 186 { 187 //STUB_CHECK(226); 188 return NV_ERR_NOT_SUPPORTED; 189 } 190 191 NV_STATUS stubOsCallWMI_NVHG_GPUSTA(OBJGPU *pGpu, NvU32 *pInOut) 192 { 193 //STUB_CHECK(227); 194 return NV_ERR_NOT_SUPPORTED; 195 } 196 197 NV_STATUS stubOsCallWMI_NVHG_MXDS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) 198 { 199 //STUB_CHECK(228); 200 return NV_ERR_NOT_SUPPORTED; 201 } 202 203 NV_STATUS stubOsCallWMI_NVHG_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) 204 { 205 //STUB_CHECK(229); 206 return NV_ERR_NOT_SUPPORTED; 207 } 208 209 NV_STATUS stubOsCallWMI_NVHG_DOS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) 210 { 211 //STUB_CHECK(230); 212 return NV_ERR_NOT_SUPPORTED; 213 } 214 215 NV_STATUS stubOsCallWMI_NVHG_DCS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) 216 { 217 //STUB_CHECK(232); 218 return NV_ERR_NOT_SUPPORTED; 219 } 220 221 NV_STATUS osCallACPI_MXID(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) 222 { 223 return NV_ERR_NOT_SUPPORTED; 224 } 225 226 NV_STATUS stubOsCallACPI_LRST(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) 227 { 228 return NV_ERR_NOT_SUPPORTED; 229 } 230 231 NvBool stubOsCheckCallback(OBJGPU *pGpu) 232 { 233 return NV_FALSE; 234 } 235 236 RC_CALLBACK_STATUS 237 stubOsRCCallback 238 ( 239 OBJGPU *pGpu, 240 NvHandle hClient, // IN The client RC is on 241 NvHandle hDevice, // IN The device RC is on 242 NvHandle hFifo, // IN The channel or TSG RC is on 243 NvHandle hChannel, // IN The channel RC is on 244 NvU32 errorLevel, // IN Error Level 245 NvU32 errorType, // IN Error type 246 NvU32 *data, // IN/OUT context of RC handler 247 void *pfnRmRCReenablePusher 248 ) 249 { 250 return RC_CALLBACK_IGNORE; 251 } 252 253 NV_STATUS stubOsSetupVBlank(OBJGPU *pGpu, void * pProc, 254 void * pParm1, void * pParm2, NvU32 Head, void * pParm3) 255 { 256 return NV_OK; 257 } 258 259 NV_STATUS stubOsObjectEventNotification(NvHandle hClient, NvHandle hObject, NvU32 hClass, PEVENTNOTIFICATION pNotifyEvent, 260 NvU32 notifyIndex, void * pEventData, NvU32 eventDataSize) 261 { 262 return NV_ERR_NOT_SUPPORTED; 263 } 264 265 RmPhysAddr 266 stubOsPageArrayGetPhysAddr(OS_GPU_INFO *pOsGpuInfo, void* pPageData, NvU32 pageIndex) 267 { 268 NV_ASSERT(0); 269 return 0; 270 } 271 272 void stubOsInternalReserveAllocCallback(NvU64 offset, NvU64 size, NvU32 gpuId) 273 { 274 return; 275 } 276 277 void stubOsInternalReserveFreeCallback(NvU64 offset, NvU32 gpuId) 278 { 279 return; 280 } 281 282 NV_STATUS osGetCurrentProcessGfid(NvU32 *pGfid) 283 { 284 return NV_ERR_NOT_SUPPORTED; 285 } 286 287 #if !(RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_DCE) || \ 288 (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) 289 NV_STATUS osTegraSocGpioGetPinState( 290 OS_GPU_INFO *pArg1, 291 NvU32 arg2, 292 NvU32 *pArg3 293 ) 294 { 295 return NV_ERR_NOT_SUPPORTED; 296 } 297 298 void osTegraSocGpioSetPinState( 299 OS_GPU_INFO *pArg1, 300 NvU32 arg2, 301 NvU32 arg3 302 ) 303 { 304 } 305 306 NV_STATUS osTegraSocGpioSetPinDirection( 307 OS_GPU_INFO *pArg1, 308 NvU32 arg2, 309 NvU32 arg3 310 ) 311 { 312 return NV_ERR_NOT_SUPPORTED; 313 } 314 315 NV_STATUS osTegraSocGpioGetPinDirection( 316 OS_GPU_INFO *pArg1, 317 NvU32 arg2, 318 NvU32 *pArg3 319 ) 320 { 321 return NV_ERR_NOT_SUPPORTED; 322 } 323 324 NV_STATUS osTegraSocGpioGetPinNumber( 325 OS_GPU_INFO *pArg1, 326 NvU32 arg2, 327 NvU32 *pArg3 328 ) 329 { 330 return NV_ERR_NOT_SUPPORTED; 331 } 332 333 NV_STATUS osTegraSocGpioGetPinInterruptStatus( 334 OS_GPU_INFO *pArg1, 335 NvU32 arg2, 336 NvU32 arg3, 337 NvBool *pArg4 338 ) 339 { 340 return NV_ERR_NOT_SUPPORTED; 341 } 342 343 NV_STATUS osTegraSocGpioSetPinInterrupt( 344 OS_GPU_INFO *pArg1, 345 NvU32 arg2, 346 NvU32 arg3 347 ) 348 { 349 return NV_ERR_NOT_SUPPORTED; 350 } 351 352 NV_STATUS 353 osTegraSocResetMipiCal 354 ( 355 OS_GPU_INFO *pOsGpuInfo 356 ) 357 { 358 return NV_ERR_NOT_SUPPORTED; 359 } 360 361 NV_STATUS osGetValidWindowHeadMask 362 ( 363 OS_GPU_INFO *pArg1, 364 NvU64 *pWindowHeadMask 365 ) 366 { 367 return NV_ERR_NOT_SUPPORTED; 368 } 369 370 NvBool 371 osTegraSocIsDsiPanelConnected 372 ( 373 OS_GPU_INFO *pOsGpuInfo 374 ) 375 { 376 return NV_FALSE; 377 } 378 379 NV_STATUS 380 osTegraSocDsiParsePanelProps 381 ( 382 OS_GPU_INFO *pOsGpuInfo, 383 void *dsiPanelInfo 384 ) 385 { 386 return NV_ERR_NOT_SUPPORTED; 387 } 388 389 NV_STATUS 390 osTegraSocDsiPanelEnable 391 ( 392 OS_GPU_INFO *pOsGpuInfo, 393 void *dsiPanelInfo 394 ) 395 { 396 return NV_ERR_NOT_SUPPORTED; 397 } 398 399 NV_STATUS 400 osTegraSocDsiPanelReset 401 ( 402 OS_GPU_INFO *pOsGpuInfo, 403 void *dsiPanelInfo 404 ) 405 { 406 return NV_ERR_NOT_SUPPORTED; 407 } 408 409 void 410 osTegraSocDsiPanelDisable 411 ( 412 OS_GPU_INFO *pOsGpuInfo, 413 void *dsiPanelInfo 414 ) 415 { 416 return; 417 } 418 419 void 420 osTegraSocDsiPanelCleanup 421 ( 422 OS_GPU_INFO *pOsGpuInfo, 423 void *dsiPanelInfo 424 ) 425 { 426 return; 427 } 428 #endif 429 430 NV_STATUS 431 osTegraSocParseFixedModeTimings 432 ( 433 OS_GPU_INFO *pOsGpuInfo, 434 NvU32 dcbIndex, 435 OS_FIXED_MODE_TIMINGS *pFixedModeTimings 436 ) 437 { 438 return NV_OK; 439 } 440 441 442 NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection) 443 { 444 return NV_OK; 445 } 446 447 NV_STATUS osUnlockPageableDataSection(RM_PAGEABLE_SECTION *pSection) 448 { 449 return NV_OK; 450 } 451 452 NV_STATUS osIsKernelBuffer(void *pArg1, NvU32 arg2) 453 { 454 return NV_OK; 455 } 456 457 NV_STATUS osMapViewToSection(OS_GPU_INFO *pArg1, 458 void *pSectionHandle, 459 void **ppAddress, 460 NvU64 actualSize, 461 NvU64 sectionOffset, 462 NvBool bIommuEnabled) 463 { 464 return NV_ERR_NOT_SUPPORTED; 465 } 466 467 NV_STATUS osUnmapViewFromSection(OS_GPU_INFO *pArg1, 468 void *pAddress, 469 NvBool bIommuEnabled) 470 { 471 return NV_ERR_NOT_SUPPORTED; 472 } 473 474 NV_STATUS osSrPinSysmem( 475 OS_GPU_INFO *pArg1, 476 NvU64 commitSize, 477 void *pMdl 478 ) 479 { 480 return NV_ERR_NOT_SUPPORTED; 481 } 482 483 NV_STATUS osSrUnpinSysmem(OS_GPU_INFO *pArg1) 484 { 485 return NV_ERR_NOT_SUPPORTED; 486 } 487 488 NV_STATUS osCreateMemFromOsDescriptorInternal( 489 OBJGPU *pGpu, 490 void *pAddress, 491 NvU32 flags, 492 NvU64 size, 493 MEMORY_DESCRIPTOR **ppMemDesc, 494 NvBool bCachedKernel, 495 RS_PRIV_LEVEL privilegeLevel 496 ) 497 { 498 return NV_ERR_NOT_SUPPORTED; 499 } 500 501 NV_STATUS osReserveCpuAddressSpaceUpperBound(void **ppSectionHandle, 502 NvU64 maxSectionSize) 503 { 504 return NV_ERR_NOT_SUPPORTED; 505 } 506 507 void osReleaseCpuAddressSpaceUpperBound(void *pSectionHandle) 508 { 509 } 510 511 void osIoWriteDword( 512 NvU32 port, 513 NvU32 data 514 ) 515 { 516 } 517 518 NvU32 osIoReadDword( 519 NvU32 port 520 ) 521 { 522 return 0; 523 } 524 525 NvBool osIsVga( 526 OS_GPU_INFO *pArg1, 527 NvBool bIsGpuPrimaryDevice 528 ) 529 { 530 return bIsGpuPrimaryDevice; 531 } 532 533 void osInitOSHwInfo( 534 OBJGPU *pGpu 535 ) 536 { 537 } 538 539 void osDestroyOSHwInfo( 540 OBJGPU *pGpu 541 ) 542 { 543 } 544 545 NV_STATUS osDoFunctionLevelReset( 546 OBJGPU *pGpu 547 ) 548 { 549 return NV_ERR_NOT_SUPPORTED; 550 } 551 552 NvBool osGrService( 553 OS_GPU_INFO *pOsGpuInfo, 554 NvU32 grIdx, 555 NvU32 intr, 556 NvU32 nstatus, 557 NvU32 addr, 558 NvU32 dataLo 559 ) 560 { 561 return NV_FALSE; 562 } 563 564 NvBool osDispService( 565 NvU32 Intr0, 566 NvU32 Intr1 567 ) 568 { 569 return NV_FALSE; 570 } 571 572 NV_STATUS osDeferredIsr( 573 OBJGPU *pGpu 574 ) 575 { 576 return NV_OK; 577 } 578 579 void osSetSurfaceName( 580 void *pDescriptor, 581 char *name 582 ) 583 { 584 } 585 586 NV_STATUS osGetAcpiTable( 587 NvU32 tableSignature, 588 void **ppTable, 589 NvU32 tableSize, 590 NvU32 *retSize 591 ) 592 { 593 return NV_ERR_NOT_SUPPORTED; 594 } 595 596 NV_STATUS osInitGetAcpiTable(void) 597 { 598 return NV_ERR_NOT_SUPPORTED; 599 } 600 601 void osDbgBugCheckOnAssert(void) 602 { 603 return; 604 } 605 606 NvBool osQueueDpc(OBJGPU *pGpu) 607 { 608 return NV_FALSE; 609 } 610 611 NvBool osBugCheckOnTimeoutEnabled(void) 612 { 613 return NV_FALSE; 614 } 615 616 NV_STATUS osNvifMethod( 617 OBJGPU *pGpu, 618 NvU32 func, 619 NvU32 subFunc, 620 void *pInParam, 621 NvU16 inParamSize, 622 NvU32 *pOutStatus, 623 void *pOutData, 624 NvU16 *pOutDataSize 625 ) 626 { 627 return NV_ERR_NOT_SUPPORTED; 628 } 629 630 NV_STATUS osNvifInitialize( 631 OBJGPU *pGpu 632 ) 633 { 634 return NV_ERR_NOT_SUPPORTED; 635 } 636 637 NV_STATUS 638 stubOsGetUefiVariable 639 ( 640 OBJGPU *pGpu, 641 char *pName, 642 LPGUID pGuid, 643 NvU8 *pBuffer, 644 NvU32 *pSize, 645 NvU32 *pAttributes 646 ) 647 { 648 return NV_ERR_NOT_SUPPORTED; 649 } 650 651 NV_STATUS 652 osGetNvGlobalRegistryDword 653 ( 654 OBJGPU *pGpu, 655 const char *pRegParmStr, 656 NvU32 *pData 657 ) 658 { 659 return NV_ERR_NOT_SUPPORTED; 660 } 661 662 NvU32 osGetDynamicPowerSupportMask(void) 663 { 664 return 0; 665 } 666 667 void osUnrefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo) 668 { 669 return; 670 } 671 672 NV_STATUS osRefGpuAccessNeeded(OS_GPU_INFO *pOsGpuInfo) 673 { 674 return NV_OK; 675 } 676 677 void osClientGcoffDisallowRefcount( 678 OS_GPU_INFO *pArg1, 679 NvBool arg2 680 ) 681 { 682 } 683 684 #if !RMCFG_FEATURE_PLATFORM_DCE /* dce_core_rm_clk_reset.c */ && \ 685 (!RMCFG_FEATURE_PLATFORM_UNIX || !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY || \ 686 RMCFG_FEATURE_DCE_CLIENT_RM /* osSocNvDisp.c */ ) 687 NV_STATUS 688 osTegraSocEnableClk 689 ( 690 OS_GPU_INFO *pOsGpuInfo, 691 NvU32 whichClkRM 692 ) 693 { 694 return NV_ERR_NOT_SUPPORTED; 695 } 696 697 NV_STATUS 698 osTegraSocDisableClk 699 ( 700 OS_GPU_INFO *pOsGpuInfo, 701 NvU32 whichClkRM 702 ) 703 { 704 return NV_ERR_NOT_SUPPORTED; 705 } 706 707 NV_STATUS 708 osTegraSocGetCurrFreqKHz 709 ( 710 OS_GPU_INFO *pOsGpuInfo, 711 NvU32 whichClkRM, 712 NvU32 *pCurrFreqKHz 713 ) 714 { 715 return NV_ERR_NOT_SUPPORTED; 716 } 717 718 NV_STATUS 719 osTegraSocGetMaxFreqKHz 720 ( 721 OS_GPU_INFO *pOsGpuInfo, 722 NvU32 whichClkRM, 723 NvU32 *pMaxFreqKHz 724 ) 725 { 726 return NV_ERR_NOT_SUPPORTED; 727 } 728 729 NV_STATUS 730 osTegraSocGetMinFreqKHz 731 ( 732 OS_GPU_INFO *pOsGpuInfo, 733 NvU32 whichClkRM, 734 NvU32 *pMinFreqKHz 735 ) 736 { 737 return NV_ERR_NOT_SUPPORTED; 738 } 739 740 NV_STATUS 741 osTegraSocSetFreqKHz 742 ( 743 OS_GPU_INFO *pOsGpuInfo, 744 NvU32 whichClkRM, 745 NvU32 reqFreqKHz 746 ) 747 { 748 return NV_ERR_NOT_SUPPORTED; 749 } 750 751 NV_STATUS 752 osTegraSocSetParent 753 ( 754 OS_GPU_INFO *pOsGpuInfo, 755 NvU32 whichClkRMsource, 756 NvU32 whichClkRMparent 757 ) 758 { 759 return NV_ERR_NOT_SUPPORTED; 760 } 761 762 NV_STATUS 763 osTegraSocGetParent 764 ( 765 OS_GPU_INFO *pOsGpuInfo, 766 NvU32 whichClkRMsource, 767 NvU32 *pWhichClkRMparent 768 ) 769 { 770 return NV_ERR_NOT_SUPPORTED; 771 } 772 773 NV_STATUS 774 osTegraSocDeviceReset 775 ( 776 OS_GPU_INFO *pOsGpuInfo 777 ) 778 { 779 return NV_ERR_NOT_SUPPORTED; 780 } 781 782 NV_STATUS 783 osTegraSocPmPowergate 784 ( 785 OS_GPU_INFO *pOsGpuInfo 786 ) 787 { 788 return NV_ERR_NOT_SUPPORTED; 789 } 790 791 NV_STATUS 792 osTegraSocPmUnpowergate 793 ( 794 OS_GPU_INFO *pOsGpuInfo 795 ) 796 { 797 return NV_ERR_NOT_SUPPORTED; 798 } 799 #endif 800 801 #if !(RMCFG_FEATURE_PLATFORM_UNIX) || \ 802 (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) 803 NvU32 804 osTegraSocFuseRegRead(NvU32 addr) 805 { 806 return 0; 807 } 808 809 NV_STATUS 810 osTegraSocHspSemaphoreAcquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout) 811 { 812 return NV_ERR_NOT_SUPPORTED; 813 } 814 815 NV_STATUS 816 osTegraSocDpUphyPllInit(OS_GPU_INFO *pOsGpuInfo, NvU32 link_rate, NvU32 lanes) 817 { 818 return NV_ERR_NOT_SUPPORTED; 819 } 820 821 NV_STATUS 822 osTegraSocDpUphyPllDeInit(OS_GPU_INFO *pOsGpuInfo) 823 { 824 return NV_ERR_NOT_SUPPORTED; 825 } 826 827 #endif 828 829 830