1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2000-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /*! 25 * @file 26 * @brief includes defines used by cpu.c to get cpu information 27 */ 28 29 #ifndef CPUID_ARM_DEF_H_ 30 #define CPUID_ARM_DEF_H_ 31 32 #if defined(__GNUC__) 33 34 #define CP_READ_CCSIDR_REGISTER() CP_READ_REGISTER(CP_CCSIDR) 35 #define CP_READ_MIDR_REGISTER() CP_READ_REGISTER(CP_MIDR) 36 #define CP_WRITE_CSSELR_REGISTER(val) CP_WRITE_REGISTER(CP_CSSELR, val) 37 38 #else 39 40 extern NvU32 CP_READ_CCSIDR_REGISTER(); 41 extern NvU32 CP_READ_MIDR_REGISTER(); 42 extern void CP_WRITE_CSSELR_REGISTER(NvU32 val); 43 44 #endif // defined(__GNUC__) 45 46 #define GET_BITMASK(f, v) ((v) >> DRF_SHIFT(CP_ ## f) & DRF_MASK(CP_ ## f)) 47 48 #define CP_MIDR_IMPLEMENTER 31:24 49 #define CP_MIDR_PRIMARY_PART_NUM 15:4 50 51 #define CP_MIDR_IMPLEMENTER_BROADCOM 0x42 52 #define CP_MIDR_IMPLEMENTER_NVIDIA 0x4e 53 #define CP_MIDR_IMPLEMENTER_AMCC 0x50 54 #define CP_MIDR_IMPLEMENTER_ARM 0x41 55 #define CP_MIDR_IMPLEMENTER_MARVELL 0x43 56 #define CP_MIDR_IMPLEMENTER_HUAWEI 0x48 57 #define CP_MIDR_IMPLEMENTER_FUJITSU 0x46 58 #define CP_MIDR_IMPLEMENTER_PHYTIUM 0x70 59 #define CP_MIDR_IMPLEMENTER_AMPERE 0x81 60 #define CP_MIDR_IMPLEMENTER_AMPERE_2 0XC0 61 62 #define CP_CSSELR_DATA_CACHE 0 63 #define CP_CSSELR_INSTRUCTION_CACHE 1 64 #define CP_CSSELR_DATA_CACHE_LEVEL2 2 65 66 #define CP_CCSIDR_CACHE_LINE_SIZE 2:0 67 #define CP_CCSIDR_CACHE_ASSOCIATIVITY 12:3 68 #define CP_CCSIDR_CACHE_NUM_SETS 27:13 69 70 #if defined(NVCPU_AARCH64) 71 72 // Main ID Register 73 #define CP_MIDR "midr_el1" 74 75 #define CP_MIDR_PRIMARY_PART_NUM_DENVER_1 0x0 76 #define CP_MIDR_PRIMARY_PART_NUM_DENVER_2 0x3 77 #define CP_MIDR_PRIMARY_PART_NUM_CARMEL 0x4 78 79 #define CP_MIDR_PRIMARY_PART_NUM_XGENE 0x0 80 #define CP_MIDR_PRIMARY_PART_NUM_CORTEX_A57 0xd07 81 #define CP_MIDR_PRIMARY_PART_NUM_CORTEX_A76 0xd0b 82 #define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_V2 0xd4f 83 #define CP_MIDR_PRIMARY_PART_NUM_THUNDER_X2 0x0af 84 #define CP_MIDR_PRIMARY_PART_NUM_KUNPENG_920 0xd01 85 #define CP_MIDR_PRIMARY_PART_NUM_BLUEFIELD 0xd08 86 #define CP_MIDR_PRIMARY_PART_NUM_BLUEFIELD3 0xd42 87 #define CP_MIDR_PRIMARY_PART_NUM_GRAVITRON2 0xd0c 88 #define CP_MIDR_PRIMARY_PART_NUM_A64FX 0x001 89 #define CP_MIDR_PRIMARY_PART_NUM_FT2000 0x662 90 #define CP_MIDR_PRIMARY_PART_NUM_S2500 0x663 91 #define CP_MIDR_PRIMARY_PART_NUM_ALTRA 0x000 92 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2 93 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1 94 #define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_N2 0xd49 95 #define CP_MIDR_PRIMARY_PART_NUM_AMPEREONE 0xac3 96 97 // Cache Size Identification Register 98 #define CP_CCSIDR "ccsidr_el1" 99 100 // Cache Size Selection Register 101 #define CP_CSSELR "csselr_el1" 102 103 #else // NVCPU_AARCH64 104 105 // Main ID Register 106 #define CP_MIDR "0" 107 108 #define CP_MIDR_PRIMARY_PART_NUM_A9 0xC09 109 #define CP_MIDR_PRIMARY_PART_NUM_A15 0xC0F 110 111 // Cache Size Identification Register 112 #define CP_CCSIDR "1" 113 114 #define CP_CCSIDR_CACHE_LINE_SIZE_8W 1 115 116 #define CP_CCSIDR_CACHE_NUM_SETS_16KB 0x7F 117 #define CP_CCSIDR_CACHE_NUM_SETS_32KB 0xFF 118 #define CP_CCSIDR_CACHE_NUM_SETS_64KB 0x1FF 119 120 #define CP_CCSIDR_CACHE_NUM_SETS_A15_32KB 0xFF 121 #define CP_CCSIDR_CACHE_NUM_SETS_A15_512KB 0x1FF 122 #define CP_CCSIDR_CACHE_NUM_SETS_A15_1024KB 0x3FF 123 #define CP_CCSIDR_CACHE_NUM_SETS_A15_2048KB 0x7FF 124 #define CP_CCSIDR_CACHE_NUM_SETS_A15_4096KB 0xFFF 125 126 // Cache Size Selection Register 127 #define CP_CSSELR "2" 128 129 #endif // NVCPU_AARCH64 130 131 #endif /* CPUID_ARM_DEF_H_ */ 132