1 /*
2  * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3  * SPDX-License-Identifier: MIT
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include "virtualization/common_vgpu_mgr.h"
25 #include "virtualization/hypervisor/hypervisor.h"
26 
27 #include "ctrl/ctrl2080/ctrl2080gpu.h"
28 
29 void
30 vgpuMgrFillVgpuType(NVA081_CTRL_VGPU_INFO *pVgpuInfo, VGPU_TYPE *pVgpuTypeNode)
31 {
32 }
33 
34 NV_STATUS
35 vgpuMgrReserveSystemChannelIDs
36 (
37     OBJGPU *pGpu,
38     VGPU_TYPE *vgpuTypeInfo,
39     NvU32 gfid,
40     NvU32 *pChidOffset,
41     NvU32 *pChannelCount,
42     Device *pMigDevice,
43     NvU32 numChannels,
44     NvU32 engineFifoListNumEntries,
45     FIFO_ENGINE_LIST *engineFifoList
46 )
47 {
48     return NV_ERR_NOT_SUPPORTED;
49 }
50 
51 void
52 vgpuMgrFreeSystemChannelIDs
53 (
54     OBJGPU *pGpu,
55     NvU32 gfid,
56     NvU32 *pChidOffset,
57     NvU32 *pChannelCount,
58     Device *pMigDevice,
59     NvU32 engineFifoListNumEntries,
60     FIFO_ENGINE_LIST *engineFifoList
61 )
62 {
63 }
64