1404b540aSrobert /* Definitions of target machine for GNU compiler, for DEC Alpha. 2404b540aSrobert Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3404b540aSrobert 2000, 2001, 2002, 2004, 2005 Free Software Foundation, Inc. 4404b540aSrobert Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 5404b540aSrobert 6404b540aSrobert This file is part of GCC. 7404b540aSrobert 8404b540aSrobert GCC is free software; you can redistribute it and/or modify 9404b540aSrobert it under the terms of the GNU General Public License as published by 10404b540aSrobert the Free Software Foundation; either version 2, or (at your option) 11404b540aSrobert any later version. 12404b540aSrobert 13404b540aSrobert GCC is distributed in the hope that it will be useful, 14404b540aSrobert but WITHOUT ANY WARRANTY; without even the implied warranty of 15404b540aSrobert MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16404b540aSrobert GNU General Public License for more details. 17404b540aSrobert 18404b540aSrobert You should have received a copy of the GNU General Public License 19404b540aSrobert along with GCC; see the file COPYING. If not, write to 20404b540aSrobert the Free Software Foundation, 51 Franklin Street, Fifth Floor, 21404b540aSrobert Boston, MA 02110-1301, USA. */ 22404b540aSrobert 23404b540aSrobert /* Target CPU builtins. */ 24404b540aSrobert #define TARGET_CPU_CPP_BUILTINS() \ 25404b540aSrobert do \ 26404b540aSrobert { \ 27404b540aSrobert builtin_define ("__alpha"); \ 28404b540aSrobert builtin_define ("__alpha__"); \ 29404b540aSrobert builtin_assert ("cpu=alpha"); \ 30404b540aSrobert builtin_assert ("machine=alpha"); \ 31404b540aSrobert if (TARGET_CIX) \ 32404b540aSrobert { \ 33404b540aSrobert builtin_define ("__alpha_cix__"); \ 34404b540aSrobert builtin_assert ("cpu=cix"); \ 35404b540aSrobert } \ 36404b540aSrobert if (TARGET_FIX) \ 37404b540aSrobert { \ 38404b540aSrobert builtin_define ("__alpha_fix__"); \ 39404b540aSrobert builtin_assert ("cpu=fix"); \ 40404b540aSrobert } \ 41404b540aSrobert if (TARGET_BWX) \ 42404b540aSrobert { \ 43404b540aSrobert builtin_define ("__alpha_bwx__"); \ 44404b540aSrobert builtin_assert ("cpu=bwx"); \ 45404b540aSrobert } \ 46404b540aSrobert if (TARGET_MAX) \ 47404b540aSrobert { \ 48404b540aSrobert builtin_define ("__alpha_max__"); \ 49404b540aSrobert builtin_assert ("cpu=max"); \ 50404b540aSrobert } \ 51404b540aSrobert if (alpha_cpu == PROCESSOR_EV6) \ 52404b540aSrobert { \ 53404b540aSrobert builtin_define ("__alpha_ev6__"); \ 54404b540aSrobert builtin_assert ("cpu=ev6"); \ 55404b540aSrobert } \ 56404b540aSrobert else if (alpha_cpu == PROCESSOR_EV5) \ 57404b540aSrobert { \ 58404b540aSrobert builtin_define ("__alpha_ev5__"); \ 59404b540aSrobert builtin_assert ("cpu=ev5"); \ 60404b540aSrobert } \ 61404b540aSrobert else /* Presumably ev4. */ \ 62404b540aSrobert { \ 63404b540aSrobert builtin_define ("__alpha_ev4__"); \ 64404b540aSrobert builtin_assert ("cpu=ev4"); \ 65404b540aSrobert } \ 66404b540aSrobert if (TARGET_IEEE || TARGET_IEEE_WITH_INEXACT) \ 67404b540aSrobert builtin_define ("_IEEE_FP"); \ 68404b540aSrobert if (TARGET_IEEE_WITH_INEXACT) \ 69404b540aSrobert builtin_define ("_IEEE_FP_INEXACT"); \ 70404b540aSrobert if (TARGET_LONG_DOUBLE_128) \ 71404b540aSrobert builtin_define ("__LONG_DOUBLE_128__"); \ 72404b540aSrobert \ 73404b540aSrobert /* Macros dependent on the C dialect. */ \ 74404b540aSrobert SUBTARGET_LANGUAGE_CPP_BUILTINS(); \ 75404b540aSrobert } while (0) 76404b540aSrobert 77404b540aSrobert #ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS 78404b540aSrobert #define SUBTARGET_LANGUAGE_CPP_BUILTINS() \ 79404b540aSrobert do \ 80404b540aSrobert { \ 81404b540aSrobert if (preprocessing_asm_p ()) \ 82404b540aSrobert builtin_define_std ("LANGUAGE_ASSEMBLY"); \ 83404b540aSrobert else if (c_dialect_cxx ()) \ 84404b540aSrobert { \ 85404b540aSrobert builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ 86404b540aSrobert builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ 87404b540aSrobert } \ 88404b540aSrobert else \ 89404b540aSrobert builtin_define_std ("LANGUAGE_C"); \ 90404b540aSrobert if (c_dialect_objc ()) \ 91404b540aSrobert { \ 92404b540aSrobert builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ 93404b540aSrobert builtin_define ("__LANGUAGE_OBJECTIVE_C__"); \ 94404b540aSrobert } \ 95404b540aSrobert } \ 96404b540aSrobert while (0) 97404b540aSrobert #endif 98404b540aSrobert 99404b540aSrobert #define CPP_SPEC "%(cpp_subtarget)" 100404b540aSrobert 101404b540aSrobert #ifndef CPP_SUBTARGET_SPEC 102404b540aSrobert #define CPP_SUBTARGET_SPEC "" 103404b540aSrobert #endif 104404b540aSrobert 105404b540aSrobert #define WORD_SWITCH_TAKES_ARG(STR) \ 106404b540aSrobert (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR)) 107404b540aSrobert 108404b540aSrobert /* Print subsidiary information on the compiler version in use. */ 109404b540aSrobert #define TARGET_VERSION 110404b540aSrobert 111404b540aSrobert /* Run-time compilation parameters selecting different hardware subsets. */ 112404b540aSrobert 113404b540aSrobert /* Which processor to schedule for. The cpu attribute defines a list that 114404b540aSrobert mirrors this list, so changes to alpha.md must be made at the same time. */ 115404b540aSrobert 116404b540aSrobert enum processor_type 117404b540aSrobert { 118404b540aSrobert PROCESSOR_EV4, /* 2106[46]{a,} */ 119404b540aSrobert PROCESSOR_EV5, /* 21164{a,pc,} */ 120404b540aSrobert PROCESSOR_EV6, /* 21264 */ 121404b540aSrobert PROCESSOR_MAX 122404b540aSrobert }; 123404b540aSrobert 124404b540aSrobert extern enum processor_type alpha_cpu; 125404b540aSrobert extern enum processor_type alpha_tune; 126404b540aSrobert 127404b540aSrobert enum alpha_trap_precision 128404b540aSrobert { 129404b540aSrobert ALPHA_TP_PROG, /* No precision (default). */ 130404b540aSrobert ALPHA_TP_FUNC, /* Trap contained within originating function. */ 131404b540aSrobert ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */ 132404b540aSrobert }; 133404b540aSrobert 134404b540aSrobert enum alpha_fp_rounding_mode 135404b540aSrobert { 136404b540aSrobert ALPHA_FPRM_NORM, /* Normal rounding mode. */ 137404b540aSrobert ALPHA_FPRM_MINF, /* Round towards minus-infinity. */ 138404b540aSrobert ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */ 139404b540aSrobert ALPHA_FPRM_DYN /* Dynamic rounding mode. */ 140404b540aSrobert }; 141404b540aSrobert 142404b540aSrobert enum alpha_fp_trap_mode 143404b540aSrobert { 144404b540aSrobert ALPHA_FPTM_N, /* Normal trap mode. */ 145404b540aSrobert ALPHA_FPTM_U, /* Underflow traps enabled. */ 146404b540aSrobert ALPHA_FPTM_SU, /* Software completion, w/underflow traps */ 147404b540aSrobert ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */ 148404b540aSrobert }; 149404b540aSrobert 150404b540aSrobert extern int target_flags; 151404b540aSrobert 152404b540aSrobert extern enum alpha_trap_precision alpha_tp; 153404b540aSrobert extern enum alpha_fp_rounding_mode alpha_fprm; 154404b540aSrobert extern enum alpha_fp_trap_mode alpha_fptm; 155404b540aSrobert 156404b540aSrobert /* Invert the easy way to make options work. */ 157404b540aSrobert #define TARGET_FP (!TARGET_SOFT_FP) 158404b540aSrobert 159404b540aSrobert /* These are for target os support and cannot be changed at runtime. */ 160404b540aSrobert #define TARGET_ABI_WINDOWS_NT 0 161404b540aSrobert #define TARGET_ABI_OPEN_VMS 0 162404b540aSrobert #define TARGET_ABI_UNICOSMK 0 163404b540aSrobert #define TARGET_ABI_OSF (!TARGET_ABI_WINDOWS_NT \ 164404b540aSrobert && !TARGET_ABI_OPEN_VMS \ 165404b540aSrobert && !TARGET_ABI_UNICOSMK) 166404b540aSrobert 167404b540aSrobert #ifndef TARGET_AS_CAN_SUBTRACT_LABELS 168404b540aSrobert #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS 169404b540aSrobert #endif 170404b540aSrobert #ifndef TARGET_AS_SLASH_BEFORE_SUFFIX 171404b540aSrobert #define TARGET_AS_SLASH_BEFORE_SUFFIX TARGET_GAS 172404b540aSrobert #endif 173404b540aSrobert #ifndef TARGET_CAN_FAULT_IN_PROLOGUE 174404b540aSrobert #define TARGET_CAN_FAULT_IN_PROLOGUE 0 175404b540aSrobert #endif 176404b540aSrobert #ifndef TARGET_HAS_XFLOATING_LIBS 177404b540aSrobert #define TARGET_HAS_XFLOATING_LIBS TARGET_LONG_DOUBLE_128 178404b540aSrobert #endif 179404b540aSrobert #ifndef TARGET_PROFILING_NEEDS_GP 180404b540aSrobert #define TARGET_PROFILING_NEEDS_GP 0 181404b540aSrobert #endif 182404b540aSrobert #ifndef TARGET_LD_BUGGY_LDGP 183404b540aSrobert #define TARGET_LD_BUGGY_LDGP 0 184404b540aSrobert #endif 185404b540aSrobert #ifndef TARGET_FIXUP_EV5_PREFETCH 186404b540aSrobert #define TARGET_FIXUP_EV5_PREFETCH 0 187404b540aSrobert #endif 188404b540aSrobert #ifndef HAVE_AS_TLS 189404b540aSrobert #define HAVE_AS_TLS 0 190404b540aSrobert #endif 191404b540aSrobert 192404b540aSrobert #define TARGET_DEFAULT MASK_FPREGS 193404b540aSrobert 194404b540aSrobert #ifndef TARGET_CPU_DEFAULT 195404b540aSrobert #define TARGET_CPU_DEFAULT 0 196404b540aSrobert #endif 197404b540aSrobert 198404b540aSrobert #ifndef TARGET_DEFAULT_EXPLICIT_RELOCS 199404b540aSrobert #ifdef HAVE_AS_EXPLICIT_RELOCS 200404b540aSrobert #define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS 201404b540aSrobert #define TARGET_SUPPORT_ARCH 1 202404b540aSrobert #else 203404b540aSrobert #define TARGET_DEFAULT_EXPLICIT_RELOCS 0 204404b540aSrobert #endif 205404b540aSrobert #endif 206404b540aSrobert 207404b540aSrobert #ifndef TARGET_SUPPORT_ARCH 208404b540aSrobert #define TARGET_SUPPORT_ARCH 0 209404b540aSrobert #endif 210404b540aSrobert 211404b540aSrobert /* Support for a compile-time default CPU, et cetera. The rules are: 212404b540aSrobert --with-cpu is ignored if -mcpu is specified. 213404b540aSrobert --with-tune is ignored if -mtune is specified. */ 214404b540aSrobert #define OPTION_DEFAULT_SPECS \ 215404b540aSrobert {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 216404b540aSrobert {"tune", "%{!mtune=*:-mtune=%(VALUE)}" } 217404b540aSrobert 218404b540aSrobert /* This macro defines names of additional specifications to put in the 219404b540aSrobert specs that can be used in various specifications like CC1_SPEC. Its 220404b540aSrobert definition is an initializer with a subgrouping for each command option. 221404b540aSrobert 222404b540aSrobert Each subgrouping contains a string constant, that defines the 223404b540aSrobert specification name, and a string constant that used by the GCC driver 224404b540aSrobert program. 225404b540aSrobert 226404b540aSrobert Do not define this macro if it does not need to do anything. */ 227404b540aSrobert 228404b540aSrobert #ifndef SUBTARGET_EXTRA_SPECS 229404b540aSrobert #define SUBTARGET_EXTRA_SPECS 230404b540aSrobert #endif 231404b540aSrobert 232404b540aSrobert #define EXTRA_SPECS \ 233404b540aSrobert { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 234404b540aSrobert SUBTARGET_EXTRA_SPECS 235404b540aSrobert 236404b540aSrobert 237404b540aSrobert /* Sometimes certain combinations of command options do not make sense 238404b540aSrobert on a particular target machine. You can define a macro 239404b540aSrobert `OVERRIDE_OPTIONS' to take account of this. This macro, if 240404b540aSrobert defined, is executed once just after all the command options have 241404b540aSrobert been parsed. 242404b540aSrobert 243404b540aSrobert On the Alpha, it is used to translate target-option strings into 244404b540aSrobert numeric values. */ 245404b540aSrobert 246404b540aSrobert #define OVERRIDE_OPTIONS override_options () 247404b540aSrobert 248404b540aSrobert 249404b540aSrobert /* Define this macro to change register usage conditional on target flags. 250404b540aSrobert 251404b540aSrobert On the Alpha, we use this to disable the floating-point registers when 252404b540aSrobert they don't exist. */ 253404b540aSrobert 254404b540aSrobert #define CONDITIONAL_REGISTER_USAGE \ 255404b540aSrobert { \ 256404b540aSrobert int i; \ 257404b540aSrobert if (! TARGET_FPREGS) \ 258404b540aSrobert for (i = 32; i < 63; i++) \ 259404b540aSrobert fixed_regs[i] = call_used_regs[i] = 1; \ 260404b540aSrobert } 261404b540aSrobert 262404b540aSrobert 263404b540aSrobert /* Show we can debug even without a frame pointer. */ 264404b540aSrobert #define CAN_DEBUG_WITHOUT_FP 265404b540aSrobert 266404b540aSrobert /* target machine storage layout */ 267404b540aSrobert 268404b540aSrobert /* Define the size of `int'. The default is the same as the word size. */ 269404b540aSrobert #define INT_TYPE_SIZE 32 270404b540aSrobert 271404b540aSrobert /* Define the size of `long long'. The default is the twice the word size. */ 272404b540aSrobert #define LONG_LONG_TYPE_SIZE 64 273404b540aSrobert 274404b540aSrobert /* We're IEEE unless someone says to use VAX. */ 275404b540aSrobert #define TARGET_FLOAT_FORMAT \ 276404b540aSrobert (TARGET_FLOAT_VAX ? VAX_FLOAT_FORMAT : IEEE_FLOAT_FORMAT) 277404b540aSrobert 278404b540aSrobert /* The two floating-point formats we support are S-floating, which is 279404b540aSrobert 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double' 280404b540aSrobert and `long double' are T. */ 281404b540aSrobert 282404b540aSrobert #define FLOAT_TYPE_SIZE 32 283404b540aSrobert #define DOUBLE_TYPE_SIZE 64 284404b540aSrobert #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) 285404b540aSrobert 286404b540aSrobert /* Define this to set long double type size to use in libgcc2.c, which can 287404b540aSrobert not depend on target_flags. */ 288404b540aSrobert #ifdef __LONG_DOUBLE_128__ 289404b540aSrobert #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 290404b540aSrobert #else 291404b540aSrobert #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 292404b540aSrobert #endif 293404b540aSrobert 294404b540aSrobert /* Work around target_flags dependency in ada/targtyps.c. */ 295404b540aSrobert #define WIDEST_HARDWARE_FP_SIZE 64 296404b540aSrobert 297404b540aSrobert #define WCHAR_TYPE "unsigned int" 298404b540aSrobert #define WCHAR_TYPE_SIZE 32 299404b540aSrobert 300404b540aSrobert /* Define this macro if it is advisable to hold scalars in registers 301404b540aSrobert in a wider mode than that declared by the program. In such cases, 302404b540aSrobert the value is constrained to be within the bounds of the declared 303404b540aSrobert type, but kept valid in the wider mode. The signedness of the 304404b540aSrobert extension may differ from that of the type. 305404b540aSrobert 306404b540aSrobert For Alpha, we always store objects in a full register. 32-bit integers 307404b540aSrobert are always sign-extended, but smaller objects retain their signedness. 308404b540aSrobert 309404b540aSrobert Note that small vector types can get mapped onto integer modes at the 310404b540aSrobert whim of not appearing in alpha-modes.def. We never promoted these 311404b540aSrobert values before; don't do so now that we've trimmed the set of modes to 312404b540aSrobert those actually implemented in the backend. */ 313404b540aSrobert 314404b540aSrobert #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 315404b540aSrobert if (GET_MODE_CLASS (MODE) == MODE_INT \ 316404b540aSrobert && (TYPE == NULL || TREE_CODE (TYPE) != VECTOR_TYPE) \ 317404b540aSrobert && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 318404b540aSrobert { \ 319404b540aSrobert if ((MODE) == SImode) \ 320404b540aSrobert (UNSIGNEDP) = 0; \ 321404b540aSrobert (MODE) = DImode; \ 322404b540aSrobert } 323404b540aSrobert 324404b540aSrobert /* Define this if most significant bit is lowest numbered 325404b540aSrobert in instructions that operate on numbered bit-fields. 326404b540aSrobert 327404b540aSrobert There are no such instructions on the Alpha, but the documentation 328404b540aSrobert is little endian. */ 329404b540aSrobert #define BITS_BIG_ENDIAN 0 330404b540aSrobert 331404b540aSrobert /* Define this if most significant byte of a word is the lowest numbered. 332404b540aSrobert This is false on the Alpha. */ 333404b540aSrobert #define BYTES_BIG_ENDIAN 0 334404b540aSrobert 335404b540aSrobert /* Define this if most significant word of a multiword number is lowest 336404b540aSrobert numbered. 337404b540aSrobert 338404b540aSrobert For Alpha we can decide arbitrarily since there are no machine instructions 339404b540aSrobert for them. Might as well be consistent with bytes. */ 340404b540aSrobert #define WORDS_BIG_ENDIAN 0 341404b540aSrobert 342404b540aSrobert /* Width of a word, in units (bytes). */ 343404b540aSrobert #define UNITS_PER_WORD 8 344404b540aSrobert 345404b540aSrobert /* Width in bits of a pointer. 346404b540aSrobert See also the macro `Pmode' defined below. */ 347404b540aSrobert #define POINTER_SIZE 64 348404b540aSrobert 349404b540aSrobert /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 350404b540aSrobert #define PARM_BOUNDARY 64 351404b540aSrobert 352404b540aSrobert /* Boundary (in *bits*) on which stack pointer should be aligned. */ 353404b540aSrobert #define STACK_BOUNDARY 128 354404b540aSrobert 355404b540aSrobert /* Allocation boundary (in *bits*) for the code of a function. */ 356404b540aSrobert #define FUNCTION_BOUNDARY 32 357404b540aSrobert 358404b540aSrobert /* Alignment of field after `int : 0' in a structure. */ 359404b540aSrobert #define EMPTY_FIELD_BOUNDARY 64 360404b540aSrobert 361404b540aSrobert /* Every structure's size must be a multiple of this. */ 362404b540aSrobert #define STRUCTURE_SIZE_BOUNDARY 8 363404b540aSrobert 364404b540aSrobert /* A bit-field declared as `int' forces `int' alignment for the struct. */ 365404b540aSrobert #define PCC_BITFIELD_TYPE_MATTERS 1 366404b540aSrobert 367404b540aSrobert /* No data type wants to be aligned rounder than this. */ 368404b540aSrobert #define BIGGEST_ALIGNMENT 128 369404b540aSrobert 370404b540aSrobert /* For atomic access to objects, must have at least 32-bit alignment 371404b540aSrobert unless the machine has byte operations. */ 372404b540aSrobert #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32)) 373404b540aSrobert 374404b540aSrobert /* Align all constants and variables to at least a word boundary so 375404b540aSrobert we can pick up pieces of them faster. */ 376404b540aSrobert #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) 377404b540aSrobert #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) 37824cce745Smiod 37924cce745Smiod /* Make local arrays of chars word-aligned for the same reasons. */ 38024cce745Smiod #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) 381404b540aSrobert 382404b540aSrobert /* Set this nonzero if move instructions will actually fail to work 383404b540aSrobert when given unaligned data. 384404b540aSrobert 385404b540aSrobert Since we get an error message when we do one, call them invalid. */ 386404b540aSrobert 387404b540aSrobert #define STRICT_ALIGNMENT 1 388404b540aSrobert 389404b540aSrobert /* Set this nonzero if unaligned move instructions are extremely slow. 390404b540aSrobert 391404b540aSrobert On the Alpha, they trap. */ 392404b540aSrobert 393404b540aSrobert #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 394404b540aSrobert 395404b540aSrobert /* Standard register usage. */ 396404b540aSrobert 397404b540aSrobert /* Number of actual hardware registers. 398404b540aSrobert The hardware registers are assigned numbers for the compiler 399404b540aSrobert from 0 to just below FIRST_PSEUDO_REGISTER. 400404b540aSrobert All registers that the compiler knows about must be given numbers, 401404b540aSrobert even those that are not normally considered general registers. 402404b540aSrobert 403404b540aSrobert We define all 32 integer registers, even though $31 is always zero, 404404b540aSrobert and all 32 floating-point registers, even though $f31 is also 405404b540aSrobert always zero. We do not bother defining the FP status register and 406404b540aSrobert there are no other registers. 407404b540aSrobert 408404b540aSrobert Since $31 is always zero, we will use register number 31 as the 409404b540aSrobert argument pointer. It will never appear in the generated code 410404b540aSrobert because we will always be eliminating it in favor of the stack 411404b540aSrobert pointer or hardware frame pointer. 412404b540aSrobert 413404b540aSrobert Likewise, we use $f31 for the frame pointer, which will always 414404b540aSrobert be eliminated in favor of the hardware frame pointer or the 415404b540aSrobert stack pointer. */ 416404b540aSrobert 417404b540aSrobert #define FIRST_PSEUDO_REGISTER 64 418404b540aSrobert 419404b540aSrobert /* 1 for registers that have pervasive standard uses 420404b540aSrobert and are not available for the register allocator. */ 421404b540aSrobert 422404b540aSrobert #define FIXED_REGISTERS \ 423404b540aSrobert {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 424404b540aSrobert 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ 425404b540aSrobert 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 426404b540aSrobert 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 } 427404b540aSrobert 428404b540aSrobert /* 1 for registers not available across function calls. 429404b540aSrobert These must include the FIXED_REGISTERS and also any 430404b540aSrobert registers that can be used without being saved. 431404b540aSrobert The latter must include the registers where values are returned 432404b540aSrobert and the register where structure-value addresses are passed. 433404b540aSrobert Aside from that, you can include as many other registers as you like. */ 434404b540aSrobert #define CALL_USED_REGISTERS \ 435404b540aSrobert {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ 436404b540aSrobert 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \ 437404b540aSrobert 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ 438404b540aSrobert 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } 439404b540aSrobert 440404b540aSrobert /* List the order in which to allocate registers. Each register must be 441404b540aSrobert listed once, even those in FIXED_REGISTERS. */ 442404b540aSrobert 443404b540aSrobert #define REG_ALLOC_ORDER { \ 444404b540aSrobert 1, 2, 3, 4, 5, 6, 7, 8, /* nonsaved integer registers */ \ 445404b540aSrobert 22, 23, 24, 25, 28, /* likewise */ \ 446404b540aSrobert 0, /* likewise, but return value */ \ 447404b540aSrobert 21, 20, 19, 18, 17, 16, /* likewise, but input args */ \ 448404b540aSrobert 27, /* likewise, but OSF procedure value */ \ 449404b540aSrobert \ 450404b540aSrobert 42, 43, 44, 45, 46, 47, /* nonsaved floating-point registers */ \ 451404b540aSrobert 54, 55, 56, 57, 58, 59, /* likewise */ \ 452404b540aSrobert 60, 61, 62, /* likewise */ \ 453404b540aSrobert 32, 33, /* likewise, but return values */ \ 454404b540aSrobert 53, 52, 51, 50, 49, 48, /* likewise, but input args */ \ 455404b540aSrobert \ 456404b540aSrobert 9, 10, 11, 12, 13, 14, /* saved integer registers */ \ 457404b540aSrobert 26, /* return address */ \ 458404b540aSrobert 15, /* hard frame pointer */ \ 459404b540aSrobert \ 460404b540aSrobert 34, 35, 36, 37, 38, 39, /* saved floating-point registers */ \ 461404b540aSrobert 40, 41, /* likewise */ \ 462404b540aSrobert \ 463404b540aSrobert 29, 30, 31, 63 /* gp, sp, ap, sfp */ \ 464404b540aSrobert } 465404b540aSrobert 466404b540aSrobert /* Return number of consecutive hard regs needed starting at reg REGNO 467404b540aSrobert to hold something of mode MODE. 468404b540aSrobert This is ordinarily the length in words of a value of mode MODE 469404b540aSrobert but can be less for certain modes in special long registers. */ 470404b540aSrobert 471404b540aSrobert #define HARD_REGNO_NREGS(REGNO, MODE) \ 472404b540aSrobert ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 473404b540aSrobert 474404b540aSrobert /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 475404b540aSrobert On Alpha, the integer registers can hold any mode. The floating-point 476404b540aSrobert registers can hold 64-bit integers as well, but not smaller values. */ 477404b540aSrobert 478404b540aSrobert #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 479404b540aSrobert ((REGNO) >= 32 && (REGNO) <= 62 \ 480404b540aSrobert ? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode \ 481404b540aSrobert || (MODE) == SCmode || (MODE) == DCmode \ 482404b540aSrobert : 1) 483404b540aSrobert 484404b540aSrobert /* A C expression that is nonzero if a value of mode 485404b540aSrobert MODE1 is accessible in mode MODE2 without copying. 486404b540aSrobert 487404b540aSrobert This asymmetric test is true when MODE1 could be put 488404b540aSrobert in an FP register but MODE2 could not. */ 489404b540aSrobert 490404b540aSrobert #define MODES_TIEABLE_P(MODE1, MODE2) \ 491404b540aSrobert (HARD_REGNO_MODE_OK (32, (MODE1)) \ 492404b540aSrobert ? HARD_REGNO_MODE_OK (32, (MODE2)) \ 493404b540aSrobert : 1) 494404b540aSrobert 495404b540aSrobert /* Specify the registers used for certain standard purposes. 496404b540aSrobert The values of these macros are register numbers. */ 497404b540aSrobert 498404b540aSrobert /* Alpha pc isn't overloaded on a register that the compiler knows about. */ 499404b540aSrobert /* #define PC_REGNUM */ 500404b540aSrobert 501404b540aSrobert /* Register to use for pushing function arguments. */ 502404b540aSrobert #define STACK_POINTER_REGNUM 30 503404b540aSrobert 504404b540aSrobert /* Base register for access to local variables of the function. */ 505404b540aSrobert #define HARD_FRAME_POINTER_REGNUM 15 506404b540aSrobert 507404b540aSrobert /* Value should be nonzero if functions must have frame pointers. 508404b540aSrobert Zero means the frame pointer need not be set up (and parms 509404b540aSrobert may be accessed via the stack pointer) in functions that seem suitable. 510404b540aSrobert This is computed in `reload', in reload1.c. */ 511404b540aSrobert #define FRAME_POINTER_REQUIRED 0 512404b540aSrobert 513404b540aSrobert /* Base register for access to arguments of the function. */ 514404b540aSrobert #define ARG_POINTER_REGNUM 31 515404b540aSrobert 516404b540aSrobert /* Base register for access to local variables of function. */ 517404b540aSrobert #define FRAME_POINTER_REGNUM 63 518404b540aSrobert 519404b540aSrobert /* Register in which static-chain is passed to a function. 520404b540aSrobert 521404b540aSrobert For the Alpha, this is based on an example; the calling sequence 522404b540aSrobert doesn't seem to specify this. */ 523404b540aSrobert #define STATIC_CHAIN_REGNUM 1 524404b540aSrobert 525404b540aSrobert /* The register number of the register used to address a table of 526404b540aSrobert static data addresses in memory. */ 527404b540aSrobert #define PIC_OFFSET_TABLE_REGNUM 29 528404b540aSrobert 529404b540aSrobert /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' 530404b540aSrobert is clobbered by calls. */ 531404b540aSrobert /* ??? It is and it isn't. It's required to be valid for a given 532404b540aSrobert function when the function returns. It isn't clobbered by 533404b540aSrobert current_file functions. Moreover, we do not expose the ldgp 534404b540aSrobert until after reload, so we're probably safe. */ 535404b540aSrobert /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 536404b540aSrobert 537404b540aSrobert /* Define the classes of registers for register constraints in the 538404b540aSrobert machine description. Also define ranges of constants. 539404b540aSrobert 540404b540aSrobert One of the classes must always be named ALL_REGS and include all hard regs. 541404b540aSrobert If there is more than one class, another class must be named NO_REGS 542404b540aSrobert and contain no registers. 543404b540aSrobert 544404b540aSrobert The name GENERAL_REGS must be the name of a class (or an alias for 545404b540aSrobert another name such as ALL_REGS). This is the class of registers 546404b540aSrobert that is allowed by "g" or "r" in a register constraint. 547404b540aSrobert Also, registers outside this class are allocated only when 548404b540aSrobert instructions express preferences for them. 549404b540aSrobert 550404b540aSrobert The classes must be numbered in nondecreasing order; that is, 551404b540aSrobert a larger-numbered class must never be contained completely 552404b540aSrobert in a smaller-numbered class. 553404b540aSrobert 554404b540aSrobert For any two classes, it is very desirable that there be another 555404b540aSrobert class that represents their union. */ 556404b540aSrobert 557404b540aSrobert enum reg_class { 558404b540aSrobert NO_REGS, R0_REG, R24_REG, R25_REG, R27_REG, 559404b540aSrobert GENERAL_REGS, FLOAT_REGS, ALL_REGS, 560404b540aSrobert LIM_REG_CLASSES 561404b540aSrobert }; 562404b540aSrobert 563404b540aSrobert #define N_REG_CLASSES (int) LIM_REG_CLASSES 564404b540aSrobert 565404b540aSrobert /* Give names of register classes as strings for dump file. */ 566404b540aSrobert 567404b540aSrobert #define REG_CLASS_NAMES \ 568404b540aSrobert {"NO_REGS", "R0_REG", "R24_REG", "R25_REG", "R27_REG", \ 569404b540aSrobert "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } 570404b540aSrobert 571404b540aSrobert /* Define which registers fit in which classes. 572404b540aSrobert This is an initializer for a vector of HARD_REG_SET 573404b540aSrobert of length N_REG_CLASSES. */ 574404b540aSrobert 575404b540aSrobert #define REG_CLASS_CONTENTS \ 576404b540aSrobert { {0x00000000, 0x00000000}, /* NO_REGS */ \ 577404b540aSrobert {0x00000001, 0x00000000}, /* R0_REG */ \ 578404b540aSrobert {0x01000000, 0x00000000}, /* R24_REG */ \ 579404b540aSrobert {0x02000000, 0x00000000}, /* R25_REG */ \ 580404b540aSrobert {0x08000000, 0x00000000}, /* R27_REG */ \ 581404b540aSrobert {0xffffffff, 0x80000000}, /* GENERAL_REGS */ \ 582404b540aSrobert {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \ 583404b540aSrobert {0xffffffff, 0xffffffff} } 584404b540aSrobert 585404b540aSrobert /* The same information, inverted: 586404b540aSrobert Return the class number of the smallest class containing 587404b540aSrobert reg number REGNO. This could be a conditional expression 588404b540aSrobert or could index an array. */ 589404b540aSrobert 590404b540aSrobert #define REGNO_REG_CLASS(REGNO) \ 591404b540aSrobert ((REGNO) == 0 ? R0_REG \ 592404b540aSrobert : (REGNO) == 24 ? R24_REG \ 593404b540aSrobert : (REGNO) == 25 ? R25_REG \ 594404b540aSrobert : (REGNO) == 27 ? R27_REG \ 595404b540aSrobert : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \ 596404b540aSrobert : GENERAL_REGS) 597404b540aSrobert 598404b540aSrobert /* The class value for index registers, and the one for base regs. */ 599404b540aSrobert #define INDEX_REG_CLASS NO_REGS 600404b540aSrobert #define BASE_REG_CLASS GENERAL_REGS 601404b540aSrobert 602404b540aSrobert /* Get reg_class from a letter such as appears in the machine description. */ 603404b540aSrobert 604404b540aSrobert #define REG_CLASS_FROM_LETTER(C) \ 605404b540aSrobert ((C) == 'a' ? R24_REG \ 606404b540aSrobert : (C) == 'b' ? R25_REG \ 607404b540aSrobert : (C) == 'c' ? R27_REG \ 608404b540aSrobert : (C) == 'f' ? FLOAT_REGS \ 609404b540aSrobert : (C) == 'v' ? R0_REG \ 610404b540aSrobert : NO_REGS) 611404b540aSrobert 612404b540aSrobert /* Define this macro to change register usage conditional on target flags. */ 613404b540aSrobert /* #define CONDITIONAL_REGISTER_USAGE */ 614404b540aSrobert 615404b540aSrobert /* The letters I, J, K, L, M, N, O, and P in a register constraint string 616404b540aSrobert can be used to stand for particular ranges of immediate operands. 617404b540aSrobert This macro defines what the ranges are. 618404b540aSrobert C is the letter, and VALUE is a constant value. 619404b540aSrobert Return 1 if VALUE is in the range specified by C. 620404b540aSrobert 621404b540aSrobert For Alpha: 622404b540aSrobert `I' is used for the range of constants most insns can contain. 623404b540aSrobert `J' is the constant zero. 624404b540aSrobert `K' is used for the constant in an LDA insn. 625404b540aSrobert `L' is used for the constant in a LDAH insn. 626404b540aSrobert `M' is used for the constants that can be AND'ed with using a ZAP insn. 627404b540aSrobert `N' is used for complemented 8-bit constants. 628404b540aSrobert `O' is used for negated 8-bit constants. 629404b540aSrobert `P' is used for the constants 1, 2 and 3. */ 630404b540aSrobert 631404b540aSrobert #define CONST_OK_FOR_LETTER_P alpha_const_ok_for_letter_p 632404b540aSrobert 633404b540aSrobert /* Similar, but for floating or large integer constants, and defining letters 634404b540aSrobert G and H. Here VALUE is the CONST_DOUBLE rtx itself. 635404b540aSrobert 636404b540aSrobert For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE 637404b540aSrobert that is the operand of a ZAP insn. */ 638404b540aSrobert 639404b540aSrobert #define CONST_DOUBLE_OK_FOR_LETTER_P alpha_const_double_ok_for_letter_p 640404b540aSrobert 641404b540aSrobert /* Optional extra constraints for this machine. 642404b540aSrobert 643404b540aSrobert For the Alpha, `Q' means that this is a memory operand but not a 644404b540aSrobert reference to an unaligned location. 645404b540aSrobert 646404b540aSrobert `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current 647404b540aSrobert function. 648404b540aSrobert 649404b540aSrobert 'S' is a 6-bit constant (valid for a shift insn). 650404b540aSrobert 651404b540aSrobert 'T' is a HIGH. 652404b540aSrobert 653404b540aSrobert 'U' is a symbolic operand. 654404b540aSrobert 655404b540aSrobert 'W' is a vector zero. */ 656404b540aSrobert 657404b540aSrobert #define EXTRA_CONSTRAINT alpha_extra_constraint 658404b540aSrobert 659404b540aSrobert /* Given an rtx X being reloaded into a reg required to be 660404b540aSrobert in class CLASS, return the class of reg to actually use. 661404b540aSrobert In general this is just CLASS; but on some machines 662404b540aSrobert in some cases it is preferable to use a more restrictive class. */ 663404b540aSrobert 664404b540aSrobert #define PREFERRED_RELOAD_CLASS alpha_preferred_reload_class 665404b540aSrobert 666404b540aSrobert /* Loading and storing HImode or QImode values to and from memory 667404b540aSrobert usually requires a scratch register. The exceptions are loading 668404b540aSrobert QImode and HImode from an aligned address to a general register 669404b540aSrobert unless byte instructions are permitted. 670404b540aSrobert We also cannot load an unaligned address or a paradoxical SUBREG into an 671404b540aSrobert FP register. */ 672404b540aSrobert 673404b540aSrobert #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ 674404b540aSrobert alpha_secondary_reload_class((CLASS), (MODE), (IN), 1) 675404b540aSrobert 676404b540aSrobert #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \ 677404b540aSrobert alpha_secondary_reload_class((CLASS), (MODE), (OUT), 0) 678404b540aSrobert 679404b540aSrobert /* If we are copying between general and FP registers, we need a memory 680404b540aSrobert location unless the FIX extension is available. */ 681404b540aSrobert 682404b540aSrobert #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 683404b540aSrobert (! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \ 684404b540aSrobert || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS))) 685404b540aSrobert 686404b540aSrobert /* Specify the mode to be used for memory when a secondary memory 687404b540aSrobert location is needed. If MODE is floating-point, use it. Otherwise, 688404b540aSrobert widen to a word like the default. This is needed because we always 689404b540aSrobert store integers in FP registers in quadword format. This whole 690404b540aSrobert area is very tricky! */ 691404b540aSrobert #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 692404b540aSrobert (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \ 693404b540aSrobert : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \ 694404b540aSrobert : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0)) 695404b540aSrobert 696404b540aSrobert /* Return the maximum number of consecutive registers 697404b540aSrobert needed to represent mode MODE in a register of class CLASS. */ 698404b540aSrobert 699404b540aSrobert #define CLASS_MAX_NREGS(CLASS, MODE) \ 700404b540aSrobert ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 701404b540aSrobert 702404b540aSrobert /* Return the class of registers that cannot change mode from FROM to TO. */ 703404b540aSrobert 704404b540aSrobert #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 705404b540aSrobert (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 706404b540aSrobert ? reg_classes_intersect_p (FLOAT_REGS, CLASS) : 0) 707404b540aSrobert 708404b540aSrobert /* Define the cost of moving between registers of various classes. Moving 709404b540aSrobert between FLOAT_REGS and anything else except float regs is expensive. 710404b540aSrobert In fact, we make it quite expensive because we really don't want to 711404b540aSrobert do these moves unless it is clearly worth it. Optimizations may 712404b540aSrobert reduce the impact of not being able to allocate a pseudo to a 713404b540aSrobert hard register. */ 714404b540aSrobert 715404b540aSrobert #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 716404b540aSrobert (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) ? 2 \ 717404b540aSrobert : TARGET_FIX ? ((CLASS1) == FLOAT_REGS ? 6 : 8) \ 718404b540aSrobert : 4+2*alpha_memory_latency) 719404b540aSrobert 720404b540aSrobert /* A C expressions returning the cost of moving data of MODE from a register to 721404b540aSrobert or from memory. 722404b540aSrobert 723404b540aSrobert On the Alpha, bump this up a bit. */ 724404b540aSrobert 725404b540aSrobert extern int alpha_memory_latency; 726404b540aSrobert #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency) 727404b540aSrobert 728404b540aSrobert /* Provide the cost of a branch. Exact meaning under development. */ 729404b540aSrobert #define BRANCH_COST 5 730404b540aSrobert 731404b540aSrobert /* Stack layout; function entry, exit and calling. */ 732404b540aSrobert 733404b540aSrobert /* Define this if pushing a word on the stack 734404b540aSrobert makes the stack pointer a smaller address. */ 735404b540aSrobert #define STACK_GROWS_DOWNWARD 736404b540aSrobert 737404b540aSrobert /* Define this to nonzero if the nominal address of the stack frame 738404b540aSrobert is at the high-address end of the local variables; 739404b540aSrobert that is, each additional local variable allocated 740404b540aSrobert goes at a more negative offset in the frame. */ 741*a38e851fSmartynas #define FRAME_GROWS_DOWNWARD 1 742404b540aSrobert 743404b540aSrobert /* Offset within stack frame to start allocating local variables at. 744404b540aSrobert If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 745404b540aSrobert first local allocated. Otherwise, it is the offset to the BEGINNING 746404b540aSrobert of the first local allocated. */ 747404b540aSrobert 748404b540aSrobert #define STARTING_FRAME_OFFSET 0 749404b540aSrobert 750404b540aSrobert /* If we generate an insn to push BYTES bytes, 751404b540aSrobert this says how many the stack pointer really advances by. 752404b540aSrobert On Alpha, don't define this because there are no push insns. */ 753404b540aSrobert /* #define PUSH_ROUNDING(BYTES) */ 754404b540aSrobert 755404b540aSrobert /* Define this to be nonzero if stack checking is built into the ABI. */ 756404b540aSrobert #define STACK_CHECK_BUILTIN 1 757404b540aSrobert 758404b540aSrobert /* Define this if the maximum size of all the outgoing args is to be 759404b540aSrobert accumulated and pushed during the prologue. The amount can be 760404b540aSrobert found in the variable current_function_outgoing_args_size. */ 761404b540aSrobert #define ACCUMULATE_OUTGOING_ARGS 1 762404b540aSrobert 763404b540aSrobert /* Offset of first parameter from the argument pointer register value. */ 764404b540aSrobert 765404b540aSrobert #define FIRST_PARM_OFFSET(FNDECL) 0 766404b540aSrobert 767404b540aSrobert /* Definitions for register eliminations. 768404b540aSrobert 769404b540aSrobert We have two registers that can be eliminated on the Alpha. First, the 770404b540aSrobert frame pointer register can often be eliminated in favor of the stack 771404b540aSrobert pointer register. Secondly, the argument pointer register can always be 772404b540aSrobert eliminated; it is replaced with either the stack or frame pointer. */ 773404b540aSrobert 774404b540aSrobert /* This is an array of structures. Each structure initializes one pair 775404b540aSrobert of eliminable registers. The "from" register number is given first, 776404b540aSrobert followed by "to". Eliminations of the same "from" register are listed 777404b540aSrobert in order of preference. */ 778404b540aSrobert 779404b540aSrobert #define ELIMINABLE_REGS \ 780404b540aSrobert {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 781404b540aSrobert { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 782404b540aSrobert { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 783404b540aSrobert { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 784404b540aSrobert 785404b540aSrobert /* Given FROM and TO register numbers, say whether this elimination is allowed. 786404b540aSrobert Frame pointer elimination is automatically handled. 787404b540aSrobert 788404b540aSrobert All eliminations are valid since the cases where FP can't be 789404b540aSrobert eliminated are already handled. */ 790404b540aSrobert 791404b540aSrobert #define CAN_ELIMINATE(FROM, TO) 1 792404b540aSrobert 793404b540aSrobert /* Round up to a multiple of 16 bytes. */ 794404b540aSrobert #define ALPHA_ROUND(X) (((X) + 15) & ~ 15) 795404b540aSrobert 796404b540aSrobert /* Define the offset between two registers, one to be eliminated, and the other 797404b540aSrobert its replacement, at the start of a routine. */ 798404b540aSrobert #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 799404b540aSrobert ((OFFSET) = alpha_initial_elimination_offset(FROM, TO)) 800404b540aSrobert 801404b540aSrobert /* Define this if stack space is still allocated for a parameter passed 802404b540aSrobert in a register. */ 803404b540aSrobert /* #define REG_PARM_STACK_SPACE */ 804404b540aSrobert 805404b540aSrobert /* Value is the number of bytes of arguments automatically 806404b540aSrobert popped when returning from a subroutine call. 807404b540aSrobert FUNDECL is the declaration node of the function (as a tree), 808404b540aSrobert FUNTYPE is the data type of the function (as a tree), 809404b540aSrobert or for a library call it is an identifier node for the subroutine name. 810404b540aSrobert SIZE is the number of bytes of arguments passed on the stack. */ 811404b540aSrobert 812404b540aSrobert #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 813404b540aSrobert 814404b540aSrobert /* Define how to find the value returned by a function. 815404b540aSrobert VALTYPE is the data type of the value (as a tree). 816404b540aSrobert If the precise function being called is known, FUNC is its FUNCTION_DECL; 817404b540aSrobert otherwise, FUNC is 0. 818404b540aSrobert 819404b540aSrobert On Alpha the value is found in $0 for integer functions and 820404b540aSrobert $f0 for floating-point functions. */ 821404b540aSrobert 822404b540aSrobert #define FUNCTION_VALUE(VALTYPE, FUNC) \ 823404b540aSrobert function_value (VALTYPE, FUNC, VOIDmode) 824404b540aSrobert 825404b540aSrobert /* Define how to find the value returned by a library function 826404b540aSrobert assuming the value has mode MODE. */ 827404b540aSrobert 828404b540aSrobert #define LIBCALL_VALUE(MODE) \ 829404b540aSrobert function_value (NULL, NULL, MODE) 830404b540aSrobert 831404b540aSrobert /* 1 if N is a possible register number for a function value 832404b540aSrobert as seen by the caller. */ 833404b540aSrobert 834404b540aSrobert #define FUNCTION_VALUE_REGNO_P(N) \ 835404b540aSrobert ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33) 836404b540aSrobert 837404b540aSrobert /* 1 if N is a possible register number for function argument passing. 838404b540aSrobert On Alpha, these are $16-$21 and $f16-$f21. */ 839404b540aSrobert 840404b540aSrobert #define FUNCTION_ARG_REGNO_P(N) \ 841404b540aSrobert (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32)) 842404b540aSrobert 843404b540aSrobert /* Define a data type for recording info about an argument list 844404b540aSrobert during the scan of that argument list. This data type should 845404b540aSrobert hold all necessary information about the function itself 846404b540aSrobert and about the args processed so far, enough to enable macros 847404b540aSrobert such as FUNCTION_ARG to determine where the next arg should go. 848404b540aSrobert 849404b540aSrobert On Alpha, this is a single integer, which is a number of words 850404b540aSrobert of arguments scanned so far. 851404b540aSrobert Thus 6 or more means all following args should go on the stack. */ 852404b540aSrobert 853404b540aSrobert #define CUMULATIVE_ARGS int 854404b540aSrobert 855404b540aSrobert /* Initialize a variable CUM of type CUMULATIVE_ARGS 856404b540aSrobert for a call to a function whose data type is FNTYPE. 857404b540aSrobert For a library call, FNTYPE is 0. */ 858404b540aSrobert 859404b540aSrobert #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 860404b540aSrobert (CUM) = 0 861404b540aSrobert 862404b540aSrobert /* Define intermediate macro to compute the size (in registers) of an argument 863404b540aSrobert for the Alpha. */ 864404b540aSrobert 865404b540aSrobert #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \ 866404b540aSrobert ((MODE) == TFmode || (MODE) == TCmode ? 1 \ 867404b540aSrobert : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ 868404b540aSrobert + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 869404b540aSrobert 870404b540aSrobert /* Update the data in CUM to advance over an argument 871404b540aSrobert of mode MODE and data type TYPE. 872404b540aSrobert (TYPE is null for libcalls where that information may not be available.) */ 873404b540aSrobert 874404b540aSrobert #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 875404b540aSrobert ((CUM) += \ 876404b540aSrobert (targetm.calls.must_pass_in_stack (MODE, TYPE)) \ 877404b540aSrobert ? 6 : ALPHA_ARG_SIZE (MODE, TYPE, NAMED)) 878404b540aSrobert 879404b540aSrobert /* Determine where to put an argument to a function. 880404b540aSrobert Value is zero to push the argument on the stack, 881404b540aSrobert or a hard register in which to store the argument. 882404b540aSrobert 883404b540aSrobert MODE is the argument's machine mode. 884404b540aSrobert TYPE is the data type of the argument (as a tree). 885404b540aSrobert This is null for libcalls where that information may 886404b540aSrobert not be available. 887404b540aSrobert CUM is a variable of type CUMULATIVE_ARGS which gives info about 888404b540aSrobert the preceding args and about the function being called. 889404b540aSrobert NAMED is nonzero if this argument is a named parameter 890404b540aSrobert (otherwise it is an extra parameter matching an ellipsis). 891404b540aSrobert 892404b540aSrobert On Alpha the first 6 words of args are normally in registers 893404b540aSrobert and the rest are pushed. */ 894404b540aSrobert 895404b540aSrobert #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 896404b540aSrobert function_arg((CUM), (MODE), (TYPE), (NAMED)) 897404b540aSrobert 898404b540aSrobert /* Try to output insns to set TARGET equal to the constant C if it can be 899404b540aSrobert done in less than N insns. Do all computations in MODE. Returns the place 900404b540aSrobert where the output has been placed if it can be done and the insns have been 901404b540aSrobert emitted. If it would take more than N insns, zero is returned and no 902404b540aSrobert insns and emitted. */ 903404b540aSrobert 904404b540aSrobert /* Define the information needed to generate branch and scc insns. This is 905404b540aSrobert stored from the compare operation. Note that we can't use "rtx" here 906404b540aSrobert since it hasn't been defined! */ 907404b540aSrobert 908404b540aSrobert struct alpha_compare 909404b540aSrobert { 910404b540aSrobert struct rtx_def *op0, *op1; 911404b540aSrobert int fp_p; 912404b540aSrobert }; 913404b540aSrobert 914404b540aSrobert extern struct alpha_compare alpha_compare; 915404b540aSrobert 916404b540aSrobert /* Make (or fake) .linkage entry for function call. 917404b540aSrobert IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */ 918404b540aSrobert 919404b540aSrobert /* This macro defines the start of an assembly comment. */ 920404b540aSrobert 921404b540aSrobert #define ASM_COMMENT_START " #" 922404b540aSrobert 923404b540aSrobert /* This macro produces the initial definition of a function. */ 924404b540aSrobert 925404b540aSrobert #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 926404b540aSrobert alpha_start_function(FILE,NAME,DECL); 927404b540aSrobert 928404b540aSrobert /* This macro closes up a function definition for the assembler. */ 929404b540aSrobert 930404b540aSrobert #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \ 931404b540aSrobert alpha_end_function(FILE,NAME,DECL) 932404b540aSrobert 933404b540aSrobert /* Output any profiling code before the prologue. */ 934404b540aSrobert 935404b540aSrobert #define PROFILE_BEFORE_PROLOGUE 1 936404b540aSrobert 937404b540aSrobert /* Never use profile counters. */ 938404b540aSrobert 939404b540aSrobert #define NO_PROFILE_COUNTERS 1 940404b540aSrobert 941404b540aSrobert /* Output assembler code to FILE to increment profiler label # LABELNO 942404b540aSrobert for profiling a function entry. Under OSF/1, profiling is enabled 943404b540aSrobert by simply passing -pg to the assembler and linker. */ 944404b540aSrobert 945404b540aSrobert #define FUNCTION_PROFILER(FILE, LABELNO) 946404b540aSrobert 947404b540aSrobert /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 948404b540aSrobert the stack pointer does not matter. The value is tested only in 949404b540aSrobert functions that have frame pointers. 950404b540aSrobert No definition is equivalent to always zero. */ 951404b540aSrobert 952404b540aSrobert #define EXIT_IGNORE_STACK 1 953404b540aSrobert 954404b540aSrobert /* Define registers used by the epilogue and return instruction. */ 955404b540aSrobert 956404b540aSrobert #define EPILOGUE_USES(REGNO) ((REGNO) == 26) 957404b540aSrobert 958404b540aSrobert /* Output assembler code for a block containing the constant parts 959404b540aSrobert of a trampoline, leaving space for the variable parts. 960404b540aSrobert 961404b540aSrobert The trampoline should set the static chain pointer to value placed 962404b540aSrobert into the trampoline and should branch to the specified routine. 963404b540aSrobert Note that $27 has been set to the address of the trampoline, so we can 964404b540aSrobert use it for addressability of the two data items. */ 965404b540aSrobert 966404b540aSrobert #define TRAMPOLINE_TEMPLATE(FILE) \ 967404b540aSrobert do { \ 968404b540aSrobert fprintf (FILE, "\tldq $1,24($27)\n"); \ 969404b540aSrobert fprintf (FILE, "\tldq $27,16($27)\n"); \ 970404b540aSrobert fprintf (FILE, "\tjmp $31,($27),0\n"); \ 971404b540aSrobert fprintf (FILE, "\tnop\n"); \ 972404b540aSrobert fprintf (FILE, "\t.quad 0,0\n"); \ 973404b540aSrobert } while (0) 974404b540aSrobert 975404b540aSrobert /* Section in which to place the trampoline. On Alpha, instructions 976404b540aSrobert may only be placed in a text segment. */ 977404b540aSrobert 978404b540aSrobert #define TRAMPOLINE_SECTION text_section 979404b540aSrobert 980404b540aSrobert /* Length in units of the trampoline for entering a nested function. */ 981404b540aSrobert 982404b540aSrobert #define TRAMPOLINE_SIZE 32 983404b540aSrobert 984404b540aSrobert /* The alignment of a trampoline, in bits. */ 985404b540aSrobert 986404b540aSrobert #define TRAMPOLINE_ALIGNMENT 64 987404b540aSrobert 988404b540aSrobert /* Emit RTL insns to initialize the variable parts of a trampoline. 989404b540aSrobert FNADDR is an RTX for the address of the function's pure code. 990404b540aSrobert CXT is an RTX for the static chain value for the function. */ 991404b540aSrobert 992404b540aSrobert #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 993404b540aSrobert alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8) 994404b540aSrobert 995404b540aSrobert /* A C expression whose value is RTL representing the value of the return 996404b540aSrobert address for the frame COUNT steps up from the current frame. 997404b540aSrobert FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of 998404b540aSrobert the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */ 999404b540aSrobert 1000404b540aSrobert #define RETURN_ADDR_RTX alpha_return_addr 1001404b540aSrobert 1002404b540aSrobert /* Before the prologue, RA lives in $26. */ 1003404b540aSrobert #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26) 1004404b540aSrobert #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26) 1005404b540aSrobert #define DWARF_ALT_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (64) 1006404b540aSrobert #define DWARF_ZERO_REG 31 1007404b540aSrobert 1008404b540aSrobert /* Describe how we implement __builtin_eh_return. */ 1009404b540aSrobert #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM) 1010404b540aSrobert #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28) 1011404b540aSrobert #define EH_RETURN_HANDLER_RTX \ 1012404b540aSrobert gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \ 1013404b540aSrobert current_function_outgoing_args_size)) 1014404b540aSrobert 1015404b540aSrobert /* Addressing modes, and classification of registers for them. */ 1016404b540aSrobert 1017404b540aSrobert /* Macros to check register numbers against specific register classes. */ 1018404b540aSrobert 1019404b540aSrobert /* These assume that REGNO is a hard or pseudo reg number. 1020404b540aSrobert They give nonzero only if REGNO is a hard reg of the suitable class 1021404b540aSrobert or a pseudo reg currently allocated to a suitable hard reg. 1022404b540aSrobert Since they use reg_renumber, they are safe only once reg_renumber 1023404b540aSrobert has been allocated, which happens in local-alloc.c. */ 1024404b540aSrobert 1025404b540aSrobert #define REGNO_OK_FOR_INDEX_P(REGNO) 0 1026404b540aSrobert #define REGNO_OK_FOR_BASE_P(REGNO) \ 1027404b540aSrobert ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \ 1028404b540aSrobert || (REGNO) == 63 || reg_renumber[REGNO] == 63) 1029404b540aSrobert 1030404b540aSrobert /* Maximum number of registers that can appear in a valid memory address. */ 1031404b540aSrobert #define MAX_REGS_PER_ADDRESS 1 1032404b540aSrobert 1033404b540aSrobert /* Recognize any constant value that is a valid address. For the Alpha, 1034404b540aSrobert there are only constants none since we want to use LDA to load any 1035404b540aSrobert symbolic addresses into registers. */ 1036404b540aSrobert 1037404b540aSrobert #define CONSTANT_ADDRESS_P(X) \ 1038404b540aSrobert (GET_CODE (X) == CONST_INT \ 1039404b540aSrobert && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) 1040404b540aSrobert 1041404b540aSrobert /* Include all constant integers and constant doubles, but not 1042404b540aSrobert floating-point, except for floating-point zero. */ 1043404b540aSrobert 1044404b540aSrobert #define LEGITIMATE_CONSTANT_P alpha_legitimate_constant_p 1045404b540aSrobert 1046404b540aSrobert /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1047404b540aSrobert and check its validity for a certain class. 1048404b540aSrobert We have two alternate definitions for each of them. 1049404b540aSrobert The usual definition accepts all pseudo regs; the other rejects 1050404b540aSrobert them unless they have been allocated suitable hard regs. 1051404b540aSrobert The symbol REG_OK_STRICT causes the latter definition to be used. 1052404b540aSrobert 1053404b540aSrobert Most source files want to accept pseudo regs in the hope that 1054404b540aSrobert they will get allocated to the class that the insn wants them to be in. 1055404b540aSrobert Source files for reload pass need to be strict. 1056404b540aSrobert After reload, it makes no difference, since pseudo regs have 1057404b540aSrobert been eliminated by then. */ 1058404b540aSrobert 1059404b540aSrobert /* Nonzero if X is a hard reg that can be used as an index 1060404b540aSrobert or if it is a pseudo reg. */ 1061404b540aSrobert #define REG_OK_FOR_INDEX_P(X) 0 1062404b540aSrobert 1063404b540aSrobert /* Nonzero if X is a hard reg that can be used as a base reg 1064404b540aSrobert or if it is a pseudo reg. */ 1065404b540aSrobert #define NONSTRICT_REG_OK_FOR_BASE_P(X) \ 1066404b540aSrobert (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1067404b540aSrobert 1068404b540aSrobert /* ??? Nonzero if X is the frame pointer, or some virtual register 1069404b540aSrobert that may eliminate to the frame pointer. These will be allowed to 1070404b540aSrobert have offsets greater than 32K. This is done because register 1071404b540aSrobert elimination offsets will change the hi/lo split, and if we split 1072404b540aSrobert before reload, we will require additional instructions. */ 1073404b540aSrobert #define NONSTRICT_REG_OK_FP_BASE_P(X) \ 1074404b540aSrobert (REGNO (X) == 31 || REGNO (X) == 63 \ 1075404b540aSrobert || (REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1076404b540aSrobert && REGNO (X) < LAST_VIRTUAL_REGISTER)) 1077404b540aSrobert 1078404b540aSrobert /* Nonzero if X is a hard reg that can be used as a base reg. */ 1079404b540aSrobert #define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1080404b540aSrobert 1081404b540aSrobert #ifdef REG_OK_STRICT 1082404b540aSrobert #define REG_OK_FOR_BASE_P(X) STRICT_REG_OK_FOR_BASE_P (X) 1083404b540aSrobert #else 1084404b540aSrobert #define REG_OK_FOR_BASE_P(X) NONSTRICT_REG_OK_FOR_BASE_P (X) 1085404b540aSrobert #endif 1086404b540aSrobert 1087404b540aSrobert /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a 1088404b540aSrobert valid memory address for an instruction. */ 1089404b540aSrobert 1090404b540aSrobert #ifdef REG_OK_STRICT 1091404b540aSrobert #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 1092404b540aSrobert do { \ 1093404b540aSrobert if (alpha_legitimate_address_p (MODE, X, 1)) \ 1094404b540aSrobert goto WIN; \ 1095404b540aSrobert } while (0) 1096404b540aSrobert #else 1097404b540aSrobert #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 1098404b540aSrobert do { \ 1099404b540aSrobert if (alpha_legitimate_address_p (MODE, X, 0)) \ 1100404b540aSrobert goto WIN; \ 1101404b540aSrobert } while (0) 1102404b540aSrobert #endif 1103404b540aSrobert 1104404b540aSrobert /* Try machine-dependent ways of modifying an illegitimate address 1105404b540aSrobert to be legitimate. If we find one, return the new, valid address. 1106404b540aSrobert This macro is used in only one place: `memory_address' in explow.c. */ 1107404b540aSrobert 1108404b540aSrobert #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1109404b540aSrobert do { \ 1110404b540aSrobert rtx new_x = alpha_legitimize_address (X, NULL_RTX, MODE); \ 1111404b540aSrobert if (new_x) \ 1112404b540aSrobert { \ 1113404b540aSrobert X = new_x; \ 1114404b540aSrobert goto WIN; \ 1115404b540aSrobert } \ 1116404b540aSrobert } while (0) 1117404b540aSrobert 1118404b540aSrobert /* Try a machine-dependent way of reloading an illegitimate address 1119404b540aSrobert operand. If we find one, push the reload and jump to WIN. This 1120404b540aSrobert macro is used in only one place: `find_reloads_address' in reload.c. */ 1121404b540aSrobert 1122404b540aSrobert #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \ 1123404b540aSrobert do { \ 1124404b540aSrobert rtx new_x = alpha_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \ 1125404b540aSrobert if (new_x) \ 1126404b540aSrobert { \ 1127404b540aSrobert X = new_x; \ 1128404b540aSrobert goto WIN; \ 1129404b540aSrobert } \ 1130404b540aSrobert } while (0) 1131404b540aSrobert 1132404b540aSrobert /* Go to LABEL if ADDR (a legitimate address expression) 1133404b540aSrobert has an effect that depends on the machine mode it is used for. 1134404b540aSrobert On the Alpha this is true only for the unaligned modes. We can 1135404b540aSrobert simplify this test since we know that the address must be valid. */ 1136404b540aSrobert 1137404b540aSrobert #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1138404b540aSrobert { if (GET_CODE (ADDR) == AND) goto LABEL; } 1139404b540aSrobert 1140404b540aSrobert /* Specify the machine mode that this machine uses 1141404b540aSrobert for the index in the tablejump instruction. */ 1142404b540aSrobert #define CASE_VECTOR_MODE SImode 1143404b540aSrobert 1144404b540aSrobert /* Define as C expression which evaluates to nonzero if the tablejump 1145404b540aSrobert instruction expects the table to contain offsets from the address of the 1146404b540aSrobert table. 1147404b540aSrobert 1148404b540aSrobert Do not define this if the table should contain absolute addresses. 1149404b540aSrobert On the Alpha, the table is really GP-relative, not relative to the PC 1150404b540aSrobert of the table, but we pretend that it is PC-relative; this should be OK, 1151404b540aSrobert but we should try to find some better way sometime. */ 1152404b540aSrobert #define CASE_VECTOR_PC_RELATIVE 1 1153404b540aSrobert 1154404b540aSrobert /* Define this as 1 if `char' should by default be signed; else as 0. */ 1155404b540aSrobert #define DEFAULT_SIGNED_CHAR 1 1156404b540aSrobert 1157404b540aSrobert /* Max number of bytes we can move to or from memory 1158404b540aSrobert in one reasonably fast instruction. */ 1159404b540aSrobert 1160404b540aSrobert #define MOVE_MAX 8 1161404b540aSrobert 1162404b540aSrobert /* If a memory-to-memory move would take MOVE_RATIO or more simple 1163404b540aSrobert move-instruction pairs, we will do a movmem or libcall instead. 1164404b540aSrobert 1165404b540aSrobert Without byte/word accesses, we want no more than four instructions; 1166404b540aSrobert with, several single byte accesses are better. */ 1167404b540aSrobert 1168404b540aSrobert #define MOVE_RATIO (TARGET_BWX ? 7 : 2) 1169404b540aSrobert 1170404b540aSrobert /* Largest number of bytes of an object that can be placed in a register. 1171404b540aSrobert On the Alpha we have plenty of registers, so use TImode. */ 1172404b540aSrobert #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 1173404b540aSrobert 1174404b540aSrobert /* Nonzero if access to memory by bytes is no faster than for words. 1175404b540aSrobert Also nonzero if doing byte operations (specifically shifts) in registers 1176404b540aSrobert is undesirable. 1177404b540aSrobert 1178404b540aSrobert On the Alpha, we want to not use the byte operation and instead use 1179404b540aSrobert masking operations to access fields; these will save instructions. */ 1180404b540aSrobert 1181404b540aSrobert #define SLOW_BYTE_ACCESS 1 1182404b540aSrobert 1183404b540aSrobert /* Define if operations between registers always perform the operation 1184404b540aSrobert on the full register even if a narrower mode is specified. */ 1185404b540aSrobert #define WORD_REGISTER_OPERATIONS 1186404b540aSrobert 1187404b540aSrobert /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1188404b540aSrobert will either zero-extend or sign-extend. The value of this macro should 1189404b540aSrobert be the code that says which one of the two operations is implicitly 1190404b540aSrobert done, UNKNOWN if none. */ 1191404b540aSrobert #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) 1192404b540aSrobert 1193404b540aSrobert /* Define if loading short immediate values into registers sign extends. */ 1194404b540aSrobert #define SHORT_IMMEDIATES_SIGN_EXTEND 1195404b540aSrobert 1196404b540aSrobert /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1197404b540aSrobert is done just by pretending it is already truncated. */ 1198404b540aSrobert #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1199404b540aSrobert 1200404b540aSrobert /* The CIX ctlz and cttz instructions return 64 for zero. */ 1201404b540aSrobert #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, TARGET_CIX) 1202404b540aSrobert #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, TARGET_CIX) 1203404b540aSrobert 1204404b540aSrobert /* Define the value returned by a floating-point comparison instruction. */ 1205404b540aSrobert 1206404b540aSrobert #define FLOAT_STORE_FLAG_VALUE(MODE) \ 1207404b540aSrobert REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE)) 1208404b540aSrobert 1209404b540aSrobert /* Canonicalize a comparison from one we don't have to one we do have. */ 1210404b540aSrobert 1211404b540aSrobert #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \ 1212404b540aSrobert do { \ 1213404b540aSrobert if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \ 1214404b540aSrobert && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \ 1215404b540aSrobert { \ 1216404b540aSrobert rtx tem = (OP0); \ 1217404b540aSrobert (OP0) = (OP1); \ 1218404b540aSrobert (OP1) = tem; \ 1219404b540aSrobert (CODE) = swap_condition (CODE); \ 1220404b540aSrobert } \ 1221404b540aSrobert if (((CODE) == LT || (CODE) == LTU) \ 1222404b540aSrobert && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \ 1223404b540aSrobert { \ 1224404b540aSrobert (CODE) = (CODE) == LT ? LE : LEU; \ 1225404b540aSrobert (OP1) = GEN_INT (255); \ 1226404b540aSrobert } \ 1227404b540aSrobert } while (0) 1228404b540aSrobert 1229404b540aSrobert /* Specify the machine mode that pointers have. 1230404b540aSrobert After generation of rtl, the compiler makes no further distinction 1231404b540aSrobert between pointers and any other objects of this machine mode. */ 1232404b540aSrobert #define Pmode DImode 1233404b540aSrobert 1234404b540aSrobert /* Mode of a function address in a call instruction (for indexing purposes). */ 1235404b540aSrobert 1236404b540aSrobert #define FUNCTION_MODE Pmode 1237404b540aSrobert 1238404b540aSrobert /* Define this if addresses of constant functions 1239404b540aSrobert shouldn't be put through pseudo regs where they can be cse'd. 1240404b540aSrobert Desirable on machines where ordinary constants are expensive 1241404b540aSrobert but a CALL with constant address is cheap. 1242404b540aSrobert 1243404b540aSrobert We define this on the Alpha so that gen_call and gen_call_value 1244404b540aSrobert get to see the SYMBOL_REF (for the hint field of the jsr). It will 1245404b540aSrobert then copy it into a register, thus actually letting the address be 1246404b540aSrobert cse'ed. */ 1247404b540aSrobert 1248404b540aSrobert #define NO_FUNCTION_CSE 1249404b540aSrobert 1250404b540aSrobert /* Define this to be nonzero if shift instructions ignore all but the low-order 1251404b540aSrobert few bits. */ 1252404b540aSrobert #define SHIFT_COUNT_TRUNCATED 1 1253404b540aSrobert 1254404b540aSrobert /* Control the assembler format that we output. */ 1255404b540aSrobert 1256404b540aSrobert /* Output to assembler file text saying following lines 1257404b540aSrobert may contain character constants, extra white space, comments, etc. */ 1258404b540aSrobert #define ASM_APP_ON (TARGET_EXPLICIT_RELOCS ? "\t.set\tmacro\n" : "") 1259404b540aSrobert 1260404b540aSrobert /* Output to assembler file text saying following lines 1261404b540aSrobert no longer contain unusual constructs. */ 1262404b540aSrobert #define ASM_APP_OFF (TARGET_EXPLICIT_RELOCS ? "\t.set\tnomacro\n" : "") 1263404b540aSrobert 1264404b540aSrobert #define TEXT_SECTION_ASM_OP "\t.text" 1265404b540aSrobert 1266404b540aSrobert /* Output before read-only data. */ 1267404b540aSrobert 1268404b540aSrobert #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" 1269404b540aSrobert 1270404b540aSrobert /* Output before writable data. */ 1271404b540aSrobert 1272404b540aSrobert #define DATA_SECTION_ASM_OP "\t.data" 1273404b540aSrobert 1274404b540aSrobert /* How to refer to registers in assembler output. 1275404b540aSrobert This sequence is indexed by compiler's hard-register-number (see above). */ 1276404b540aSrobert 1277404b540aSrobert #define REGISTER_NAMES \ 1278404b540aSrobert {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \ 1279404b540aSrobert "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 1280404b540aSrobert "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ 1281404b540aSrobert "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \ 1282404b540aSrobert "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \ 1283404b540aSrobert "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 1284404b540aSrobert "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\ 1285404b540aSrobert "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"} 1286404b540aSrobert 1287404b540aSrobert /* Strip name encoding when emitting labels. */ 1288404b540aSrobert 1289404b540aSrobert #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ 1290404b540aSrobert do { \ 1291404b540aSrobert const char *name_ = NAME; \ 1292404b540aSrobert if (*name_ == '@' || *name_ == '%') \ 1293404b540aSrobert name_ += 2; \ 1294404b540aSrobert if (*name_ == '*') \ 1295404b540aSrobert name_++; \ 1296404b540aSrobert else \ 1297404b540aSrobert fputs (user_label_prefix, STREAM); \ 1298404b540aSrobert fputs (name_, STREAM); \ 1299404b540aSrobert } while (0) 1300404b540aSrobert 1301404b540aSrobert /* Globalizing directive for a label. */ 1302404b540aSrobert #define GLOBAL_ASM_OP "\t.globl " 1303404b540aSrobert 1304404b540aSrobert /* The prefix to add to user-visible assembler symbols. */ 1305404b540aSrobert 1306404b540aSrobert #define USER_LABEL_PREFIX "" 1307404b540aSrobert 1308404b540aSrobert /* This is how to output a label for a jump table. Arguments are the same as 1309404b540aSrobert for (*targetm.asm_out.internal_label), except the insn for the jump table is 1310404b540aSrobert passed. */ 1311404b540aSrobert 1312404b540aSrobert #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ 1313404b540aSrobert { ASM_OUTPUT_ALIGN (FILE, 2); (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); } 1314404b540aSrobert 1315404b540aSrobert /* This is how to store into the string LABEL 1316404b540aSrobert the symbol_ref name of an internal numbered label where 1317404b540aSrobert PREFIX is the class of label and NUM is the number within the class. 1318404b540aSrobert This is suitable for output with `assemble_name'. */ 1319404b540aSrobert 1320404b540aSrobert #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1321404b540aSrobert sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM)) 1322404b540aSrobert 1323404b540aSrobert /* We use the default ASCII-output routine, except that we don't write more 1324404b540aSrobert than 50 characters since the assembler doesn't support very long lines. */ 1325404b540aSrobert 1326404b540aSrobert #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \ 1327404b540aSrobert do { \ 1328404b540aSrobert FILE *_hide_asm_out_file = (MYFILE); \ 1329404b540aSrobert const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \ 1330404b540aSrobert int _hide_thissize = (MYLENGTH); \ 1331404b540aSrobert int _size_so_far = 0; \ 1332404b540aSrobert { \ 1333404b540aSrobert FILE *asm_out_file = _hide_asm_out_file; \ 1334404b540aSrobert const unsigned char *p = _hide_p; \ 1335404b540aSrobert int thissize = _hide_thissize; \ 1336404b540aSrobert int i; \ 1337404b540aSrobert fprintf (asm_out_file, "\t.ascii \""); \ 1338404b540aSrobert \ 1339404b540aSrobert for (i = 0; i < thissize; i++) \ 1340404b540aSrobert { \ 1341404b540aSrobert register int c = p[i]; \ 1342404b540aSrobert \ 1343404b540aSrobert if (_size_so_far ++ > 50 && i < thissize - 4) \ 1344404b540aSrobert _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ 1345404b540aSrobert \ 1346404b540aSrobert if (c == '\"' || c == '\\') \ 1347404b540aSrobert putc ('\\', asm_out_file); \ 1348404b540aSrobert if (c >= ' ' && c < 0177) \ 1349404b540aSrobert putc (c, asm_out_file); \ 1350404b540aSrobert else \ 1351404b540aSrobert { \ 1352404b540aSrobert fprintf (asm_out_file, "\\%o", c); \ 1353404b540aSrobert /* After an octal-escape, if a digit follows, \ 1354404b540aSrobert terminate one string constant and start another. \ 1355404b540aSrobert The VAX assembler fails to stop reading the escape \ 1356404b540aSrobert after three digits, so this is the only way we \ 1357404b540aSrobert can get it to parse the data properly. */ \ 1358404b540aSrobert if (i < thissize - 1 && ISDIGIT (p[i + 1])) \ 1359404b540aSrobert _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ 1360404b540aSrobert } \ 1361404b540aSrobert } \ 1362404b540aSrobert fprintf (asm_out_file, "\"\n"); \ 1363404b540aSrobert } \ 1364404b540aSrobert } \ 1365404b540aSrobert while (0) 1366404b540aSrobert 1367404b540aSrobert /* This is how to output an element of a case-vector that is relative. */ 1368404b540aSrobert 1369404b540aSrobert #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1370404b540aSrobert fprintf (FILE, "\t.%s $L%d\n", TARGET_ABI_WINDOWS_NT ? "long" : "gprel32", \ 1371404b540aSrobert (VALUE)) 1372404b540aSrobert 1373404b540aSrobert /* This is how to output an assembler line 1374404b540aSrobert that says to advance the location counter 1375404b540aSrobert to a multiple of 2**LOG bytes. */ 1376404b540aSrobert 1377404b540aSrobert #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1378404b540aSrobert if ((LOG) != 0) \ 1379404b540aSrobert fprintf (FILE, "\t.align %d\n", LOG); 1380404b540aSrobert 1381404b540aSrobert /* This is how to advance the location counter by SIZE bytes. */ 1382404b540aSrobert 1383404b540aSrobert #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1384404b540aSrobert fprintf (FILE, "\t.space "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 1385404b540aSrobert 1386404b540aSrobert /* This says how to output an assembler line 1387404b540aSrobert to define a global common symbol. */ 1388404b540aSrobert 1389404b540aSrobert #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1390404b540aSrobert ( fputs ("\t.comm ", (FILE)), \ 1391404b540aSrobert assemble_name ((FILE), (NAME)), \ 1392404b540aSrobert fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))) 1393404b540aSrobert 1394404b540aSrobert /* This says how to output an assembler line 1395404b540aSrobert to define a local common symbol. */ 1396404b540aSrobert 1397404b540aSrobert #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ 1398404b540aSrobert ( fputs ("\t.lcomm ", (FILE)), \ 1399404b540aSrobert assemble_name ((FILE), (NAME)), \ 1400404b540aSrobert fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))) 1401404b540aSrobert 1402404b540aSrobert 1403404b540aSrobert /* Print operand X (an rtx) in assembler syntax to file FILE. 1404404b540aSrobert CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1405404b540aSrobert For `%' followed by punctuation, CODE is the punctuation and X is null. */ 1406404b540aSrobert 1407404b540aSrobert #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 1408404b540aSrobert 1409404b540aSrobert /* Determine which codes are valid without a following integer. These must 1410404b540aSrobert not be alphabetic. 1411404b540aSrobert 1412404b540aSrobert ~ Generates the name of the current function. 1413404b540aSrobert 1414404b540aSrobert / Generates the instruction suffix. The TRAP_SUFFIX and ROUND_SUFFIX 1415404b540aSrobert attributes are examined to determine what is appropriate. 1416404b540aSrobert 1417404b540aSrobert , Generates single precision suffix for floating point 1418404b540aSrobert instructions (s for IEEE, f for VAX) 1419404b540aSrobert 1420404b540aSrobert - Generates double precision suffix for floating point 1421404b540aSrobert instructions (t for IEEE, g for VAX) 1422404b540aSrobert 1423404b540aSrobert + Generates a nop instruction after a noreturn call at the very end 1424404b540aSrobert of the function 1425404b540aSrobert */ 1426404b540aSrobert 1427404b540aSrobert #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1428404b540aSrobert ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~' \ 1429404b540aSrobert || (CODE) == '#' || (CODE) == '*' || (CODE) == '&' || (CODE) == '+') 1430404b540aSrobert 1431404b540aSrobert /* Print a memory address as an operand to reference that memory location. */ 1432404b540aSrobert 1433404b540aSrobert #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1434404b540aSrobert print_operand_address((FILE), (ADDR)) 1435404b540aSrobert 1436404b540aSrobert /* Implement `va_start' for varargs and stdarg. */ 1437404b540aSrobert #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1438404b540aSrobert alpha_va_start (valist, nextarg) 1439404b540aSrobert 1440404b540aSrobert /* Tell collect that the object format is ECOFF. */ 1441404b540aSrobert #define OBJECT_FORMAT_COFF 1442404b540aSrobert #define EXTENDED_COFF 1443404b540aSrobert 1444404b540aSrobert /* If we use NM, pass -g to it so it only lists globals. */ 1445404b540aSrobert #define NM_FLAGS "-pg" 1446404b540aSrobert 1447404b540aSrobert /* Definitions for debugging. */ 1448404b540aSrobert 1449404b540aSrobert #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */ 1450404b540aSrobert #define DBX_DEBUGGING_INFO 1 /* generate embedded stabs */ 1451404b540aSrobert #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */ 1452404b540aSrobert 1453404b540aSrobert #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */ 1454404b540aSrobert #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG 1455404b540aSrobert #endif 1456404b540aSrobert 1457404b540aSrobert 1458404b540aSrobert /* Correct the offset of automatic variables and arguments. Note that 1459404b540aSrobert the Alpha debug format wants all automatic variables and arguments 1460404b540aSrobert to be in terms of two different offsets from the virtual frame pointer, 1461404b540aSrobert which is the stack pointer before any adjustment in the function. 1462404b540aSrobert The offset for the argument pointer is fixed for the native compiler, 1463404b540aSrobert it is either zero (for the no arguments case) or large enough to hold 1464404b540aSrobert all argument registers. 1465404b540aSrobert The offset for the auto pointer is the fourth argument to the .frame 1466404b540aSrobert directive (local_offset). 1467404b540aSrobert To stay compatible with the native tools we use the same offsets 1468404b540aSrobert from the virtual frame pointer and adjust the debugger arg/auto offsets 1469404b540aSrobert accordingly. These debugger offsets are set up in output_prolog. */ 1470404b540aSrobert 1471404b540aSrobert extern long alpha_arg_offset; 1472404b540aSrobert extern long alpha_auto_offset; 1473404b540aSrobert #define DEBUGGER_AUTO_OFFSET(X) \ 1474404b540aSrobert ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset) 1475404b540aSrobert #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset) 1476404b540aSrobert 1477404b540aSrobert /* mips-tfile doesn't understand .stabd directives. */ 1478404b540aSrobert #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \ 1479404b540aSrobert dbxout_begin_stabn_sline (LINE); \ 1480404b540aSrobert dbxout_stab_value_internal_label ("LM", &COUNTER); \ 1481404b540aSrobert } while (0) 1482404b540aSrobert 1483404b540aSrobert /* We want to use MIPS-style .loc directives for SDB line numbers. */ 1484404b540aSrobert extern int num_source_filenames; 1485404b540aSrobert #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \ 1486404b540aSrobert fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE) 1487404b540aSrobert 1488404b540aSrobert #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ 1489404b540aSrobert alpha_output_filename (STREAM, NAME) 1490404b540aSrobert 1491404b540aSrobert /* mips-tfile.c limits us to strings of one page. We must underestimate this 1492404b540aSrobert number, because the real length runs past this up to the next 1493404b540aSrobert continuation point. This is really a dbxout.c bug. */ 1494404b540aSrobert #define DBX_CONTIN_LENGTH 3000 1495404b540aSrobert 1496404b540aSrobert /* By default, turn on GDB extensions. */ 1497404b540aSrobert #define DEFAULT_GDB_EXTENSIONS 1 1498404b540aSrobert 1499404b540aSrobert /* Stabs-in-ECOFF can't handle dbxout_function_end(). */ 1500404b540aSrobert #define NO_DBX_FUNCTION_END 1 1501404b540aSrobert 1502404b540aSrobert /* If we are smuggling stabs through the ALPHA ECOFF object 1503404b540aSrobert format, put a comment in front of the .stab<x> operation so 1504404b540aSrobert that the ALPHA assembler does not choke. The mips-tfile program 1505404b540aSrobert will correctly put the stab into the object file. */ 1506404b540aSrobert 1507404b540aSrobert #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t") 1508404b540aSrobert #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t") 1509404b540aSrobert #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t") 1510404b540aSrobert 1511404b540aSrobert /* Forward references to tags are allowed. */ 1512404b540aSrobert #define SDB_ALLOW_FORWARD_REFERENCES 1513404b540aSrobert 1514404b540aSrobert /* Unknown tags are also allowed. */ 1515404b540aSrobert #define SDB_ALLOW_UNKNOWN_REFERENCES 1516404b540aSrobert 1517404b540aSrobert #define PUT_SDB_DEF(a) \ 1518404b540aSrobert do { \ 1519404b540aSrobert fprintf (asm_out_file, "\t%s.def\t", \ 1520404b540aSrobert (TARGET_GAS) ? "" : "#"); \ 1521404b540aSrobert ASM_OUTPUT_LABELREF (asm_out_file, a); \ 1522404b540aSrobert fputc (';', asm_out_file); \ 1523404b540aSrobert } while (0) 1524404b540aSrobert 1525404b540aSrobert #define PUT_SDB_PLAIN_DEF(a) \ 1526404b540aSrobert do { \ 1527404b540aSrobert fprintf (asm_out_file, "\t%s.def\t.%s;", \ 1528404b540aSrobert (TARGET_GAS) ? "" : "#", (a)); \ 1529404b540aSrobert } while (0) 1530404b540aSrobert 1531404b540aSrobert #define PUT_SDB_TYPE(a) \ 1532404b540aSrobert do { \ 1533404b540aSrobert fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \ 1534404b540aSrobert } while (0) 1535404b540aSrobert 1536404b540aSrobert /* For block start and end, we create labels, so that 1537404b540aSrobert later we can figure out where the correct offset is. 1538404b540aSrobert The normal .ent/.end serve well enough for functions, 1539404b540aSrobert so those are just commented out. */ 1540404b540aSrobert 1541404b540aSrobert extern int sdb_label_count; /* block start/end next label # */ 1542404b540aSrobert 1543404b540aSrobert #define PUT_SDB_BLOCK_START(LINE) \ 1544404b540aSrobert do { \ 1545404b540aSrobert fprintf (asm_out_file, \ 1546404b540aSrobert "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \ 1547404b540aSrobert sdb_label_count, \ 1548404b540aSrobert (TARGET_GAS) ? "" : "#", \ 1549404b540aSrobert sdb_label_count, \ 1550404b540aSrobert (LINE)); \ 1551404b540aSrobert sdb_label_count++; \ 1552404b540aSrobert } while (0) 1553404b540aSrobert 1554404b540aSrobert #define PUT_SDB_BLOCK_END(LINE) \ 1555404b540aSrobert do { \ 1556404b540aSrobert fprintf (asm_out_file, \ 1557404b540aSrobert "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \ 1558404b540aSrobert sdb_label_count, \ 1559404b540aSrobert (TARGET_GAS) ? "" : "#", \ 1560404b540aSrobert sdb_label_count, \ 1561404b540aSrobert (LINE)); \ 1562404b540aSrobert sdb_label_count++; \ 1563404b540aSrobert } while (0) 1564404b540aSrobert 1565404b540aSrobert #define PUT_SDB_FUNCTION_START(LINE) 1566404b540aSrobert 1567404b540aSrobert #define PUT_SDB_FUNCTION_END(LINE) 1568404b540aSrobert 1569404b540aSrobert #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME)) 1570404b540aSrobert 1571404b540aSrobert /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for 1572404b540aSrobert mips-tdump.c to print them out. 1573404b540aSrobert 1574404b540aSrobert These must match the corresponding definitions in gdb/mipsread.c. 1575404b540aSrobert Unfortunately, gcc and gdb do not currently share any directories. */ 1576404b540aSrobert 1577404b540aSrobert #define CODE_MASK 0x8F300 1578404b540aSrobert #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) 1579404b540aSrobert #define MIPS_MARK_STAB(code) ((code)+CODE_MASK) 1580404b540aSrobert #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK) 1581404b540aSrobert 1582404b540aSrobert /* Override some mips-tfile definitions. */ 1583404b540aSrobert 1584404b540aSrobert #define SHASH_SIZE 511 1585404b540aSrobert #define THASH_SIZE 55 1586404b540aSrobert 1587404b540aSrobert /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */ 1588404b540aSrobert 1589404b540aSrobert #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7) 1590404b540aSrobert 1591404b540aSrobert /* The system headers under Alpha systems are generally C++-aware. */ 1592404b540aSrobert #define NO_IMPLICIT_EXTERN_C 1593