1*404b540aSrobert /* Definitions for the Blackfin port. 2*404b540aSrobert Copyright (C) 2005 Free Software Foundation, Inc. 3*404b540aSrobert Contributed by Analog Devices. 4*404b540aSrobert 5*404b540aSrobert This file is part of GCC. 6*404b540aSrobert 7*404b540aSrobert GCC is free software; you can redistribute it and/or modify it 8*404b540aSrobert under the terms of the GNU General Public License as published 9*404b540aSrobert by the Free Software Foundation; either version 2, or (at your 10*404b540aSrobert option) any later version. 11*404b540aSrobert 12*404b540aSrobert GCC is distributed in the hope that it will be useful, but WITHOUT 13*404b540aSrobert ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14*404b540aSrobert or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15*404b540aSrobert License for more details. 16*404b540aSrobert 17*404b540aSrobert You should have received a copy of the GNU General Public License 18*404b540aSrobert along with GCC; see the file COPYING. If not, write to 19*404b540aSrobert the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20*404b540aSrobert Boston, MA 02110-1301, USA. */ 21*404b540aSrobert 22*404b540aSrobert #ifndef _BFIN_CONFIG 23*404b540aSrobert #define _BFIN_CONFIG 24*404b540aSrobert 25*404b540aSrobert #define OBJECT_FORMAT_ELF 26*404b540aSrobert 27*404b540aSrobert #define BRT 1 28*404b540aSrobert #define BRF 0 29*404b540aSrobert 30*404b540aSrobert /* Print subsidiary information on the compiler version in use. */ 31*404b540aSrobert #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)") 32*404b540aSrobert 33*404b540aSrobert /* Run-time compilation parameters selecting different hardware subsets. */ 34*404b540aSrobert 35*404b540aSrobert extern int target_flags; 36*404b540aSrobert 37*404b540aSrobert /* Predefinition in the preprocessor for this target machine */ 38*404b540aSrobert #ifndef TARGET_CPU_CPP_BUILTINS 39*404b540aSrobert #define TARGET_CPU_CPP_BUILTINS() \ 40*404b540aSrobert do \ 41*404b540aSrobert { \ 42*404b540aSrobert builtin_define_std ("bfin"); \ 43*404b540aSrobert builtin_define_std ("BFIN"); \ 44*404b540aSrobert builtin_define ("__ADSPBLACKFIN__"); \ 45*404b540aSrobert if (TARGET_FDPIC) \ 46*404b540aSrobert builtin_define ("__BFIN_FDPIC__"); \ 47*404b540aSrobert if (TARGET_ID_SHARED_LIBRARY) \ 48*404b540aSrobert builtin_define ("__ID_SHARED_LIB__"); \ 49*404b540aSrobert } \ 50*404b540aSrobert while (0) 51*404b540aSrobert #endif 52*404b540aSrobert 53*404b540aSrobert #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\ 54*404b540aSrobert %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ 55*404b540aSrobert %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \ 56*404b540aSrobert " 57*404b540aSrobert #ifndef SUBTARGET_DRIVER_SELF_SPECS 58*404b540aSrobert # define SUBTARGET_DRIVER_SELF_SPECS 59*404b540aSrobert #endif 60*404b540aSrobert 61*404b540aSrobert #define LINK_GCC_C_SEQUENCE_SPEC \ 62*404b540aSrobert "%{mfdpic:%{!static: %L} %{static: %G %L %G}} \ 63*404b540aSrobert %{!mfdpic:%G %L %G}" 64*404b540aSrobert 65*404b540aSrobert /* A C string constant that tells the GCC driver program options to pass to 66*404b540aSrobert the assembler. It can also specify how to translate options you give to GNU 67*404b540aSrobert CC into options for GCC to pass to the assembler. See the file `sun3.h' 68*404b540aSrobert for an example of this. 69*404b540aSrobert 70*404b540aSrobert Do not define this macro if it does not need to do anything. 71*404b540aSrobert 72*404b540aSrobert Defined in svr4.h. */ 73*404b540aSrobert #undef ASM_SPEC 74*404b540aSrobert #define ASM_SPEC "\ 75*404b540aSrobert %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \ 76*404b540aSrobert %{mno-fdpic:-mnopic} %{mfdpic}" 77*404b540aSrobert 78*404b540aSrobert #define LINK_SPEC "\ 79*404b540aSrobert %{h*} %{v:-V} \ 80*404b540aSrobert %{b} \ 81*404b540aSrobert %{mfdpic:-melf32bfinfd -z text} \ 82*404b540aSrobert %{static:-dn -Bstatic} \ 83*404b540aSrobert %{shared:-G -Bdynamic} \ 84*404b540aSrobert %{symbolic:-Bsymbolic} \ 85*404b540aSrobert %{G*} \ 86*404b540aSrobert %{YP,*} \ 87*404b540aSrobert %{Qy:} %{!Qn:-Qy} \ 88*404b540aSrobert -init __init -fini __fini " 89*404b540aSrobert 90*404b540aSrobert /* Generate DSP instructions, like DSP halfword loads */ 91*404b540aSrobert #define TARGET_DSP (1) 92*404b540aSrobert 93*404b540aSrobert #define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY) 94*404b540aSrobert 95*404b540aSrobert /* Maximum number of library ids we permit */ 96*404b540aSrobert #define MAX_LIBRARY_ID 255 97*404b540aSrobert 98*404b540aSrobert extern const char *bfin_library_id_string; 99*404b540aSrobert 100*404b540aSrobert /* Sometimes certain combinations of command options do not make 101*404b540aSrobert sense on a particular target machine. You can define a macro 102*404b540aSrobert `OVERRIDE_OPTIONS' to take account of this. This macro, if 103*404b540aSrobert defined, is executed once just after all the command options have 104*404b540aSrobert been parsed. 105*404b540aSrobert 106*404b540aSrobert Don't use this macro to turn on various extra optimizations for 107*404b540aSrobert `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 108*404b540aSrobert 109*404b540aSrobert #define OVERRIDE_OPTIONS override_options () 110*404b540aSrobert 111*404b540aSrobert #define FUNCTION_MODE SImode 112*404b540aSrobert #define Pmode SImode 113*404b540aSrobert 114*404b540aSrobert /* store-condition-codes instructions store 0 for false 115*404b540aSrobert This is the value stored for true. */ 116*404b540aSrobert #define STORE_FLAG_VALUE 1 117*404b540aSrobert 118*404b540aSrobert /* Define this if pushing a word on the stack 119*404b540aSrobert makes the stack pointer a smaller address. */ 120*404b540aSrobert #define STACK_GROWS_DOWNWARD 121*404b540aSrobert 122*404b540aSrobert #define STACK_PUSH_CODE PRE_DEC 123*404b540aSrobert 124*404b540aSrobert /* Define this to nonzero if the nominal address of the stack frame 125*404b540aSrobert is at the high-address end of the local variables; 126*404b540aSrobert that is, each additional local variable allocated 127*404b540aSrobert goes at a more negative offset in the frame. */ 128*404b540aSrobert #define FRAME_GROWS_DOWNWARD 1 129*404b540aSrobert 130*404b540aSrobert /* We define a dummy ARGP register; the parameters start at offset 0 from 131*404b540aSrobert it. */ 132*404b540aSrobert #define FIRST_PARM_OFFSET(DECL) 0 133*404b540aSrobert 134*404b540aSrobert /* Offset within stack frame to start allocating local variables at. 135*404b540aSrobert If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 136*404b540aSrobert first local allocated. Otherwise, it is the offset to the BEGINNING 137*404b540aSrobert of the first local allocated. */ 138*404b540aSrobert #define STARTING_FRAME_OFFSET 0 139*404b540aSrobert 140*404b540aSrobert /* Register to use for pushing function arguments. */ 141*404b540aSrobert #define STACK_POINTER_REGNUM REG_P6 142*404b540aSrobert 143*404b540aSrobert /* Base register for access to local variables of the function. */ 144*404b540aSrobert #define FRAME_POINTER_REGNUM REG_P7 145*404b540aSrobert 146*404b540aSrobert /* A dummy register that will be eliminated to either FP or SP. */ 147*404b540aSrobert #define ARG_POINTER_REGNUM REG_ARGP 148*404b540aSrobert 149*404b540aSrobert /* `PIC_OFFSET_TABLE_REGNUM' 150*404b540aSrobert The register number of the register used to address a table of 151*404b540aSrobert static data addresses in memory. In some cases this register is 152*404b540aSrobert defined by a processor's "application binary interface" (ABI). 153*404b540aSrobert When this macro is defined, RTL is generated for this register 154*404b540aSrobert once, as with the stack pointer and frame pointer registers. If 155*404b540aSrobert this macro is not defined, it is up to the machine-dependent files 156*404b540aSrobert to allocate such a register (if necessary). */ 157*404b540aSrobert #define PIC_OFFSET_TABLE_REGNUM (REG_P5) 158*404b540aSrobert 159*404b540aSrobert #define FDPIC_FPTR_REGNO REG_P1 160*404b540aSrobert #define FDPIC_REGNO REG_P3 161*404b540aSrobert #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) 162*404b540aSrobert 163*404b540aSrobert /* A static chain register for nested functions. We need to use a 164*404b540aSrobert call-clobbered register for this. */ 165*404b540aSrobert #define STATIC_CHAIN_REGNUM REG_P2 166*404b540aSrobert 167*404b540aSrobert /* Define this if functions should assume that stack space has been 168*404b540aSrobert allocated for arguments even when their values are passed in 169*404b540aSrobert registers. 170*404b540aSrobert 171*404b540aSrobert The value of this macro is the size, in bytes, of the area reserved for 172*404b540aSrobert arguments passed in registers. 173*404b540aSrobert 174*404b540aSrobert This space can either be allocated by the caller or be a part of the 175*404b540aSrobert machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' 176*404b540aSrobert says which. */ 177*404b540aSrobert #define FIXED_STACK_AREA 12 178*404b540aSrobert #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA 179*404b540aSrobert 180*404b540aSrobert /* Define this if the above stack space is to be considered part of the 181*404b540aSrobert * space allocated by the caller. */ 182*404b540aSrobert #define OUTGOING_REG_PARM_STACK_SPACE 183*404b540aSrobert 184*404b540aSrobert /* Define this if the maximum size of all the outgoing args is to be 185*404b540aSrobert accumulated and pushed during the prologue. The amount can be 186*404b540aSrobert found in the variable current_function_outgoing_args_size. */ 187*404b540aSrobert #define ACCUMULATE_OUTGOING_ARGS 1 188*404b540aSrobert 189*404b540aSrobert /* Value should be nonzero if functions must have frame pointers. 190*404b540aSrobert Zero means the frame pointer need not be set up (and parms 191*404b540aSrobert may be accessed via the stack pointer) in functions that seem suitable. 192*404b540aSrobert This is computed in `reload', in reload1.c. 193*404b540aSrobert */ 194*404b540aSrobert #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ()) 195*404b540aSrobert 196*404b540aSrobert /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ 197*404b540aSrobert 198*404b540aSrobert /* Make strings word-aligned so strcpy from constants will be faster. */ 199*404b540aSrobert #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 200*404b540aSrobert (TREE_CODE (EXP) == STRING_CST \ 201*404b540aSrobert && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 202*404b540aSrobert 203*404b540aSrobert #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18) 204*404b540aSrobert #define TRAMPOLINE_TEMPLATE(FILE) \ 205*404b540aSrobert if (TARGET_FDPIC) \ 206*404b540aSrobert { \ 207*404b540aSrobert fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \ 208*404b540aSrobert fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \ 209*404b540aSrobert fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \ 210*404b540aSrobert fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \ 211*404b540aSrobert fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \ 212*404b540aSrobert fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \ 213*404b540aSrobert fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \ 214*404b540aSrobert fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \ 215*404b540aSrobert fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \ 216*404b540aSrobert } \ 217*404b540aSrobert else \ 218*404b540aSrobert { \ 219*404b540aSrobert fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \ 220*404b540aSrobert fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \ 221*404b540aSrobert fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \ 222*404b540aSrobert fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \ 223*404b540aSrobert fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \ 224*404b540aSrobert } 225*404b540aSrobert 226*404b540aSrobert #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 227*404b540aSrobert initialize_trampoline (TRAMP, FNADDR, CXT) 228*404b540aSrobert 229*404b540aSrobert /* Definitions for register eliminations. 230*404b540aSrobert 231*404b540aSrobert This is an array of structures. Each structure initializes one pair 232*404b540aSrobert of eliminable registers. The "from" register number is given first, 233*404b540aSrobert followed by "to". Eliminations of the same "from" register are listed 234*404b540aSrobert in order of preference. 235*404b540aSrobert 236*404b540aSrobert There are two registers that can always be eliminated on the i386. 237*404b540aSrobert The frame pointer and the arg pointer can be replaced by either the 238*404b540aSrobert hard frame pointer or to the stack pointer, depending upon the 239*404b540aSrobert circumstances. The hard frame pointer is not used before reload and 240*404b540aSrobert so it is not eligible for elimination. */ 241*404b540aSrobert 242*404b540aSrobert #define ELIMINABLE_REGS \ 243*404b540aSrobert {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 244*404b540aSrobert { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 245*404b540aSrobert { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ 246*404b540aSrobert 247*404b540aSrobert /* Given FROM and TO register numbers, say whether this elimination is 248*404b540aSrobert allowed. Frame pointer elimination is automatically handled. 249*404b540aSrobert 250*404b540aSrobert All other eliminations are valid. */ 251*404b540aSrobert 252*404b540aSrobert #define CAN_ELIMINATE(FROM, TO) \ 253*404b540aSrobert ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 254*404b540aSrobert 255*404b540aSrobert /* Define the offset between two registers, one to be eliminated, and the other 256*404b540aSrobert its replacement, at the start of a routine. */ 257*404b540aSrobert 258*404b540aSrobert #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 259*404b540aSrobert ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) 260*404b540aSrobert 261*404b540aSrobert /* This processor has 262*404b540aSrobert 8 data register for doing arithmetic 263*404b540aSrobert 8 pointer register for doing addressing, including 264*404b540aSrobert 1 stack pointer P6 265*404b540aSrobert 1 frame pointer P7 266*404b540aSrobert 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) 267*404b540aSrobert 1 condition code flag register CC 268*404b540aSrobert 5 return address registers RETS/I/X/N/E 269*404b540aSrobert 1 arithmetic status register (ASTAT). */ 270*404b540aSrobert 271*404b540aSrobert #define FIRST_PSEUDO_REGISTER 50 272*404b540aSrobert 273*404b540aSrobert #define D_REGNO_P(X) ((X) <= REG_R7) 274*404b540aSrobert #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7) 275*404b540aSrobert #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3) 276*404b540aSrobert #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X)) 277*404b540aSrobert #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) 278*404b540aSrobert #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) 279*404b540aSrobert #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X))) 280*404b540aSrobert #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X))) 281*404b540aSrobert #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X))) 282*404b540aSrobert 283*404b540aSrobert #define REGISTER_NAMES { \ 284*404b540aSrobert "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ 285*404b540aSrobert "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ 286*404b540aSrobert "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \ 287*404b540aSrobert "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \ 288*404b540aSrobert "A0", "A1", \ 289*404b540aSrobert "CC", \ 290*404b540aSrobert "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ 291*404b540aSrobert "ARGP", \ 292*404b540aSrobert "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \ 293*404b540aSrobert } 294*404b540aSrobert 295*404b540aSrobert #define SHORT_REGISTER_NAMES { \ 296*404b540aSrobert "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ 297*404b540aSrobert "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ 298*404b540aSrobert "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \ 299*404b540aSrobert "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } 300*404b540aSrobert 301*404b540aSrobert #define HIGH_REGISTER_NAMES { \ 302*404b540aSrobert "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ 303*404b540aSrobert "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ 304*404b540aSrobert "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \ 305*404b540aSrobert "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } 306*404b540aSrobert 307*404b540aSrobert #define DREGS_PAIR_NAMES { \ 308*404b540aSrobert "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } 309*404b540aSrobert 310*404b540aSrobert #define BYTE_REGISTER_NAMES { \ 311*404b540aSrobert "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } 312*404b540aSrobert 313*404b540aSrobert 314*404b540aSrobert /* 1 for registers that have pervasive standard uses 315*404b540aSrobert and are not available for the register allocator. */ 316*404b540aSrobert 317*404b540aSrobert #define FIXED_REGISTERS \ 318*404b540aSrobert /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 319*404b540aSrobert { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 320*404b540aSrobert /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 321*404b540aSrobert 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \ 322*404b540aSrobert /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 323*404b540aSrobert 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 324*404b540aSrobert /*lb0/1 */ \ 325*404b540aSrobert 1, 1 \ 326*404b540aSrobert } 327*404b540aSrobert 328*404b540aSrobert /* 1 for registers not available across function calls. 329*404b540aSrobert These must include the FIXED_REGISTERS and also any 330*404b540aSrobert registers that can be used without being saved. 331*404b540aSrobert The latter must include the registers where values are returned 332*404b540aSrobert and the register where structure-value addresses are passed. 333*404b540aSrobert Aside from that, you can include as many other registers as you like. */ 334*404b540aSrobert 335*404b540aSrobert #define CALL_USED_REGISTERS \ 336*404b540aSrobert /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 337*404b540aSrobert { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ 338*404b540aSrobert /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 339*404b540aSrobert 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 340*404b540aSrobert /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 341*404b540aSrobert 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 342*404b540aSrobert /*lb0/1 */ \ 343*404b540aSrobert 1, 1 \ 344*404b540aSrobert } 345*404b540aSrobert 346*404b540aSrobert /* Order in which to allocate registers. Each register must be 347*404b540aSrobert listed once, even those in FIXED_REGISTERS. List frame pointer 348*404b540aSrobert late and fixed registers last. Note that, in general, we prefer 349*404b540aSrobert registers listed in CALL_USED_REGISTERS, keeping the others 350*404b540aSrobert available for storage of persistent values. */ 351*404b540aSrobert 352*404b540aSrobert #define REG_ALLOC_ORDER \ 353*404b540aSrobert { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ 354*404b540aSrobert REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ 355*404b540aSrobert REG_A0, REG_A1, \ 356*404b540aSrobert REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \ 357*404b540aSrobert REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ 358*404b540aSrobert REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ 359*404b540aSrobert REG_ASTAT, REG_SEQSTAT, REG_USP, \ 360*404b540aSrobert REG_CC, REG_ARGP, \ 361*404b540aSrobert REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \ 362*404b540aSrobert } 363*404b540aSrobert 364*404b540aSrobert /* Macro to conditionally modify fixed_regs/call_used_regs. */ 365*404b540aSrobert #define CONDITIONAL_REGISTER_USAGE \ 366*404b540aSrobert { \ 367*404b540aSrobert conditional_register_usage(); \ 368*404b540aSrobert if (TARGET_FDPIC) \ 369*404b540aSrobert call_used_regs[FDPIC_REGNO] = 1; \ 370*404b540aSrobert if (!TARGET_FDPIC && flag_pic) \ 371*404b540aSrobert { \ 372*404b540aSrobert fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 373*404b540aSrobert call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 374*404b540aSrobert } \ 375*404b540aSrobert } 376*404b540aSrobert 377*404b540aSrobert /* Define the classes of registers for register constraints in the 378*404b540aSrobert machine description. Also define ranges of constants. 379*404b540aSrobert 380*404b540aSrobert One of the classes must always be named ALL_REGS and include all hard regs. 381*404b540aSrobert If there is more than one class, another class must be named NO_REGS 382*404b540aSrobert and contain no registers. 383*404b540aSrobert 384*404b540aSrobert The name GENERAL_REGS must be the name of a class (or an alias for 385*404b540aSrobert another name such as ALL_REGS). This is the class of registers 386*404b540aSrobert that is allowed by "g" or "r" in a register constraint. 387*404b540aSrobert Also, registers outside this class are allocated only when 388*404b540aSrobert instructions express preferences for them. 389*404b540aSrobert 390*404b540aSrobert The classes must be numbered in nondecreasing order; that is, 391*404b540aSrobert a larger-numbered class must never be contained completely 392*404b540aSrobert in a smaller-numbered class. 393*404b540aSrobert 394*404b540aSrobert For any two classes, it is very desirable that there be another 395*404b540aSrobert class that represents their union. */ 396*404b540aSrobert 397*404b540aSrobert 398*404b540aSrobert enum reg_class 399*404b540aSrobert { 400*404b540aSrobert NO_REGS, 401*404b540aSrobert IREGS, 402*404b540aSrobert BREGS, 403*404b540aSrobert LREGS, 404*404b540aSrobert MREGS, 405*404b540aSrobert CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ 406*404b540aSrobert DAGREGS, 407*404b540aSrobert EVEN_AREGS, 408*404b540aSrobert ODD_AREGS, 409*404b540aSrobert AREGS, 410*404b540aSrobert CCREGS, 411*404b540aSrobert EVEN_DREGS, 412*404b540aSrobert ODD_DREGS, 413*404b540aSrobert DREGS, 414*404b540aSrobert FDPIC_REGS, 415*404b540aSrobert FDPIC_FPTR_REGS, 416*404b540aSrobert PREGS_CLOBBERED, 417*404b540aSrobert PREGS, 418*404b540aSrobert IPREGS, 419*404b540aSrobert DPREGS, 420*404b540aSrobert MOST_REGS, 421*404b540aSrobert LT_REGS, 422*404b540aSrobert LC_REGS, 423*404b540aSrobert LB_REGS, 424*404b540aSrobert PROLOGUE_REGS, 425*404b540aSrobert NON_A_CC_REGS, 426*404b540aSrobert ALL_REGS, LIM_REG_CLASSES 427*404b540aSrobert }; 428*404b540aSrobert 429*404b540aSrobert #define N_REG_CLASSES ((int)LIM_REG_CLASSES) 430*404b540aSrobert 431*404b540aSrobert #define GENERAL_REGS DPREGS 432*404b540aSrobert 433*404b540aSrobert /* Give names of register classes as strings for dump file. */ 434*404b540aSrobert 435*404b540aSrobert #define REG_CLASS_NAMES \ 436*404b540aSrobert { "NO_REGS", \ 437*404b540aSrobert "IREGS", \ 438*404b540aSrobert "BREGS", \ 439*404b540aSrobert "LREGS", \ 440*404b540aSrobert "MREGS", \ 441*404b540aSrobert "CIRCREGS", \ 442*404b540aSrobert "DAGREGS", \ 443*404b540aSrobert "EVEN_AREGS", \ 444*404b540aSrobert "ODD_AREGS", \ 445*404b540aSrobert "AREGS", \ 446*404b540aSrobert "CCREGS", \ 447*404b540aSrobert "EVEN_DREGS", \ 448*404b540aSrobert "ODD_DREGS", \ 449*404b540aSrobert "DREGS", \ 450*404b540aSrobert "FDPIC_REGS", \ 451*404b540aSrobert "FDPIC_FPTR_REGS", \ 452*404b540aSrobert "PREGS_CLOBBERED", \ 453*404b540aSrobert "PREGS", \ 454*404b540aSrobert "IPREGS", \ 455*404b540aSrobert "DPREGS", \ 456*404b540aSrobert "MOST_REGS", \ 457*404b540aSrobert "LT_REGS", \ 458*404b540aSrobert "LC_REGS", \ 459*404b540aSrobert "LB_REGS", \ 460*404b540aSrobert "PROLOGUE_REGS", \ 461*404b540aSrobert "NON_A_CC_REGS", \ 462*404b540aSrobert "ALL_REGS" } 463*404b540aSrobert 464*404b540aSrobert /* An initializer containing the contents of the register classes, as integers 465*404b540aSrobert which are bit masks. The Nth integer specifies the contents of class N. 466*404b540aSrobert The way the integer MASK is interpreted is that register R is in the class 467*404b540aSrobert if `MASK & (1 << R)' is 1. 468*404b540aSrobert 469*404b540aSrobert When the machine has more than 32 registers, an integer does not suffice. 470*404b540aSrobert Then the integers are replaced by sub-initializers, braced groupings 471*404b540aSrobert containing several integers. Each sub-initializer must be suitable as an 472*404b540aSrobert initializer for the type `HARD_REG_SET' which is defined in 473*404b540aSrobert `hard-reg-set.h'. */ 474*404b540aSrobert 475*404b540aSrobert /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use 476*404b540aSrobert MOST_REGS as the union of DPREGS and DAGREGS. */ 477*404b540aSrobert 478*404b540aSrobert #define REG_CLASS_CONTENTS \ 479*404b540aSrobert /* 31 - 0 63-32 */ \ 480*404b540aSrobert { { 0x00000000, 0 }, /* NO_REGS */ \ 481*404b540aSrobert { 0x000f0000, 0 }, /* IREGS */ \ 482*404b540aSrobert { 0x00f00000, 0 }, /* BREGS */ \ 483*404b540aSrobert { 0x0f000000, 0 }, /* LREGS */ \ 484*404b540aSrobert { 0xf0000000, 0 }, /* MREGS */ \ 485*404b540aSrobert { 0x0fff0000, 0 }, /* CIRCREGS */ \ 486*404b540aSrobert { 0xffff0000, 0 }, /* DAGREGS */ \ 487*404b540aSrobert { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ 488*404b540aSrobert { 0x00000000, 0x2 }, /* ODD_AREGS */ \ 489*404b540aSrobert { 0x00000000, 0x3 }, /* AREGS */ \ 490*404b540aSrobert { 0x00000000, 0x4 }, /* CCREGS */ \ 491*404b540aSrobert { 0x00000055, 0 }, /* EVEN_DREGS */ \ 492*404b540aSrobert { 0x000000aa, 0 }, /* ODD_DREGS */ \ 493*404b540aSrobert { 0x000000ff, 0 }, /* DREGS */ \ 494*404b540aSrobert { 0x00000800, 0x000 }, /* FDPIC_REGS */ \ 495*404b540aSrobert { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \ 496*404b540aSrobert { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ 497*404b540aSrobert { 0x0000ff00, 0x800 }, /* PREGS */ \ 498*404b540aSrobert { 0x000fff00, 0x800 }, /* IPREGS */ \ 499*404b540aSrobert { 0x0000ffff, 0x800 }, /* DPREGS */ \ 500*404b540aSrobert { 0xffffffff, 0x800 }, /* MOST_REGS */\ 501*404b540aSrobert { 0x00000000, 0x3000 }, /* LT_REGS */\ 502*404b540aSrobert { 0x00000000, 0xc000 }, /* LC_REGS */\ 503*404b540aSrobert { 0x00000000, 0x30000 }, /* LB_REGS */\ 504*404b540aSrobert { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\ 505*404b540aSrobert { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\ 506*404b540aSrobert { 0xffffffff, 0x3ffff }} /* ALL_REGS */ 507*404b540aSrobert 508*404b540aSrobert #define IREG_POSSIBLE_P(OUTER) \ 509*404b540aSrobert ((OUTER) == POST_INC || (OUTER) == PRE_INC \ 510*404b540aSrobert || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \ 511*404b540aSrobert || (OUTER) == MEM || (OUTER) == ADDRESS) 512*404b540aSrobert 513*404b540aSrobert #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \ 514*404b540aSrobert ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS) 515*404b540aSrobert 516*404b540aSrobert #define INDEX_REG_CLASS PREGS 517*404b540aSrobert 518*404b540aSrobert #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \ 519*404b540aSrobert (P_REGNO_P (X) || (X) == REG_ARGP \ 520*404b540aSrobert || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \ 521*404b540aSrobert && I_REGNO_P (X))) 522*404b540aSrobert 523*404b540aSrobert #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \ 524*404b540aSrobert ((X) >= FIRST_PSEUDO_REGISTER \ 525*404b540aSrobert || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)) 526*404b540aSrobert 527*404b540aSrobert #ifdef REG_OK_STRICT 528*404b540aSrobert #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \ 529*404b540aSrobert REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX) 530*404b540aSrobert #else 531*404b540aSrobert #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \ 532*404b540aSrobert REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX) 533*404b540aSrobert #endif 534*404b540aSrobert 535*404b540aSrobert #define REGNO_OK_FOR_INDEX_P(X) 0 536*404b540aSrobert 537*404b540aSrobert /* Get reg_class from a letter such as appears in the machine description. */ 538*404b540aSrobert 539*404b540aSrobert #define REG_CLASS_FROM_LETTER(LETTER) \ 540*404b540aSrobert ((LETTER) == 'a' ? PREGS : \ 541*404b540aSrobert (LETTER) == 'Z' ? FDPIC_REGS : \ 542*404b540aSrobert (LETTER) == 'Y' ? FDPIC_FPTR_REGS : \ 543*404b540aSrobert (LETTER) == 'd' ? DREGS : \ 544*404b540aSrobert (LETTER) == 'z' ? PREGS_CLOBBERED : \ 545*404b540aSrobert (LETTER) == 'D' ? EVEN_DREGS : \ 546*404b540aSrobert (LETTER) == 'W' ? ODD_DREGS : \ 547*404b540aSrobert (LETTER) == 'e' ? AREGS : \ 548*404b540aSrobert (LETTER) == 'A' ? EVEN_AREGS : \ 549*404b540aSrobert (LETTER) == 'B' ? ODD_AREGS : \ 550*404b540aSrobert (LETTER) == 'b' ? IREGS : \ 551*404b540aSrobert (LETTER) == 'v' ? BREGS : \ 552*404b540aSrobert (LETTER) == 'f' ? MREGS : \ 553*404b540aSrobert (LETTER) == 'c' ? CIRCREGS : \ 554*404b540aSrobert (LETTER) == 'C' ? CCREGS : \ 555*404b540aSrobert (LETTER) == 't' ? LT_REGS : \ 556*404b540aSrobert (LETTER) == 'k' ? LC_REGS : \ 557*404b540aSrobert (LETTER) == 'u' ? LB_REGS : \ 558*404b540aSrobert (LETTER) == 'x' ? MOST_REGS : \ 559*404b540aSrobert (LETTER) == 'y' ? PROLOGUE_REGS : \ 560*404b540aSrobert (LETTER) == 'w' ? NON_A_CC_REGS : \ 561*404b540aSrobert NO_REGS) 562*404b540aSrobert 563*404b540aSrobert /* The same information, inverted: 564*404b540aSrobert Return the class number of the smallest class containing 565*404b540aSrobert reg number REGNO. This could be a conditional expression 566*404b540aSrobert or could index an array. */ 567*404b540aSrobert 568*404b540aSrobert #define REGNO_REG_CLASS(REGNO) \ 569*404b540aSrobert ((REGNO) < REG_P0 ? DREGS \ 570*404b540aSrobert : (REGNO) < REG_I0 ? PREGS \ 571*404b540aSrobert : (REGNO) == REG_ARGP ? PREGS \ 572*404b540aSrobert : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ 573*404b540aSrobert : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ 574*404b540aSrobert : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ 575*404b540aSrobert : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ 576*404b540aSrobert : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ 577*404b540aSrobert : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \ 578*404b540aSrobert : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \ 579*404b540aSrobert : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \ 580*404b540aSrobert : (REGNO) == REG_CC ? CCREGS \ 581*404b540aSrobert : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ 582*404b540aSrobert : NO_REGS) 583*404b540aSrobert 584*404b540aSrobert /* When defined, the compiler allows registers explicitly used in the 585*404b540aSrobert rtl to be used as spill registers but prevents the compiler from 586*404b540aSrobert extending the lifetime of these registers. */ 587*404b540aSrobert #define SMALL_REGISTER_CLASSES 1 588*404b540aSrobert 589*404b540aSrobert #define CLASS_LIKELY_SPILLED_P(CLASS) \ 590*404b540aSrobert ((CLASS) == PREGS_CLOBBERED \ 591*404b540aSrobert || (CLASS) == PROLOGUE_REGS \ 592*404b540aSrobert || (CLASS) == CCREGS) 593*404b540aSrobert 594*404b540aSrobert /* Do not allow to store a value in REG_CC for any mode */ 595*404b540aSrobert /* Do not allow to store value in pregs if mode is not SI*/ 596*404b540aSrobert #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE)) 597*404b540aSrobert 598*404b540aSrobert /* Return the maximum number of consecutive registers 599*404b540aSrobert needed to represent mode MODE in a register of class CLASS. */ 600*404b540aSrobert #define CLASS_MAX_NREGS(CLASS, MODE) \ 601*404b540aSrobert ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \ 602*404b540aSrobert : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 603*404b540aSrobert 604*404b540aSrobert #define HARD_REGNO_NREGS(REGNO, MODE) \ 605*404b540aSrobert ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \ 606*404b540aSrobert : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \ 607*404b540aSrobert : CLASS_MAX_NREGS (GENERAL_REGS, MODE)) 608*404b540aSrobert 609*404b540aSrobert /* A C expression that is nonzero if hard register TO can be 610*404b540aSrobert considered for use as a rename register for FROM register */ 611*404b540aSrobert #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) 612*404b540aSrobert 613*404b540aSrobert /* A C expression that is nonzero if it is desirable to choose 614*404b540aSrobert register allocation so as to avoid move instructions between a 615*404b540aSrobert value of mode MODE1 and a value of mode MODE2. 616*404b540aSrobert 617*404b540aSrobert If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 618*404b540aSrobert MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 619*404b540aSrobert MODE2)' must be zero. */ 620*404b540aSrobert #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) 621*404b540aSrobert 622*404b540aSrobert /* `PREFERRED_RELOAD_CLASS (X, CLASS)' 623*404b540aSrobert A C expression that places additional restrictions on the register 624*404b540aSrobert class to use when it is necessary to copy value X into a register 625*404b540aSrobert in class CLASS. The value is a register class; perhaps CLASS, or 626*404b540aSrobert perhaps another, smaller class. */ 627*404b540aSrobert #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) 628*404b540aSrobert 629*404b540aSrobert /* Function Calling Conventions. */ 630*404b540aSrobert 631*404b540aSrobert /* The type of the current function; normal functions are of type 632*404b540aSrobert SUBROUTINE. */ 633*404b540aSrobert typedef enum { 634*404b540aSrobert SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER 635*404b540aSrobert } e_funkind; 636*404b540aSrobert 637*404b540aSrobert #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } 638*404b540aSrobert 639*404b540aSrobert /* Flags for the call/call_value rtl operations set up by function_arg */ 640*404b540aSrobert #define CALL_NORMAL 0x00000000 /* no special processing */ 641*404b540aSrobert #define CALL_LONG 0x00000001 /* always call indirect */ 642*404b540aSrobert #define CALL_SHORT 0x00000002 /* always call by symbol */ 643*404b540aSrobert 644*404b540aSrobert typedef struct { 645*404b540aSrobert int words; /* # words passed so far */ 646*404b540aSrobert int nregs; /* # registers available for passing */ 647*404b540aSrobert int *arg_regs; /* array of register -1 terminated */ 648*404b540aSrobert int call_cookie; /* Do special things for this call */ 649*404b540aSrobert } CUMULATIVE_ARGS; 650*404b540aSrobert 651*404b540aSrobert /* Define where to put the arguments to a function. 652*404b540aSrobert Value is zero to push the argument on the stack, 653*404b540aSrobert or a hard register in which to store the argument. 654*404b540aSrobert 655*404b540aSrobert MODE is the argument's machine mode. 656*404b540aSrobert TYPE is the data type of the argument (as a tree). 657*404b540aSrobert This is null for libcalls where that information may 658*404b540aSrobert not be available. 659*404b540aSrobert CUM is a variable of type CUMULATIVE_ARGS which gives info about 660*404b540aSrobert the preceding args and about the function being called. 661*404b540aSrobert NAMED is nonzero if this argument is a named parameter 662*404b540aSrobert (otherwise it is an extra parameter matching an ellipsis). */ 663*404b540aSrobert 664*404b540aSrobert #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 665*404b540aSrobert (function_arg (&CUM, MODE, TYPE, NAMED)) 666*404b540aSrobert 667*404b540aSrobert #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) 668*404b540aSrobert 669*404b540aSrobert 670*404b540aSrobert /* Initialize a variable CUM of type CUMULATIVE_ARGS 671*404b540aSrobert for a call to a function whose data type is FNTYPE. 672*404b540aSrobert For a library call, FNTYPE is 0. */ 673*404b540aSrobert #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ 674*404b540aSrobert (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 675*404b540aSrobert 676*404b540aSrobert /* Update the data in CUM to advance over an argument 677*404b540aSrobert of mode MODE and data type TYPE. 678*404b540aSrobert (TYPE is null for libcalls where that information may not be available.) */ 679*404b540aSrobert #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 680*404b540aSrobert (function_arg_advance (&CUM, MODE, TYPE, NAMED)) 681*404b540aSrobert 682*404b540aSrobert #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0 683*404b540aSrobert 684*404b540aSrobert /* Define how to find the value returned by a function. 685*404b540aSrobert VALTYPE is the data type of the value (as a tree). 686*404b540aSrobert If the precise function being called is known, FUNC is its FUNCTION_DECL; 687*404b540aSrobert otherwise, FUNC is 0. 688*404b540aSrobert */ 689*404b540aSrobert 690*404b540aSrobert #define VALUE_REGNO(MODE) (REG_R0) 691*404b540aSrobert 692*404b540aSrobert #define FUNCTION_VALUE(VALTYPE, FUNC) \ 693*404b540aSrobert gen_rtx_REG (TYPE_MODE (VALTYPE), \ 694*404b540aSrobert VALUE_REGNO(TYPE_MODE(VALTYPE))) 695*404b540aSrobert 696*404b540aSrobert /* Define how to find the value returned by a library function 697*404b540aSrobert assuming the value has mode MODE. */ 698*404b540aSrobert 699*404b540aSrobert #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) 700*404b540aSrobert 701*404b540aSrobert #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) 702*404b540aSrobert 703*404b540aSrobert #define DEFAULT_PCC_STRUCT_RETURN 0 704*404b540aSrobert #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE) 705*404b540aSrobert 706*404b540aSrobert /* Before the prologue, the return address is in the RETS register. */ 707*404b540aSrobert #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) 708*404b540aSrobert 709*404b540aSrobert #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) 710*404b540aSrobert 711*404b540aSrobert #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) 712*404b540aSrobert 713*404b540aSrobert /* Call instructions don't modify the stack pointer on the Blackfin. */ 714*404b540aSrobert #define INCOMING_FRAME_SP_OFFSET 0 715*404b540aSrobert 716*404b540aSrobert /* Describe how we implement __builtin_eh_return. */ 717*404b540aSrobert #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 718*404b540aSrobert #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) 719*404b540aSrobert #define EH_RETURN_HANDLER_RTX \ 720*404b540aSrobert gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD)) 721*404b540aSrobert 722*404b540aSrobert /* Addressing Modes */ 723*404b540aSrobert 724*404b540aSrobert /* Recognize any constant value that is a valid address. */ 725*404b540aSrobert #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) 726*404b540aSrobert 727*404b540aSrobert /* Nonzero if the constant value X is a legitimate general operand. 728*404b540aSrobert symbol_ref are not legitimate and will be put into constant pool. 729*404b540aSrobert See force_const_mem(). 730*404b540aSrobert If -mno-pool, all constants are legitimate. 731*404b540aSrobert */ 732*404b540aSrobert #define LEGITIMATE_CONSTANT_P(x) 1 733*404b540aSrobert 734*404b540aSrobert /* A number, the maximum number of registers that can appear in a 735*404b540aSrobert valid memory address. Note that it is up to you to specify a 736*404b540aSrobert value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS' 737*404b540aSrobert would ever accept. */ 738*404b540aSrobert #define MAX_REGS_PER_ADDRESS 1 739*404b540aSrobert 740*404b540aSrobert /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 741*404b540aSrobert that is a valid memory address for an instruction. 742*404b540aSrobert The MODE argument is the machine mode for the MEM expression 743*404b540aSrobert that wants to use this address. 744*404b540aSrobert 745*404b540aSrobert Blackfin addressing modes are as follows: 746*404b540aSrobert 747*404b540aSrobert [preg] 748*404b540aSrobert [preg + imm16] 749*404b540aSrobert 750*404b540aSrobert B [ Preg + uimm15 ] 751*404b540aSrobert W [ Preg + uimm16m2 ] 752*404b540aSrobert [ Preg + uimm17m4 ] 753*404b540aSrobert 754*404b540aSrobert [preg++] 755*404b540aSrobert [preg--] 756*404b540aSrobert [--sp] 757*404b540aSrobert */ 758*404b540aSrobert 759*404b540aSrobert #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ 760*404b540aSrobert (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) 761*404b540aSrobert 762*404b540aSrobert #ifdef REG_OK_STRICT 763*404b540aSrobert #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 764*404b540aSrobert do { \ 765*404b540aSrobert if (bfin_legitimate_address_p (MODE, X, 1)) \ 766*404b540aSrobert goto WIN; \ 767*404b540aSrobert } while (0); 768*404b540aSrobert #else 769*404b540aSrobert #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 770*404b540aSrobert do { \ 771*404b540aSrobert if (bfin_legitimate_address_p (MODE, X, 0)) \ 772*404b540aSrobert goto WIN; \ 773*404b540aSrobert } while (0); 774*404b540aSrobert #endif 775*404b540aSrobert 776*404b540aSrobert /* Try machine-dependent ways of modifying an illegitimate address 777*404b540aSrobert to be legitimate. If we find one, return the new, valid address. 778*404b540aSrobert This macro is used in only one place: `memory_address' in explow.c. 779*404b540aSrobert 780*404b540aSrobert OLDX is the address as it was before break_out_memory_refs was called. 781*404b540aSrobert In some cases it is useful to look at this to decide what needs to be done. 782*404b540aSrobert 783*404b540aSrobert MODE and WIN are passed so that this macro can use 784*404b540aSrobert GO_IF_LEGITIMATE_ADDRESS. 785*404b540aSrobert 786*404b540aSrobert It is always safe for this macro to do nothing. It exists to recognize 787*404b540aSrobert opportunities to optimize the output. 788*404b540aSrobert */ 789*404b540aSrobert #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 790*404b540aSrobert do { \ 791*404b540aSrobert rtx _q = legitimize_address(X, OLDX, MODE); \ 792*404b540aSrobert if (_q) { X = _q; goto WIN; } \ 793*404b540aSrobert } while (0) 794*404b540aSrobert 795*404b540aSrobert #define HAVE_POST_INCREMENT 1 796*404b540aSrobert #define HAVE_POST_DECREMENT 1 797*404b540aSrobert #define HAVE_PRE_DECREMENT 1 798*404b540aSrobert 799*404b540aSrobert /* `LEGITIMATE_PIC_OPERAND_P (X)' 800*404b540aSrobert A C expression that is nonzero if X is a legitimate immediate 801*404b540aSrobert operand on the target machine when generating position independent 802*404b540aSrobert code. You can assume that X satisfies `CONSTANT_P', so you need 803*404b540aSrobert not check this. You can also assume FLAG_PIC is true, so you need 804*404b540aSrobert not check it either. You need not define this macro if all 805*404b540aSrobert constants (including `SYMBOL_REF') can be immediate operands when 806*404b540aSrobert generating position independent code. */ 807*404b540aSrobert #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) 808*404b540aSrobert 809*404b540aSrobert #define SYMBOLIC_CONST(X) \ 810*404b540aSrobert (GET_CODE (X) == SYMBOL_REF \ 811*404b540aSrobert || GET_CODE (X) == LABEL_REF \ 812*404b540aSrobert || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 813*404b540aSrobert 814*404b540aSrobert /* 815*404b540aSrobert A C statement or compound statement with a conditional `goto 816*404b540aSrobert LABEL;' executed if memory address X (an RTX) can have different 817*404b540aSrobert meanings depending on the machine mode of the memory reference it 818*404b540aSrobert is used for or if the address is valid for some modes but not 819*404b540aSrobert others. 820*404b540aSrobert 821*404b540aSrobert Autoincrement and autodecrement addresses typically have 822*404b540aSrobert mode-dependent effects because the amount of the increment or 823*404b540aSrobert decrement is the size of the operand being addressed. Some 824*404b540aSrobert machines have other mode-dependent addresses. Many RISC machines 825*404b540aSrobert have no mode-dependent addresses. 826*404b540aSrobert 827*404b540aSrobert You may assume that ADDR is a valid address for the machine. 828*404b540aSrobert */ 829*404b540aSrobert #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 830*404b540aSrobert do { \ 831*404b540aSrobert if (GET_CODE (ADDR) == POST_INC \ 832*404b540aSrobert || GET_CODE (ADDR) == POST_DEC \ 833*404b540aSrobert || GET_CODE (ADDR) == PRE_DEC) \ 834*404b540aSrobert goto LABEL; \ 835*404b540aSrobert } while (0) 836*404b540aSrobert 837*404b540aSrobert #define NOTICE_UPDATE_CC(EXPR, INSN) 0 838*404b540aSrobert 839*404b540aSrobert /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 840*404b540aSrobert is done just by pretending it is already truncated. */ 841*404b540aSrobert #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 842*404b540aSrobert 843*404b540aSrobert /* Max number of bytes we can move from memory to memory 844*404b540aSrobert in one reasonably fast instruction. */ 845*404b540aSrobert #define MOVE_MAX UNITS_PER_WORD 846*404b540aSrobert 847*404b540aSrobert 848*404b540aSrobert /* STORAGE LAYOUT: target machine storage layout 849*404b540aSrobert Define this macro as a C expression which is nonzero if accessing 850*404b540aSrobert less than a word of memory (i.e. a `char' or a `short') is no 851*404b540aSrobert faster than accessing a word of memory, i.e., if such access 852*404b540aSrobert require more than one instruction or if there is no difference in 853*404b540aSrobert cost between byte and (aligned) word loads. 854*404b540aSrobert 855*404b540aSrobert When this macro is not defined, the compiler will access a field by 856*404b540aSrobert finding the smallest containing object; when it is defined, a 857*404b540aSrobert fullword load will be used if alignment permits. Unless bytes 858*404b540aSrobert accesses are faster than word accesses, using word accesses is 859*404b540aSrobert preferable since it may eliminate subsequent memory access if 860*404b540aSrobert subsequent accesses occur to other fields in the same word of the 861*404b540aSrobert structure, but to different bytes. */ 862*404b540aSrobert #define SLOW_BYTE_ACCESS 0 863*404b540aSrobert #define SLOW_SHORT_ACCESS 0 864*404b540aSrobert 865*404b540aSrobert /* Define this if most significant bit is lowest numbered 866*404b540aSrobert in instructions that operate on numbered bit-fields. */ 867*404b540aSrobert #define BITS_BIG_ENDIAN 0 868*404b540aSrobert 869*404b540aSrobert /* Define this if most significant byte of a word is the lowest numbered. 870*404b540aSrobert We can't access bytes but if we could we would in the Big Endian order. */ 871*404b540aSrobert #define BYTES_BIG_ENDIAN 0 872*404b540aSrobert 873*404b540aSrobert /* Define this if most significant word of a multiword number is numbered. */ 874*404b540aSrobert #define WORDS_BIG_ENDIAN 0 875*404b540aSrobert 876*404b540aSrobert /* number of bits in an addressable storage unit */ 877*404b540aSrobert #define BITS_PER_UNIT 8 878*404b540aSrobert 879*404b540aSrobert /* Width in bits of a "word", which is the contents of a machine register. 880*404b540aSrobert Note that this is not necessarily the width of data type `int'; 881*404b540aSrobert if using 16-bit ints on a 68000, this would still be 32. 882*404b540aSrobert But on a machine with 16-bit registers, this would be 16. */ 883*404b540aSrobert #define BITS_PER_WORD 32 884*404b540aSrobert 885*404b540aSrobert /* Width of a word, in units (bytes). */ 886*404b540aSrobert #define UNITS_PER_WORD 4 887*404b540aSrobert 888*404b540aSrobert /* Width in bits of a pointer. 889*404b540aSrobert See also the macro `Pmode1' defined below. */ 890*404b540aSrobert #define POINTER_SIZE 32 891*404b540aSrobert 892*404b540aSrobert /* Allocation boundary (in *bits*) for storing pointers in memory. */ 893*404b540aSrobert #define POINTER_BOUNDARY 32 894*404b540aSrobert 895*404b540aSrobert /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 896*404b540aSrobert #define PARM_BOUNDARY 32 897*404b540aSrobert 898*404b540aSrobert /* Boundary (in *bits*) on which stack pointer should be aligned. */ 899*404b540aSrobert #define STACK_BOUNDARY 32 900*404b540aSrobert 901*404b540aSrobert /* Allocation boundary (in *bits*) for the code of a function. */ 902*404b540aSrobert #define FUNCTION_BOUNDARY 32 903*404b540aSrobert 904*404b540aSrobert /* Alignment of field after `int : 0' in a structure. */ 905*404b540aSrobert #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 906*404b540aSrobert 907*404b540aSrobert /* No data type wants to be aligned rounder than this. */ 908*404b540aSrobert #define BIGGEST_ALIGNMENT 32 909*404b540aSrobert 910*404b540aSrobert /* Define this if move instructions will actually fail to work 911*404b540aSrobert when given unaligned data. */ 912*404b540aSrobert #define STRICT_ALIGNMENT 1 913*404b540aSrobert 914*404b540aSrobert /* (shell-command "rm c-decl.o stor-layout.o") 915*404b540aSrobert * never define PCC_BITFIELD_TYPE_MATTERS 916*404b540aSrobert * really cause some alignment problem 917*404b540aSrobert */ 918*404b540aSrobert 919*404b540aSrobert #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 920*404b540aSrobert BITS_PER_UNIT) 921*404b540aSrobert 922*404b540aSrobert #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 923*404b540aSrobert BITS_PER_UNIT) 924*404b540aSrobert 925*404b540aSrobert 926*404b540aSrobert /* what is the 'type' of size_t */ 927*404b540aSrobert #define SIZE_TYPE "long unsigned int" 928*404b540aSrobert 929*404b540aSrobert /* Define this as 1 if `char' should by default be signed; else as 0. */ 930*404b540aSrobert #define DEFAULT_SIGNED_CHAR 1 931*404b540aSrobert #define FLOAT_TYPE_SIZE BITS_PER_WORD 932*404b540aSrobert #define SHORT_TYPE_SIZE 16 933*404b540aSrobert #define CHAR_TYPE_SIZE 8 934*404b540aSrobert #define INT_TYPE_SIZE 32 935*404b540aSrobert #define LONG_TYPE_SIZE 32 936*404b540aSrobert #define LONG_LONG_TYPE_SIZE 64 937*404b540aSrobert 938*404b540aSrobert /* Note: Fix this to depend on target switch. -- lev */ 939*404b540aSrobert 940*404b540aSrobert /* Note: Try to implement double and force long double. -- tonyko 941*404b540aSrobert * #define __DOUBLES_ARE_FLOATS__ 942*404b540aSrobert * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE 943*404b540aSrobert * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE 944*404b540aSrobert * #define DOUBLES_ARE_FLOATS 1 945*404b540aSrobert */ 946*404b540aSrobert 947*404b540aSrobert #define DOUBLE_TYPE_SIZE 64 948*404b540aSrobert #define LONG_DOUBLE_TYPE_SIZE 64 949*404b540aSrobert 950*404b540aSrobert /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' 951*404b540aSrobert A macro to update M and UNSIGNEDP when an object whose type is 952*404b540aSrobert TYPE and which has the specified mode and signedness is to be 953*404b540aSrobert stored in a register. This macro is only called when TYPE is a 954*404b540aSrobert scalar type. 955*404b540aSrobert 956*404b540aSrobert On most RISC machines, which only have operations that operate on 957*404b540aSrobert a full register, define this macro to set M to `word_mode' if M is 958*404b540aSrobert an integer mode narrower than `BITS_PER_WORD'. In most cases, 959*404b540aSrobert only integer modes should be widened because wider-precision 960*404b540aSrobert floating-point operations are usually more expensive than their 961*404b540aSrobert narrower counterparts. 962*404b540aSrobert 963*404b540aSrobert For most machines, the macro definition does not change UNSIGNEDP. 964*404b540aSrobert However, some machines, have instructions that preferentially 965*404b540aSrobert handle either signed or unsigned quantities of certain modes. For 966*404b540aSrobert example, on the DEC Alpha, 32-bit loads from memory and 32-bit add 967*404b540aSrobert instructions sign-extend the result to 64 bits. On such machines, 968*404b540aSrobert set UNSIGNEDP according to which kind of extension is more 969*404b540aSrobert efficient. 970*404b540aSrobert 971*404b540aSrobert Do not define this macro if it would never modify M.*/ 972*404b540aSrobert 973*404b540aSrobert #define BFIN_PROMOTE_MODE_P(MODE) \ 974*404b540aSrobert (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ 975*404b540aSrobert && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) 976*404b540aSrobert 977*404b540aSrobert #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 978*404b540aSrobert if (BFIN_PROMOTE_MODE_P(MODE)) \ 979*404b540aSrobert { \ 980*404b540aSrobert if (MODE == QImode) \ 981*404b540aSrobert UNSIGNEDP = 1; \ 982*404b540aSrobert else if (MODE == HImode) \ 983*404b540aSrobert UNSIGNEDP = 0; \ 984*404b540aSrobert (MODE) = SImode; \ 985*404b540aSrobert } 986*404b540aSrobert 987*404b540aSrobert /* Describing Relative Costs of Operations */ 988*404b540aSrobert 989*404b540aSrobert /* Do not put function addr into constant pool */ 990*404b540aSrobert #define NO_FUNCTION_CSE 1 991*404b540aSrobert 992*404b540aSrobert /* A C expression for the cost of moving data from a register in class FROM to 993*404b540aSrobert one in class TO. The classes are expressed using the enumeration values 994*404b540aSrobert such as `GENERAL_REGS'. A value of 2 is the default; other values are 995*404b540aSrobert interpreted relative to that. 996*404b540aSrobert 997*404b540aSrobert It is not required that the cost always equal 2 when FROM is the same as TO; 998*404b540aSrobert on some machines it is expensive to move between registers if they are not 999*404b540aSrobert general registers. */ 1000*404b540aSrobert 1001*404b540aSrobert #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1002*404b540aSrobert bfin_register_move_cost ((MODE), (CLASS1), (CLASS2)) 1003*404b540aSrobert 1004*404b540aSrobert /* A C expression for the cost of moving data of mode M between a 1005*404b540aSrobert register and memory. A value of 2 is the default; this cost is 1006*404b540aSrobert relative to those in `REGISTER_MOVE_COST'. 1007*404b540aSrobert 1008*404b540aSrobert If moving between registers and memory is more expensive than 1009*404b540aSrobert between two registers, you should define this macro to express the 1010*404b540aSrobert relative cost. */ 1011*404b540aSrobert 1012*404b540aSrobert #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 1013*404b540aSrobert bfin_memory_move_cost ((MODE), (CLASS), (IN)) 1014*404b540aSrobert 1015*404b540aSrobert /* Specify the machine mode that this machine uses 1016*404b540aSrobert for the index in the tablejump instruction. */ 1017*404b540aSrobert #define CASE_VECTOR_MODE SImode 1018*404b540aSrobert 1019*404b540aSrobert #define JUMP_TABLES_IN_TEXT_SECTION flag_pic 1020*404b540aSrobert 1021*404b540aSrobert /* Define if operations between registers always perform the operation 1022*404b540aSrobert on the full register even if a narrower mode is specified. 1023*404b540aSrobert #define WORD_REGISTER_OPERATIONS 1024*404b540aSrobert */ 1025*404b540aSrobert 1026*404b540aSrobert #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140) 1027*404b540aSrobert #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767) 1028*404b540aSrobert #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535) 1029*404b540aSrobert #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63) 1030*404b540aSrobert #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0) 1031*404b540aSrobert #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31) 1032*404b540aSrobert #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7) 1033*404b540aSrobert #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15) 1034*404b540aSrobert #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3) 1035*404b540aSrobert #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7) 1036*404b540aSrobert 1037*404b540aSrobert #define CONSTRAINT_LEN(C, STR) \ 1038*404b540aSrobert ((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2 \ 1039*404b540aSrobert : (C) == 'K' ? 3 \ 1040*404b540aSrobert : DEFAULT_CONSTRAINT_LEN ((C), (STR))) 1041*404b540aSrobert 1042*404b540aSrobert #define CONST_OK_FOR_P(VALUE, STR) \ 1043*404b540aSrobert ((STR)[1] == '0' ? (VALUE) == 0 \ 1044*404b540aSrobert : (STR)[1] == '1' ? (VALUE) == 1 \ 1045*404b540aSrobert : (STR)[1] == '2' ? (VALUE) == 2 \ 1046*404b540aSrobert : (STR)[1] == '3' ? (VALUE) == 3 \ 1047*404b540aSrobert : (STR)[1] == '4' ? (VALUE) == 4 \ 1048*404b540aSrobert : 0) 1049*404b540aSrobert 1050*404b540aSrobert #define CONST_OK_FOR_K(VALUE, STR) \ 1051*404b540aSrobert ((STR)[1] == 'u' \ 1052*404b540aSrobert ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \ 1053*404b540aSrobert : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \ 1054*404b540aSrobert : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \ 1055*404b540aSrobert : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \ 1056*404b540aSrobert : 0) \ 1057*404b540aSrobert : (STR)[1] == 's' \ 1058*404b540aSrobert ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \ 1059*404b540aSrobert : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \ 1060*404b540aSrobert : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \ 1061*404b540aSrobert : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \ 1062*404b540aSrobert : 0) \ 1063*404b540aSrobert : (STR)[1] == 'n' \ 1064*404b540aSrobert ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \ 1065*404b540aSrobert : 0) \ 1066*404b540aSrobert : (STR)[1] == 'N' \ 1067*404b540aSrobert ? ((STR)[2] == '7' ? CONST_7BIT_IMM_P (-(VALUE)) \ 1068*404b540aSrobert : 0) \ 1069*404b540aSrobert : 0) 1070*404b540aSrobert 1071*404b540aSrobert #define CONST_OK_FOR_M(VALUE, STR) \ 1072*404b540aSrobert ((STR)[1] == '1' ? (VALUE) == 255 \ 1073*404b540aSrobert : (STR)[1] == '2' ? (VALUE) == 65535 \ 1074*404b540aSrobert : 0) 1075*404b540aSrobert 1076*404b540aSrobert /* The letters I, J, K, L and M in a register constraint string 1077*404b540aSrobert can be used to stand for particular ranges of immediate operands. 1078*404b540aSrobert This macro defines what the ranges are. 1079*404b540aSrobert C is the letter, and VALUE is a constant value. 1080*404b540aSrobert Return 1 if VALUE is in the range specified by C. 1081*404b540aSrobert 1082*404b540aSrobert bfin constant operands are as follows 1083*404b540aSrobert 1084*404b540aSrobert J 2**N 5bit imm scaled 1085*404b540aSrobert Ks7 -64 .. 63 signed 7bit imm 1086*404b540aSrobert Ku5 0..31 unsigned 5bit imm 1087*404b540aSrobert Ks4 -8 .. 7 signed 4bit imm 1088*404b540aSrobert Ks3 -4 .. 3 signed 3bit imm 1089*404b540aSrobert Ku3 0 .. 7 unsigned 3bit imm 1090*404b540aSrobert Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n 1091*404b540aSrobert */ 1092*404b540aSrobert #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \ 1093*404b540aSrobert ((C) == 'J' ? (log2constp (VALUE)) \ 1094*404b540aSrobert : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \ 1095*404b540aSrobert : (C) == 'L' ? log2constp (~(VALUE)) \ 1096*404b540aSrobert : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \ 1097*404b540aSrobert : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \ 1098*404b540aSrobert : 0) 1099*404b540aSrobert 1100*404b540aSrobert /*Constant Output Formats */ 1101*404b540aSrobert #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1102*404b540aSrobert ((C) == 'H' ? 1 : 0) 1103*404b540aSrobert 1104*404b540aSrobert #define EXTRA_CONSTRAINT(VALUE, D) \ 1105*404b540aSrobert ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0) 1106*404b540aSrobert 1107*404b540aSrobert /* Switch into a generic section. */ 1108*404b540aSrobert #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section 1109*404b540aSrobert 1110*404b540aSrobert #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) 1111*404b540aSrobert #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) 1112*404b540aSrobert 1113*404b540aSrobert typedef enum sections { 1114*404b540aSrobert CODE_DIR, 1115*404b540aSrobert DATA_DIR, 1116*404b540aSrobert LAST_SECT_NM 1117*404b540aSrobert } SECT_ENUM_T; 1118*404b540aSrobert 1119*404b540aSrobert typedef enum directives { 1120*404b540aSrobert LONG_CONST_DIR, 1121*404b540aSrobert SHORT_CONST_DIR, 1122*404b540aSrobert BYTE_CONST_DIR, 1123*404b540aSrobert SPACE_DIR, 1124*404b540aSrobert INIT_DIR, 1125*404b540aSrobert LAST_DIR_NM 1126*404b540aSrobert } DIR_ENUM_T; 1127*404b540aSrobert 1128*404b540aSrobert #define TEXT_SECTION_ASM_OP ".text;" 1129*404b540aSrobert #define DATA_SECTION_ASM_OP ".data;" 1130*404b540aSrobert 1131*404b540aSrobert #define ASM_APP_ON "" 1132*404b540aSrobert #define ASM_APP_OFF "" 1133*404b540aSrobert 1134*404b540aSrobert #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ 1135*404b540aSrobert do { fputs (".global ", FILE); \ 1136*404b540aSrobert assemble_name (FILE, NAME); \ 1137*404b540aSrobert fputc (';',FILE); \ 1138*404b540aSrobert fputc ('\n',FILE); \ 1139*404b540aSrobert } while (0) 1140*404b540aSrobert 1141*404b540aSrobert #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 1142*404b540aSrobert do { \ 1143*404b540aSrobert fputs (".type ", FILE); \ 1144*404b540aSrobert assemble_name (FILE, NAME); \ 1145*404b540aSrobert fputs (", STT_FUNC", FILE); \ 1146*404b540aSrobert fputc (';',FILE); \ 1147*404b540aSrobert fputc ('\n',FILE); \ 1148*404b540aSrobert ASM_OUTPUT_LABEL(FILE, NAME); \ 1149*404b540aSrobert } while (0) 1150*404b540aSrobert 1151*404b540aSrobert #define ASM_OUTPUT_LABEL(FILE, NAME) \ 1152*404b540aSrobert do { assemble_name (FILE, NAME); \ 1153*404b540aSrobert fputs (":\n",FILE); \ 1154*404b540aSrobert } while (0) 1155*404b540aSrobert 1156*404b540aSrobert #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1157*404b540aSrobert do { fprintf (FILE, "_%s", NAME); \ 1158*404b540aSrobert } while (0) 1159*404b540aSrobert 1160*404b540aSrobert #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1161*404b540aSrobert do { char __buf[256]; \ 1162*404b540aSrobert fprintf (FILE, "\t.dd\t"); \ 1163*404b540aSrobert ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1164*404b540aSrobert assemble_name (FILE, __buf); \ 1165*404b540aSrobert fputc (';', FILE); \ 1166*404b540aSrobert fputc ('\n', FILE); \ 1167*404b540aSrobert } while (0) 1168*404b540aSrobert 1169*404b540aSrobert #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1170*404b540aSrobert MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) 1171*404b540aSrobert 1172*404b540aSrobert #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1173*404b540aSrobert do { \ 1174*404b540aSrobert char __buf[256]; \ 1175*404b540aSrobert fprintf (FILE, "\t.dd\t"); \ 1176*404b540aSrobert ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1177*404b540aSrobert assemble_name (FILE, __buf); \ 1178*404b540aSrobert fputs (" - ", FILE); \ 1179*404b540aSrobert ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ 1180*404b540aSrobert assemble_name (FILE, __buf); \ 1181*404b540aSrobert fputc (';', FILE); \ 1182*404b540aSrobert fputc ('\n', FILE); \ 1183*404b540aSrobert } while (0) 1184*404b540aSrobert 1185*404b540aSrobert #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1186*404b540aSrobert do { \ 1187*404b540aSrobert if ((LOG) != 0) \ 1188*404b540aSrobert fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ 1189*404b540aSrobert } while (0) 1190*404b540aSrobert 1191*404b540aSrobert #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1192*404b540aSrobert do { \ 1193*404b540aSrobert asm_output_skip (FILE, SIZE); \ 1194*404b540aSrobert } while (0) 1195*404b540aSrobert 1196*404b540aSrobert #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1197*404b540aSrobert do { \ 1198*404b540aSrobert switch_to_section (data_section); \ 1199*404b540aSrobert if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ 1200*404b540aSrobert ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ 1201*404b540aSrobert ASM_OUTPUT_LABEL (FILE, NAME); \ 1202*404b540aSrobert fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ 1203*404b540aSrobert (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ 1204*404b540aSrobert } while (0) 1205*404b540aSrobert 1206*404b540aSrobert #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1207*404b540aSrobert do { \ 1208*404b540aSrobert ASM_GLOBALIZE_LABEL1(FILE,NAME); \ 1209*404b540aSrobert ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) 1210*404b540aSrobert 1211*404b540aSrobert #define ASM_COMMENT_START "//" 1212*404b540aSrobert 1213*404b540aSrobert #define FUNCTION_PROFILER(FILE, LABELNO) \ 1214*404b540aSrobert do { \ 1215*404b540aSrobert fprintf (FILE, "\tCALL __mcount;\n"); \ 1216*404b540aSrobert } while(0) 1217*404b540aSrobert 1218*404b540aSrobert #undef NO_PROFILE_COUNTERS 1219*404b540aSrobert #define NO_PROFILE_COUNTERS 1 1220*404b540aSrobert 1221*404b540aSrobert #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO]) 1222*404b540aSrobert #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO]) 1223*404b540aSrobert 1224*404b540aSrobert extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1; 1225*404b540aSrobert extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx; 1226*404b540aSrobert 1227*404b540aSrobert /* This works for GAS and some other assemblers. */ 1228*404b540aSrobert #define SET_ASM_OP ".set " 1229*404b540aSrobert 1230*404b540aSrobert /* DBX register number for a given compiler register number */ 1231*404b540aSrobert #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1232*404b540aSrobert 1233*404b540aSrobert #define SIZE_ASM_OP "\t.size\t" 1234*404b540aSrobert 1235*404b540aSrobert #endif /* _BFIN_CONFIG */ 1236