1*404b540aSrobert;; Predicate definitions for Renesas H8/300. 2*404b540aSrobert;; Copyright (C) 2005 Free Software Foundation, Inc. 3*404b540aSrobert;; 4*404b540aSrobert;; This file is part of GCC. 5*404b540aSrobert;; 6*404b540aSrobert;; GCC is free software; you can redistribute it and/or modify 7*404b540aSrobert;; it under the terms of the GNU General Public License as published by 8*404b540aSrobert;; the Free Software Foundation; either version 2, or (at your option) 9*404b540aSrobert;; any later version. 10*404b540aSrobert;; 11*404b540aSrobert;; GCC is distributed in the hope that it will be useful, 12*404b540aSrobert;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13*404b540aSrobert;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*404b540aSrobert;; GNU General Public License for more details. 15*404b540aSrobert;; 16*404b540aSrobert;; You should have received a copy of the GNU General Public License 17*404b540aSrobert;; along with GCC; see the file COPYING. If not, write to 18*404b540aSrobert;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19*404b540aSrobert;; Boston, MA 02110-1301, USA. 20*404b540aSrobert 21*404b540aSrobert;; Return true if OP is a valid source operand for an integer move 22*404b540aSrobert;; instruction. 23*404b540aSrobert 24*404b540aSrobert(define_predicate "general_operand_src" 25*404b540aSrobert (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem") 26*404b540aSrobert{ 27*404b540aSrobert if (GET_MODE (op) == mode 28*404b540aSrobert && GET_CODE (op) == MEM 29*404b540aSrobert && GET_CODE (XEXP (op, 0)) == POST_INC) 30*404b540aSrobert return 1; 31*404b540aSrobert return general_operand (op, mode); 32*404b540aSrobert}) 33*404b540aSrobert 34*404b540aSrobert;; Return true if OP is a valid destination operand for an integer 35*404b540aSrobert;; move instruction. 36*404b540aSrobert 37*404b540aSrobert(define_predicate "general_operand_dst" 38*404b540aSrobert (match_code "subreg,reg,mem") 39*404b540aSrobert{ 40*404b540aSrobert if (GET_MODE (op) == mode 41*404b540aSrobert && GET_CODE (op) == MEM 42*404b540aSrobert && GET_CODE (XEXP (op, 0)) == PRE_DEC) 43*404b540aSrobert return 1; 44*404b540aSrobert return general_operand (op, mode); 45*404b540aSrobert}) 46*404b540aSrobert 47*404b540aSrobert;; Likewise the second operand. 48*404b540aSrobert 49*404b540aSrobert(define_predicate "h8300_src_operand" 50*404b540aSrobert (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem") 51*404b540aSrobert{ 52*404b540aSrobert if (TARGET_H8300SX) 53*404b540aSrobert return general_operand (op, mode); 54*404b540aSrobert return nonmemory_operand (op, mode); 55*404b540aSrobert}) 56*404b540aSrobert 57*404b540aSrobert;; Return true if OP is a suitable first operand for a general 58*404b540aSrobert;; arithmetic insn such as "add". 59*404b540aSrobert 60*404b540aSrobert(define_predicate "h8300_dst_operand" 61*404b540aSrobert (match_code "subreg,reg,mem") 62*404b540aSrobert{ 63*404b540aSrobert if (TARGET_H8300SX) 64*404b540aSrobert return nonimmediate_operand (op, mode); 65*404b540aSrobert return register_operand (op, mode); 66*404b540aSrobert}) 67*404b540aSrobert 68*404b540aSrobert;; Check that an operand is either a register or an unsigned 4-bit 69*404b540aSrobert;; constant. 70*404b540aSrobert 71*404b540aSrobert(define_predicate "nibble_operand" 72*404b540aSrobert (match_code "const_int") 73*404b540aSrobert{ 74*404b540aSrobert return (GET_CODE (op) == CONST_INT && TARGET_H8300SX 75*404b540aSrobert && INTVAL (op) >= 0 && INTVAL (op) <= 15); 76*404b540aSrobert}) 77*404b540aSrobert 78*404b540aSrobert;; Check that an operand is either a register or an unsigned 4-bit 79*404b540aSrobert;; constant. 80*404b540aSrobert 81*404b540aSrobert(define_predicate "reg_or_nibble_operand" 82*404b540aSrobert (match_code "const_int,subreg,reg") 83*404b540aSrobert{ 84*404b540aSrobert return (nibble_operand (op, mode) || register_operand (op, mode)); 85*404b540aSrobert}) 86*404b540aSrobert 87*404b540aSrobert;; Return true if X is a shift operation of type H8SX_SHIFT_UNARY. 88*404b540aSrobert 89*404b540aSrobert(define_predicate "h8sx_unary_shift_operator" 90*404b540aSrobert (match_code "ashiftrt,lshiftrt,ashift,rotate") 91*404b540aSrobert{ 92*404b540aSrobert return (BINARY_P (op) && NON_COMMUTATIVE_P (op) 93*404b540aSrobert && (h8sx_classify_shift (GET_MODE (op), GET_CODE (op), XEXP (op, 1)) 94*404b540aSrobert == H8SX_SHIFT_UNARY)); 95*404b540aSrobert}) 96*404b540aSrobert 97*404b540aSrobert;; Likewise H8SX_SHIFT_BINARY. 98*404b540aSrobert 99*404b540aSrobert(define_predicate "h8sx_binary_shift_operator" 100*404b540aSrobert (match_code "ashiftrt,lshiftrt,ashift") 101*404b540aSrobert{ 102*404b540aSrobert return (BINARY_P (op) && NON_COMMUTATIVE_P (op) 103*404b540aSrobert && (h8sx_classify_shift (GET_MODE (op), GET_CODE (op), XEXP (op, 1)) 104*404b540aSrobert == H8SX_SHIFT_BINARY)); 105*404b540aSrobert}) 106*404b540aSrobert 107*404b540aSrobert;; Return true if OP is a binary operator in which it would be safe to 108*404b540aSrobert;; replace register operands with memory operands. 109*404b540aSrobert 110*404b540aSrobert(define_predicate "h8sx_binary_memory_operator" 111*404b540aSrobert (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt,rotate") 112*404b540aSrobert{ 113*404b540aSrobert if (!TARGET_H8300SX) 114*404b540aSrobert return false; 115*404b540aSrobert 116*404b540aSrobert if (GET_MODE (op) != QImode 117*404b540aSrobert && GET_MODE (op) != HImode 118*404b540aSrobert && GET_MODE (op) != SImode) 119*404b540aSrobert return false; 120*404b540aSrobert 121*404b540aSrobert switch (GET_CODE (op)) 122*404b540aSrobert { 123*404b540aSrobert case PLUS: 124*404b540aSrobert case MINUS: 125*404b540aSrobert case AND: 126*404b540aSrobert case IOR: 127*404b540aSrobert case XOR: 128*404b540aSrobert return true; 129*404b540aSrobert 130*404b540aSrobert default: 131*404b540aSrobert return h8sx_unary_shift_operator (op, mode); 132*404b540aSrobert } 133*404b540aSrobert}) 134*404b540aSrobert 135*404b540aSrobert;; Like h8sx_binary_memory_operator, but applies to unary operators. 136*404b540aSrobert 137*404b540aSrobert(define_predicate "h8sx_unary_memory_operator" 138*404b540aSrobert (match_code "neg,not") 139*404b540aSrobert{ 140*404b540aSrobert if (!TARGET_H8300SX) 141*404b540aSrobert return false; 142*404b540aSrobert 143*404b540aSrobert if (GET_MODE (op) != QImode 144*404b540aSrobert && GET_MODE (op) != HImode 145*404b540aSrobert && GET_MODE (op) != SImode) 146*404b540aSrobert return false; 147*404b540aSrobert 148*404b540aSrobert switch (GET_CODE (op)) 149*404b540aSrobert { 150*404b540aSrobert case NEG: 151*404b540aSrobert case NOT: 152*404b540aSrobert return true; 153*404b540aSrobert 154*404b540aSrobert default: 155*404b540aSrobert return false; 156*404b540aSrobert } 157*404b540aSrobert}) 158*404b540aSrobert 159*404b540aSrobert;; Return true if X is an ldm.l pattern. X is known to be parallel. 160*404b540aSrobert 161*404b540aSrobert(define_predicate "h8300_ldm_parallel" 162*404b540aSrobert (match_code "parallel") 163*404b540aSrobert{ 164*404b540aSrobert return h8300_ldm_stm_parallel (XVEC (op, 0), 1, 0); 165*404b540aSrobert}) 166*404b540aSrobert 167*404b540aSrobert;; Likewise stm.l. 168*404b540aSrobert 169*404b540aSrobert(define_predicate "h8300_stm_parallel" 170*404b540aSrobert (match_code "parallel") 171*404b540aSrobert{ 172*404b540aSrobert return h8300_ldm_stm_parallel (XVEC (op, 0), 0, 0); 173*404b540aSrobert}) 174*404b540aSrobert 175*404b540aSrobert;; Likewise rts/l and rte/l. Note that the .md pattern will check for 176*404b540aSrobert;; the return so there's no need to do that here. 177*404b540aSrobert 178*404b540aSrobert(define_predicate "h8300_return_parallel" 179*404b540aSrobert (match_code "parallel") 180*404b540aSrobert{ 181*404b540aSrobert return h8300_ldm_stm_parallel (XVEC (op, 0), 1, 1); 182*404b540aSrobert}) 183*404b540aSrobert 184*404b540aSrobert;; Return true if OP is a constant that contains only one 1 in its 185*404b540aSrobert;; binary representation. 186*404b540aSrobert 187*404b540aSrobert(define_predicate "single_one_operand" 188*404b540aSrobert (match_code "const_int") 189*404b540aSrobert{ 190*404b540aSrobert if (GET_CODE (op) == CONST_INT) 191*404b540aSrobert { 192*404b540aSrobert /* We really need to do this masking because 0x80 in QImode is 193*404b540aSrobert represented as -128 for example. */ 194*404b540aSrobert if (exact_log2 (INTVAL (op) & GET_MODE_MASK (mode)) >= 0) 195*404b540aSrobert return 1; 196*404b540aSrobert } 197*404b540aSrobert 198*404b540aSrobert return 0; 199*404b540aSrobert}) 200*404b540aSrobert 201*404b540aSrobert;; Return true if OP is a constant that contains only one 0 in its 202*404b540aSrobert;; binary representation. 203*404b540aSrobert 204*404b540aSrobert(define_predicate "single_zero_operand" 205*404b540aSrobert (match_code "const_int") 206*404b540aSrobert{ 207*404b540aSrobert if (GET_CODE (op) == CONST_INT) 208*404b540aSrobert { 209*404b540aSrobert /* We really need to do this masking because 0x80 in QImode is 210*404b540aSrobert represented as -128 for example. */ 211*404b540aSrobert if (exact_log2 (~INTVAL (op) & GET_MODE_MASK (mode)) >= 0) 212*404b540aSrobert return 1; 213*404b540aSrobert } 214*404b540aSrobert 215*404b540aSrobert return 0; 216*404b540aSrobert}) 217*404b540aSrobert 218*404b540aSrobert;; Return true if OP is a valid call operand. 219*404b540aSrobert 220*404b540aSrobert(define_predicate "call_insn_operand" 221*404b540aSrobert (match_code "mem") 222*404b540aSrobert{ 223*404b540aSrobert if (GET_CODE (op) == MEM) 224*404b540aSrobert { 225*404b540aSrobert rtx inside = XEXP (op, 0); 226*404b540aSrobert if (register_operand (inside, Pmode)) 227*404b540aSrobert return 1; 228*404b540aSrobert if (CONSTANT_ADDRESS_P (inside)) 229*404b540aSrobert return 1; 230*404b540aSrobert } 231*404b540aSrobert return 0; 232*404b540aSrobert}) 233*404b540aSrobert 234*404b540aSrobert;; Return true if OP is a valid call operand, and OP represents an 235*404b540aSrobert;; operand for a small call (4 bytes instead of 6 bytes). 236*404b540aSrobert 237*404b540aSrobert(define_predicate "small_call_insn_operand" 238*404b540aSrobert (match_code "mem") 239*404b540aSrobert{ 240*404b540aSrobert if (GET_CODE (op) == MEM) 241*404b540aSrobert { 242*404b540aSrobert rtx inside = XEXP (op, 0); 243*404b540aSrobert 244*404b540aSrobert /* Register indirect is a small call. */ 245*404b540aSrobert if (register_operand (inside, Pmode)) 246*404b540aSrobert return 1; 247*404b540aSrobert 248*404b540aSrobert /* A call through the function vector is a small call too. */ 249*404b540aSrobert if (GET_CODE (inside) == SYMBOL_REF 250*404b540aSrobert && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION)) 251*404b540aSrobert return 1; 252*404b540aSrobert } 253*404b540aSrobert /* Otherwise it's a large call. */ 254*404b540aSrobert return 0; 255*404b540aSrobert}) 256*404b540aSrobert 257*404b540aSrobert;; Return true if OP is a valid jump operand. 258*404b540aSrobert 259*404b540aSrobert(define_predicate "jump_address_operand" 260*404b540aSrobert (match_code "reg,mem") 261*404b540aSrobert{ 262*404b540aSrobert if (GET_CODE (op) == REG) 263*404b540aSrobert return mode == Pmode; 264*404b540aSrobert 265*404b540aSrobert if (GET_CODE (op) == MEM) 266*404b540aSrobert { 267*404b540aSrobert rtx inside = XEXP (op, 0); 268*404b540aSrobert if (register_operand (inside, Pmode)) 269*404b540aSrobert return 1; 270*404b540aSrobert if (CONSTANT_ADDRESS_P (inside)) 271*404b540aSrobert return 1; 272*404b540aSrobert } 273*404b540aSrobert return 0; 274*404b540aSrobert}) 275*404b540aSrobert 276*404b540aSrobert;; Return 1 if an addition/subtraction of a constant integer can be 277*404b540aSrobert;; transformed into two consecutive adds/subs that are faster than the 278*404b540aSrobert;; straightforward way. Otherwise, return 0. 279*404b540aSrobert 280*404b540aSrobert(define_predicate "two_insn_adds_subs_operand" 281*404b540aSrobert (match_code "const_int") 282*404b540aSrobert{ 283*404b540aSrobert if (TARGET_H8300SX) 284*404b540aSrobert return 0; 285*404b540aSrobert 286*404b540aSrobert if (GET_CODE (op) == CONST_INT) 287*404b540aSrobert { 288*404b540aSrobert HOST_WIDE_INT value = INTVAL (op); 289*404b540aSrobert 290*404b540aSrobert /* Force VALUE to be positive so that we do not have to consider 291*404b540aSrobert the negative case. */ 292*404b540aSrobert if (value < 0) 293*404b540aSrobert value = -value; 294*404b540aSrobert if (TARGET_H8300H || TARGET_H8300S) 295*404b540aSrobert { 296*404b540aSrobert /* A constant addition/subtraction takes 2 states in QImode, 297*404b540aSrobert 4 states in HImode, and 6 states in SImode. Thus, the 298*404b540aSrobert only case we can win is when SImode is used, in which 299*404b540aSrobert case, two adds/subs are used, taking 4 states. */ 300*404b540aSrobert if (mode == SImode 301*404b540aSrobert && (value == 2 + 1 302*404b540aSrobert || value == 4 + 1 303*404b540aSrobert || value == 4 + 2 304*404b540aSrobert || value == 4 + 4)) 305*404b540aSrobert return 1; 306*404b540aSrobert } 307*404b540aSrobert else 308*404b540aSrobert { 309*404b540aSrobert /* We do not profit directly by splitting addition or 310*404b540aSrobert subtraction of 3 and 4. However, since these are 311*404b540aSrobert implemented as a sequence of adds or subs, they do not 312*404b540aSrobert clobber (cc0) unlike a sequence of add.b and add.x. */ 313*404b540aSrobert if (mode == HImode 314*404b540aSrobert && (value == 2 + 1 315*404b540aSrobert || value == 2 + 2)) 316*404b540aSrobert return 1; 317*404b540aSrobert } 318*404b540aSrobert } 319*404b540aSrobert 320*404b540aSrobert return 0; 321*404b540aSrobert}) 322*404b540aSrobert 323*404b540aSrobert;; Recognize valid operands for bit-field instructions. 324*404b540aSrobert 325*404b540aSrobert(define_predicate "bit_operand" 326*404b540aSrobert (match_code "reg,subreg,mem") 327*404b540aSrobert{ 328*404b540aSrobert /* We can accept any nonimmediate operand, except that MEM operands must 329*404b540aSrobert be limited to those that use addresses valid for the 'U' constraint. */ 330*404b540aSrobert if (!nonimmediate_operand (op, mode)) 331*404b540aSrobert return 0; 332*404b540aSrobert 333*404b540aSrobert /* H8SX accepts pretty much anything here. */ 334*404b540aSrobert if (TARGET_H8300SX) 335*404b540aSrobert return 1; 336*404b540aSrobert 337*404b540aSrobert /* Accept any mem during RTL generation. Otherwise, the code that does 338*404b540aSrobert insv and extzv will think that we cannot handle memory. However, 339*404b540aSrobert to avoid reload problems, we only accept 'U' MEM operands after RTL 340*404b540aSrobert generation. This means that any named pattern which uses this predicate 341*404b540aSrobert must force its operands to match 'U' before emitting RTL. */ 342*404b540aSrobert 343*404b540aSrobert if (GET_CODE (op) == REG) 344*404b540aSrobert return 1; 345*404b540aSrobert if (GET_CODE (op) == SUBREG) 346*404b540aSrobert return 1; 347*404b540aSrobert return (GET_CODE (op) == MEM 348*404b540aSrobert && OK_FOR_U (op)); 349*404b540aSrobert}) 350*404b540aSrobert 351*404b540aSrobert;; Return nonzero if OP is a MEM suitable for bit manipulation insns. 352*404b540aSrobert 353*404b540aSrobert(define_predicate "bit_memory_operand" 354*404b540aSrobert (match_code "mem") 355*404b540aSrobert{ 356*404b540aSrobert return (GET_CODE (op) == MEM 357*404b540aSrobert && OK_FOR_U (op)); 358*404b540aSrobert}) 359*404b540aSrobert 360*404b540aSrobert;; Return nonzero if X is a stack pointer. 361*404b540aSrobert 362*404b540aSrobert(define_predicate "stack_pointer_operand" 363*404b540aSrobert (match_code "reg") 364*404b540aSrobert{ 365*404b540aSrobert return op == stack_pointer_rtx; 366*404b540aSrobert}) 367*404b540aSrobert 368*404b540aSrobert;; Return nonzero if X is a constant whose absolute value is greater 369*404b540aSrobert;; than 2. 370*404b540aSrobert 371*404b540aSrobert(define_predicate "const_int_gt_2_operand" 372*404b540aSrobert (match_code "const_int") 373*404b540aSrobert{ 374*404b540aSrobert return (GET_CODE (op) == CONST_INT 375*404b540aSrobert && abs (INTVAL (op)) > 2); 376*404b540aSrobert}) 377*404b540aSrobert 378*404b540aSrobert;; Return nonzero if X is a constant whose absolute value is no 379*404b540aSrobert;; smaller than 8. 380*404b540aSrobert 381*404b540aSrobert(define_predicate "const_int_ge_8_operand" 382*404b540aSrobert (match_code "const_int") 383*404b540aSrobert{ 384*404b540aSrobert return (GET_CODE (op) == CONST_INT 385*404b540aSrobert && abs (INTVAL (op)) >= 8); 386*404b540aSrobert}) 387*404b540aSrobert 388*404b540aSrobert;; Return nonzero if X is a constant expressible in QImode. 389*404b540aSrobert 390*404b540aSrobert(define_predicate "const_int_qi_operand" 391*404b540aSrobert (match_code "const_int") 392*404b540aSrobert{ 393*404b540aSrobert return (GET_CODE (op) == CONST_INT 394*404b540aSrobert && (INTVAL (op) & 0xff) == INTVAL (op)); 395*404b540aSrobert}) 396*404b540aSrobert 397*404b540aSrobert;; Return nonzero if X is a constant expressible in HImode. 398*404b540aSrobert 399*404b540aSrobert(define_predicate "const_int_hi_operand" 400*404b540aSrobert (match_code "const_int") 401*404b540aSrobert{ 402*404b540aSrobert return (GET_CODE (op) == CONST_INT 403*404b540aSrobert && (INTVAL (op) & 0xffff) == INTVAL (op)); 404*404b540aSrobert}) 405*404b540aSrobert 406*404b540aSrobert;; Return nonzero if X is a constant suitable for inc/dec. 407*404b540aSrobert 408*404b540aSrobert(define_predicate "incdec_operand" 409*404b540aSrobert (match_code "const_int") 410*404b540aSrobert{ 411*404b540aSrobert return (GET_CODE (op) == CONST_INT 412*404b540aSrobert && (CONST_OK_FOR_M (INTVAL (op)) 413*404b540aSrobert || CONST_OK_FOR_O (INTVAL (op)))); 414*404b540aSrobert}) 415*404b540aSrobert 416*404b540aSrobert;; Recognize valid operators for bit instructions. 417*404b540aSrobert 418*404b540aSrobert(define_predicate "bit_operator" 419*404b540aSrobert (match_code "xor,and,ior") 420*404b540aSrobert{ 421*404b540aSrobert enum rtx_code code = GET_CODE (op); 422*404b540aSrobert 423*404b540aSrobert return (code == XOR 424*404b540aSrobert || code == AND 425*404b540aSrobert || code == IOR); 426*404b540aSrobert}) 427*404b540aSrobert 428*404b540aSrobert;; Return nonzero if OP is a shift operator. 429*404b540aSrobert 430*404b540aSrobert(define_predicate "nshift_operator" 431*404b540aSrobert (match_code "ashiftrt,lshiftrt,ashift") 432*404b540aSrobert{ 433*404b540aSrobert switch (GET_CODE (op)) 434*404b540aSrobert { 435*404b540aSrobert case ASHIFTRT: 436*404b540aSrobert case LSHIFTRT: 437*404b540aSrobert case ASHIFT: 438*404b540aSrobert return 1; 439*404b540aSrobert 440*404b540aSrobert default: 441*404b540aSrobert return 0; 442*404b540aSrobert } 443*404b540aSrobert}) 444*404b540aSrobert 445*404b540aSrobert;; Return nonzero if X is either EQ or NE. 446*404b540aSrobert 447*404b540aSrobert(define_predicate "eqne_operator" 448*404b540aSrobert (match_code "eq,ne") 449*404b540aSrobert{ 450*404b540aSrobert enum rtx_code code = GET_CODE (op); 451*404b540aSrobert 452*404b540aSrobert return (code == EQ || code == NE); 453*404b540aSrobert}) 454*404b540aSrobert 455*404b540aSrobert;; Return nonzero if X is either GT or LE. 456*404b540aSrobert 457*404b540aSrobert(define_predicate "gtle_operator" 458*404b540aSrobert (match_code "gt,le,gtu,leu") 459*404b540aSrobert{ 460*404b540aSrobert enum rtx_code code = GET_CODE (op); 461*404b540aSrobert 462*404b540aSrobert return (code == GT || code == LE); 463*404b540aSrobert}) 464*404b540aSrobert 465*404b540aSrobert;; Return nonzero if X is either GTU or LEU. 466*404b540aSrobert 467*404b540aSrobert(define_predicate "gtuleu_operator" 468*404b540aSrobert (match_code "gtu,leu") 469*404b540aSrobert{ 470*404b540aSrobert enum rtx_code code = GET_CODE (op); 471*404b540aSrobert 472*404b540aSrobert return (code == GTU || code == LEU); 473*404b540aSrobert}) 474*404b540aSrobert 475*404b540aSrobert;; Return nonzero if X is either IOR or XOR. 476*404b540aSrobert 477*404b540aSrobert(define_predicate "iorxor_operator" 478*404b540aSrobert (match_code "ior,xor") 479*404b540aSrobert{ 480*404b540aSrobert enum rtx_code code = GET_CODE (op); 481*404b540aSrobert 482*404b540aSrobert return (code == IOR || code == XOR); 483*404b540aSrobert}) 484