1*404b540aSrobert;; 2*404b540aSrobert;; Pipeline description for the VR4130 family. 3*404b540aSrobert;; 4*404b540aSrobert;; The processor issues each 8-byte aligned pair of instructions together, 5*404b540aSrobert;; stalling the second instruction if it depends on the first. Thus, if we 6*404b540aSrobert;; want two instructions to issue in parallel, we need to make sure that the 7*404b540aSrobert;; first one is 8-byte aligned. 8*404b540aSrobert;; 9*404b540aSrobert;; For the purposes of this pipeline description, we treat the processor 10*404b540aSrobert;; like a standard two-way superscalar architecture. If scheduling were 11*404b540aSrobert;; the last pass to run, we could use the scheduler hooks to vary the 12*404b540aSrobert;; issue rate depending on whether an instruction is at an aligned or 13*404b540aSrobert;; unaligned address. Unfortunately, delayed branch scheduling and 14*404b540aSrobert;; hazard avoidance are done after the final scheduling pass, and they 15*404b540aSrobert;; can change the addresses of many instructions. 16*404b540aSrobert;; 17*404b540aSrobert;; We get around this in two ways: 18*404b540aSrobert;; 19*404b540aSrobert;; (1) By running an extra pass at the end of compilation. This pass goes 20*404b540aSrobert;; through the function looking for pairs of instructions that could 21*404b540aSrobert;; execute in parallel. It makes sure that the first instruction in 22*404b540aSrobert;; each pair is suitably aligned, inserting nops if necessary. Doing 23*404b540aSrobert;; this gives the same kind of pipeline behavior we would see on a 24*404b540aSrobert;; normal superscalar target. 25*404b540aSrobert;; 26*404b540aSrobert;; This pass is generally a speed improvement, but the extra nops will 27*404b540aSrobert;; obviously make the program bigger. It is therefore unsuitable for 28*404b540aSrobert;; -Os (at the very least). 29*404b540aSrobert;; 30*404b540aSrobert;; (2) By modifying the scheduler hooks so that, where possible: 31*404b540aSrobert;; 32*404b540aSrobert;; (a) dependent instructions are separated by a non-dependent 33*404b540aSrobert;; instruction; 34*404b540aSrobert;; 35*404b540aSrobert;; (b) instructions that use the multiplication unit are separated 36*404b540aSrobert;; by non-multiplication instructions; and 37*404b540aSrobert;; 38*404b540aSrobert;; (c) memory access instructions are separated by non-memory 39*404b540aSrobert;; instructions. 40*404b540aSrobert;; 41*404b540aSrobert;; The idea is to keep conflicting instructions apart wherever possible 42*404b540aSrobert;; and thus make the schedule less dependent on alignment. 43*404b540aSrobert 44*404b540aSrobert(define_automaton "vr4130_main, vr4130_muldiv, vr4130_mulpre") 45*404b540aSrobert 46*404b540aSrobert(define_cpu_unit "vr4130_alu1, vr4130_alu2, vr4130_dcache" "vr4130_main") 47*404b540aSrobert(define_cpu_unit "vr4130_muldiv" "vr4130_muldiv") 48*404b540aSrobert 49*404b540aSrobert;; This is a fake unit for pre-reload scheduling of multiplications. 50*404b540aSrobert;; It enforces the true post-reload repeat rate. 51*404b540aSrobert(define_cpu_unit "vr4130_mulpre" "vr4130_mulpre") 52*404b540aSrobert 53*404b540aSrobert;; The scheduling hooks use this attribute for (b) above. 54*404b540aSrobert(define_attr "vr4130_class" "mul,mem,alu" 55*404b540aSrobert (cond [(eq_attr "type" "load,store") 56*404b540aSrobert (const_string "mem") 57*404b540aSrobert 58*404b540aSrobert (eq_attr "type" "mfhilo,mthilo,imul,imul3,imadd,idiv") 59*404b540aSrobert (const_string "mul")] 60*404b540aSrobert (const_string "alu"))) 61*404b540aSrobert 62*404b540aSrobert(define_insn_reservation "vr4130_multi" 1 63*404b540aSrobert (and (eq_attr "cpu" "r4130") 64*404b540aSrobert (eq_attr "type" "multi,unknown")) 65*404b540aSrobert "vr4130_alu1 + vr4130_alu2 + vr4130_dcache + vr4130_muldiv") 66*404b540aSrobert 67*404b540aSrobert(define_insn_reservation "vr4130_int" 1 68*404b540aSrobert (and (eq_attr "cpu" "r4130") 69*404b540aSrobert (eq_attr "type" "const,arith,shift,slt,nop")) 70*404b540aSrobert "vr4130_alu1 | vr4130_alu2") 71*404b540aSrobert 72*404b540aSrobert(define_insn_reservation "vr4130_load" 3 73*404b540aSrobert (and (eq_attr "cpu" "r4130") 74*404b540aSrobert (eq_attr "type" "load")) 75*404b540aSrobert "vr4130_dcache") 76*404b540aSrobert 77*404b540aSrobert(define_insn_reservation "vr4130_store" 1 78*404b540aSrobert (and (eq_attr "cpu" "r4130") 79*404b540aSrobert (eq_attr "type" "store")) 80*404b540aSrobert "vr4130_dcache") 81*404b540aSrobert 82*404b540aSrobert(define_insn_reservation "vr4130_mfhilo" 3 83*404b540aSrobert (and (eq_attr "cpu" "r4130") 84*404b540aSrobert (eq_attr "type" "mfhilo")) 85*404b540aSrobert "vr4130_muldiv") 86*404b540aSrobert 87*404b540aSrobert(define_insn_reservation "vr4130_mthilo" 1 88*404b540aSrobert (and (eq_attr "cpu" "r4130") 89*404b540aSrobert (eq_attr "type" "mthilo")) 90*404b540aSrobert "vr4130_muldiv") 91*404b540aSrobert 92*404b540aSrobert;; The product is available in LO & HI after one cycle. Moving the result 93*404b540aSrobert;; into an integer register will take an additional three cycles, see mflo 94*404b540aSrobert;; & mfhi above. Note that the same latencies and repeat rates apply if we 95*404b540aSrobert;; use "mtlo; macc" instead of "mult; mflo". 96*404b540aSrobert(define_insn_reservation "vr4130_mulsi" 4 97*404b540aSrobert (and (eq_attr "cpu" "r4130") 98*404b540aSrobert (and (eq_attr "type" "imul,imul3") 99*404b540aSrobert (eq_attr "mode" "SI"))) 100*404b540aSrobert "vr4130_muldiv + (vr4130_mulpre * 2)") 101*404b540aSrobert 102*404b540aSrobert;; As for vr4130_mulsi, but the product is available in LO and HI 103*404b540aSrobert;; after 3 cycles. 104*404b540aSrobert(define_insn_reservation "vr4130_muldi" 6 105*404b540aSrobert (and (eq_attr "cpu" "r4130") 106*404b540aSrobert (and (eq_attr "type" "imul,imul3") 107*404b540aSrobert (eq_attr "mode" "DI"))) 108*404b540aSrobert "(vr4130_muldiv * 3) + (vr4130_mulpre * 4)") 109*404b540aSrobert 110*404b540aSrobert;; maccs can execute in consecutive cycles without stalling, but it 111*404b540aSrobert;; is 3 cycles before the integer destination can be read. 112*404b540aSrobert(define_insn_reservation "vr4130_macc" 3 113*404b540aSrobert (and (eq_attr "cpu" "r4130") 114*404b540aSrobert (eq_attr "type" "imadd")) 115*404b540aSrobert "vr4130_muldiv") 116*404b540aSrobert 117*404b540aSrobert(define_bypass 1 "vr4130_mulsi,vr4130_macc" "vr4130_macc" "mips_linked_madd_p") 118*404b540aSrobert(define_bypass 1 "vr4130_mulsi,vr4130_macc" "vr4130_mfhilo") 119*404b540aSrobert(define_bypass 3 "vr4130_muldi" "vr4130_mfhilo") 120*404b540aSrobert 121*404b540aSrobert(define_insn_reservation "vr4130_divsi" 36 122*404b540aSrobert (and (eq_attr "cpu" "r4130") 123*404b540aSrobert (and (eq_attr "type" "idiv") 124*404b540aSrobert (eq_attr "mode" "SI"))) 125*404b540aSrobert "vr4130_muldiv * 36") 126*404b540aSrobert 127*404b540aSrobert(define_insn_reservation "vr4130_divdi" 72 128*404b540aSrobert (and (eq_attr "cpu" "r4130") 129*404b540aSrobert (and (eq_attr "type" "idiv") 130*404b540aSrobert (eq_attr "mode" "DI"))) 131*404b540aSrobert "vr4130_muldiv * 72") 132*404b540aSrobert 133*404b540aSrobert(define_insn_reservation "vr4130_branch" 0 134*404b540aSrobert (and (eq_attr "cpu" "r4130") 135*404b540aSrobert (eq_attr "type" "branch,jump,call")) 136*404b540aSrobert "vr4130_alu1 | vr4130_alu2") 137