1*404b540aSrobert;; DFA-based pipeline description for 5500 2*404b540aSrobert(define_automaton "vr55") 3*404b540aSrobert(define_cpu_unit "vr55_dp0" "vr55") 4*404b540aSrobert(define_cpu_unit "vr55_dp1" "vr55") 5*404b540aSrobert(define_cpu_unit "vr55_mem" "vr55") 6*404b540aSrobert(define_cpu_unit "vr55_mac" "vr55") 7*404b540aSrobert(define_cpu_unit "vr55_fp" "vr55") 8*404b540aSrobert(define_cpu_unit "vr55_bru" "vr55") 9*404b540aSrobert 10*404b540aSrobert;; 11*404b540aSrobert;; The ordering of the instruction-execution-path/resource-usage 12*404b540aSrobert;; descriptions (also known as reservation RTL) is roughly ordered 13*404b540aSrobert;; based on the define attribute RTL for the "type" classification. 14*404b540aSrobert;; When modifying, remember that the first test that matches is the 15*404b540aSrobert;; reservation used! 16*404b540aSrobert;; 17*404b540aSrobert 18*404b540aSrobert(define_insn_reservation "ir_vr55_unknown" 1 19*404b540aSrobert (and (eq_attr "cpu" "r5500") 20*404b540aSrobert (eq_attr "type" "unknown")) 21*404b540aSrobert "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru") 22*404b540aSrobert 23*404b540aSrobert;; Assume prediction fails. 24*404b540aSrobert(define_insn_reservation "ir_vr55_branch" 2 25*404b540aSrobert (and (eq_attr "cpu" "r5500") 26*404b540aSrobert (eq_attr "type" "branch,jump,call")) 27*404b540aSrobert "vr55_bru") 28*404b540aSrobert 29*404b540aSrobert(define_insn_reservation "ir_vr55_load" 3 30*404b540aSrobert (and (eq_attr "cpu" "r5500") 31*404b540aSrobert (eq_attr "type" "load,fpload,fpidxload")) 32*404b540aSrobert "vr55_mem") 33*404b540aSrobert 34*404b540aSrobert(define_bypass 4 35*404b540aSrobert "ir_vr55_load" 36*404b540aSrobert "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd, 37*404b540aSrobert ir_vr55_idiv_si,ir_vr55_idiv_di") 38*404b540aSrobert 39*404b540aSrobert(define_insn_reservation "ir_vr55_store" 0 40*404b540aSrobert (and (eq_attr "cpu" "r5500") 41*404b540aSrobert (eq_attr "type" "store,fpstore,fpidxstore")) 42*404b540aSrobert "vr55_mem") 43*404b540aSrobert 44*404b540aSrobert;; This reservation is for conditional move based on integer 45*404b540aSrobert;; or floating point CC. 46*404b540aSrobert(define_insn_reservation "ir_vr55_condmove" 2 47*404b540aSrobert (and (eq_attr "cpu" "r5500") 48*404b540aSrobert (eq_attr "type" "condmove")) 49*404b540aSrobert "vr55_dp0|vr55_dp1") 50*404b540aSrobert 51*404b540aSrobert;; Move to/from FPU registers 52*404b540aSrobert(define_insn_reservation "ir_vr55_xfer" 2 53*404b540aSrobert (and (eq_attr "cpu" "r5500") 54*404b540aSrobert (eq_attr "type" "xfer")) 55*404b540aSrobert "vr55_dp0|vr55_dp1") 56*404b540aSrobert 57*404b540aSrobert(define_insn_reservation "ir_vr55_arith" 1 58*404b540aSrobert (and (eq_attr "cpu" "r5500") 59*404b540aSrobert (eq_attr "type" "arith,shift,slt,clz,const,nop,trap")) 60*404b540aSrobert "vr55_dp0|vr55_dp1") 61*404b540aSrobert 62*404b540aSrobert(define_bypass 2 63*404b540aSrobert "ir_vr55_arith" 64*404b540aSrobert "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd, 65*404b540aSrobert ir_vr55_idiv_si,ir_vr55_idiv_di") 66*404b540aSrobert 67*404b540aSrobert(define_insn_reservation "ir_vr55_mthilo" 1 68*404b540aSrobert (and (eq_attr "cpu" "r5500") 69*404b540aSrobert (eq_attr "type" "mthilo")) 70*404b540aSrobert "vr55_mac") 71*404b540aSrobert 72*404b540aSrobert(define_insn_reservation "ir_vr55_mfhilo" 5 73*404b540aSrobert (and (eq_attr "cpu" "r5500") 74*404b540aSrobert (eq_attr "type" "mfhilo")) 75*404b540aSrobert "vr55_mac") 76*404b540aSrobert 77*404b540aSrobert;; The default latency is for the GPR result of a mul. Bypasses handle the 78*404b540aSrobert;; latency of {mul,mult}->{mfhi,mflo}. 79*404b540aSrobert(define_insn_reservation "ir_vr55_imul_si" 5 80*404b540aSrobert (and (eq_attr "cpu" "r5500") 81*404b540aSrobert (and (eq_attr "type" "imul,imul3") 82*404b540aSrobert (eq_attr "mode" "SI"))) 83*404b540aSrobert "vr55_mac") 84*404b540aSrobert 85*404b540aSrobert;; The default latency is for pre-reload scheduling and handles the case 86*404b540aSrobert;; where a pseudo destination will be stored in a GPR (as it usually is). 87*404b540aSrobert;; The delay includes the latency of the dmult itself and the anticipated 88*404b540aSrobert;; mflo or mfhi. 89*404b540aSrobert;; 90*404b540aSrobert;; Once the mflo or mfhi has been created, bypasses handle the latency 91*404b540aSrobert;; between it and the dmult. 92*404b540aSrobert(define_insn_reservation "ir_vr55_imul_di" 9 93*404b540aSrobert (and (eq_attr "cpu" "r5500") 94*404b540aSrobert (and (eq_attr "type" "imul,imul3") 95*404b540aSrobert (eq_attr "mode" "DI"))) 96*404b540aSrobert "vr55_mac*4") 97*404b540aSrobert 98*404b540aSrobert;; The default latency is as for ir_vr55_imul_si. 99*404b540aSrobert(define_insn_reservation "ir_vr55_imadd" 5 100*404b540aSrobert (and (eq_attr "cpu" "r5500") 101*404b540aSrobert (eq_attr "type" "imadd")) 102*404b540aSrobert "vr55_mac") 103*404b540aSrobert 104*404b540aSrobert(define_bypass 1 105*404b540aSrobert "ir_vr55_imul_si,ir_vr55_imadd" 106*404b540aSrobert "ir_vr55_imadd" 107*404b540aSrobert "mips_linked_madd_p") 108*404b540aSrobert 109*404b540aSrobert(define_bypass 2 110*404b540aSrobert "ir_vr55_imul_si,ir_vr55_imadd" 111*404b540aSrobert "ir_vr55_mfhilo") 112*404b540aSrobert 113*404b540aSrobert(define_bypass 4 114*404b540aSrobert "ir_vr55_imul_di" 115*404b540aSrobert "ir_vr55_mfhilo") 116*404b540aSrobert 117*404b540aSrobert;; Divide algorithm is early out with best latency of 7 pcycles. 118*404b540aSrobert;; Use worst case for scheduling purposes. 119*404b540aSrobert(define_insn_reservation "ir_vr55_idiv_si" 42 120*404b540aSrobert (and (eq_attr "cpu" "r5500") 121*404b540aSrobert (and (eq_attr "type" "idiv") 122*404b540aSrobert (eq_attr "mode" "SI"))) 123*404b540aSrobert "vr55_mac") 124*404b540aSrobert 125*404b540aSrobert(define_insn_reservation "ir_vr55_idiv_di" 74 126*404b540aSrobert (and (eq_attr "cpu" "r5500") 127*404b540aSrobert (and (eq_attr "type" "idiv") 128*404b540aSrobert (eq_attr "mode" "DI"))) 129*404b540aSrobert "vr55_mac") 130*404b540aSrobert 131*404b540aSrobert(define_insn_reservation "ir_vr55_fadd" 4 132*404b540aSrobert (and (eq_attr "cpu" "r5500") 133*404b540aSrobert (eq_attr "type" "fadd")) 134*404b540aSrobert "vr55_fp") 135*404b540aSrobert 136*404b540aSrobert(define_insn_reservation "ir_vr55_fmul_sf" 5 137*404b540aSrobert (and (eq_attr "cpu" "r5500") 138*404b540aSrobert (and (eq_attr "type" "fmul") 139*404b540aSrobert (eq_attr "mode" "SF"))) 140*404b540aSrobert "vr55_mac") 141*404b540aSrobert 142*404b540aSrobert(define_insn_reservation "ir_vr55_fmul_df" 6 143*404b540aSrobert (and (eq_attr "cpu" "r5500") 144*404b540aSrobert (and (eq_attr "type" "fmul") 145*404b540aSrobert (eq_attr "mode" "DF"))) 146*404b540aSrobert "vr55_mac") 147*404b540aSrobert 148*404b540aSrobert(define_insn_reservation "ir_vr55_fmadd_sf" 9 149*404b540aSrobert (and (eq_attr "cpu" "r5500") 150*404b540aSrobert (and (eq_attr "type" "fmadd") 151*404b540aSrobert (eq_attr "mode" "SF"))) 152*404b540aSrobert "vr55_mac") 153*404b540aSrobert 154*404b540aSrobert(define_insn_reservation "ir_vr55_fmadd_df" 10 155*404b540aSrobert (and (eq_attr "cpu" "r5500") 156*404b540aSrobert (and (eq_attr "type" "fmadd") 157*404b540aSrobert (eq_attr "mode" "DF"))) 158*404b540aSrobert "vr55_mac") 159*404b540aSrobert 160*404b540aSrobert(define_insn_reservation "ir_vr55_fdiv_sf" 30 161*404b540aSrobert (and (eq_attr "cpu" "r5500") 162*404b540aSrobert (and (eq_attr "type" "fdiv,frdiv,fsqrt") 163*404b540aSrobert (eq_attr "mode" "SF"))) 164*404b540aSrobert "vr55_mac") 165*404b540aSrobert 166*404b540aSrobert(define_insn_reservation "ir_vr55_fdiv_df" 59 167*404b540aSrobert (and (eq_attr "cpu" "r5500") 168*404b540aSrobert (and (eq_attr "type" "fdiv,frdiv,fsqrt") 169*404b540aSrobert (eq_attr "mode" "DF"))) 170*404b540aSrobert "vr55_mac") 171*404b540aSrobert 172*404b540aSrobert(define_insn_reservation "ir_vr55_fabs" 2 173*404b540aSrobert (and (eq_attr "cpu" "r5500") 174*404b540aSrobert (eq_attr "type" "fabs,fneg,fmove")) 175*404b540aSrobert "vr55_fp") 176*404b540aSrobert 177*404b540aSrobert(define_insn_reservation "ir_vr55_fcmp" 2 178*404b540aSrobert (and (eq_attr "cpu" "r5500") 179*404b540aSrobert (eq_attr "type" "fcmp")) 180*404b540aSrobert "vr55_fp") 181*404b540aSrobert 182*404b540aSrobert(define_insn_reservation "ir_vr55_fcvt_sf" 4 183*404b540aSrobert (and (eq_attr "cpu" "r5500") 184*404b540aSrobert (and (eq_attr "type" "fcvt") 185*404b540aSrobert (eq_attr "mode" "SF"))) 186*404b540aSrobert "vr55_fp") 187*404b540aSrobert 188*404b540aSrobert(define_insn_reservation "ir_vr55_fcvt_df" 6 189*404b540aSrobert (and (eq_attr "cpu" "r5500") 190*404b540aSrobert (and (eq_attr "type" "fcvt") 191*404b540aSrobert (eq_attr "mode" "DF"))) 192*404b540aSrobert "vr55_fp") 193*404b540aSrobert 194*404b540aSrobert(define_insn_reservation "ir_vr55_frsqrt_sf" 60 195*404b540aSrobert (and (eq_attr "cpu" "r5500") 196*404b540aSrobert (and (eq_attr "type" "frsqrt") 197*404b540aSrobert (eq_attr "mode" "SF"))) 198*404b540aSrobert "vr55_mac") 199*404b540aSrobert 200*404b540aSrobert(define_insn_reservation "ir_vr55_frsqrt_df" 118 201*404b540aSrobert (and (eq_attr "cpu" "r5500") 202*404b540aSrobert (and (eq_attr "type" "frsqrt") 203*404b540aSrobert (eq_attr "mode" "DF"))) 204*404b540aSrobert "vr55_mac") 205*404b540aSrobert 206*404b540aSrobert(define_insn_reservation "ir_vr55_multi" 1 207*404b540aSrobert (and (eq_attr "cpu" "r5500") 208*404b540aSrobert (eq_attr "type" "multi")) 209*404b540aSrobert "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru") 210