1*404b540aSrobert;; DFA-based pipeline descriptions for MIPS32 5K processor family 2*404b540aSrobert;; Contributed by David Ung (davidu@mips.com) 3*404b540aSrobert;; and Nigel Stephens (nigel@mips.com) 4*404b540aSrobert;; 5*404b540aSrobert;; References: 6*404b540aSrobert;; "MIPS64 5K Processor Core Family Software User's Manual, 7*404b540aSrobert;; Doc no: MD00012, Rev 2.09, Jan 28, 2005." 8*404b540aSrobert;; 9*404b540aSrobert;; 5Kc - Single issue with no floating point unit. 10*404b540aSrobert;; 5kf - Separate floating point pipe which can dual-issue with the 11*404b540aSrobert;; integer pipe. 12*404b540aSrobert;; 13*404b540aSrobert;; Copyright (C) 2005 Free Software Foundation, Inc. 14*404b540aSrobert;; 15*404b540aSrobert;; This file is part of GCC. 16*404b540aSrobert;; 17*404b540aSrobert;; GCC is free software; you can redistribute it and/or modify it 18*404b540aSrobert;; under the terms of the GNU General Public License as published 19*404b540aSrobert;; by the Free Software Foundation; either version 2, or (at your 20*404b540aSrobert;; option) any later version. 21*404b540aSrobert 22*404b540aSrobert;; GCC is distributed in the hope that it will be useful, but WITHOUT 23*404b540aSrobert;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24*404b540aSrobert;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 25*404b540aSrobert;; License for more details. 26*404b540aSrobert 27*404b540aSrobert;; You should have received a copy of the GNU General Public License 28*404b540aSrobert;; along with GCC; see the file COPYING. If not, write to the 29*404b540aSrobert;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 30*404b540aSrobert;; MA 02110-1301, USA. 31*404b540aSrobert 32*404b540aSrobert(define_automaton "r5k_cpu, r5k_mdu, r5k_fpu") 33*404b540aSrobert 34*404b540aSrobert;; Integer execution unit. 35*404b540aSrobert(define_cpu_unit "r5k_ixu_arith" "r5k_cpu") 36*404b540aSrobert(define_cpu_unit "r5k_ixu_mpydiv" "r5k_mdu") 37*404b540aSrobert(define_cpu_unit "r5kf_fpu_arith" "r5k_fpu") 38*404b540aSrobert 39*404b540aSrobert(define_insn_reservation "r5k_int_load" 2 40*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 41*404b540aSrobert (eq_attr "type" "load")) 42*404b540aSrobert "r5k_ixu_arith") 43*404b540aSrobert 44*404b540aSrobert(define_insn_reservation "r5k_int_prefetch" 1 45*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 46*404b540aSrobert (eq_attr "type" "prefetch,prefetchx")) 47*404b540aSrobert "r5k_ixu_arith") 48*404b540aSrobert 49*404b540aSrobert(define_insn_reservation "r5k_int_store" 1 50*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 51*404b540aSrobert (eq_attr "type" "store")) 52*404b540aSrobert "r5k_ixu_arith") 53*404b540aSrobert 54*404b540aSrobert;; Divides 55*404b540aSrobert(define_insn_reservation "r5k_int_divsi" 34 56*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 57*404b540aSrobert (and (eq_attr "type" "idiv") 58*404b540aSrobert (eq_attr "mode" "!DI"))) 59*404b540aSrobert "r5k_ixu_arith+(r5k_ixu_mpydiv*34)") 60*404b540aSrobert 61*404b540aSrobert(define_insn_reservation "r5k_int_divdi" 66 62*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 63*404b540aSrobert (and (eq_attr "type" "idiv") 64*404b540aSrobert (eq_attr "mode" "DI"))) 65*404b540aSrobert "r5k_ixu_arith+(r5k_ixu_mpydiv*66)") 66*404b540aSrobert 67*404b540aSrobert;; 32x32 multiply 68*404b540aSrobert;; 32x16 is faster, but there's no way to detect this 69*404b540aSrobert(define_insn_reservation "r5k_int_mult" 2 70*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 71*404b540aSrobert (and (eq_attr "type" "imul,imadd") 72*404b540aSrobert (eq_attr "mode" "SI"))) 73*404b540aSrobert "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") 74*404b540aSrobert 75*404b540aSrobert;; 64x64 multiply 76*404b540aSrobert(define_insn_reservation "r5k_int_mult_64" 9 77*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 78*404b540aSrobert (and (eq_attr "type" "imul,imadd") 79*404b540aSrobert (eq_attr "mode" "DI"))) 80*404b540aSrobert "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") 81*404b540aSrobert 82*404b540aSrobert;; 3 operand MUL 32x32 83*404b540aSrobert(define_insn_reservation "r5k_int_mul" 4 84*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 85*404b540aSrobert (and (eq_attr "type" "imul3") 86*404b540aSrobert (eq_attr "mode" "SI"))) 87*404b540aSrobert "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") 88*404b540aSrobert 89*404b540aSrobert;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency. 90*404b540aSrobert(define_insn_reservation "r5k_int_mthilo" 1 91*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 92*404b540aSrobert (eq_attr "type" "mthilo")) 93*404b540aSrobert "r5k_ixu_arith+r5k_ixu_mpydiv") 94*404b540aSrobert 95*404b540aSrobert;; Move from HI/LO -> integer operation has a 2 cycle latency. 96*404b540aSrobert(define_insn_reservation "r5k_int_mfhilo" 2 97*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 98*404b540aSrobert (eq_attr "type" "mfhilo")) 99*404b540aSrobert "r5k_ixu_arith+r5k_ixu_mpydiv") 100*404b540aSrobert 101*404b540aSrobert;; All other integer insns. 102*404b540aSrobert(define_insn_reservation "r5k_int_alu" 1 103*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 104*404b540aSrobert (eq_attr "type" "arith,condmove,shift,const,nop,slt")) 105*404b540aSrobert "r5k_ixu_arith") 106*404b540aSrobert 107*404b540aSrobert(define_insn_reservation "r5k_int_branch" 1 108*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 109*404b540aSrobert (eq_attr "type" "branch")) 110*404b540aSrobert "r5k_ixu_arith") 111*404b540aSrobert 112*404b540aSrobert;; JR/JALR always cause one pipeline bubble because of interlock. 113*404b540aSrobert(define_insn_reservation "r5k_int_jump" 2 114*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 115*404b540aSrobert (eq_attr "type" "jump,call")) 116*404b540aSrobert "r5k_ixu_arith") 117*404b540aSrobert 118*404b540aSrobert;; Any -> JR/JALR (without dependency) : 1 clock issue delay 119*404b540aSrobert;; Any -> JR/JALR (with dependency) : 2 clock issue delay 120*404b540aSrobert;; load -> JR/JALR (with dependency) : 3 clock issue delay 121*404b540aSrobert;; mfhilo -> JR/JALR (with dependency) : 3 clock issue delay 122*404b540aSrobert;; mul -> JR/JALR (with dependency) : 3 clock issue delay 123*404b540aSrobert(define_bypass 2 "r5k_int_alu" "r5k_int_jump") 124*404b540aSrobert(define_bypass 3 "r5k_int_load" "r5k_int_jump") 125*404b540aSrobert(define_bypass 3 "r5k_int_mfhilo" "r5k_int_jump") 126*404b540aSrobert(define_bypass 3 "r5k_int_mul" "r5k_int_jump") 127*404b540aSrobert 128*404b540aSrobert;; Unknown or multi - single issue 129*404b540aSrobert(define_insn_reservation "r5k_int_unknown" 1 130*404b540aSrobert (and (eq_attr "cpu" "5kc,5kf") 131*404b540aSrobert (eq_attr "type" "unknown,multi")) 132*404b540aSrobert "r5k_ixu_arith+r5k_ixu_mpydiv") 133*404b540aSrobert 134*404b540aSrobert 135*404b540aSrobert;; Floating Point Instructions 136*404b540aSrobert;; The 5Kf is a partial dual-issue cpu which can dual issue an integer 137*404b540aSrobert;; and floating-point instruction in the same cycle. 138*404b540aSrobert 139*404b540aSrobert;; fadd, fabs, fneg 140*404b540aSrobert(define_insn_reservation "r5kf_fadd" 4 141*404b540aSrobert (and (eq_attr "cpu" "5kf") 142*404b540aSrobert (eq_attr "type" "fadd,fabs,fneg")) 143*404b540aSrobert "r5kf_fpu_arith") 144*404b540aSrobert 145*404b540aSrobert;; fmove, fcmove 146*404b540aSrobert(define_insn_reservation "r5kf_fmove" 4 147*404b540aSrobert (and (eq_attr "cpu" "5kf") 148*404b540aSrobert (eq_attr "type" "fmove")) 149*404b540aSrobert "r5kf_fpu_arith") 150*404b540aSrobert 151*404b540aSrobert;; fload 152*404b540aSrobert(define_insn_reservation "r5kf_fload" 3 153*404b540aSrobert (and (eq_attr "cpu" "5kf") 154*404b540aSrobert (eq_attr "type" "fpload,fpidxload")) 155*404b540aSrobert "r5kf_fpu_arith") 156*404b540aSrobert 157*404b540aSrobert;; fstore 158*404b540aSrobert(define_insn_reservation "r5kf_fstore" 1 159*404b540aSrobert (and (eq_attr "cpu" "5kf") 160*404b540aSrobert (eq_attr "type" "fpstore")) 161*404b540aSrobert "r5kf_fpu_arith") 162*404b540aSrobert 163*404b540aSrobert;; fmul, fmadd 164*404b540aSrobert(define_insn_reservation "r5kf_fmul_sf" 4 165*404b540aSrobert (and (eq_attr "cpu" "5kf") 166*404b540aSrobert (and (eq_attr "type" "fmul,fmadd") 167*404b540aSrobert (eq_attr "mode" "SF"))) 168*404b540aSrobert "r5kf_fpu_arith") 169*404b540aSrobert 170*404b540aSrobert(define_insn_reservation "r5kf_fmul_df" 5 171*404b540aSrobert (and (eq_attr "cpu" "5kf") 172*404b540aSrobert (and (eq_attr "type" "fmul,fmadd") 173*404b540aSrobert (eq_attr "mode" "DF"))) 174*404b540aSrobert "r5kf_fpu_arith*2") 175*404b540aSrobert 176*404b540aSrobert;; fdiv, fsqrt, frsqrt 177*404b540aSrobert(define_insn_reservation "r5kf_fdiv_sf" 17 178*404b540aSrobert (and (eq_attr "cpu" "5kf") 179*404b540aSrobert (and (eq_attr "type" "fdiv,fsqrt,frsqrt") 180*404b540aSrobert (eq_attr "mode" "SF"))) 181*404b540aSrobert "r5kf_fpu_arith*14") 182*404b540aSrobert 183*404b540aSrobert(define_insn_reservation "r5kf_fdiv_df" 32 184*404b540aSrobert (and (eq_attr "cpu" "5kf") 185*404b540aSrobert (and (eq_attr "type" "fdiv,fsqrt") 186*404b540aSrobert (eq_attr "mode" "DF"))) 187*404b540aSrobert "r5kf_fpu_arith*29") 188*404b540aSrobert 189*404b540aSrobert;; frsqrt 190*404b540aSrobert(define_insn_reservation "r5kf_frsqrt_df" 35 191*404b540aSrobert (and (eq_attr "cpu" "5kf") 192*404b540aSrobert (and (eq_attr "type" "frsqrt") 193*404b540aSrobert (eq_attr "mode" "DF"))) 194*404b540aSrobert "r5kf_fpu_arith*31") 195*404b540aSrobert 196*404b540aSrobert;; fcmp 197*404b540aSrobert(define_insn_reservation "r5kf_fcmp" 2 198*404b540aSrobert (and (eq_attr "cpu" "5kf") 199*404b540aSrobert (eq_attr "type" "fcmp")) 200*404b540aSrobert "r5kf_fpu_arith") 201*404b540aSrobert 202*404b540aSrobert;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on condition) 203*404b540aSrobert(define_bypass 1 "r5kf_fcmp" "r5kf_fmove") 204*404b540aSrobert 205*404b540aSrobert;; fcvt (cvt.d.s, cvt.[sd].[wl] 206*404b540aSrobert(define_insn_reservation "r5kf_fcvt_d2s" 4 207*404b540aSrobert (and (eq_attr "cpu" "5kf") 208*404b540aSrobert (and (eq_attr "type" "fcvt") 209*404b540aSrobert (eq_attr "cnv_mode" "I2S,I2D,S2D"))) 210*404b540aSrobert "r5kf_fpu_arith") 211*404b540aSrobert 212*404b540aSrobert;; fcvt (cvt.s.d) 213*404b540aSrobert(define_insn_reservation "r5kf_fcvt_s2d" 6 214*404b540aSrobert (and (eq_attr "cpu" "5kc") 215*404b540aSrobert (and (eq_attr "type" "fcvt") 216*404b540aSrobert (eq_attr "cnv_mode" "D2S"))) 217*404b540aSrobert "r5kf_fpu_arith") 218*404b540aSrobert 219*404b540aSrobert;; fcvt (cvt.[wl].[sd], etc) 220*404b540aSrobert(define_insn_reservation "r5kf_fcvt_f2i" 5 221*404b540aSrobert (and (eq_attr "cpu" "5kf") 222*404b540aSrobert (and (eq_attr "type" "fcvt") 223*404b540aSrobert (eq_attr "cnv_mode" "S2I,D2I"))) 224*404b540aSrobert "r5kf_fpu_arith") 225*404b540aSrobert 226*404b540aSrobert;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue 227*404b540aSrobert(define_insn_reservation "r5kf_fxfer" 2 228*404b540aSrobert (and (eq_attr "cpu" "5kf") 229*404b540aSrobert (eq_attr "type" "xfer")) 230*404b540aSrobert "r5k_ixu_arith+r5kf_fpu_arith") 231