1 /* Definitions of target machine for GNU compiler. MIPS version. 2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4 Contributed by A. Lichnewsky (lich@inria.inria.fr). 5 Changed by Michael Meissner (meissner@osf.org). 6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and 7 Brendan Eich (brendan@microunity.com). 8 9 This file is part of GCC. 10 11 GCC is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 2, or (at your option) 14 any later version. 15 16 GCC is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with GCC; see the file COPYING. If not, write to 23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 24 Boston, MA 02110-1301, USA. */ 25 26 27 /* MIPS external variables defined in mips.c. */ 28 29 /* Which processor to schedule for. Since there is no difference between 30 a R2000 and R3000 in terms of the scheduler, we collapse them into 31 just an R3000. The elements of the enumeration must match exactly 32 the cpu attribute in the mips.md machine description. */ 33 34 enum processor_type { 35 PROCESSOR_R3000, 36 PROCESSOR_4KC, 37 PROCESSOR_4KP, 38 PROCESSOR_5KC, 39 PROCESSOR_5KF, 40 PROCESSOR_20KC, 41 PROCESSOR_24K, 42 PROCESSOR_24KX, 43 PROCESSOR_M4K, 44 PROCESSOR_R3900, 45 PROCESSOR_R6000, 46 PROCESSOR_R4000, 47 PROCESSOR_R4100, 48 PROCESSOR_R4111, 49 PROCESSOR_R4120, 50 PROCESSOR_R4130, 51 PROCESSOR_R4300, 52 PROCESSOR_R4600, 53 PROCESSOR_R4650, 54 PROCESSOR_R5000, 55 PROCESSOR_R5400, 56 PROCESSOR_R5500, 57 PROCESSOR_R7000, 58 PROCESSOR_R8000, 59 PROCESSOR_R9000, 60 PROCESSOR_SB1, 61 PROCESSOR_SB1A, 62 PROCESSOR_SR71000, 63 PROCESSOR_MAX 64 }; 65 66 /* Costs of various operations on the different architectures. */ 67 68 struct mips_rtx_cost_data 69 { 70 unsigned short fp_add; 71 unsigned short fp_mult_sf; 72 unsigned short fp_mult_df; 73 unsigned short fp_div_sf; 74 unsigned short fp_div_df; 75 unsigned short int_mult_si; 76 unsigned short int_mult_di; 77 unsigned short int_div_si; 78 unsigned short int_div_di; 79 unsigned short branch_cost; 80 unsigned short memory_latency; 81 }; 82 83 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), 84 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended 85 to work on a 64 bit machine. */ 86 87 #define ABI_32 0 88 #define ABI_N32 1 89 #define ABI_64 2 90 #define ABI_EABI 3 91 #define ABI_O64 4 92 93 /* Information about one recognized processor. Defined here for the 94 benefit of TARGET_CPU_CPP_BUILTINS. */ 95 struct mips_cpu_info { 96 /* The 'canonical' name of the processor as far as GCC is concerned. 97 It's typically a manufacturer's prefix followed by a numerical 98 designation. It should be lower case. */ 99 const char *name; 100 101 /* The internal processor number that most closely matches this 102 entry. Several processors can have the same value, if there's no 103 difference between them from GCC's point of view. */ 104 enum processor_type cpu; 105 106 /* The ISA level that the processor implements. */ 107 int isa; 108 }; 109 110 #ifndef USED_FOR_TARGET 111 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */ 112 extern const char *current_function_file; /* filename current function is in */ 113 extern int num_source_filenames; /* current .file # */ 114 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */ 115 extern int sym_lineno; /* sgi next label # for each stmt */ 116 extern int set_noreorder; /* # of nested .set noreorder's */ 117 extern int set_nomacro; /* # of nested .set nomacro's */ 118 extern int set_noat; /* # of nested .set noat's */ 119 extern int set_volatile; /* # of nested .set volatile's */ 120 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */ 121 extern int mips_dbx_regno[]; /* Map register # to debug register # */ 122 extern bool mips_split_p[]; 123 extern GTY(()) rtx cmp_operands[2]; 124 extern enum processor_type mips_arch; /* which cpu to codegen for */ 125 extern enum processor_type mips_tune; /* which cpu to schedule for */ 126 extern int mips_isa; /* architectural level */ 127 extern int mips_abi; /* which ABI to use */ 128 extern int mips16_hard_float; /* mips16 without -msoft-float */ 129 extern const struct mips_cpu_info mips_cpu_info_table[]; 130 extern const struct mips_cpu_info *mips_arch_info; 131 extern const struct mips_cpu_info *mips_tune_info; 132 extern const struct mips_rtx_cost_data *mips_cost; 133 #endif 134 135 /* Macros to silence warnings about numbers being signed in traditional 136 C and unsigned in ISO C when compiled on 32-bit hosts. */ 137 138 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ 139 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ 140 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ 141 142 143 /* Run-time compilation parameters selecting different hardware subsets. */ 144 145 /* True if the call patterns should be split into a jalr followed by 146 an instruction to restore $gp. This is only ever true for SVR4 PIC, 147 in which $gp is call-clobbered. It is only safe to split the load 148 from the call when every use of $gp is explicit. */ 149 150 #define TARGET_SPLIT_CALLS \ 151 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI) 152 153 /* True if we're generating a form of -mabicalls in which we can use 154 operators like %hi and %lo to refer to locally-binding symbols. 155 We can only do this for -mno-shared, and only then if we can use 156 relocation operations instead of assembly macros. It isn't really 157 worth using absolute sequences for 64-bit symbols because GOT 158 accesses are so much shorter. */ 159 160 #define TARGET_ABSOLUTE_ABICALLS \ 161 (TARGET_ABICALLS \ 162 && !TARGET_SHARED \ 163 && TARGET_EXPLICIT_RELOCS \ 164 && !ABI_HAS_64BIT_SYMBOLS) 165 166 /* True if we can optimize sibling calls. For simplicity, we only 167 handle cases in which call_insn_operand will reject invalid 168 sibcall addresses. There are two cases in which this isn't true: 169 170 - TARGET_MIPS16. call_insn_operand accepts constant addresses 171 but there is no direct jump instruction. It isn't worth 172 using sibling calls in this case anyway; they would usually 173 be longer than normal calls. 174 175 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand 176 accepts global constants, but "jr $25" is the only allowed 177 sibcall. */ 178 179 #define TARGET_SIBCALLS \ 180 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS)) 181 182 /* True if .gpword or .gpdword should be used for switch tables. 183 184 Although GAS does understand .gpdword, the SGI linker mishandles 185 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64). 186 We therefore disable GP-relative switch tables for n64 on IRIX targets. */ 187 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX)) 188 189 /* Generate mips16 code */ 190 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) 191 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */ 192 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) 193 194 /* Generic ISA defines. */ 195 #define ISA_MIPS1 (mips_isa == 1) 196 #define ISA_MIPS2 (mips_isa == 2) 197 #define ISA_MIPS3 (mips_isa == 3) 198 #define ISA_MIPS4 (mips_isa == 4) 199 #define ISA_MIPS32 (mips_isa == 32) 200 #define ISA_MIPS32R2 (mips_isa == 33) 201 #define ISA_MIPS64 (mips_isa == 64) 202 203 /* Architecture target defines. */ 204 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) 205 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) 206 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) 207 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) 208 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) 209 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) 210 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) 211 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) 212 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ 213 || mips_arch == PROCESSOR_SB1A) 214 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) 215 216 /* Scheduling target defines. */ 217 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) 218 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) 219 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) 220 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) 221 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) 222 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) 223 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) 224 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) 225 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) 226 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) 227 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) 228 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ 229 || mips_tune == PROCESSOR_SB1A) 230 231 /* True if the pre-reload scheduler should try to create chains of 232 multiply-add or multiply-subtract instructions. For example, 233 suppose we have: 234 235 t1 = a * b 236 t2 = t1 + c * d 237 t3 = e * f 238 t4 = t3 - g * h 239 240 t1 will have a higher priority than t2 and t3 will have a higher 241 priority than t4. However, before reload, there is no dependence 242 between t1 and t3, and they can often have similar priorities. 243 The scheduler will then tend to prefer: 244 245 t1 = a * b 246 t3 = e * f 247 t2 = t1 + c * d 248 t4 = t3 - g * h 249 250 which stops us from making full use of macc/madd-style instructions. 251 This sort of situation occurs frequently in Fourier transforms and 252 in unrolled loops. 253 254 To counter this, the TUNE_MACC_CHAINS code will reorder the ready 255 queue so that chained multiply-add and multiply-subtract instructions 256 appear ahead of any other instruction that is likely to clobber lo. 257 In the example above, if t2 and t3 become ready at the same time, 258 the code ensures that t2 is scheduled first. 259 260 Multiply-accumulate instructions are a bigger win for some targets 261 than others, so this macro is defined on an opt-in basis. */ 262 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ 263 || TUNE_MIPS4120 \ 264 || TUNE_MIPS4130) 265 266 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) 267 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) 268 269 /* IRIX specific stuff. */ 270 #define TARGET_IRIX 0 271 #define TARGET_IRIX6 0 272 273 /* Define preprocessor macros for the -march and -mtune options. 274 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected 275 processor. If INFO's canonical name is "foo", define PREFIX to 276 be "foo", and define an additional macro PREFIX_FOO. */ 277 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ 278 do \ 279 { \ 280 char *macro, *p; \ 281 \ 282 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ 283 for (p = macro; *p != 0; p++) \ 284 *p = TOUPPER (*p); \ 285 \ 286 builtin_define (macro); \ 287 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ 288 free (macro); \ 289 } \ 290 while (0) 291 292 /* Target CPU builtins. */ 293 #define TARGET_CPU_CPP_BUILTINS() \ 294 do \ 295 { \ 296 /* Everyone but IRIX defines this to mips. */ \ 297 if (!TARGET_IRIX) \ 298 builtin_assert ("machine=mips"); \ 299 \ 300 builtin_assert ("cpu=mips"); \ 301 builtin_define ("__mips__"); \ 302 builtin_define ("_mips"); \ 303 \ 304 /* We do this here because __mips is defined below \ 305 and so we can't use builtin_define_std. */ \ 306 if (!flag_iso) \ 307 builtin_define ("mips"); \ 308 \ 309 if (TARGET_64BIT) \ 310 builtin_define ("__mips64"); \ 311 \ 312 if (!TARGET_IRIX) \ 313 { \ 314 /* Treat _R3000 and _R4000 like register-size \ 315 defines, which is how they've historically \ 316 been used. */ \ 317 if (TARGET_64BIT) \ 318 { \ 319 builtin_define_std ("R4000"); \ 320 builtin_define ("_R4000"); \ 321 } \ 322 else \ 323 { \ 324 builtin_define_std ("R3000"); \ 325 builtin_define ("_R3000"); \ 326 } \ 327 } \ 328 if (TARGET_FLOAT64) \ 329 builtin_define ("__mips_fpr=64"); \ 330 else \ 331 builtin_define ("__mips_fpr=32"); \ 332 \ 333 if (TARGET_MIPS16) \ 334 builtin_define ("__mips16"); \ 335 \ 336 if (TARGET_MIPS3D) \ 337 builtin_define ("__mips3d"); \ 338 \ 339 if (TARGET_DSP) \ 340 builtin_define ("__mips_dsp"); \ 341 \ 342 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ 343 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ 344 \ 345 if (ISA_MIPS1) \ 346 { \ 347 builtin_define ("__mips=1"); \ 348 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ 349 } \ 350 else if (ISA_MIPS2) \ 351 { \ 352 builtin_define ("__mips=2"); \ 353 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ 354 } \ 355 else if (ISA_MIPS3) \ 356 { \ 357 builtin_define ("__mips=3"); \ 358 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ 359 } \ 360 else if (ISA_MIPS4) \ 361 { \ 362 builtin_define ("__mips=4"); \ 363 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ 364 } \ 365 else if (ISA_MIPS32) \ 366 { \ 367 builtin_define ("__mips=32"); \ 368 builtin_define ("__mips_isa_rev=1"); \ 369 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 370 } \ 371 else if (ISA_MIPS32R2) \ 372 { \ 373 builtin_define ("__mips=32"); \ 374 builtin_define ("__mips_isa_rev=2"); \ 375 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ 376 } \ 377 else if (ISA_MIPS64) \ 378 { \ 379 builtin_define ("__mips=64"); \ 380 builtin_define ("__mips_isa_rev=1"); \ 381 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ 382 } \ 383 \ 384 if (TARGET_HARD_FLOAT) \ 385 builtin_define ("__mips_hard_float"); \ 386 else if (TARGET_SOFT_FLOAT) \ 387 builtin_define ("__mips_soft_float"); \ 388 \ 389 if (TARGET_SINGLE_FLOAT) \ 390 builtin_define ("__mips_single_float"); \ 391 \ 392 if (TARGET_PAIRED_SINGLE_FLOAT) \ 393 builtin_define ("__mips_paired_single_float"); \ 394 \ 395 if (TARGET_BIG_ENDIAN) \ 396 { \ 397 builtin_define_std ("MIPSEB"); \ 398 builtin_define ("_MIPSEB"); \ 399 } \ 400 else \ 401 { \ 402 builtin_define_std ("MIPSEL"); \ 403 builtin_define ("_MIPSEL"); \ 404 } \ 405 \ 406 /* Macros dependent on the C dialect. */ \ 407 if (preprocessing_asm_p ()) \ 408 { \ 409 builtin_define_std ("LANGUAGE_ASSEMBLY"); \ 410 builtin_define ("_LANGUAGE_ASSEMBLY"); \ 411 } \ 412 else if (c_dialect_cxx ()) \ 413 { \ 414 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ 415 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ 416 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ 417 } \ 418 else \ 419 { \ 420 builtin_define_std ("LANGUAGE_C"); \ 421 builtin_define ("_LANGUAGE_C"); \ 422 } \ 423 if (c_dialect_objc ()) \ 424 { \ 425 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ 426 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ 427 /* Bizarre, but needed at least for Irix. */ \ 428 builtin_define_std ("LANGUAGE_C"); \ 429 builtin_define ("_LANGUAGE_C"); \ 430 } \ 431 \ 432 if (mips_abi == ABI_EABI) \ 433 builtin_define ("__mips_eabi"); \ 434 \ 435 } while (0) 436 437 /* Default target_flags if no switches are specified */ 438 439 #ifndef TARGET_DEFAULT 440 #define TARGET_DEFAULT 0 441 #endif 442 443 #ifndef TARGET_CPU_DEFAULT 444 #define TARGET_CPU_DEFAULT 0 445 #endif 446 447 #ifndef TARGET_ENDIAN_DEFAULT 448 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN 449 #endif 450 451 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT 452 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS 453 #endif 454 455 /* 'from-abi' makes a good default: you get whatever the ABI requires. */ 456 #ifndef MIPS_ISA_DEFAULT 457 #ifndef MIPS_CPU_STRING_DEFAULT 458 #define MIPS_CPU_STRING_DEFAULT "from-abi" 459 #endif 460 #endif 461 462 #ifdef IN_LIBGCC2 463 #undef TARGET_64BIT 464 /* Make this compile time constant for libgcc2 */ 465 #ifdef __mips64 466 #define TARGET_64BIT 1 467 #else 468 #define TARGET_64BIT 0 469 #endif 470 #endif /* IN_LIBGCC2 */ 471 472 #define TARGET_LIBGCC_SDATA_SECTION ".sdata" 473 474 #ifndef MULTILIB_ENDIAN_DEFAULT 475 #if TARGET_ENDIAN_DEFAULT == 0 476 #define MULTILIB_ENDIAN_DEFAULT "EL" 477 #else 478 #define MULTILIB_ENDIAN_DEFAULT "EB" 479 #endif 480 #endif 481 482 #ifndef MULTILIB_ISA_DEFAULT 483 # if MIPS_ISA_DEFAULT == 1 484 # define MULTILIB_ISA_DEFAULT "mips1" 485 # else 486 # if MIPS_ISA_DEFAULT == 2 487 # define MULTILIB_ISA_DEFAULT "mips2" 488 # else 489 # if MIPS_ISA_DEFAULT == 3 490 # define MULTILIB_ISA_DEFAULT "mips3" 491 # else 492 # if MIPS_ISA_DEFAULT == 4 493 # define MULTILIB_ISA_DEFAULT "mips4" 494 # else 495 # if MIPS_ISA_DEFAULT == 32 496 # define MULTILIB_ISA_DEFAULT "mips32" 497 # else 498 # if MIPS_ISA_DEFAULT == 33 499 # define MULTILIB_ISA_DEFAULT "mips32r2" 500 # else 501 # if MIPS_ISA_DEFAULT == 64 502 # define MULTILIB_ISA_DEFAULT "mips64" 503 # else 504 # define MULTILIB_ISA_DEFAULT "mips1" 505 # endif 506 # endif 507 # endif 508 # endif 509 # endif 510 # endif 511 # endif 512 #endif 513 514 #ifndef MULTILIB_DEFAULTS 515 #define MULTILIB_DEFAULTS \ 516 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } 517 #endif 518 519 /* We must pass -EL to the linker by default for little endian embedded 520 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the 521 linker will default to using big-endian output files. The OUTPUT_FORMAT 522 line must be in the linker script, otherwise -EB/-EL will not work. */ 523 524 #ifndef ENDIAN_SPEC 525 #if TARGET_ENDIAN_DEFAULT == 0 526 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" 527 #else 528 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" 529 #endif 530 #endif 531 532 /* Support for a compile-time default CPU, et cetera. The rules are: 533 --with-arch is ignored if -march is specified or a -mips is specified 534 (other than -mips16). 535 --with-tune is ignored if -mtune is specified. 536 --with-abi is ignored if -mabi is specified. 537 --with-float is ignored if -mhard-float or -msoft-float are 538 specified. 539 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are 540 specified. */ 541 #define OPTION_DEFAULT_SPECS \ 542 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \ 543 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 544 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ 545 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ 546 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" } 547 548 549 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ 550 && ISA_HAS_COND_TRAP) 551 552 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \ 553 && !TARGET_SR71K \ 554 && !TARGET_MIPS16) 555 556 /* Generate three-operand multiply instructions for SImode. */ 557 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \ 558 || TARGET_MIPS5400 \ 559 || TARGET_MIPS5500 \ 560 || TARGET_MIPS7000 \ 561 || TARGET_MIPS9000 \ 562 || TARGET_MAD \ 563 || ISA_MIPS32 \ 564 || ISA_MIPS32R2 \ 565 || ISA_MIPS64) \ 566 && !TARGET_MIPS16) 567 568 /* Generate three-operand multiply instructions for DImode. */ 569 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \ 570 && !TARGET_MIPS16) 571 572 /* True if the ABI can only work with 64-bit integer registers. We 573 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but 574 otherwise floating-point registers must also be 64-bit. */ 575 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64) 576 577 /* Likewise for 32-bit regs. */ 578 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32) 579 580 /* True if symbols are 64 bits wide. At present, n64 is the only 581 ABI for which this is true. */ 582 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32) 583 584 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */ 585 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ 586 || ISA_MIPS4 \ 587 || ISA_MIPS64) 588 589 /* ISA has branch likely instructions (e.g. mips2). */ 590 /* Disable branchlikely for tx39 until compare rewrite. They haven't 591 been generated up to this point. */ 592 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1) 593 594 /* ISA has the conditional move instructions introduced in mips4. */ 595 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \ 596 || ISA_MIPS32 \ 597 || ISA_MIPS32R2 \ 598 || ISA_MIPS64) \ 599 && !TARGET_MIPS5500 \ 600 && !TARGET_MIPS16) 601 602 /* ISA has the mips4 FP condition code instructions: FP-compare to CC, 603 branch on CC, and move (both FP and non-FP) on CC. */ 604 #define ISA_HAS_8CC (ISA_MIPS4 \ 605 || ISA_MIPS32 \ 606 || ISA_MIPS32R2 \ 607 || ISA_MIPS64) 608 609 /* This is a catch all for other mips4 instructions: indexed load, the 610 FP madd and msub instructions, and the FP recip and recip sqrt 611 instructions. */ 612 #define ISA_HAS_FP4 ((ISA_MIPS4 \ 613 || ISA_MIPS64) \ 614 && !TARGET_MIPS16) 615 616 /* ISA has conditional trap instructions. */ 617 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ 618 && !TARGET_MIPS16) 619 620 /* ISA has integer multiply-accumulate instructions, madd and msub. */ 621 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ 622 || ISA_MIPS32R2 \ 623 || ISA_MIPS64 \ 624 ) && !TARGET_MIPS16) 625 626 /* ISA has floating-point nmadd and nmsub instructions. */ 627 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \ 628 || ISA_MIPS64) \ 629 && (!TARGET_MIPS5400 || TARGET_MAD) \ 630 && ! TARGET_MIPS16) 631 632 /* ISA has count leading zeroes/ones instruction (not implemented). */ 633 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ 634 || ISA_MIPS32R2 \ 635 || ISA_MIPS64 \ 636 ) && !TARGET_MIPS16) 637 638 /* ISA has double-word count leading zeroes/ones instruction (not 639 implemented). */ 640 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \ 641 && !TARGET_MIPS16) 642 643 /* ISA has three operand multiply instructions that put 644 the high part in an accumulator: mulhi or mulhiu. */ 645 #define ISA_HAS_MULHI (TARGET_MIPS5400 \ 646 || TARGET_MIPS5500 \ 647 || TARGET_SR71K \ 648 ) 649 650 /* ISA has three operand multiply instructions that 651 negates the result and puts the result in an accumulator. */ 652 #define ISA_HAS_MULS (TARGET_MIPS5400 \ 653 || TARGET_MIPS5500 \ 654 || TARGET_SR71K \ 655 ) 656 657 /* ISA has three operand multiply instructions that subtracts the 658 result from a 4th operand and puts the result in an accumulator. */ 659 #define ISA_HAS_MSAC (TARGET_MIPS5400 \ 660 || TARGET_MIPS5500 \ 661 || TARGET_SR71K \ 662 ) 663 /* ISA has three operand multiply instructions that the result 664 from a 4th operand and puts the result in an accumulator. */ 665 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \ 666 || (TARGET_MIPS4130 && !TARGET_MIPS16) \ 667 || TARGET_MIPS5400 \ 668 || TARGET_MIPS5500 \ 669 || TARGET_SR71K \ 670 ) 671 672 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ 673 #define ISA_HAS_MACCHI (!TARGET_MIPS16 \ 674 && (TARGET_MIPS4120 \ 675 || TARGET_MIPS4130)) 676 677 /* ISA has 32-bit rotate right instruction. */ 678 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \ 679 && (ISA_MIPS32R2 \ 680 || TARGET_MIPS5400 \ 681 || TARGET_MIPS5500 \ 682 || TARGET_SR71K \ 683 )) 684 685 /* ISA has 64-bit rotate right instruction. */ 686 #define ISA_HAS_ROTR_DI (TARGET_64BIT \ 687 && !TARGET_MIPS16 \ 688 && (TARGET_MIPS5400 \ 689 || TARGET_MIPS5500 \ 690 || TARGET_SR71K \ 691 )) 692 693 /* ISA has data prefetch instructions. This controls use of 'pref'. */ 694 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ 695 || ISA_MIPS32 \ 696 || ISA_MIPS32R2 \ 697 || ISA_MIPS64) \ 698 && !TARGET_MIPS16) 699 700 /* ISA has data indexed prefetch instructions. This controls use of 701 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. 702 (prefx is a cop1x instruction, so can only be used if FP is 703 enabled.) */ 704 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ 705 || ISA_MIPS64) \ 706 && !TARGET_MIPS16) 707 708 /* True if trunc.w.s and trunc.w.d are real (not synthetic) 709 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d 710 also requires TARGET_DOUBLE_FLOAT. */ 711 #define ISA_HAS_TRUNC_W (!ISA_MIPS1) 712 713 /* ISA includes the MIPS32r2 seb and seh instructions. */ 714 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \ 715 && (ISA_MIPS32R2 \ 716 )) 717 718 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ 719 #define ISA_HAS_EXT_INS (!TARGET_MIPS16 \ 720 && (ISA_MIPS32R2 \ 721 )) 722 723 /* True if the result of a load is not available to the next instruction. 724 A nop will then be needed between instructions like "lw $4,..." 725 and "addiu $4,$4,1". */ 726 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \ 727 && !TARGET_MIPS3900 \ 728 && !TARGET_MIPS16) 729 730 /* Likewise mtc1 and mfc1. */ 731 #define ISA_HAS_XFER_DELAY (mips_isa <= 3) 732 733 /* Likewise floating-point comparisons. */ 734 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3) 735 736 /* True if mflo and mfhi can be immediately followed by instructions 737 which write to the HI and LO registers. 738 739 According to MIPS specifications, MIPS ISAs I, II, and III need 740 (at least) two instructions between the reads of HI/LO and 741 instructions which write them, and later ISAs do not. Contradicting 742 the MIPS specifications, some MIPS IV processor user manuals (e.g. 743 the UM for the NEC Vr5000) document needing the instructions between 744 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 745 MIPS64 and later ISAs to have the interlocks, plus any specific 746 earlier-ISA CPUs for which CPU documentation declares that the 747 instructions are really interlocked. */ 748 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ 749 || ISA_MIPS32R2 \ 750 || ISA_MIPS64 \ 751 || TARGET_MIPS5500) 752 753 /* Add -G xx support. */ 754 755 #undef SWITCH_TAKES_ARG 756 #define SWITCH_TAKES_ARG(CHAR) \ 757 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') 758 759 #define OVERRIDE_OPTIONS override_options () 760 761 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage () 762 763 /* Show we can debug even without a frame pointer. */ 764 #define CAN_DEBUG_WITHOUT_FP 765 766 /* Tell collect what flags to pass to nm. */ 767 #ifndef NM_FLAGS 768 #define NM_FLAGS "-Bn" 769 #endif 770 771 772 #ifndef MIPS_ABI_DEFAULT 773 #define MIPS_ABI_DEFAULT ABI_32 774 #endif 775 776 /* Use the most portable ABI flag for the ASM specs. */ 777 778 #if MIPS_ABI_DEFAULT == ABI_32 779 #define MULTILIB_ABI_DEFAULT "mabi=32" 780 #endif 781 782 #if MIPS_ABI_DEFAULT == ABI_O64 783 #define MULTILIB_ABI_DEFAULT "mabi=o64" 784 #endif 785 786 #if MIPS_ABI_DEFAULT == ABI_N32 787 #define MULTILIB_ABI_DEFAULT "mabi=n32" 788 #endif 789 790 #if MIPS_ABI_DEFAULT == ABI_64 791 #define MULTILIB_ABI_DEFAULT "mabi=64" 792 #endif 793 794 #if MIPS_ABI_DEFAULT == ABI_EABI 795 #define MULTILIB_ABI_DEFAULT "mabi=eabi" 796 #endif 797 798 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options 799 to the assembler. It may be overridden by subtargets. */ 800 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC 801 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\ 802 %{noasmopt:-O0} \ 803 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}" 804 #endif 805 806 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to 807 the assembler. It may be overridden by subtargets. 808 809 Beginning with gas 2.13, -mdebug must be passed to correctly handle 810 COFF debugging info. */ 811 812 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC 813 #define SUBTARGET_ASM_DEBUGGING_SPEC "\ 814 %{g} %{g0} %{g1} %{g2} %{g3} \ 815 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ 816 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ 817 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ 818 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \ 819 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}" 820 #endif 821 822 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be 823 overridden by subtargets. */ 824 825 #ifndef SUBTARGET_ASM_SPEC 826 #define SUBTARGET_ASM_SPEC "" 827 #endif 828 829 #undef ASM_SPEC 830 #define ASM_SPEC "\ 831 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ 832 %{mips32} %{mips32r2} %{mips64} \ 833 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \ 834 %{mips3d:-mips3d} \ 835 %{mdsp} \ 836 %{mfix-vr4120} %{mfix-vr4130} \ 837 %(subtarget_asm_optimizing_spec) \ 838 %(subtarget_asm_debugging_spec) \ 839 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \ 840 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ 841 %{mshared} %{mno-shared} \ 842 %{msym32} %{mno-sym32} \ 843 %{mtune=*} %{v} \ 844 %(subtarget_asm_spec)" 845 846 /* Extra switches sometimes passed to the linker. */ 847 /* ??? The bestGnum will never be passed to the linker, because the gcc driver 848 will interpret it as a -b option. */ 849 850 #ifndef LINK_SPEC 851 #define LINK_SPEC "\ 852 %(endian_spec) \ 853 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \ 854 %{bestGnum} %{shared} %{non_shared}" 855 #endif /* LINK_SPEC defined */ 856 857 858 /* Specs for the compiler proper */ 859 860 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be 861 overridden by subtargets. */ 862 #ifndef SUBTARGET_CC1_SPEC 863 #define SUBTARGET_CC1_SPEC "" 864 #endif 865 866 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */ 867 868 #undef CC1_SPEC 869 #define CC1_SPEC "\ 870 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ 871 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ 872 %{save-temps: } \ 873 %(subtarget_cc1_spec)" 874 875 /* Preprocessor specs. */ 876 877 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be 878 overridden by subtargets. */ 879 #ifndef SUBTARGET_CPP_SPEC 880 #define SUBTARGET_CPP_SPEC "" 881 #endif 882 883 #undef CPP_SPEC 884 #define CPP_SPEC "%(subtarget_cpp_spec)" 885 886 /* This macro defines names of additional specifications to put in the specs 887 that can be used in various specifications like CC1_SPEC. Its definition 888 is an initializer with a subgrouping for each command option. 889 890 Each subgrouping contains a string constant, that defines the 891 specification name, and a string constant that used by the GCC driver 892 program. 893 894 Do not define this macro if it does not need to do anything. */ 895 896 #define EXTRA_SPECS \ 897 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ 898 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 899 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \ 900 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ 901 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ 902 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \ 903 { "endian_spec", ENDIAN_SPEC }, \ 904 SUBTARGET_EXTRA_SPECS 905 906 #ifndef SUBTARGET_EXTRA_SPECS 907 #define SUBTARGET_EXTRA_SPECS 908 #endif 909 910 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */ 911 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */ 912 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */ 913 914 #ifndef PREFERRED_DEBUGGING_TYPE 915 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 916 #endif 917 918 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4) 919 920 /* By default, turn on GDB extensions. */ 921 #define DEFAULT_GDB_EXTENSIONS 1 922 923 /* Local compiler-generated symbols must have a prefix that the assembler 924 understands. By default, this is $, although some targets (e.g., 925 NetBSD-ELF) need to override this. */ 926 927 #ifndef LOCAL_LABEL_PREFIX 928 #define LOCAL_LABEL_PREFIX "$" 929 #endif 930 931 /* By default on the mips, external symbols do not have an underscore 932 prepended, but some targets (e.g., NetBSD) require this. */ 933 934 #ifndef USER_LABEL_PREFIX 935 #define USER_LABEL_PREFIX "" 936 #endif 937 938 /* On Sun 4, this limit is 2048. We use 1500 to be safe, 939 since the length can run past this up to a continuation point. */ 940 #undef DBX_CONTIN_LENGTH 941 #define DBX_CONTIN_LENGTH 1500 942 943 /* How to renumber registers for dbx and gdb. */ 944 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ] 945 946 /* The mapping from gcc register number to DWARF 2 CFA column number. */ 947 #define DWARF_FRAME_REGNUM(REG) (REG) 948 949 /* The DWARF 2 CFA column which tracks the return address. */ 950 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31) 951 952 /* The DWARF 2 CFA column which tracks the return address from a 953 signal handler context. */ 954 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1) 955 956 /* Before the prologue, RA lives in r31. */ 957 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31) 958 959 /* Describe how we implement __builtin_eh_return. */ 960 #define EH_RETURN_DATA_REGNO(N) \ 961 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 962 963 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) 964 965 /* Offsets recorded in opcodes are a multiple of this alignment factor. 966 The default for this in 64-bit mode is 8, which causes problems with 967 SFmode register saves. */ 968 #define DWARF_CIE_DATA_ALIGNMENT -4 969 970 /* Correct the offset of automatic variables and arguments. Note that 971 the MIPS debug format wants all automatic variables and arguments 972 to be in terms of the virtual frame pointer (stack pointer before 973 any adjustment in the function), while the MIPS 3.0 linker wants 974 the frame pointer to be the stack pointer after the initial 975 adjustment. */ 976 977 #define DEBUGGER_AUTO_OFFSET(X) \ 978 mips_debugger_offset (X, (HOST_WIDE_INT) 0) 979 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ 980 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) 981 982 /* Target machine storage layout */ 983 984 #define BITS_BIG_ENDIAN 0 985 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 986 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 987 988 /* Define this to set the endianness to use in libgcc2.c, which can 989 not depend on target_flags. */ 990 #if !defined(MIPSEL) && !defined(__MIPSEL__) 991 #define LIBGCC2_WORDS_BIG_ENDIAN 1 992 #else 993 #define LIBGCC2_WORDS_BIG_ENDIAN 0 994 #endif 995 996 #define MAX_BITS_PER_WORD 64 997 998 /* Width of a word, in units (bytes). */ 999 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 1000 #ifndef IN_LIBGCC2 1001 #define MIN_UNITS_PER_WORD 4 1002 #endif 1003 1004 /* For MIPS, width of a floating point register. */ 1005 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) 1006 1007 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is 1008 the next available register. */ 1009 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) 1010 1011 /* The largest size of value that can be held in floating-point 1012 registers and moved with a single instruction. */ 1013 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG) 1014 1015 /* The largest size of value that can be held in floating-point 1016 registers. */ 1017 #define UNITS_PER_FPVALUE \ 1018 (TARGET_SOFT_FLOAT ? 0 \ 1019 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ 1020 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) 1021 1022 /* The number of bytes in a double. */ 1023 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) 1024 1025 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD) 1026 1027 /* Set the sizes of the core types. */ 1028 #define SHORT_TYPE_SIZE 16 1029 #define INT_TYPE_SIZE 32 1030 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) 1031 #define LONG_LONG_TYPE_SIZE 64 1032 1033 #define FLOAT_TYPE_SIZE 32 1034 #define DOUBLE_TYPE_SIZE 64 1035 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64) 1036 1037 /* long double is not a fixed mode, but the idea is that, if we 1038 support long double, we also want a 128-bit integer type. */ 1039 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE 1040 1041 #ifdef IN_LIBGCC2 1042 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \ 1043 || (defined _ABI64 && _MIPS_SIM == _ABI64) 1044 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 1045 # else 1046 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 1047 # endif 1048 #endif 1049 1050 /* Width in bits of a pointer. */ 1051 #ifndef POINTER_SIZE 1052 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32) 1053 #endif 1054 1055 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 1056 #define PARM_BOUNDARY BITS_PER_WORD 1057 1058 /* Allocation boundary (in *bits*) for the code of a function. */ 1059 #define FUNCTION_BOUNDARY 32 1060 1061 /* Alignment of field after `int : 0' in a structure. */ 1062 #define EMPTY_FIELD_BOUNDARY 32 1063 1064 /* Every structure's size must be a multiple of this. */ 1065 /* 8 is observed right on a DECstation and on riscos 4.02. */ 1066 #define STRUCTURE_SIZE_BOUNDARY 8 1067 1068 /* There is no point aligning anything to a rounder boundary than this. */ 1069 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE 1070 1071 /* All accesses must be aligned. */ 1072 #define STRICT_ALIGNMENT 1 1073 1074 /* Define this if you wish to imitate the way many other C compilers 1075 handle alignment of bitfields and the structures that contain 1076 them. 1077 1078 The behavior is that the type written for a bit-field (`int', 1079 `short', or other integer type) imposes an alignment for the 1080 entire structure, as if the structure really did contain an 1081 ordinary field of that type. In addition, the bit-field is placed 1082 within the structure so that it would fit within such a field, 1083 not crossing a boundary for it. 1084 1085 Thus, on most machines, a bit-field whose type is written as `int' 1086 would not cross a four-byte boundary, and would force four-byte 1087 alignment for the whole structure. (The alignment used may not 1088 be four bytes; it is controlled by the other alignment 1089 parameters.) 1090 1091 If the macro is defined, its definition should be a C expression; 1092 a nonzero value for the expression enables this behavior. */ 1093 1094 #define PCC_BITFIELD_TYPE_MATTERS 1 1095 1096 /* If defined, a C expression to compute the alignment given to a 1097 constant that is being placed in memory. CONSTANT is the constant 1098 and ALIGN is the alignment that the object would ordinarily have. 1099 The value of this macro is used instead of that alignment to align 1100 the object. 1101 1102 If this macro is not defined, then ALIGN is used. 1103 1104 The typical use of this macro is to increase alignment for string 1105 constants to be word aligned so that `strcpy' calls that copy 1106 constants can be done inline. */ 1107 1108 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 1109 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ 1110 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 1111 1112 /* If defined, a C expression to compute the alignment for a static 1113 variable. TYPE is the data type, and ALIGN is the alignment that 1114 the object would ordinarily have. The value of this macro is used 1115 instead of that alignment to align the object. 1116 1117 If this macro is not defined, then ALIGN is used. 1118 1119 One use of this macro is to increase alignment of medium-size 1120 data to make it all fit in fewer cache lines. Another is to 1121 cause character arrays to be word-aligned so that `strcpy' calls 1122 that copy constants to character arrays can be done inline. */ 1123 1124 #undef DATA_ALIGNMENT 1125 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 1126 ((((ALIGN) < BITS_PER_WORD) \ 1127 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 1128 || TREE_CODE (TYPE) == UNION_TYPE \ 1129 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 1130 1131 /* Make local arrays of chars word-aligned for the same reasons. */ 1132 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) 1133 1134 #define PAD_VARARGS_DOWN \ 1135 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1136 1137 /* Define if operations between registers always perform the operation 1138 on the full register even if a narrower mode is specified. */ 1139 #define WORD_REGISTER_OPERATIONS 1140 1141 /* When in 64 bit mode, move insns will sign extend SImode and CCmode 1142 moves. All other references are zero extended. */ 1143 #define LOAD_EXTEND_OP(MODE) \ 1144 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ 1145 ? SIGN_EXTEND : ZERO_EXTEND) 1146 1147 /* Define this macro if it is advisable to hold scalars in registers 1148 in a wider mode than that declared by the program. In such cases, 1149 the value is constrained to be within the bounds of the declared 1150 type, but kept valid in the wider mode. The signedness of the 1151 extension may differ from that of the type. */ 1152 1153 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1154 if (GET_MODE_CLASS (MODE) == MODE_INT \ 1155 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 1156 { \ 1157 if ((MODE) == SImode) \ 1158 (UNSIGNEDP) = 0; \ 1159 (MODE) = Pmode; \ 1160 } 1161 1162 /* Define if loading short immediate values into registers sign extends. */ 1163 #define SHORT_IMMEDIATES_SIGN_EXTEND 1164 1165 /* The [d]clz instructions have the natural values at 0. */ 1166 1167 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1168 ((VALUE) = GET_MODE_BITSIZE (MODE), true) 1169 1170 /* Standard register usage. */ 1171 1172 /* Number of hardware registers. We have: 1173 1174 - 32 integer registers 1175 - 32 floating point registers 1176 - 8 condition code registers 1177 - 2 accumulator registers (hi and lo) 1178 - 32 registers each for coprocessors 0, 2 and 3 1179 - 3 fake registers: 1180 - ARG_POINTER_REGNUM 1181 - FRAME_POINTER_REGNUM 1182 - FAKE_CALL_REGNO (see the comment above load_callsi for details) 1183 - 3 dummy entries that were used at various times in the past. 1184 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE 1185 - 6 DSP control registers */ 1186 1187 #define FIRST_PSEUDO_REGISTER 188 1188 1189 /* By default, fix the kernel registers ($26 and $27), the global 1190 pointer ($28) and the stack pointer ($29). This can change 1191 depending on the command-line options. 1192 1193 Regarding coprocessor registers: without evidence to the contrary, 1194 it's best to assume that each coprocessor register has a unique 1195 use. This can be overridden, in, e.g., override_options() or 1196 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate 1197 for a particular target. */ 1198 1199 #define FIXED_REGISTERS \ 1200 { \ 1201 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1202 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ 1203 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1204 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1205 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \ 1206 /* COP0 registers */ \ 1207 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1208 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1209 /* COP2 registers */ \ 1210 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1211 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1212 /* COP3 registers */ \ 1213 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1214 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1215 /* 6 DSP accumulator registers & 6 control registers */ \ 1216 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \ 1217 } 1218 1219 1220 /* Set up this array for o32 by default. 1221 1222 Note that we don't mark $31 as a call-clobbered register. The idea is 1223 that it's really the call instructions themselves which clobber $31. 1224 We don't care what the called function does with it afterwards. 1225 1226 This approach makes it easier to implement sibcalls. Unlike normal 1227 calls, sibcalls don't clobber $31, so the register reaches the 1228 called function in tact. EPILOGUE_USES says that $31 is useful 1229 to the called function. */ 1230 1231 #define CALL_USED_REGISTERS \ 1232 { \ 1233 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1234 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ 1235 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1236 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1237 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1238 /* COP0 registers */ \ 1239 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1240 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1241 /* COP2 registers */ \ 1242 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1243 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1244 /* COP3 registers */ \ 1245 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1246 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1247 /* 6 DSP accumulator registers & 6 control registers */ \ 1248 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ 1249 } 1250 1251 1252 /* Define this since $28, though fixed, is call-saved in many ABIs. */ 1253 1254 #define CALL_REALLY_USED_REGISTERS \ 1255 { /* General registers. */ \ 1256 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1257 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \ 1258 /* Floating-point registers. */ \ 1259 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1260 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1261 /* Others. */ \ 1262 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1263 /* COP0 registers */ \ 1264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1266 /* COP2 registers */ \ 1267 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1268 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1269 /* COP3 registers */ \ 1270 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1271 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1272 /* 6 DSP accumulator registers & 6 control registers */ \ 1273 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \ 1274 } 1275 1276 /* Internal macros to classify a register number as to whether it's a 1277 general purpose register, a floating point register, a 1278 multiply/divide register, or a status register. */ 1279 1280 #define GP_REG_FIRST 0 1281 #define GP_REG_LAST 31 1282 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 1283 #define GP_DBX_FIRST 0 1284 1285 #define FP_REG_FIRST 32 1286 #define FP_REG_LAST 63 1287 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 1288 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) 1289 1290 #define MD_REG_FIRST 64 1291 #define MD_REG_LAST 65 1292 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) 1293 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM) 1294 1295 #define ST_REG_FIRST 67 1296 #define ST_REG_LAST 74 1297 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) 1298 1299 1300 /* FIXME: renumber. */ 1301 #define COP0_REG_FIRST 80 1302 #define COP0_REG_LAST 111 1303 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) 1304 1305 #define COP2_REG_FIRST 112 1306 #define COP2_REG_LAST 143 1307 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) 1308 1309 #define COP3_REG_FIRST 144 1310 #define COP3_REG_LAST 175 1311 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) 1312 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */ 1313 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1) 1314 1315 #define DSP_ACC_REG_FIRST 176 1316 #define DSP_ACC_REG_LAST 181 1317 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1) 1318 1319 #define AT_REGNUM (GP_REG_FIRST + 1) 1320 #define HI_REGNUM (MD_REG_FIRST + 0) 1321 #define LO_REGNUM (MD_REG_FIRST + 1) 1322 #define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0) 1323 #define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1) 1324 #define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2) 1325 #define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3) 1326 #define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4) 1327 #define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5) 1328 1329 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC. 1330 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG 1331 should be used instead. */ 1332 #define FPSW_REGNUM ST_REG_FIRST 1333 1334 #define GP_REG_P(REGNO) \ 1335 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 1336 #define M16_REG_P(REGNO) \ 1337 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) 1338 #define FP_REG_P(REGNO) \ 1339 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 1340 #define MD_REG_P(REGNO) \ 1341 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) 1342 #define ST_REG_P(REGNO) \ 1343 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) 1344 #define COP0_REG_P(REGNO) \ 1345 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) 1346 #define COP2_REG_P(REGNO) \ 1347 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) 1348 #define COP3_REG_P(REGNO) \ 1349 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) 1350 #define ALL_COP_REG_P(REGNO) \ 1351 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) 1352 /* Test if REGNO is one of the 6 new DSP accumulators. */ 1353 #define DSP_ACC_REG_P(REGNO) \ 1354 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM) 1355 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */ 1356 #define ACC_REG_P(REGNO) \ 1357 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO)) 1358 /* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */ 1359 #define ACC_HI_REG_P(REGNO) \ 1360 ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \ 1361 || (REGNO) == AC3HI_REGNUM) 1362 1363 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 1364 1365 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used 1366 to initialize the mips16 gp pseudo register. */ 1367 #define CONST_GP_P(X) \ 1368 (GET_CODE (X) == CONST \ 1369 && GET_CODE (XEXP (X, 0)) == UNSPEC \ 1370 && XINT (XEXP (X, 0), 1) == UNSPEC_GP) 1371 1372 /* Return coprocessor number from register number. */ 1373 1374 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ 1375 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ 1376 : COP3_REG_P (REGNO) ? '3' : '?') 1377 1378 1379 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE) 1380 1381 /* To make the code simpler, HARD_REGNO_MODE_OK just references an 1382 array built in override_options. Because machmodes.h is not yet 1383 included before this file is processed, the MODE bound can't be 1384 expressed here. */ 1385 1386 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; 1387 1388 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1389 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ] 1390 1391 /* Value is 1 if it is a good idea to tie two pseudo registers 1392 when one has mode MODE1 and one has mode MODE2. 1393 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1394 for any hard reg, then this must be 0 for correct output. */ 1395 #define MODES_TIEABLE_P(MODE1, MODE2) \ 1396 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ 1397 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 1398 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ 1399 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) 1400 1401 /* Register to use for pushing function arguments. */ 1402 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) 1403 1404 /* These two registers don't really exist: they get eliminated to either 1405 the stack or hard frame pointer. */ 1406 #define ARG_POINTER_REGNUM 77 1407 #define FRAME_POINTER_REGNUM 78 1408 1409 /* $30 is not available on the mips16, so we use $17 as the frame 1410 pointer. */ 1411 #define HARD_FRAME_POINTER_REGNUM \ 1412 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) 1413 1414 /* Value should be nonzero if functions must have frame pointers. 1415 Zero means the frame pointer need not be set up (and parms 1416 may be accessed via the stack pointer) in functions that seem suitable. 1417 This is computed in `reload', in reload1.c. */ 1418 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca) 1419 1420 /* Register in which static-chain is passed to a function. */ 1421 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2) 1422 1423 /* Registers used as temporaries in prologue/epilogue code. If we're 1424 generating mips16 code, these registers must come from the core set 1425 of 8. The prologue register mustn't conflict with any incoming 1426 arguments, the static chain pointer, or the frame pointer. The 1427 epilogue temporary mustn't conflict with the return registers, the 1428 frame pointer, the EH stack adjustment, or the EH data registers. */ 1429 1430 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3) 1431 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8)) 1432 1433 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM) 1434 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM) 1435 1436 /* Define this macro if it is as good or better to call a constant 1437 function address than to call an address kept in a register. */ 1438 #define NO_FUNCTION_CSE 1 1439 1440 /* The ABI-defined global pointer. Sometimes we use a different 1441 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ 1442 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) 1443 1444 /* We normally use $28 as the global pointer. However, when generating 1445 n32/64 PIC, it is better for leaf functions to use a call-clobbered 1446 register instead. They can then avoid saving and restoring $28 1447 and perhaps avoid using a frame at all. 1448 1449 When a leaf function uses something other than $28, mips_expand_prologue 1450 will modify pic_offset_table_rtx in place. Take the register number 1451 from there after reload. */ 1452 #define PIC_OFFSET_TABLE_REGNUM \ 1453 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM) 1454 1455 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25) 1456 1457 /* Define the classes of registers for register constraints in the 1458 machine description. Also define ranges of constants. 1459 1460 One of the classes must always be named ALL_REGS and include all hard regs. 1461 If there is more than one class, another class must be named NO_REGS 1462 and contain no registers. 1463 1464 The name GENERAL_REGS must be the name of a class (or an alias for 1465 another name such as ALL_REGS). This is the class of registers 1466 that is allowed by "g" or "r" in a register constraint. 1467 Also, registers outside this class are allocated only when 1468 instructions express preferences for them. 1469 1470 The classes must be numbered in nondecreasing order; that is, 1471 a larger-numbered class must never be contained completely 1472 in a smaller-numbered class. 1473 1474 For any two classes, it is very desirable that there be another 1475 class that represents their union. */ 1476 1477 enum reg_class 1478 { 1479 NO_REGS, /* no registers in set */ 1480 M16_NA_REGS, /* mips16 regs not used to pass args */ 1481 M16_REGS, /* mips16 directly accessible registers */ 1482 T_REG, /* mips16 T register ($24) */ 1483 M16_T_REGS, /* mips16 registers plus T register */ 1484 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ 1485 V1_REG, /* Register $v1 ($3) used for TLS access. */ 1486 LEA_REGS, /* Every GPR except $25 */ 1487 GR_REGS, /* integer registers */ 1488 FP_REGS, /* floating point registers */ 1489 HI_REG, /* hi register */ 1490 LO_REG, /* lo register */ 1491 MD_REGS, /* multiply/divide registers (hi/lo) */ 1492 COP0_REGS, /* generic coprocessor classes */ 1493 COP2_REGS, 1494 COP3_REGS, 1495 HI_AND_GR_REGS, /* union classes */ 1496 LO_AND_GR_REGS, 1497 HI_AND_FP_REGS, 1498 COP0_AND_GR_REGS, 1499 COP2_AND_GR_REGS, 1500 COP3_AND_GR_REGS, 1501 ALL_COP_REGS, 1502 ALL_COP_AND_GR_REGS, 1503 ST_REGS, /* status registers (fp status) */ 1504 DSP_ACC_REGS, /* DSP accumulator registers */ 1505 ACC_REGS, /* Hi/Lo and DSP accumulator registers */ 1506 ALL_REGS, /* all registers */ 1507 LIM_REG_CLASSES /* max value + 1 */ 1508 }; 1509 1510 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1511 1512 #define GENERAL_REGS GR_REGS 1513 1514 /* An initializer containing the names of the register classes as C 1515 string constants. These names are used in writing some of the 1516 debugging dumps. */ 1517 1518 #define REG_CLASS_NAMES \ 1519 { \ 1520 "NO_REGS", \ 1521 "M16_NA_REGS", \ 1522 "M16_REGS", \ 1523 "T_REG", \ 1524 "M16_T_REGS", \ 1525 "PIC_FN_ADDR_REG", \ 1526 "V1_REG", \ 1527 "LEA_REGS", \ 1528 "GR_REGS", \ 1529 "FP_REGS", \ 1530 "HI_REG", \ 1531 "LO_REG", \ 1532 "MD_REGS", \ 1533 /* coprocessor registers */ \ 1534 "COP0_REGS", \ 1535 "COP2_REGS", \ 1536 "COP3_REGS", \ 1537 "HI_AND_GR_REGS", \ 1538 "LO_AND_GR_REGS", \ 1539 "HI_AND_FP_REGS", \ 1540 "COP0_AND_GR_REGS", \ 1541 "COP2_AND_GR_REGS", \ 1542 "COP3_AND_GR_REGS", \ 1543 "ALL_COP_REGS", \ 1544 "ALL_COP_AND_GR_REGS", \ 1545 "ST_REGS", \ 1546 "DSP_ACC_REGS", \ 1547 "ACC_REGS", \ 1548 "ALL_REGS" \ 1549 } 1550 1551 /* An initializer containing the contents of the register classes, 1552 as integers which are bit masks. The Nth integer specifies the 1553 contents of class N. The way the integer MASK is interpreted is 1554 that register R is in the class if `MASK & (1 << R)' is 1. 1555 1556 When the machine has more than 32 registers, an integer does not 1557 suffice. Then the integers are replaced by sub-initializers, 1558 braced groupings containing several integers. Each 1559 sub-initializer must be suitable as an initializer for the type 1560 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 1561 1562 #define REG_CLASS_CONTENTS \ 1563 { \ 1564 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \ 1565 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\ 1566 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \ 1567 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \ 1568 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \ 1569 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \ 1570 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \ 1571 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \ 1572 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \ 1573 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \ 1574 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \ 1575 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \ 1576 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \ 1577 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \ 1578 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \ 1579 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \ 1580 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \ 1581 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \ 1582 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \ 1583 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \ 1584 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \ 1585 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \ 1586 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ 1587 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ 1588 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \ 1589 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \ 1590 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \ 1591 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \ 1592 } 1593 1594 1595 /* A C expression whose value is a register class containing hard 1596 register REGNO. In general there is more that one such class; 1597 choose a class which is "minimal", meaning that no smaller class 1598 also contains the register. */ 1599 1600 extern const enum reg_class mips_regno_to_class[]; 1601 1602 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] 1603 1604 /* A macro whose definition is the name of the class to which a 1605 valid base register must belong. A base register is one used in 1606 an address which is the register value plus a displacement. */ 1607 1608 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS) 1609 1610 /* A macro whose definition is the name of the class to which a 1611 valid index register must belong. An index register is one used 1612 in an address where its value is either multiplied by a scale 1613 factor or added to another register (as well as added to a 1614 displacement). */ 1615 1616 #define INDEX_REG_CLASS NO_REGS 1617 1618 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 1619 registers explicitly used in the rtl to be used as spill registers 1620 but prevents the compiler from extending the lifetime of these 1621 registers. */ 1622 1623 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16) 1624 1625 /* This macro is used later on in the file. */ 1626 #define GR_REG_CLASS_P(CLASS) \ 1627 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \ 1628 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \ 1629 || (CLASS) == V1_REG \ 1630 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS) 1631 1632 /* This macro is also used later on in the file. */ 1633 #define COP_REG_CLASS_P(CLASS) \ 1634 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS) 1635 1636 /* REG_ALLOC_ORDER is to order in which to allocate registers. This 1637 is the default value (allocate the registers in numeric order). We 1638 define it just so that we can override it for the mips16 target in 1639 ORDER_REGS_FOR_LOCAL_ALLOC. */ 1640 1641 #define REG_ALLOC_ORDER \ 1642 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 1643 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 1644 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1645 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ 1646 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 1647 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ 1648 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ 1649 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ 1650 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ 1651 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ 1652 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ 1653 176,177,178,179,180,181,182,183,184,185,186,187 \ 1654 } 1655 1656 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 1657 to be rearranged based on a particular function. On the mips16, we 1658 want to allocate $24 (T_REG) before other registers for 1659 instructions for which it is possible. */ 1660 1661 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () 1662 1663 /* True if VALUE is an unsigned 6-bit number. */ 1664 1665 #define UIMM6_OPERAND(VALUE) \ 1666 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) 1667 1668 /* True if VALUE is a signed 10-bit number. */ 1669 1670 #define IMM10_OPERAND(VALUE) \ 1671 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) 1672 1673 /* True if VALUE is a signed 16-bit number. */ 1674 1675 #define SMALL_OPERAND(VALUE) \ 1676 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) 1677 1678 /* True if VALUE is an unsigned 16-bit number. */ 1679 1680 #define SMALL_OPERAND_UNSIGNED(VALUE) \ 1681 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) 1682 1683 /* True if VALUE can be loaded into a register using LUI. */ 1684 1685 #define LUI_OPERAND(VALUE) \ 1686 (((VALUE) | 0x7fff0000) == 0x7fff0000 \ 1687 || ((VALUE) | 0x7fff0000) + 0x10000 == 0) 1688 1689 /* Return a value X with the low 16 bits clear, and such that 1690 VALUE - X is a signed 16-bit value. */ 1691 1692 #define CONST_HIGH_PART(VALUE) \ 1693 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) 1694 1695 #define CONST_LOW_PART(VALUE) \ 1696 ((VALUE) - CONST_HIGH_PART (VALUE)) 1697 1698 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) 1699 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X)) 1700 #define LUI_INT(X) LUI_OPERAND (INTVAL (X)) 1701 1702 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1703 mips_preferred_reload_class (X, CLASS) 1704 1705 /* Certain machines have the property that some registers cannot be 1706 copied to some other registers without using memory. Define this 1707 macro on those machines to be a C expression that is nonzero if 1708 objects of mode MODE in registers of CLASS1 can only be copied to 1709 registers of class CLASS2 by storing a register of CLASS1 into 1710 memory and loading that memory location into a register of CLASS2. 1711 1712 Do not define this macro if its value would always be zero. */ 1713 #if 0 1714 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1715 ((!TARGET_DEBUG_H_MODE \ 1716 && GET_MODE_CLASS (MODE) == MODE_INT \ 1717 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \ 1718 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \ 1719 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \ 1720 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \ 1721 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS)))) 1722 #endif 1723 /* The HI and LO registers can only be reloaded via the general 1724 registers. Condition code registers can only be loaded to the 1725 general registers, and from the floating point registers. */ 1726 1727 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1728 mips_secondary_reload_class (CLASS, MODE, X, 1) 1729 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1730 mips_secondary_reload_class (CLASS, MODE, X, 0) 1731 1732 /* Return the maximum number of consecutive registers 1733 needed to represent mode MODE in a register of class CLASS. */ 1734 1735 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) 1736 1737 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1738 mips_cannot_change_mode_class (FROM, TO, CLASS) 1739 1740 /* Stack layout; function entry, exit and calling. */ 1741 1742 #define STACK_GROWS_DOWNWARD 1743 1744 #define FRAME_GROWS_DOWNWARD 1 1745 1746 /* The offset of the first local variable from the beginning of the frame. 1747 See compute_frame_size for details about the frame layout. 1748 1749 ??? If flag_profile_values is true, and we are generating 32-bit code, then 1750 we assume that we will need 16 bytes of argument space. This is because 1751 the value profiling code may emit calls to cmpdi2 in leaf functions. 1752 Without this hack, the local variables will start at sp+8 and the gp save 1753 area will be at sp+16, and thus they will overlap. compute_frame_size is 1754 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which 1755 will end up as 24 instead of 8. This won't be needed if profiling code is 1756 inserted before virtual register instantiation. */ 1757 1758 #define STARTING_FRAME_OFFSET 0 1759 1760 #define RETURN_ADDR_RTX mips_return_addr 1761 1762 /* Since the mips16 ISA mode is encoded in the least-significant bit 1763 of the address, mask it off return addresses for purposes of 1764 finding exception handling regions. */ 1765 1766 #define MASK_RETURN_ADDR GEN_INT (-2) 1767 1768 1769 /* Similarly, don't use the least-significant bit to tell pointers to 1770 code from vtable index. */ 1771 1772 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 1773 1774 /* The eliminations to $17 are only used for mips16 code. See the 1775 definition of HARD_FRAME_POINTER_REGNUM. */ 1776 1777 #define ELIMINABLE_REGS \ 1778 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1779 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 1780 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ 1781 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1782 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ 1783 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} 1784 1785 /* We can always eliminate to the hard frame pointer. We can eliminate 1786 to the stack pointer unless a frame pointer is needed. 1787 1788 In mips16 mode, we need a frame pointer for a large frame; otherwise, 1789 reload may be unable to compute the address of a local variable, 1790 since there is no way to add a large constant to the stack pointer 1791 without using a temporary register. */ 1792 #define CAN_ELIMINATE(FROM, TO) \ 1793 ((TO) == HARD_FRAME_POINTER_REGNUM \ 1794 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \ 1795 && (!TARGET_MIPS16 \ 1796 || compute_frame_size (get_frame_size ()) < 32768))) 1797 1798 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1799 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO)) 1800 1801 /* Allocate stack space for arguments at the beginning of each function. */ 1802 #define ACCUMULATE_OUTGOING_ARGS 1 1803 1804 /* The argument pointer always points to the first argument. */ 1805 #define FIRST_PARM_OFFSET(FNDECL) 0 1806 1807 /* o32 and o64 reserve stack space for all argument registers. */ 1808 #define REG_PARM_STACK_SPACE(FNDECL) \ 1809 (TARGET_OLDABI \ 1810 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \ 1811 : 0) 1812 1813 /* Define this if it is the responsibility of the caller to 1814 allocate the area reserved for arguments passed in registers. 1815 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 1816 of this macro is to determine whether the space is included in 1817 `current_function_outgoing_args_size'. */ 1818 #define OUTGOING_REG_PARM_STACK_SPACE 1819 1820 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) 1821 1822 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1823 1824 /* Symbolic macros for the registers used to return integer and floating 1825 point values. */ 1826 1827 #define GP_RETURN (GP_REG_FIRST + 2) 1828 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) 1829 1830 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8) 1831 1832 /* Symbolic macros for the first/last argument registers. */ 1833 1834 #define GP_ARG_FIRST (GP_REG_FIRST + 4) 1835 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 1836 #define FP_ARG_FIRST (FP_REG_FIRST + 12) 1837 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 1838 1839 #define LIBCALL_VALUE(MODE) \ 1840 mips_function_value (NULL_TREE, NULL, (MODE)) 1841 1842 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1843 mips_function_value ((VALTYPE), (FUNC), VOIDmode) 1844 1845 /* 1 if N is a possible register number for a function value. 1846 On the MIPS, R2 R3 and F0 F2 are the only register thus used. 1847 Currently, R2 and F0 are only implemented here (C has no complex type) */ 1848 1849 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \ 1850 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \ 1851 && (N) == FP_RETURN + 2)) 1852 1853 /* 1 if N is a possible register number for function argument passing. 1854 We have no FP argument registers when soft-float. When FP registers 1855 are 32 bits, we can't directly reference the odd numbered ones. */ 1856 1857 #define FUNCTION_ARG_REGNO_P(N) \ 1858 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ 1859 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \ 1860 && !fixed_regs[N]) 1861 1862 /* This structure has to cope with two different argument allocation 1863 schemes. Most MIPS ABIs view the arguments as a structure, of which 1864 the first N words go in registers and the rest go on the stack. If I 1865 < N, the Ith word might go in Ith integer argument register or in a 1866 floating-point register. For these ABIs, we only need to remember 1867 the offset of the current argument into the structure. 1868 1869 The EABI instead allocates the integer and floating-point arguments 1870 separately. The first N words of FP arguments go in FP registers, 1871 the rest go on the stack. Likewise, the first N words of the other 1872 arguments go in integer registers, and the rest go on the stack. We 1873 need to maintain three counts: the number of integer registers used, 1874 the number of floating-point registers used, and the number of words 1875 passed on the stack. 1876 1877 We could keep separate information for the two ABIs (a word count for 1878 the standard ABIs, and three separate counts for the EABI). But it 1879 seems simpler to view the standard ABIs as forms of EABI that do not 1880 allocate floating-point registers. 1881 1882 So for the standard ABIs, the first N words are allocated to integer 1883 registers, and function_arg decides on an argument-by-argument basis 1884 whether that argument should really go in an integer register, or in 1885 a floating-point one. */ 1886 1887 typedef struct mips_args { 1888 /* Always true for varargs functions. Otherwise true if at least 1889 one argument has been passed in an integer register. */ 1890 int gp_reg_found; 1891 1892 /* The number of arguments seen so far. */ 1893 unsigned int arg_number; 1894 1895 /* The number of integer registers used so far. For all ABIs except 1896 EABI, this is the number of words that have been added to the 1897 argument structure, limited to MAX_ARGS_IN_REGISTERS. */ 1898 unsigned int num_gprs; 1899 1900 /* For EABI, the number of floating-point registers used so far. */ 1901 unsigned int num_fprs; 1902 1903 /* The number of words passed on the stack. */ 1904 unsigned int stack_words; 1905 1906 /* On the mips16, we need to keep track of which floating point 1907 arguments were passed in general registers, but would have been 1908 passed in the FP regs if this were a 32 bit function, so that we 1909 can move them to the FP regs if we wind up calling a 32 bit 1910 function. We record this information in fp_code, encoded in base 1911 four. A zero digit means no floating point argument, a one digit 1912 means an SFmode argument, and a two digit means a DFmode argument, 1913 and a three digit is not used. The low order digit is the first 1914 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by 1915 an SFmode argument. ??? A more sophisticated approach will be 1916 needed if MIPS_ABI != ABI_32. */ 1917 int fp_code; 1918 1919 /* True if the function has a prototype. */ 1920 int prototype; 1921 } CUMULATIVE_ARGS; 1922 1923 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1924 for a call to a function whose data type is FNTYPE. 1925 For a library call, FNTYPE is 0. */ 1926 1927 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1928 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \ 1929 1930 /* Update the data in CUM to advance over an argument 1931 of mode MODE and data type TYPE. 1932 (TYPE is null for libcalls where that information may not be available.) */ 1933 1934 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1935 function_arg_advance (&CUM, MODE, TYPE, NAMED) 1936 1937 /* Determine where to put an argument to a function. 1938 Value is zero to push the argument on the stack, 1939 or a hard register in which to store the argument. 1940 1941 MODE is the argument's machine mode. 1942 TYPE is the data type of the argument (as a tree). 1943 This is null for libcalls where that information may 1944 not be available. 1945 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1946 the preceding args and about the function being called. 1947 NAMED is nonzero if this argument is a named parameter 1948 (otherwise it is an extra parameter matching an ellipsis). */ 1949 1950 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1951 function_arg( &CUM, MODE, TYPE, NAMED) 1952 1953 #define FUNCTION_ARG_BOUNDARY function_arg_boundary 1954 1955 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1956 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward) 1957 1958 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1959 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward) 1960 1961 /* True if using EABI and varargs can be passed in floating-point 1962 registers. Under these conditions, we need a more complex form 1963 of va_list, which tracks GPR, FPR and stack arguments separately. */ 1964 #define EABI_FLOAT_VARARGS_P \ 1965 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) 1966 1967 1968 /* Say that the epilogue uses the return address register. Note that 1969 in the case of sibcalls, the values "used by the epilogue" are 1970 considered live at the start of the called function. */ 1971 #define EPILOGUE_USES(REGNO) ((REGNO) == 31) 1972 1973 /* Treat LOC as a byte offset from the stack pointer and round it up 1974 to the next fully-aligned offset. */ 1975 #define MIPS_STACK_ALIGN(LOC) \ 1976 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8) 1977 1978 1979 /* Implement `va_start' for varargs and stdarg. */ 1980 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1981 mips_va_start (valist, nextarg) 1982 1983 /* Output assembler code to FILE to increment profiler label # LABELNO 1984 for profiling a function entry. */ 1985 1986 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1987 { \ 1988 if (TARGET_MIPS16) \ 1989 sorry ("mips16 function profiling"); \ 1990 fprintf (FILE, "\t.set\tnoat\n"); \ 1991 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \ 1992 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \ 1993 if (!TARGET_NEWABI) \ 1994 { \ 1995 fprintf (FILE, \ 1996 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \ 1997 TARGET_64BIT ? "dsubu" : "subu", \ 1998 reg_names[STACK_POINTER_REGNUM], \ 1999 reg_names[STACK_POINTER_REGNUM], \ 2000 Pmode == DImode ? 16 : 8); \ 2001 } \ 2002 fprintf (FILE, "\tjal\t_mcount\n"); \ 2003 fprintf (FILE, "\t.set\tat\n"); \ 2004 } 2005 2006 /* No mips port has ever used the profiler counter word, so don't emit it 2007 or the label for it. */ 2008 2009 #define NO_PROFILE_COUNTERS 1 2010 2011 /* Define this macro if the code for function profiling should come 2012 before the function prologue. Normally, the profiling code comes 2013 after. */ 2014 2015 /* #define PROFILE_BEFORE_PROLOGUE */ 2016 2017 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 2018 the stack pointer does not matter. The value is tested only in 2019 functions that have frame pointers. 2020 No definition is equivalent to always zero. */ 2021 2022 #define EXIT_IGNORE_STACK 1 2023 2024 2025 /* A C statement to output, on the stream FILE, assembler code for a 2026 block of data that contains the constant parts of a trampoline. 2027 This code should not include a label--the label is taken care of 2028 automatically. */ 2029 2030 #define TRAMPOLINE_TEMPLATE(STREAM) \ 2031 { \ 2032 if (ptr_mode == DImode) \ 2033 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \ 2034 else \ 2035 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \ 2036 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \ 2037 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \ 2038 if (ptr_mode == DImode) \ 2039 { \ 2040 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \ 2041 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \ 2042 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \ 2043 } \ 2044 else \ 2045 { \ 2046 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \ 2047 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \ 2048 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \ 2049 } \ 2050 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \ 2051 if (ptr_mode == DImode) \ 2052 { \ 2053 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \ 2054 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \ 2055 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \ 2056 } \ 2057 else \ 2058 { \ 2059 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \ 2060 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \ 2061 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \ 2062 } \ 2063 } 2064 2065 /* A C expression for the size in bytes of the trampoline, as an 2066 integer. */ 2067 2068 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2) 2069 2070 /* Alignment required for trampolines, in bits. */ 2071 2072 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode) 2073 2074 /* INITIALIZE_TRAMPOLINE calls this library function to flush 2075 program and data caches. */ 2076 2077 #ifndef CACHE_FLUSH_FUNC 2078 #define CACHE_FLUSH_FUNC "_flush_cache" 2079 #endif 2080 2081 /* A C statement to initialize the variable parts of a trampoline. 2082 ADDR is an RTX for the address of the trampoline; FNADDR is an 2083 RTX for the address of the nested function; STATIC_CHAIN is an 2084 RTX for the static chain value that should be passed to the 2085 function when it is called. */ 2086 2087 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \ 2088 { \ 2089 rtx func_addr, chain_addr; \ 2090 \ 2091 func_addr = plus_constant (ADDR, 32); \ 2092 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \ 2093 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \ 2094 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \ 2095 \ 2096 /* Flush both caches. We need to flush the data cache in case \ 2097 the system has a write-back cache. */ \ 2098 /* ??? Should check the return value for errors. */ \ 2099 if (mips_cache_flush_func && mips_cache_flush_func[0]) \ 2100 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ 2101 0, VOIDmode, 3, ADDR, Pmode, \ 2102 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\ 2103 GEN_INT (3), TYPE_MODE (integer_type_node)); \ 2104 } 2105 2106 /* Addressing modes, and classification of registers for them. */ 2107 2108 #define REGNO_OK_FOR_INDEX_P(REGNO) 0 2109 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 2110 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1) 2111 2112 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2113 and check its validity for a certain class. 2114 We have two alternate definitions for each of them. 2115 The usual definition accepts all pseudo regs; the other rejects them all. 2116 The symbol REG_OK_STRICT causes the latter definition to be used. 2117 2118 Most source files want to accept pseudo regs in the hope that 2119 they will get allocated to the class that the insn wants them to be in. 2120 Some source files that are used after register allocation 2121 need to be strict. */ 2122 2123 #ifndef REG_OK_STRICT 2124 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2125 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) 2126 #else 2127 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2128 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) 2129 #endif 2130 2131 #define REG_OK_FOR_INDEX_P(X) 0 2132 2133 2134 /* Maximum number of registers that can appear in a valid memory address. */ 2135 2136 #define MAX_REGS_PER_ADDRESS 1 2137 2138 #ifdef REG_OK_STRICT 2139 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2140 { \ 2141 if (mips_legitimate_address_p (MODE, X, 1)) \ 2142 goto ADDR; \ 2143 } 2144 #else 2145 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2146 { \ 2147 if (mips_legitimate_address_p (MODE, X, 0)) \ 2148 goto ADDR; \ 2149 } 2150 #endif 2151 2152 /* Check for constness inline but use mips_legitimate_address_p 2153 to check whether a constant really is an address. */ 2154 2155 #define CONSTANT_ADDRESS_P(X) \ 2156 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0)) 2157 2158 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0) 2159 2160 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2161 do { \ 2162 if (mips_legitimize_address (&(X), MODE)) \ 2163 goto WIN; \ 2164 } while (0) 2165 2166 2167 /* A C statement or compound statement with a conditional `goto 2168 LABEL;' executed if memory address X (an RTX) can have different 2169 meanings depending on the machine mode of the memory reference it 2170 is used for. 2171 2172 Autoincrement and autodecrement addresses typically have 2173 mode-dependent effects because the amount of the increment or 2174 decrement is the size of the operand being addressed. Some 2175 machines have other mode-dependent addresses. Many RISC machines 2176 have no mode-dependent addresses. 2177 2178 You may assume that ADDR is a valid address for the machine. */ 2179 2180 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {} 2181 2182 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means 2183 'the start of the function that this code is output in'. */ 2184 2185 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 2186 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 2187 asm_fprintf ((FILE), "%U%s", \ 2188 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ 2189 else \ 2190 asm_fprintf ((FILE), "%U%s", (NAME)) 2191 2192 /* Flag to mark a function decl symbol that requires a long call. */ 2193 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0) 2194 #define SYMBOL_REF_LONG_CALL_P(X) \ 2195 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) 2196 2197 /* Specify the machine mode that this machine uses 2198 for the index in the tablejump instruction. 2199 ??? Using HImode in mips16 mode can cause overflow. */ 2200 #define CASE_VECTOR_MODE \ 2201 (TARGET_MIPS16 ? HImode : ptr_mode) 2202 2203 /* Define as C expression which evaluates to nonzero if the tablejump 2204 instruction expects the table to contain offsets from the address of the 2205 table. 2206 Do not define this if the table should contain absolute addresses. */ 2207 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16) 2208 2209 /* Define this as 1 if `char' should by default be signed; else as 0. */ 2210 #ifndef DEFAULT_SIGNED_CHAR 2211 #define DEFAULT_SIGNED_CHAR 1 2212 #endif 2213 2214 /* Max number of bytes we can move from memory to memory 2215 in one reasonably fast instruction. */ 2216 #define MOVE_MAX (TARGET_64BIT ? 8 : 4) 2217 #define MAX_MOVE_MAX 8 2218 2219 /* Define this macro as a C expression which is nonzero if 2220 accessing less than a word of memory (i.e. a `char' or a 2221 `short') is no faster than accessing a word of memory, i.e., if 2222 such access require more than one instruction or if there is no 2223 difference in cost between byte and (aligned) word loads. 2224 2225 On RISC machines, it tends to generate better code to define 2226 this as 1, since it avoids making a QI or HI mode register. */ 2227 #define SLOW_BYTE_ACCESS 1 2228 2229 /* Define this to be nonzero if shift instructions ignore all but the low-order 2230 few bits. */ 2231 #define SHIFT_COUNT_TRUNCATED 1 2232 2233 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2234 is done just by pretending it is already truncated. */ 2235 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \ 2236 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1) 2237 2238 2239 /* Specify the machine mode that pointers have. 2240 After generation of rtl, the compiler makes no further distinction 2241 between pointers and any other objects of this machine mode. */ 2242 2243 #ifndef Pmode 2244 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode) 2245 #endif 2246 2247 /* Give call MEMs SImode since it is the "most permissive" mode 2248 for both 32-bit and 64-bit targets. */ 2249 2250 #define FUNCTION_MODE SImode 2251 2252 2253 /* The cost of loading values from the constant pool. It should be 2254 larger than the cost of any constant we want to synthesize in-line. */ 2255 2256 #define CONSTANT_POOL_COST COSTS_N_INSNS (8) 2257 2258 /* A C expression for the cost of moving data from a register in 2259 class FROM to one in class TO. The classes are expressed using 2260 the enumeration values such as `GENERAL_REGS'. A value of 2 is 2261 the default; other values are interpreted relative to that. 2262 2263 It is not required that the cost always equal 2 when FROM is the 2264 same as TO; on some machines it is expensive to move between 2265 registers if they are not general registers. 2266 2267 If reload sees an insn consisting of a single `set' between two 2268 hard registers, and if `REGISTER_MOVE_COST' applied to their 2269 classes returns a value of 2, reload does not check to ensure 2270 that the constraints of the insn are met. Setting a cost of 2271 other than 2 will allow reload to verify that the constraints are 2272 met. You should do this if the `movM' pattern's constraints do 2273 not allow such copying. */ 2274 2275 #define REGISTER_MOVE_COST(MODE, FROM, TO) \ 2276 mips_register_move_cost (MODE, FROM, TO) 2277 2278 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ 2279 (mips_cost->memory_latency \ 2280 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P))) 2281 2282 /* Define if copies to/from condition code registers should be avoided. 2283 2284 This is needed for the MIPS because reload_outcc is not complete; 2285 it needs to handle cases where the source is a general or another 2286 condition code register. */ 2287 #define AVOID_CCMODE_COPIES 2288 2289 /* A C expression for the cost of a branch instruction. A value of 2290 1 is the default; other values are interpreted relative to that. */ 2291 2292 #define BRANCH_COST mips_cost->branch_cost 2293 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 2294 2295 /* If defined, modifies the length assigned to instruction INSN as a 2296 function of the context in which it is used. LENGTH is an lvalue 2297 that contains the initially computed length of the insn and should 2298 be updated with the correct length of the insn. */ 2299 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2300 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) 2301 2302 /* Return the asm template for a non-MIPS16 conditional branch instruction. 2303 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for 2304 its operands. */ 2305 #define MIPS_BRANCH(OPCODE, OPERANDS) \ 2306 "%*" OPCODE "%?\t" OPERANDS "%/" 2307 2308 /* Return the asm template for a call. INSN is the instruction's mnemonic 2309 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number 2310 of the target. 2311 2312 When generating -mabicalls without explicit relocation operators, 2313 all calls should use assembly macros. Otherwise, all indirect 2314 calls should use "jr" or "jalr"; we will arrange to restore $gp 2315 afterwards if necessary. Finally, we can only generate direct 2316 calls for -mabicalls by temporarily switching to non-PIC mode. */ 2317 #define MIPS_CALL(INSN, OPERANDS, OPNO) \ 2318 (TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS \ 2319 ? "%*" INSN "\t%" #OPNO "%/" \ 2320 : REG_P (OPERANDS[OPNO]) \ 2321 ? "%*" INSN "r\t%" #OPNO "%/" \ 2322 : TARGET_ABICALLS \ 2323 ? (".option\tpic0\n\t" \ 2324 "%*" INSN "\t%" #OPNO "%/\n\t" \ 2325 ".option\tpic2") \ 2326 : "%*" INSN "\t%" #OPNO "%/") 2327 2328 /* Control the assembler format that we output. */ 2329 2330 /* Output to assembler file text saying following lines 2331 may contain character constants, extra white space, comments, etc. */ 2332 2333 #ifndef ASM_APP_ON 2334 #define ASM_APP_ON " #APP\n" 2335 #endif 2336 2337 /* Output to assembler file text saying following lines 2338 no longer contain unusual constructs. */ 2339 2340 #ifndef ASM_APP_OFF 2341 #define ASM_APP_OFF " #NO_APP\n" 2342 #endif 2343 2344 #define REGISTER_NAMES \ 2345 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ 2346 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 2347 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ 2348 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \ 2349 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ 2350 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 2351 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ 2352 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ 2353 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ 2354 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \ 2355 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \ 2356 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \ 2357 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \ 2358 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \ 2359 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \ 2360 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \ 2361 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \ 2362 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \ 2363 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \ 2364 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \ 2365 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \ 2366 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \ 2367 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \ 2368 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" } 2369 2370 /* List the "software" names for each register. Also list the numerical 2371 names for $fp and $sp. */ 2372 2373 #define ADDITIONAL_REGISTER_NAMES \ 2374 { \ 2375 { "$29", 29 + GP_REG_FIRST }, \ 2376 { "$30", 30 + GP_REG_FIRST }, \ 2377 { "at", 1 + GP_REG_FIRST }, \ 2378 { "v0", 2 + GP_REG_FIRST }, \ 2379 { "v1", 3 + GP_REG_FIRST }, \ 2380 { "a0", 4 + GP_REG_FIRST }, \ 2381 { "a1", 5 + GP_REG_FIRST }, \ 2382 { "a2", 6 + GP_REG_FIRST }, \ 2383 { "a3", 7 + GP_REG_FIRST }, \ 2384 { "t0", 8 + GP_REG_FIRST }, \ 2385 { "t1", 9 + GP_REG_FIRST }, \ 2386 { "t2", 10 + GP_REG_FIRST }, \ 2387 { "t3", 11 + GP_REG_FIRST }, \ 2388 { "t4", 12 + GP_REG_FIRST }, \ 2389 { "t5", 13 + GP_REG_FIRST }, \ 2390 { "t6", 14 + GP_REG_FIRST }, \ 2391 { "t7", 15 + GP_REG_FIRST }, \ 2392 { "s0", 16 + GP_REG_FIRST }, \ 2393 { "s1", 17 + GP_REG_FIRST }, \ 2394 { "s2", 18 + GP_REG_FIRST }, \ 2395 { "s3", 19 + GP_REG_FIRST }, \ 2396 { "s4", 20 + GP_REG_FIRST }, \ 2397 { "s5", 21 + GP_REG_FIRST }, \ 2398 { "s6", 22 + GP_REG_FIRST }, \ 2399 { "s7", 23 + GP_REG_FIRST }, \ 2400 { "t8", 24 + GP_REG_FIRST }, \ 2401 { "t9", 25 + GP_REG_FIRST }, \ 2402 { "k0", 26 + GP_REG_FIRST }, \ 2403 { "k1", 27 + GP_REG_FIRST }, \ 2404 { "gp", 28 + GP_REG_FIRST }, \ 2405 { "sp", 29 + GP_REG_FIRST }, \ 2406 { "fp", 30 + GP_REG_FIRST }, \ 2407 { "ra", 31 + GP_REG_FIRST }, \ 2408 ALL_COP_ADDITIONAL_REGISTER_NAMES \ 2409 } 2410 2411 /* This is meant to be redefined in the host dependent files. It is a 2412 set of alternative names and regnums for mips coprocessors. */ 2413 2414 #define ALL_COP_ADDITIONAL_REGISTER_NAMES 2415 2416 /* A C compound statement to output to stdio stream STREAM the 2417 assembler syntax for an instruction operand X. X is an RTL 2418 expression. 2419 2420 CODE is a value that can be used to specify one of several ways 2421 of printing the operand. It is used when identical operands 2422 must be printed differently depending on the context. CODE 2423 comes from the `%' specification that was used to request 2424 printing of the operand. If the specification was just `%DIGIT' 2425 then CODE is 0; if the specification was `%LTR DIGIT' then CODE 2426 is the ASCII code for LTR. 2427 2428 If X is a register, this macro should print the register's name. 2429 The names can be found in an array `reg_names' whose type is 2430 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. 2431 2432 When the machine description has a specification `%PUNCT' (a `%' 2433 followed by a punctuation character), this macro is called with 2434 a null pointer for X and the punctuation character for CODE. 2435 2436 See mips.c for the MIPS specific codes. */ 2437 2438 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2439 2440 /* A C expression which evaluates to true if CODE is a valid 2441 punctuation character for use in the `PRINT_OPERAND' macro. If 2442 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no 2443 punctuation characters (except for the standard one, `%') are 2444 used in this way. */ 2445 2446 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE] 2447 2448 /* A C compound statement to output to stdio stream STREAM the 2449 assembler syntax for an instruction operand that is a memory 2450 reference whose address is ADDR. ADDR is an RTL expression. */ 2451 2452 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2453 2454 2455 /* A C statement, to be executed after all slot-filler instructions 2456 have been output. If necessary, call `dbr_sequence_length' to 2457 determine the number of slots filled in a sequence (zero if not 2458 currently outputting a sequence), to decide how many no-ops to 2459 output, or whatever. 2460 2461 Don't define this macro if it has nothing to do, but it is 2462 helpful in reading assembly output if the extent of the delay 2463 sequence is made explicit (e.g. with white space). 2464 2465 Note that output routines for instructions with delay slots must 2466 be prepared to deal with not being output as part of a sequence 2467 (i.e. when the scheduling pass is not run, or when no slot 2468 fillers could be found.) The variable `final_sequence' is null 2469 when not processing a sequence, otherwise it contains the 2470 `sequence' rtx being output. */ 2471 2472 #define DBR_OUTPUT_SEQEND(STREAM) \ 2473 do \ 2474 { \ 2475 if (set_nomacro > 0 && --set_nomacro == 0) \ 2476 fputs ("\t.set\tmacro\n", STREAM); \ 2477 \ 2478 if (set_noreorder > 0 && --set_noreorder == 0) \ 2479 fputs ("\t.set\treorder\n", STREAM); \ 2480 \ 2481 fputs ("\n", STREAM); \ 2482 } \ 2483 while (0) 2484 2485 2486 /* How to tell the debugger about changes of source files. */ 2487 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ 2488 mips_output_filename (STREAM, NAME) 2489 2490 /* mips-tfile does not understand .stabd directives. */ 2491 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \ 2492 dbxout_begin_stabn_sline (LINE); \ 2493 dbxout_stab_value_internal_label ("LM", &COUNTER); \ 2494 } while (0) 2495 2496 /* Use .loc directives for SDB line numbers. */ 2497 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \ 2498 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE) 2499 2500 /* The MIPS implementation uses some labels for its own purpose. The 2501 following lists what labels are created, and are all formed by the 2502 pattern $L[a-z].*. The machine independent portion of GCC creates 2503 labels matching: $L[A-Z][0-9]+ and $L[0-9]+. 2504 2505 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. 2506 $Lb[0-9]+ Begin blocks for MIPS debug support 2507 $Lc[0-9]+ Label for use in s<xx> operation. 2508 $Le[0-9]+ End blocks for MIPS debug support */ 2509 2510 #undef ASM_DECLARE_OBJECT_NAME 2511 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ 2512 mips_declare_object (STREAM, NAME, "", ":\n", 0) 2513 2514 /* Globalizing directive for a label. */ 2515 #define GLOBAL_ASM_OP "\t.globl\t" 2516 2517 /* This says how to define a global common symbol. */ 2518 2519 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common 2520 2521 /* This says how to define a local common symbol (i.e., not visible to 2522 linker). */ 2523 2524 #ifndef ASM_OUTPUT_ALIGNED_LOCAL 2525 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ 2526 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false) 2527 #endif 2528 2529 /* This says how to output an external. It would be possible not to 2530 output anything and let undefined symbol become external. However 2531 the assembler uses length information on externals to allocate in 2532 data/sdata bss/sbss, thereby saving exec time. */ 2533 2534 #undef ASM_OUTPUT_EXTERNAL 2535 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ 2536 mips_output_external(STREAM,DECL,NAME) 2537 2538 /* This is how to declare a function name. The actual work of 2539 emitting the label is moved to function_prologue, so that we can 2540 get the line number correctly emitted before the .ent directive, 2541 and after any .file directives. Define as empty so that the function 2542 is not declared before the .ent directive elsewhere. */ 2543 2544 #undef ASM_DECLARE_FUNCTION_NAME 2545 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) 2546 2547 #ifndef FUNCTION_NAME_ALREADY_DECLARED 2548 #define FUNCTION_NAME_ALREADY_DECLARED 0 2549 #endif 2550 2551 /* This is how to store into the string LABEL 2552 the symbol_ref name of an internal numbered label where 2553 PREFIX is the class of label and NUM is the number within the class. 2554 This is suitable for output with `assemble_name'. */ 2555 2556 #undef ASM_GENERATE_INTERNAL_LABEL 2557 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2558 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 2559 2560 /* This is how to output an element of a case-vector that is absolute. */ 2561 2562 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 2563 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2564 ptr_mode == DImode ? ".dword" : ".word", \ 2565 LOCAL_LABEL_PREFIX, \ 2566 VALUE) 2567 2568 /* This is how to output an element of a case-vector. We can make the 2569 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word 2570 is supported. */ 2571 2572 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 2573 do { \ 2574 if (TARGET_MIPS16) \ 2575 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ 2576 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ 2577 else if (TARGET_GPWORD) \ 2578 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2579 ptr_mode == DImode ? ".gpdword" : ".gpword", \ 2580 LOCAL_LABEL_PREFIX, VALUE); \ 2581 else \ 2582 fprintf (STREAM, "\t%s\t%sL%d\n", \ 2583 ptr_mode == DImode ? ".dword" : ".word", \ 2584 LOCAL_LABEL_PREFIX, VALUE); \ 2585 } while (0) 2586 2587 /* When generating MIPS16 code, we want the jump table to be in the text 2588 section so that we can load its address using a PC-relative addition. */ 2589 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16 2590 2591 /* This is how to output an assembler line 2592 that says to advance the location counter 2593 to a multiple of 2**LOG bytes. */ 2594 2595 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 2596 fprintf (STREAM, "\t.align\t%d\n", (LOG)) 2597 2598 /* This is how to output an assembler line to advance the location 2599 counter by SIZE bytes. */ 2600 2601 #undef ASM_OUTPUT_SKIP 2602 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ 2603 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 2604 2605 /* This is how to output a string. */ 2606 #undef ASM_OUTPUT_ASCII 2607 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \ 2608 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t") 2609 2610 /* Output #ident as a in the read-only data section. */ 2611 #undef ASM_OUTPUT_IDENT 2612 #define ASM_OUTPUT_IDENT(FILE, STRING) \ 2613 { \ 2614 const char *p = STRING; \ 2615 int size = strlen (p) + 1; \ 2616 switch_to_section (readonly_data_section); \ 2617 assemble_string (p, size); \ 2618 } 2619 2620 /* Default to -G 8 */ 2621 #ifndef MIPS_DEFAULT_GVALUE 2622 #define MIPS_DEFAULT_GVALUE 8 2623 #endif 2624 2625 /* Define the strings to put out for each section in the object file. */ 2626 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 2627 #define DATA_SECTION_ASM_OP "\t.data" /* large data */ 2628 2629 #undef READONLY_DATA_SECTION_ASM_OP 2630 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ 2631 2632 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 2633 do \ 2634 { \ 2635 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \ 2636 TARGET_64BIT ? "dsubu" : "subu", \ 2637 reg_names[STACK_POINTER_REGNUM], \ 2638 reg_names[STACK_POINTER_REGNUM], \ 2639 TARGET_64BIT ? "sd" : "sw", \ 2640 reg_names[REGNO], \ 2641 reg_names[STACK_POINTER_REGNUM]); \ 2642 } \ 2643 while (0) 2644 2645 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 2646 do \ 2647 { \ 2648 if (! set_noreorder) \ 2649 fprintf (STREAM, "\t.set\tnoreorder\n"); \ 2650 \ 2651 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ 2652 TARGET_64BIT ? "ld" : "lw", \ 2653 reg_names[REGNO], \ 2654 reg_names[STACK_POINTER_REGNUM], \ 2655 TARGET_64BIT ? "daddu" : "addu", \ 2656 reg_names[STACK_POINTER_REGNUM], \ 2657 reg_names[STACK_POINTER_REGNUM]); \ 2658 \ 2659 if (! set_noreorder) \ 2660 fprintf (STREAM, "\t.set\treorder\n"); \ 2661 } \ 2662 while (0) 2663 2664 /* How to start an assembler comment. 2665 The leading space is important (the mips native assembler requires it). */ 2666 #ifndef ASM_COMMENT_START 2667 #define ASM_COMMENT_START " #" 2668 #endif 2669 2670 /* Default definitions for size_t and ptrdiff_t. We must override the 2671 definitions from ../svr4.h on mips-*-linux-gnu. */ 2672 2673 #undef SIZE_TYPE 2674 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 2675 2676 #undef PTRDIFF_TYPE 2677 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 2678 2679 #ifndef __mips16 2680 /* Since the bits of the _init and _fini function is spread across 2681 many object files, each potentially with its own GP, we must assume 2682 we need to load our GP. We don't preserve $gp or $ra, since each 2683 init/fini chunk is supposed to initialize $gp, and crti/crtn 2684 already take care of preserving $ra and, when appropriate, $gp. */ 2685 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32) 2686 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2687 asm (SECTION_OP "\n\ 2688 .set noreorder\n\ 2689 bal 1f\n\ 2690 nop\n\ 2691 1: .cpload $31\n\ 2692 .set reorder\n\ 2693 jal " USER_LABEL_PREFIX #FUNC "\n\ 2694 " TEXT_SECTION_ASM_OP); 2695 #endif /* Switch to #elif when we're no longer limited by K&R C. */ 2696 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \ 2697 || (defined _ABI64 && _MIPS_SIM == _ABI64) 2698 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2699 asm (SECTION_OP "\n\ 2700 .set noreorder\n\ 2701 bal 1f\n\ 2702 nop\n\ 2703 1: .set reorder\n\ 2704 .cpsetup $31, $2, 1b\n\ 2705 jal " USER_LABEL_PREFIX #FUNC "\n\ 2706 " TEXT_SECTION_ASM_OP); 2707 #endif 2708 #endif 2709 2710 #ifndef HAVE_AS_TLS 2711 #define HAVE_AS_TLS 0 2712 #endif 2713