1;; Scheduling description for Motorola PowerPC 750 and PowerPC 7400 processors. 2;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 2, or (at your 9;; option) any later version. 10 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to the 18;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19;; MA 02110-1301, USA. 20 21(define_automaton "ppc7xx,ppc7xxfp") 22(define_cpu_unit "iu1_7xx,iu2_7xx" "ppc7xx") 23(define_cpu_unit "fpu_7xx" "ppc7xxfp") 24(define_cpu_unit "lsu_7xx,bpu_7xx,sru_7xx" "ppc7xx") 25(define_cpu_unit "du1_7xx,du2_7xx" "ppc7xx") 26(define_cpu_unit "veccmplx_7xx,vecperm_7xx,vdu_7xx" "ppc7xx") 27 28;; PPC740/PPC750/PPC7400 32-bit 2xIU, LSU, SRU, FPU, BPU 29;; IU1 can perform all integer operations 30;; IU2 can perform all integer operations except imul and idiv 31;; LSU 2 stage pipelined 32;; FPU 3 stage pipelined 33;; Max issue 3 insns/clock cycle (includes 1 branch) 34;; In-order execution 35 36 37;; The PPC750 user's manual recommends that to reduce branch mispredictions, 38;; the insn that sets CR bits should be separated from the branch insn 39;; that evaluates them. There is no advantage have more than 10 cycles 40;; of separation. 41;; This could be artificially achieved by exaggerating the latency of 42;; compare insns but at the expense of a poorer schedule. 43 44;; Branches go straight to the BPU. All other insns are handled 45;; by a dispatch unit which can issue a max of 2 insns per cycle. 46(define_reservation "ppc750_du" "du1_7xx|du2_7xx") 47(define_reservation "ppc7400_vec_du" "vdu_7xx") 48 49(define_insn_reservation "ppc750-load" 2 50 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\ 51 load_ux,load_u,fpload,fpload_ux,fpload_u,\ 52 vecload,load_l") 53 (eq_attr "cpu" "ppc750,ppc7400")) 54 "ppc750_du,lsu_7xx") 55 56(define_insn_reservation "ppc750-store" 2 57 (and (eq_attr "type" "store,store_ux,store_u,\ 58 fpstore,fpstore_ux,fpstore_u,vecstore") 59 (eq_attr "cpu" "ppc750,ppc7400")) 60 "ppc750_du,lsu_7xx") 61 62(define_insn_reservation "ppc750-storec" 8 63 (and (eq_attr "type" "store_c") 64 (eq_attr "cpu" "ppc750,ppc7400")) 65 "ppc750_du,lsu_7xx") 66 67(define_insn_reservation "ppc750-integer" 1 68 (and (eq_attr "type" "integer,insert_word") 69 (eq_attr "cpu" "ppc750,ppc7400")) 70 "ppc750_du,iu1_7xx|iu2_7xx") 71 72(define_insn_reservation "ppc750-two" 1 73 (and (eq_attr "type" "two") 74 (eq_attr "cpu" "ppc750,ppc7400")) 75 "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx") 76 77(define_insn_reservation "ppc750-three" 1 78 (and (eq_attr "type" "three") 79 (eq_attr "cpu" "ppc750,ppc7400")) 80 "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx") 81 82(define_insn_reservation "ppc750-imul" 4 83 (and (eq_attr "type" "imul,imul_compare") 84 (eq_attr "cpu" "ppc750,ppc7400")) 85 "ppc750_du,iu1_7xx*4") 86 87(define_insn_reservation "ppc750-imul2" 3 88 (and (eq_attr "type" "imul2") 89 (eq_attr "cpu" "ppc750,ppc7400")) 90 "ppc750_du,iu1_7xx*2") 91 92(define_insn_reservation "ppc750-imul3" 2 93 (and (eq_attr "type" "imul3") 94 (eq_attr "cpu" "ppc750,ppc7400")) 95 "ppc750_du,iu1_7xx") 96 97(define_insn_reservation "ppc750-idiv" 19 98 (and (eq_attr "type" "idiv") 99 (eq_attr "cpu" "ppc750,ppc7400")) 100 "ppc750_du,iu1_7xx*19") 101 102(define_insn_reservation "ppc750-compare" 2 103 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare") 104 (eq_attr "cpu" "ppc750,ppc7400")) 105 "ppc750_du,(iu1_7xx|iu2_7xx)") 106 107(define_insn_reservation "ppc750-fpcompare" 2 108 (and (eq_attr "type" "fpcompare") 109 (eq_attr "cpu" "ppc750,ppc7400")) 110 "ppc750_du,fpu_7xx") 111 112(define_insn_reservation "ppc750-fp" 3 113 (and (eq_attr "type" "fp") 114 (eq_attr "cpu" "ppc750,ppc7400")) 115 "ppc750_du,fpu_7xx") 116 117(define_insn_reservation "ppc750-dmul" 4 118 (and (eq_attr "type" "dmul") 119 (eq_attr "cpu" "ppc750")) 120 "ppc750_du,fpu_7xx*2") 121 122(define_insn_reservation "ppc7400-dmul" 3 123 (and (eq_attr "type" "dmul") 124 (eq_attr "cpu" "ppc7400")) 125 "ppc750_du,fpu_7xx") 126 127; Divides are not pipelined 128(define_insn_reservation "ppc750-sdiv" 17 129 (and (eq_attr "type" "sdiv") 130 (eq_attr "cpu" "ppc750,ppc7400")) 131 "ppc750_du,fpu_7xx*17") 132 133(define_insn_reservation "ppc750-ddiv" 31 134 (and (eq_attr "type" "ddiv") 135 (eq_attr "cpu" "ppc750,ppc7400")) 136 "ppc750_du,fpu_7xx*31") 137 138(define_insn_reservation "ppc750-mfcr" 2 139 (and (eq_attr "type" "mfcr,mtcr") 140 (eq_attr "cpu" "ppc750,ppc7400")) 141 "ppc750_du,iu1_7xx") 142 143(define_insn_reservation "ppc750-crlogical" 3 144 (and (eq_attr "type" "cr_logical,delayed_cr") 145 (eq_attr "cpu" "ppc750,ppc7400")) 146 "nothing,sru_7xx*2") 147 148(define_insn_reservation "ppc750-mtjmpr" 2 149 (and (eq_attr "type" "mtjmpr,isync,sync") 150 (eq_attr "cpu" "ppc750,ppc7400")) 151 "nothing,sru_7xx*2") 152 153(define_insn_reservation "ppc750-mfjmpr" 3 154 (and (eq_attr "type" "mfjmpr") 155 (eq_attr "cpu" "ppc750,ppc7400")) 156 "nothing,sru_7xx*2") 157 158(define_insn_reservation "ppc750-jmpreg" 1 159 (and (eq_attr "type" "jmpreg,branch,isync") 160 (eq_attr "cpu" "ppc750,ppc7400")) 161 "nothing,bpu_7xx") 162 163;; Altivec 164(define_insn_reservation "ppc7400-vecsimple" 1 165 (and (eq_attr "type" "vecsimple,veccmp") 166 (eq_attr "cpu" "ppc7400")) 167 "ppc750_du,ppc7400_vec_du,veccmplx_7xx") 168 169(define_insn_reservation "ppc7400-veccomplex" 4 170 (and (eq_attr "type" "veccomplex") 171 (eq_attr "cpu" "ppc7400")) 172 "ppc750_du,ppc7400_vec_du,veccmplx_7xx") 173 174(define_insn_reservation "ppc7400-vecfloat" 4 175 (and (eq_attr "type" "vecfloat") 176 (eq_attr "cpu" "ppc7400")) 177 "ppc750_du,ppc7400_vec_du,veccmplx_7xx") 178 179(define_insn_reservation "ppc7400-vecperm" 2 180 (and (eq_attr "type" "vecperm") 181 (eq_attr "cpu" "ppc7400")) 182 "ppc750_du,ppc7400_vec_du,vecperm_7xx") 183 184