1 //===-- ARMDefines.h --------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_ARMDEFINES_H 10 #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_ARMDEFINES_H 11 12 #include "llvm/Support/ErrorHandling.h" 13 14 #include <cassert> 15 #include <cstdint> 16 17 // Common definitions for the ARM/Thumb Instruction Set Architecture. 18 19 namespace lldb_private { 20 21 // ARM shifter types 22 enum ARM_ShifterType { 23 SRType_LSL, 24 SRType_LSR, 25 SRType_ASR, 26 SRType_ROR, 27 SRType_RRX, 28 SRType_Invalid 29 }; 30 31 // ARM conditions // Meaning (integer) Meaning (floating-point) 32 // Condition flags 33 #define COND_EQ \ 34 0x0 // Equal Equal Z == 1 35 #define COND_NE \ 36 0x1 // Not equal Not equal, or unordered Z == 0 37 #define COND_CS \ 38 0x2 // Carry set >, ==, or unordered C == 1 39 #define COND_HS 0x2 40 #define COND_CC \ 41 0x3 // Carry clear Less than C == 0 42 #define COND_LO 0x3 43 #define COND_MI \ 44 0x4 // Minus, negative Less than N == 1 45 #define COND_PL \ 46 0x5 // Plus, positive or zero >, ==, or unordered N == 0 47 #define COND_VS \ 48 0x6 // Overflow Unordered V == 1 49 #define COND_VC \ 50 0x7 // No overflow Not unordered V == 0 51 #define COND_HI \ 52 0x8 // Unsigned higher Greater than, or unordered C == 1 and Z == 53 // 0 54 #define COND_LS \ 55 0x9 // Unsigned lower or same Less than or equal C == 0 or Z == 56 // 1 57 #define COND_GE \ 58 0xA // Greater than or equal Greater than or equal N == V 59 #define COND_LT \ 60 0xB // Less than Less than, or unordered N != V 61 #define COND_GT \ 62 0xC // Greater than Greater than Z == 0 and N == 63 // V 64 #define COND_LE \ 65 0xD // Less than or equal <, ==, or unordered Z == 1 or N != 66 // V 67 #define COND_AL \ 68 0xE // Always (unconditional) Always (unconditional) Any 69 #define COND_UNCOND 0xF 70 71 static inline const char *ARMCondCodeToString(uint32_t CC) { 72 switch (CC) { 73 case COND_EQ: 74 return "eq"; 75 case COND_NE: 76 return "ne"; 77 case COND_HS: 78 return "hs"; 79 case COND_LO: 80 return "lo"; 81 case COND_MI: 82 return "mi"; 83 case COND_PL: 84 return "pl"; 85 case COND_VS: 86 return "vs"; 87 case COND_VC: 88 return "vc"; 89 case COND_HI: 90 return "hi"; 91 case COND_LS: 92 return "ls"; 93 case COND_GE: 94 return "ge"; 95 case COND_LT: 96 return "lt"; 97 case COND_GT: 98 return "gt"; 99 case COND_LE: 100 return "le"; 101 case COND_AL: 102 return "al"; 103 } 104 llvm_unreachable("Unknown condition code"); 105 } 106 107 static inline bool ARMConditionPassed(const uint32_t condition, 108 const uint32_t cpsr) { 109 const uint32_t cpsr_n = (cpsr >> 31) & 1u; // Negative condition code flag 110 const uint32_t cpsr_z = (cpsr >> 30) & 1u; // Zero condition code flag 111 const uint32_t cpsr_c = (cpsr >> 29) & 1u; // Carry condition code flag 112 const uint32_t cpsr_v = (cpsr >> 28) & 1u; // Overflow condition code flag 113 114 switch (condition) { 115 case COND_EQ: 116 return (cpsr_z == 1); 117 case COND_NE: 118 return (cpsr_z == 0); 119 case COND_CS: 120 return (cpsr_c == 1); 121 case COND_CC: 122 return (cpsr_c == 0); 123 case COND_MI: 124 return (cpsr_n == 1); 125 case COND_PL: 126 return (cpsr_n == 0); 127 case COND_VS: 128 return (cpsr_v == 1); 129 case COND_VC: 130 return (cpsr_v == 0); 131 case COND_HI: 132 return ((cpsr_c == 1) && (cpsr_z == 0)); 133 case COND_LS: 134 return ((cpsr_c == 0) || (cpsr_z == 1)); 135 case COND_GE: 136 return (cpsr_n == cpsr_v); 137 case COND_LT: 138 return (cpsr_n != cpsr_v); 139 case COND_GT: 140 return ((cpsr_z == 0) && (cpsr_n == cpsr_v)); 141 case COND_LE: 142 return ((cpsr_z == 1) || (cpsr_n != cpsr_v)); 143 case COND_AL: 144 case COND_UNCOND: 145 default: 146 return true; 147 } 148 return false; 149 } 150 151 // Bit positions for CPSR 152 #define CPSR_T_POS 5 153 #define CPSR_F_POS 6 154 #define CPSR_I_POS 7 155 #define CPSR_A_POS 8 156 #define CPSR_E_POS 9 157 #define CPSR_J_POS 24 158 #define CPSR_Q_POS 27 159 #define CPSR_V_POS 28 160 #define CPSR_C_POS 29 161 #define CPSR_Z_POS 30 162 #define CPSR_N_POS 31 163 164 // CPSR mode definitions 165 #define CPSR_MODE_USR 0x10u 166 #define CPSR_MODE_FIQ 0x11u 167 #define CPSR_MODE_IRQ 0x12u 168 #define CPSR_MODE_SVC 0x13u 169 #define CPSR_MODE_ABT 0x17u 170 #define CPSR_MODE_UND 0x1bu 171 #define CPSR_MODE_SYS 0x1fu 172 173 // Masks for CPSR 174 #define MASK_CPSR_MODE_MASK (0x0000001fu) 175 #define MASK_CPSR_IT_MASK (0x0600fc00u) 176 #define MASK_CPSR_T (1u << CPSR_T_POS) 177 #define MASK_CPSR_F (1u << CPSR_F_POS) 178 #define MASK_CPSR_I (1u << CPSR_I_POS) 179 #define MASK_CPSR_A (1u << CPSR_A_POS) 180 #define MASK_CPSR_E (1u << CPSR_E_POS) 181 #define MASK_CPSR_GE_MASK (0x000f0000u) 182 #define MASK_CPSR_J (1u << CPSR_J_POS) 183 #define MASK_CPSR_Q (1u << CPSR_Q_POS) 184 #define MASK_CPSR_V (1u << CPSR_V_POS) 185 #define MASK_CPSR_C (1u << CPSR_C_POS) 186 #define MASK_CPSR_Z (1u << CPSR_Z_POS) 187 #define MASK_CPSR_N (1u << CPSR_N_POS) 188 189 } // namespace lldb_private 190 191 #endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_ARMDEFINES_H 192