109467b48Spatrick//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 209467b48Spatrick// 309467b48Spatrick// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 409467b48Spatrick// See https://llvm.org/LICENSE.txt for license information. 509467b48Spatrick// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 609467b48Spatrick// 709467b48Spatrick//===----------------------------------------------------------------------===// 809467b48Spatrick// 909467b48Spatrick// 1009467b48Spatrick//===----------------------------------------------------------------------===// 1109467b48Spatrick 1209467b48Spatrick//===----------------------------------------------------------------------===// 1309467b48Spatrick// Target-independent interfaces which we are implementing. 1409467b48Spatrick//===----------------------------------------------------------------------===// 1509467b48Spatrick 1609467b48Spatrickinclude "llvm/Target/Target.td" 1709467b48Spatrick 1809467b48Spatrick//===----------------------------------------------------------------------===// 1909467b48Spatrick// AArch64 Subtarget features. 2009467b48Spatrick// 2109467b48Spatrick 22*d415bd75Srobert// Each SubtargetFeature which corresponds to an Arm Architecture feature should 23*d415bd75Srobert// be annotated with the respective FEAT_ feature name from the Architecture 24*d415bd75Srobert// Reference Manual. If a SubtargetFeature enables instructions from multiple 25*d415bd75Srobert// Arm Architecture Features, it should list all the relevant features. Not all 26*d415bd75Srobert// FEAT_ features have a corresponding SubtargetFeature. 27*d415bd75Srobert 2809467b48Spatrickdef FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 29*d415bd75Srobert "Enable ARMv8 FP (FEAT_FP)">; 3009467b48Spatrick 3109467b48Spatrickdef FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 32*d415bd75Srobert "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>; 3309467b48Spatrick 3409467b48Spatrickdef FeatureSM4 : SubtargetFeature< 3509467b48Spatrick "sm4", "HasSM4", "true", 36*d415bd75Srobert "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>; 3709467b48Spatrick 3809467b48Spatrickdef FeatureSHA2 : SubtargetFeature< 3909467b48Spatrick "sha2", "HasSHA2", "true", 40*d415bd75Srobert "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>; 4109467b48Spatrick 4209467b48Spatrickdef FeatureSHA3 : SubtargetFeature< 4309467b48Spatrick "sha3", "HasSHA3", "true", 44*d415bd75Srobert "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2]>; 4509467b48Spatrick 4609467b48Spatrickdef FeatureAES : SubtargetFeature< 4709467b48Spatrick "aes", "HasAES", "true", 48*d415bd75Srobert "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>; 4909467b48Spatrick 5009467b48Spatrick// Crypto has been split up and any combination is now valid (see the 51097a140dSpatrick// crypto definitions above). Also, crypto is now context sensitive: 5209467b48Spatrick// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 5309467b48Spatrick// Therefore, we rely on Clang, the user interacing tool, to pass on the 5409467b48Spatrick// appropriate crypto options. But here in the backend, crypto has very little 55097a140dSpatrick// meaning anymore. We kept the Crypto definition here for backward 5609467b48Spatrick// compatibility, and now imply features SHA2 and AES, which was the 5709467b48Spatrick// "traditional" meaning of Crypto. 5809467b48Spatrickdef FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 5909467b48Spatrick "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 6009467b48Spatrick 6109467b48Spatrickdef FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 62*d415bd75Srobert "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">; 6309467b48Spatrick 6409467b48Spatrickdef FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 65*d415bd75Srobert "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">; 66*d415bd75Srobert 67*d415bd75Srobertdef FeatureRASv2 : SubtargetFeature<"rasv2", "HasRASv2", "true", 68*d415bd75Srobert "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)", 69*d415bd75Srobert [FeatureRAS]>; 7009467b48Spatrick 7109467b48Spatrickdef FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 72*d415bd75Srobert "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">; 73*d415bd75Srobert 74*d415bd75Srobertdef FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true", 75*d415bd75Srobert "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">; 7609467b48Spatrick 7773471bf0Spatrickdef FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", 7873471bf0Spatrick "Enable out of line atomics to support LSE instructions">; 7973471bf0Spatrick 80*d415bd75Srobertdef FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true", 81*d415bd75Srobert "Enable Function Multi Versioning support.">; 82*d415bd75Srobert 8309467b48Spatrickdef FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 84*d415bd75Srobert "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)">; 8509467b48Spatrick 8609467b48Spatrickdef FeaturePAN : SubtargetFeature< 8709467b48Spatrick "pan", "HasPAN", "true", 88*d415bd75Srobert "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">; 8909467b48Spatrick 9009467b48Spatrickdef FeatureLOR : SubtargetFeature< 9109467b48Spatrick "lor", "HasLOR", "true", 92*d415bd75Srobert "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">; 9309467b48Spatrick 9473471bf0Spatrickdef FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", 9573471bf0Spatrick "true", "Enable RW operand CONTEXTIDR_EL2" >; 9673471bf0Spatrick 9773471bf0Spatrickdef FeatureVH : SubtargetFeature<"vh", "HasVH", "true", 98*d415bd75Srobert "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >; 9909467b48Spatrick 100*d415bd75Srobert// This SubtargetFeature is special. It controls only whether codegen will turn 101*d415bd75Srobert// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The 102*d415bd75Srobert// `FEAT_PMUv3*` system registers are always available for assembly/disassembly. 10309467b48Spatrickdef FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 104*d415bd75Srobert "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">; 10509467b48Spatrick 10609467b48Spatrickdef FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 107*d415bd75Srobert "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>; 10809467b48Spatrick 10909467b48Spatrickdef FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 110*d415bd75Srobert "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>; 11109467b48Spatrick 11209467b48Spatrickdef FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 113*d415bd75Srobert "Enable Statistical Profiling extension (FEAT_SPE)">; 11409467b48Spatrick 11509467b48Spatrickdef FeaturePAN_RWV : SubtargetFeature< 11609467b48Spatrick "pan-rwv", "HasPAN_RWV", "true", 117*d415bd75Srobert "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)", 11809467b48Spatrick [FeaturePAN]>; 11909467b48Spatrick 12009467b48Spatrick// UAO PState 12109467b48Spatrickdef FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 122*d415bd75Srobert "Enable v8.2 UAO PState (FEAT_UAO)">; 12309467b48Spatrick 12409467b48Spatrickdef FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 125*d415bd75Srobert "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >; 12609467b48Spatrick 12709467b48Spatrickdef FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 128*d415bd75Srobert "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>; 129097a140dSpatrick 130097a140dSpatrick// This flag is currently still labeled as Experimental, but when fully 131097a140dSpatrick// implemented this should tell the compiler to use the zeroing pseudos to 132097a140dSpatrick// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive 133097a140dSpatrick// lanes are known to be zero. The pseudos will then be expanded using the 134097a140dSpatrick// MOVPRFX instruction to zero the inactive lanes. This feature should only be 135097a140dSpatrick// enabled if MOVPRFX instructions are known to merge with the destructive 136097a140dSpatrick// operations they prefix. 137097a140dSpatrick// 138097a140dSpatrick// This feature could similarly be extended to support cheap merging of _any_ 139097a140dSpatrick// value into the inactive lanes using the MOVPRFX instruction that uses 140097a140dSpatrick// merging-predication. 141097a140dSpatrickdef FeatureExperimentalZeroingPseudos 142097a140dSpatrick : SubtargetFeature<"use-experimental-zeroing-pseudos", 143097a140dSpatrick "UseExperimentalZeroingPseudos", "true", 144097a140dSpatrick "Hint to the compiler that the MOVPRFX instruction is " 145097a140dSpatrick "merged with destructive operations", 146097a140dSpatrick []>; 14709467b48Spatrick 148*d415bd75Srobertdef FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl", 149*d415bd75Srobert "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">; 150*d415bd75Srobert 15109467b48Spatrickdef FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 152*d415bd75Srobert "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)", 153*d415bd75Srobert [FeatureSVE, FeatureUseScalarIncVL]>; 15409467b48Spatrick 15509467b48Spatrickdef FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 156*d415bd75Srobert "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)", 157*d415bd75Srobert [FeatureSVE2, FeatureAES]>; 15809467b48Spatrick 15909467b48Spatrickdef FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 160*d415bd75Srobert "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>; 16109467b48Spatrick 16209467b48Spatrickdef FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 163*d415bd75Srobert "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>; 16409467b48Spatrick 16509467b48Spatrickdef FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 166*d415bd75Srobert "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2]>; 167*d415bd75Srobert 168*d415bd75Srobertdef FeatureSVE2p1: SubtargetFeature<"sve2p1", "HasSVE2p1", "true", 169*d415bd75Srobert "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>; 170*d415bd75Srobert 171*d415bd75Srobertdef FeatureB16B16 : SubtargetFeature<"b16b16", "HasB16B16", "true", 172*d415bd75Srobert "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", []>; 17309467b48Spatrick 17409467b48Spatrickdef FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 17509467b48Spatrick "Has zero-cycle register moves">; 17609467b48Spatrick 17709467b48Spatrickdef FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 17809467b48Spatrick "Has zero-cycle zeroing instructions for generic registers">; 17909467b48Spatrick 180*d415bd75Srobert// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0". 181*d415bd75Srobert// as movi is more efficient across all cores. Newer cores can eliminate 182*d415bd75Srobert// fmovs early and there is no difference with movi, but this not true for 183*d415bd75Srobert// all implementations. 18473471bf0Spatrickdef FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false", 18573471bf0Spatrick "Has no zero-cycle zeroing instructions for FP registers">; 18609467b48Spatrick 18709467b48Spatrickdef FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 18809467b48Spatrick "Has zero-cycle zeroing instructions", 18973471bf0Spatrick [FeatureZCZeroingGP]>; 19009467b48Spatrick 19109467b48Spatrick/// ... but the floating-point version doesn't quite work in rare cases on older 19209467b48Spatrick/// CPUs. 19309467b48Spatrickdef FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 19409467b48Spatrick "HasZeroCycleZeroingFPWorkaround", "true", 19509467b48Spatrick "The zero-cycle floating-point zeroing instruction has a bug">; 19609467b48Spatrick 19709467b48Spatrickdef FeatureStrictAlign : SubtargetFeature<"strict-align", 198*d415bd75Srobert "RequiresStrictAlign", "true", 19909467b48Spatrick "Disallow all unaligned memory " 20009467b48Spatrick "access">; 20109467b48Spatrick 202097a140dSpatrickforeach i = {1-7,9-15,18,20-28,30} in 20309467b48Spatrick def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 20409467b48Spatrick "Reserve X"#i#", making it unavailable " 20509467b48Spatrick "as a GPR">; 20609467b48Spatrick 20709467b48Spatrickforeach i = {8-15,18} in 20809467b48Spatrick def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 20909467b48Spatrick "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 21009467b48Spatrick 21109467b48Spatrickdef FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 21209467b48Spatrick "true", 21309467b48Spatrick "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 21409467b48Spatrick 21509467b48Spatrickdef FeaturePredictableSelectIsExpensive : SubtargetFeature< 21609467b48Spatrick "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 21709467b48Spatrick "Prefer likely predicted branches over selects">; 21809467b48Spatrick 219*d415bd75Srobertdef FeatureEnableSelectOptimize : SubtargetFeature< 220*d415bd75Srobert "enable-select-opt", "EnableSelectOptimize", "true", 221*d415bd75Srobert "Enable the select optimize pass for select loop heuristics">; 222*d415bd75Srobert 22309467b48Spatrickdef FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 224*d415bd75Srobert "HasCustomCheapAsMoveHandling", "true", 22509467b48Spatrick "Use custom handling of cheap instructions">; 22609467b48Spatrick 22709467b48Spatrickdef FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 228*d415bd75Srobert "HasExynosCheapAsMoveHandling", "true", 22909467b48Spatrick "Use Exynos specific handling of cheap instructions", 23009467b48Spatrick [FeatureCustomCheapAsMoveHandling]>; 23109467b48Spatrick 23209467b48Spatrickdef FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 23309467b48Spatrick "UsePostRAScheduler", "true", "Schedule again after register allocation">; 23409467b48Spatrick 23509467b48Spatrickdef FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 236*d415bd75Srobert "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">; 23709467b48Spatrick 23809467b48Spatrickdef FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 239*d415bd75Srobert "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">; 24009467b48Spatrick 241*d415bd75Srobertdef FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address", 242*d415bd75Srobert "IsStoreAddressAscend", "true", 243*d415bd75Srobert "Schedule vector stores by ascending address">; 244*d415bd75Srobert 245*d415bd75Srobertdef FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow", 24609467b48Spatrick "true", "STR of Q register with register offset is slow">; 24709467b48Spatrick 24809467b48Spatrickdef FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 24909467b48Spatrick "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 25009467b48Spatrick "true", "Use alternative pattern for sextload convert to f32">; 25109467b48Spatrick 25209467b48Spatrickdef FeatureArithmeticBccFusion : SubtargetFeature< 25309467b48Spatrick "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 25409467b48Spatrick "CPU fuses arithmetic+bcc operations">; 25509467b48Spatrick 25609467b48Spatrickdef FeatureArithmeticCbzFusion : SubtargetFeature< 25709467b48Spatrick "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 25809467b48Spatrick "CPU fuses arithmetic + cbz/cbnz operations">; 25909467b48Spatrick 26073471bf0Spatrickdef FeatureCmpBccFusion : SubtargetFeature< 26173471bf0Spatrick "cmp-bcc-fusion", "HasCmpBccFusion", "true", 26273471bf0Spatrick "CPU fuses cmp+bcc operations">; 26373471bf0Spatrick 26409467b48Spatrickdef FeatureFuseAddress : SubtargetFeature< 26509467b48Spatrick "fuse-address", "HasFuseAddress", "true", 26609467b48Spatrick "CPU fuses address generation and memory operations">; 26709467b48Spatrick 26809467b48Spatrickdef FeatureFuseAES : SubtargetFeature< 26909467b48Spatrick "fuse-aes", "HasFuseAES", "true", 27009467b48Spatrick "CPU fuses AES crypto operations">; 27109467b48Spatrick 27209467b48Spatrickdef FeatureFuseArithmeticLogic : SubtargetFeature< 27309467b48Spatrick "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 27409467b48Spatrick "CPU fuses arithmetic and logic operations">; 27509467b48Spatrick 27609467b48Spatrickdef FeatureFuseCCSelect : SubtargetFeature< 27709467b48Spatrick "fuse-csel", "HasFuseCCSelect", "true", 27809467b48Spatrick "CPU fuses conditional select operations">; 27909467b48Spatrick 28009467b48Spatrickdef FeatureFuseCryptoEOR : SubtargetFeature< 28109467b48Spatrick "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 28209467b48Spatrick "CPU fuses AES/PMULL and EOR operations">; 28309467b48Spatrick 284*d415bd75Srobertdef FeatureFuseAdrpAdd : SubtargetFeature< 285*d415bd75Srobert "fuse-adrp-add", "HasFuseAdrpAdd", "true", 286*d415bd75Srobert "CPU fuses adrp+add operations">; 287*d415bd75Srobert 28809467b48Spatrickdef FeatureFuseLiterals : SubtargetFeature< 28909467b48Spatrick "fuse-literals", "HasFuseLiterals", "true", 29009467b48Spatrick "CPU fuses literal generation operations">; 29109467b48Spatrick 29209467b48Spatrickdef FeatureDisableLatencySchedHeuristic : SubtargetFeature< 29309467b48Spatrick "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 29409467b48Spatrick "Disable latency scheduling heuristic">; 29509467b48Spatrick 29609467b48Spatrickdef FeatureForce32BitJumpTables 29709467b48Spatrick : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 29809467b48Spatrick "Force jump table entries to be 32-bits wide except at MinSize">; 29909467b48Spatrick 30009467b48Spatrickdef FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 301*d415bd75Srobert "Enable support for RCPC extension (FEAT_LRCPC)">; 30209467b48Spatrick 30309467b48Spatrickdef FeatureUseRSqrt : SubtargetFeature< 30409467b48Spatrick "use-reciprocal-square-root", "UseRSqrt", "true", 30509467b48Spatrick "Use the reciprocal square root approximation">; 30609467b48Spatrick 30709467b48Spatrickdef FeatureDotProd : SubtargetFeature< 30809467b48Spatrick "dotprod", "HasDotProd", "true", 309*d415bd75Srobert "Enable dot product support (FEAT_DotProd)">; 31009467b48Spatrick 31173471bf0Spatrickdef FeaturePAuth : SubtargetFeature< 31273471bf0Spatrick "pauth", "HasPAuth", "true", 313*d415bd75Srobert "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">; 31409467b48Spatrick 31509467b48Spatrickdef FeatureJS : SubtargetFeature< 31609467b48Spatrick "jsconv", "HasJS", "true", 317*d415bd75Srobert "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)", 31809467b48Spatrick [FeatureFPARMv8]>; 31909467b48Spatrick 32009467b48Spatrickdef FeatureCCIDX : SubtargetFeature< 32109467b48Spatrick "ccidx", "HasCCIDX", "true", 322*d415bd75Srobert "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">; 32309467b48Spatrick 32409467b48Spatrickdef FeatureComplxNum : SubtargetFeature< 32509467b48Spatrick "complxnum", "HasComplxNum", "true", 326*d415bd75Srobert "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)", 32709467b48Spatrick [FeatureNEON]>; 32809467b48Spatrick 32909467b48Spatrickdef FeatureNV : SubtargetFeature< 33009467b48Spatrick "nv", "HasNV", "true", 331*d415bd75Srobert "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">; 33209467b48Spatrick 33309467b48Spatrickdef FeatureMPAM : SubtargetFeature< 33409467b48Spatrick "mpam", "HasMPAM", "true", 335*d415bd75Srobert "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">; 33609467b48Spatrick 33709467b48Spatrickdef FeatureDIT : SubtargetFeature< 33809467b48Spatrick "dit", "HasDIT", "true", 339*d415bd75Srobert "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)">; 34009467b48Spatrick 34109467b48Spatrickdef FeatureTRACEV8_4 : SubtargetFeature< 34209467b48Spatrick "tracev8.4", "HasTRACEV8_4", "true", 343*d415bd75Srobert "Enable v8.4-A Trace extension (FEAT_TRF)">; 34409467b48Spatrick 34509467b48Spatrickdef FeatureAM : SubtargetFeature< 34609467b48Spatrick "am", "HasAM", "true", 347*d415bd75Srobert "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">; 34809467b48Spatrick 349097a140dSpatrickdef FeatureAMVS : SubtargetFeature< 350097a140dSpatrick "amvs", "HasAMVS", "true", 351*d415bd75Srobert "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)", 352097a140dSpatrick [FeatureAM]>; 353097a140dSpatrick 35409467b48Spatrickdef FeatureSEL2 : SubtargetFeature< 35509467b48Spatrick "sel2", "HasSEL2", "true", 356*d415bd75Srobert "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">; 35709467b48Spatrick 35809467b48Spatrickdef FeatureTLB_RMI : SubtargetFeature< 35909467b48Spatrick "tlb-rmi", "HasTLB_RMI", "true", 360*d415bd75Srobert "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">; 36109467b48Spatrick 36273471bf0Spatrickdef FeatureFlagM : SubtargetFeature< 36373471bf0Spatrick "flagm", "HasFlagM", "true", 364*d415bd75Srobert "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">; 36509467b48Spatrick 36609467b48Spatrick// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 36709467b48Spatrickdef FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 368*d415bd75Srobert "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)", 36909467b48Spatrick [FeatureRCPC]>; 37009467b48Spatrick 37109467b48Spatrickdef FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 37209467b48Spatrick "NegativeImmediates", "false", 37309467b48Spatrick "Convert immediates and instructions " 37409467b48Spatrick "to their negated or complemented " 37509467b48Spatrick "equivalent when the immediate does " 37609467b48Spatrick "not fit in the encoding.">; 37709467b48Spatrick 37809467b48Spatrickdef FeatureLSLFast : SubtargetFeature< 37909467b48Spatrick "lsl-fast", "HasLSLFast", "true", 38009467b48Spatrick "CPU has a fastpath logical shift of up to 3 places">; 38109467b48Spatrick 38209467b48Spatrickdef FeatureAggressiveFMA : 38309467b48Spatrick SubtargetFeature<"aggressive-fma", 38409467b48Spatrick "HasAggressiveFMA", 38509467b48Spatrick "true", 38609467b48Spatrick "Enable Aggressive FMA for floating-point.">; 38709467b48Spatrick 38809467b48Spatrickdef FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 389*d415bd75Srobert "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">; 39009467b48Spatrick 39109467b48Spatrickdef FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 39209467b48Spatrick "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 393*d415bd75Srobert "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >; 39409467b48Spatrick 39509467b48Spatrickdef FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 396*d415bd75Srobert "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">; 39709467b48Spatrick 39809467b48Spatrickdef FeatureSB : SubtargetFeature<"sb", "HasSB", 399*d415bd75Srobert "true", "Enable v8.5 Speculation Barrier (FEAT_SB)" >; 40009467b48Spatrick 40109467b48Spatrickdef FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 402*d415bd75Srobert "true", "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >; 40309467b48Spatrick 40409467b48Spatrickdef FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 405*d415bd75Srobert "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >; 40609467b48Spatrick 40709467b48Spatrickdef FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 408*d415bd75Srobert "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >; 40909467b48Spatrick 41009467b48Spatrickdef FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 411*d415bd75Srobert "true", "Enable Branch Target Identification (FEAT_BTI)" >; 41209467b48Spatrick 41309467b48Spatrickdef FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 414*d415bd75Srobert "true", "Enable Random Number generation instructions (FEAT_RNG)" >; 41509467b48Spatrick 41609467b48Spatrickdef FeatureMTE : SubtargetFeature<"mte", "HasMTE", 417*d415bd75Srobert "true", "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >; 41809467b48Spatrick 41909467b48Spatrickdef FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", 420*d415bd75Srobert "true", "Enable Trace Buffer Extension (FEAT_TRBE)">; 42109467b48Spatrick 42209467b48Spatrickdef FeatureETE : SubtargetFeature<"ete", "HasETE", 423*d415bd75Srobert "true", "Enable Embedded Trace Extension (FEAT_ETE)", 42409467b48Spatrick [FeatureTRBE]>; 42509467b48Spatrick 42609467b48Spatrickdef FeatureTME : SubtargetFeature<"tme", "HasTME", 427*d415bd75Srobert "true", "Enable Transactional Memory Extension (FEAT_TME)" >; 42809467b48Spatrick 42909467b48Spatrickdef FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 43009467b48Spatrick "AllowTaggedGlobals", 43109467b48Spatrick "true", "Use an instruction sequence for taking the address of a global " 43209467b48Spatrick "that allows a memory tag in the upper address bits">; 43309467b48Spatrick 434097a140dSpatrickdef FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", 435*d415bd75Srobert "true", "Enable BFloat16 Extension (FEAT_BF16)" >; 436097a140dSpatrick 437097a140dSpatrickdef FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 438*d415bd75Srobert "true", "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">; 439097a140dSpatrick 440097a140dSpatrickdef FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32", 441*d415bd75Srobert "true", "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>; 442097a140dSpatrick 443097a140dSpatrickdef FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64", 444*d415bd75Srobert "true", "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>; 445097a140dSpatrick 44673471bf0Spatrickdef FeatureXS : SubtargetFeature<"xs", "HasXS", 447*d415bd75Srobert "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">; 44873471bf0Spatrick 44973471bf0Spatrickdef FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", 450*d415bd75Srobert "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">; 45173471bf0Spatrick 45273471bf0Spatrickdef FeatureHCX : SubtargetFeature< 453*d415bd75Srobert "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; 45473471bf0Spatrick 45573471bf0Spatrickdef FeatureLS64 : SubtargetFeature<"ls64", "HasLS64", 456*d415bd75Srobert "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">; 457*d415bd75Srobert 458*d415bd75Srobertdef FeatureHBC : SubtargetFeature<"hbc", "HasHBC", 459*d415bd75Srobert "true", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">; 460*d415bd75Srobert 461*d415bd75Srobertdef FeatureMOPS : SubtargetFeature<"mops", "HasMOPS", 462*d415bd75Srobert "true", "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">; 463*d415bd75Srobert 464*d415bd75Srobertdef FeatureNMI : SubtargetFeature<"nmi", "HasNMI", 465*d415bd75Srobert "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">; 46673471bf0Spatrick 46773471bf0Spatrickdef FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE", 468*d415bd75Srobert "true", "Enable Branch Record Buffer Extension (FEAT_BRBE)">; 46973471bf0Spatrick 47073471bf0Spatrickdef FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF", 471*d415bd75Srobert "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">; 47273471bf0Spatrick 473097a140dSpatrickdef FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", 474*d415bd75Srobert "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">; 475097a140dSpatrick 476097a140dSpatrickdef FeatureEnhancedCounterVirtualization : 477097a140dSpatrick SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", 478*d415bd75Srobert "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">; 479097a140dSpatrick 48073471bf0Spatrickdef FeatureRME : SubtargetFeature<"rme", "HasRME", 481*d415bd75Srobert "true", "Enable Realm Management Extension (FEAT_RME)">; 48273471bf0Spatrick 48373471bf0Spatrickdef FeatureSME : SubtargetFeature<"sme", "HasSME", "true", 484*d415bd75Srobert "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>; 48573471bf0Spatrick 486*d415bd75Srobertdef FeatureSMEF64F64 : SubtargetFeature<"sme-f64f64", "HasSMEF64F64", "true", 487*d415bd75Srobert "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>; 48873471bf0Spatrick 489*d415bd75Srobertdef FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64", "HasSMEI16I64", "true", 490*d415bd75Srobert "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>; 491*d415bd75Srobert 492*d415bd75Srobertdef FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true", 493*d415bd75Srobert "Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>; 494*d415bd75Srobert 495*d415bd75Srobertdef FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true", 496*d415bd75Srobert "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>; 497*d415bd75Srobert 498*d415bd75Srobertdef FeatureSME2p1 : SubtargetFeature<"sme2p1", "HasSME2p1", "true", 499*d415bd75Srobert "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>; 500*d415bd75Srobert 501*d415bd75Srobertdef FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", 502*d415bd75Srobert "Apple A7 (the CPU formerly known as Cyclone)">; 503*d415bd75Srobert 504*d415bd75Srobertdef FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", 505*d415bd75Srobert "Enable Exception Level 2 Virtual Memory System Architecture">; 506*d415bd75Srobert 507*d415bd75Srobertdef FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", 508*d415bd75Srobert "Enable Exception Level 3">; 509*d415bd75Srobert 510*d415bd75Srobertdef FeatureCSSC : SubtargetFeature<"cssc", "HasCSSC", "true", 511*d415bd75Srobert "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">; 512*d415bd75Srobert 513*d415bd75Srobertdef FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769", 514*d415bd75Srobert "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">; 515*d415bd75Srobert 516*d415bd75Srobertdef FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice", 517*d415bd75Srobert "NoBTIAtReturnTwice", "true", 518*d415bd75Srobert "Don't place a BTI instruction " 519*d415bd75Srobert "after a return-twice">; 520*d415bd75Srobert 521*d415bd75Srobertdef FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB", 522*d415bd75Srobert "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">; 523*d415bd75Srobert 524*d415bd75Srobertdef FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC", 525*d415bd75Srobert "true", "Enable SLC target for PRFM instruction">; 526*d415bd75Srobert 527*d415bd75Srobertdef FeatureSPECRES2 : SubtargetFeature<"specres2", "HasSPECRES2", 528*d415bd75Srobert "true", "Enable Speculation Restriction Instruction (FEAT_SPECRES2)", 529*d415bd75Srobert [FeaturePredRes]>; 530*d415bd75Srobert 531*d415bd75Srobertdef FeatureMEC : SubtargetFeature<"mec", "HasMEC", 532*d415bd75Srobert "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>; 533*d415bd75Srobert 534*d415bd75Srobertdef FeatureITE : SubtargetFeature<"ite", "HasITE", 535*d415bd75Srobert "true", "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE, 536*d415bd75Srobert FeatureTRBE]>; 537*d415bd75Srobert 538*d415bd75Srobertdef FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3", 539*d415bd75Srobert "true", "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)", 540*d415bd75Srobert [FeatureRCPC_IMMO]>; 541*d415bd75Srobert 542*d415bd75Srobertdef FeatureTHE : SubtargetFeature<"the", "HasTHE", 543*d415bd75Srobert "true", "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">; 544*d415bd75Srobert 545*d415bd75Srobertdef FeatureLSE128 : SubtargetFeature<"lse128", "HasLSE128", 546*d415bd75Srobert "true", "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)", 547*d415bd75Srobert [FeatureLSE]>; 548*d415bd75Srobert 549*d415bd75Srobert// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit. 550*d415bd75Srobert// Therefore group them all under a single feature flag, d128: 551*d415bd75Srobertdef FeatureD128 : SubtargetFeature<"d128", "HasD128", 552*d415bd75Srobert "true", "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers " 553*d415bd75Srobert "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)", 554*d415bd75Srobert [FeatureLSE128]>; 55573471bf0Spatrick 55609467b48Spatrick//===----------------------------------------------------------------------===// 55709467b48Spatrick// Architectures. 55809467b48Spatrick// 559*d415bd75Srobertdef HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", 560*d415bd75Srobert "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; 56109467b48Spatrick 56209467b48Spatrickdef HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 563*d415bd75Srobert "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, 564*d415bd75Srobert FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>; 56509467b48Spatrick 56609467b48Spatrickdef HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 56709467b48Spatrick "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 56809467b48Spatrick FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 56909467b48Spatrick 57009467b48Spatrickdef HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 57173471bf0Spatrick "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, 57209467b48Spatrick FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 57309467b48Spatrick 57409467b48Spatrickdef HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 57509467b48Spatrick "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 57673471bf0Spatrick FeatureNV, FeatureMPAM, FeatureDIT, 577*d415bd75Srobert FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, 578*d415bd75Srobert FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>; 57909467b48Spatrick 58009467b48Spatrickdef HasV8_5aOps : SubtargetFeature< 58109467b48Spatrick "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 58209467b48Spatrick [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 58309467b48Spatrick FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 584097a140dSpatrick FeatureBranchTargetId]>; 585097a140dSpatrick 586097a140dSpatrickdef HasV8_6aOps : SubtargetFeature< 587097a140dSpatrick "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", 588097a140dSpatrick [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, 589097a140dSpatrick FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; 59009467b48Spatrick 59173471bf0Spatrickdef HasV8_7aOps : SubtargetFeature< 59273471bf0Spatrick "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", 59373471bf0Spatrick [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; 59473471bf0Spatrick 595*d415bd75Srobertdef HasV8_8aOps : SubtargetFeature< 596*d415bd75Srobert "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions", 597*d415bd75Srobert [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>; 598*d415bd75Srobert 599*d415bd75Srobertdef HasV8_9aOps : SubtargetFeature< 600*d415bd75Srobert "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions", 601*d415bd75Srobert [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2, 602*d415bd75Srobert FeatureCSSC, FeatureRASv2]>; 603*d415bd75Srobert 604*d415bd75Srobertdef HasV9_0aOps : SubtargetFeature< 605*d415bd75Srobert "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions", 606*d415bd75Srobert [HasV8_5aOps, FeatureMEC, FeatureSVE2]>; 607*d415bd75Srobert 608*d415bd75Srobertdef HasV9_1aOps : SubtargetFeature< 609*d415bd75Srobert "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions", 610*d415bd75Srobert [HasV8_6aOps, HasV9_0aOps]>; 611*d415bd75Srobert 612*d415bd75Srobertdef HasV9_2aOps : SubtargetFeature< 613*d415bd75Srobert "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions", 614*d415bd75Srobert [HasV8_7aOps, HasV9_1aOps]>; 615*d415bd75Srobert 616*d415bd75Srobertdef HasV9_3aOps : SubtargetFeature< 617*d415bd75Srobert "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions", 618*d415bd75Srobert [HasV8_8aOps, HasV9_2aOps]>; 619*d415bd75Srobert 620*d415bd75Srobertdef HasV9_4aOps : SubtargetFeature< 621*d415bd75Srobert "v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions", 622*d415bd75Srobert [HasV8_9aOps, HasV9_3aOps]>; 623*d415bd75Srobert 62473471bf0Spatrickdef HasV8_0rOps : SubtargetFeature< 62573471bf0Spatrick "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", 62673471bf0Spatrick [//v8.1 62773471bf0Spatrick FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2, 62873471bf0Spatrick //v8.2 629*d415bd75Srobert FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV, 63073471bf0Spatrick //v8.3 63173471bf0Spatrick FeatureComplxNum, FeatureCCIDX, FeatureJS, 63273471bf0Spatrick FeaturePAuth, FeatureRCPC, 63373471bf0Spatrick //v8.4 634*d415bd75Srobert FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI, 635*d415bd75Srobert FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO, 636*d415bd75Srobert // Not mandatory in v8.0-R, but included here on the grounds that it 637*d415bd75Srobert // only enables names of system registers 638*d415bd75Srobert FeatureSpecRestrict 639*d415bd75Srobert ]>; 640*d415bd75Srobert 641*d415bd75Srobert// Only intended to be used by disassemblers. 642*d415bd75Srobertdef FeatureAll 643*d415bd75Srobert : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>; 644*d415bd75Srobert 645*d415bd75Srobertclass AssemblerPredicateWithAll<dag cond, string name=""> 646*d415bd75Srobert : AssemblerPredicate<(any_of FeatureAll, cond), name>; 64773471bf0Spatrick 64809467b48Spatrick//===----------------------------------------------------------------------===// 64909467b48Spatrick// Register File Description 65009467b48Spatrick//===----------------------------------------------------------------------===// 65109467b48Spatrick 65209467b48Spatrickinclude "AArch64RegisterInfo.td" 65309467b48Spatrickinclude "AArch64RegisterBanks.td" 65409467b48Spatrickinclude "AArch64CallingConvention.td" 65509467b48Spatrick 65609467b48Spatrick//===----------------------------------------------------------------------===// 65709467b48Spatrick// Instruction Descriptions 65809467b48Spatrick//===----------------------------------------------------------------------===// 65909467b48Spatrick 66009467b48Spatrickinclude "AArch64Schedule.td" 66109467b48Spatrickinclude "AArch64InstrInfo.td" 66209467b48Spatrickinclude "AArch64SchedPredicates.td" 66309467b48Spatrickinclude "AArch64SchedPredExynos.td" 664*d415bd75Srobertinclude "AArch64SchedPredAmpere.td" 66509467b48Spatrickinclude "AArch64Combine.td" 66609467b48Spatrick 66709467b48Spatrickdef AArch64InstrInfo : InstrInfo; 66809467b48Spatrick 66909467b48Spatrick//===----------------------------------------------------------------------===// 67009467b48Spatrick// Named operands for MRS/MSR/TLBI/... 67109467b48Spatrick//===----------------------------------------------------------------------===// 67209467b48Spatrick 67309467b48Spatrickinclude "AArch64SystemOperands.td" 67409467b48Spatrick 67509467b48Spatrick//===----------------------------------------------------------------------===// 67609467b48Spatrick// Access to privileged registers 67709467b48Spatrick//===----------------------------------------------------------------------===// 67809467b48Spatrick 67909467b48Spatrickforeach i = 1-3 in 68009467b48Spatrickdef FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 68109467b48Spatrick "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 68209467b48Spatrick 68309467b48Spatrick//===----------------------------------------------------------------------===// 684097a140dSpatrick// Control codegen mitigation against Straight Line Speculation vulnerability. 685097a140dSpatrick//===----------------------------------------------------------------------===// 686097a140dSpatrick 687097a140dSpatrickdef FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 688097a140dSpatrick "HardenSlsRetBr", "true", 689097a140dSpatrick "Harden against straight line speculation across RET and BR instructions">; 690097a140dSpatrickdef FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 691097a140dSpatrick "HardenSlsBlr", "true", 692097a140dSpatrick "Harden against straight line speculation across BLR instructions">; 69373471bf0Spatrickdef FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 69473471bf0Spatrick "HardenSlsNoComdat", "true", 69573471bf0Spatrick "Generate thunk code for SLS mitigation in the normal text section">; 696097a140dSpatrick 697097a140dSpatrick//===----------------------------------------------------------------------===// 69809467b48Spatrick// AArch64 Processors supported. 69909467b48Spatrick// 70009467b48Spatrick 70109467b48Spatrick//===----------------------------------------------------------------------===// 70209467b48Spatrick// Unsupported features to disable for scheduling models 70309467b48Spatrick//===----------------------------------------------------------------------===// 70409467b48Spatrick 70509467b48Spatrickclass AArch64Unsupported { list<Predicate> F; } 70609467b48Spatrick 70709467b48Spatrickdef SVEUnsupported : AArch64Unsupported { 70809467b48Spatrick let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, 709*d415bd75Srobert HasSVE2BitPerm, HasSVEorSME, HasSVE2p1, HasSVE2orSME, HasSVE2p1_or_HasSME2p1]; 71009467b48Spatrick} 71109467b48Spatrick 7127299aa8dSpatrickdef PAUnsupported : AArch64Unsupported { 71373471bf0Spatrick let F = [HasPAuth]; 71473471bf0Spatrick} 71573471bf0Spatrick 71673471bf0Spatrickdef SMEUnsupported : AArch64Unsupported { 717*d415bd75Srobert let F = [HasSME, HasSMEF64F64, HasSMEI16I64, HasSME2, HasSVE2p1_or_HasSME2, 718*d415bd75Srobert HasSVE2p1_or_HasSME2p1, HasSME2p1, HasSMEF16F16]; 7197299aa8dSpatrick} 7207299aa8dSpatrick 72109467b48Spatrickinclude "AArch64SchedA53.td" 72273471bf0Spatrickinclude "AArch64SchedA55.td" 72309467b48Spatrickinclude "AArch64SchedA57.td" 72409467b48Spatrickinclude "AArch64SchedCyclone.td" 72509467b48Spatrickinclude "AArch64SchedFalkor.td" 72609467b48Spatrickinclude "AArch64SchedKryo.td" 72709467b48Spatrickinclude "AArch64SchedExynosM3.td" 72809467b48Spatrickinclude "AArch64SchedExynosM4.td" 72909467b48Spatrickinclude "AArch64SchedExynosM5.td" 73009467b48Spatrickinclude "AArch64SchedThunderX.td" 73109467b48Spatrickinclude "AArch64SchedThunderX2T99.td" 73273471bf0Spatrickinclude "AArch64SchedA64FX.td" 7337299aa8dSpatrickinclude "AArch64SchedThunderX3T110.td" 73473471bf0Spatrickinclude "AArch64SchedTSV110.td" 735*d415bd75Srobertinclude "AArch64SchedAmpere1.td" 736*d415bd75Srobertinclude "AArch64SchedNeoverseN2.td" 73709467b48Spatrick 738*d415bd75Srobertdef TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 739*d415bd75Srobert "Cortex-A35 ARM processors">; 74009467b48Spatrick 741*d415bd75Srobertdef TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 74209467b48Spatrick "Cortex-A53 ARM processors", [ 74309467b48Spatrick FeatureFuseAES, 744*d415bd75Srobert FeatureFuseAdrpAdd, 745*d415bd75Srobert FeatureBalanceFPOps, 746*d415bd75Srobert FeatureCustomCheapAsMoveHandling, 747*d415bd75Srobert FeaturePostRAScheduler]>; 74809467b48Spatrick 749*d415bd75Srobertdef TuneA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 75009467b48Spatrick "Cortex-A55 ARM processors", [ 75109467b48Spatrick FeatureFuseAES, 752*d415bd75Srobert FeatureFuseAdrpAdd, 75373471bf0Spatrick FeaturePostRAScheduler, 754*d415bd75Srobert FeatureFuseAddress]>; 755*d415bd75Srobert 756*d415bd75Srobertdef TuneA510 : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510", 757*d415bd75Srobert "Cortex-A510 ARM processors", [ 758*d415bd75Srobert FeatureFuseAES, 759*d415bd75Srobert FeatureFuseAdrpAdd, 760*d415bd75Srobert FeaturePostRAScheduler 76109467b48Spatrick ]>; 76209467b48Spatrick 763*d415bd75Srobertdef TuneA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 76409467b48Spatrick "Cortex-A57 ARM processors", [ 765*d415bd75Srobert FeatureFuseAES, 76609467b48Spatrick FeatureBalanceFPOps, 76709467b48Spatrick FeatureCustomCheapAsMoveHandling, 768*d415bd75Srobert FeatureFuseAdrpAdd, 76909467b48Spatrick FeatureFuseLiterals, 77009467b48Spatrick FeaturePostRAScheduler, 771*d415bd75Srobert FeatureEnableSelectOptimize, 772*d415bd75Srobert FeaturePredictableSelectIsExpensive]>; 77309467b48Spatrick 774*d415bd75Srobertdef TuneA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65", 77509467b48Spatrick "Cortex-A65 ARM processors", [ 776*d415bd75Srobert FeatureFuseAES, 77773471bf0Spatrick FeatureFuseAddress, 778*d415bd75Srobert FeatureFuseAdrpAdd, 77973471bf0Spatrick FeatureFuseLiterals, 780*d415bd75Srobert FeatureEnableSelectOptimize]>; 78109467b48Spatrick 782*d415bd75Srobertdef TuneA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 78309467b48Spatrick "Cortex-A72 ARM processors", [ 78409467b48Spatrick FeatureFuseAES, 785*d415bd75Srobert FeatureFuseAdrpAdd, 78673471bf0Spatrick FeatureFuseLiterals, 787*d415bd75Srobert FeatureEnableSelectOptimize]>; 78809467b48Spatrick 789*d415bd75Srobertdef TuneA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 79009467b48Spatrick "Cortex-A73 ARM processors", [ 79109467b48Spatrick FeatureFuseAES, 792*d415bd75Srobert FeatureFuseAdrpAdd, 793*d415bd75Srobert FeatureEnableSelectOptimize]>; 79409467b48Spatrick 795*d415bd75Srobertdef TuneA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 79609467b48Spatrick "Cortex-A75 ARM processors", [ 79709467b48Spatrick FeatureFuseAES, 798*d415bd75Srobert FeatureFuseAdrpAdd, 799*d415bd75Srobert FeatureEnableSelectOptimize]>; 80009467b48Spatrick 801*d415bd75Srobertdef TuneA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 80209467b48Spatrick "Cortex-A76 ARM processors", [ 80373471bf0Spatrick FeatureFuseAES, 804*d415bd75Srobert FeatureFuseAdrpAdd, 805*d415bd75Srobert FeatureLSLFast, 806*d415bd75Srobert FeatureEnableSelectOptimize]>; 80709467b48Spatrick 808*d415bd75Srobertdef TuneA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 809097a140dSpatrick "Cortex-A77 ARM processors", [ 81073471bf0Spatrick FeatureCmpBccFusion, 81173471bf0Spatrick FeatureFuseAES, 812*d415bd75Srobert FeatureFuseAdrpAdd, 813*d415bd75Srobert FeatureLSLFast, 814*d415bd75Srobert FeatureEnableSelectOptimize]>; 815097a140dSpatrick 816*d415bd75Srobertdef TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78", 817097a140dSpatrick "Cortex-A78 ARM processors", [ 81873471bf0Spatrick FeatureCmpBccFusion, 819097a140dSpatrick FeatureFuseAES, 820*d415bd75Srobert FeatureFuseAdrpAdd, 821*d415bd75Srobert FeatureLSLFast, 822097a140dSpatrick FeaturePostRAScheduler, 823*d415bd75Srobert FeatureEnableSelectOptimize]>; 824097a140dSpatrick 825*d415bd75Srobertdef TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily", 82673471bf0Spatrick "CortexA78C", 82773471bf0Spatrick "Cortex-A78C ARM processors", [ 82873471bf0Spatrick FeatureCmpBccFusion, 82973471bf0Spatrick FeatureFuseAES, 830*d415bd75Srobert FeatureFuseAdrpAdd, 831*d415bd75Srobert FeatureLSLFast, 83273471bf0Spatrick FeaturePostRAScheduler, 833*d415bd75Srobert FeatureEnableSelectOptimize]>; 83473471bf0Spatrick 835*d415bd75Srobertdef TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710", 836*d415bd75Srobert "Cortex-A710 ARM processors", [ 837*d415bd75Srobert FeatureCmpBccFusion, 838*d415bd75Srobert FeatureFuseAES, 839*d415bd75Srobert FeatureFuseAdrpAdd, 840*d415bd75Srobert FeatureLSLFast, 841*d415bd75Srobert FeaturePostRAScheduler, 842*d415bd75Srobert FeatureEnableSelectOptimize]>; 843*d415bd75Srobert 844*d415bd75Srobertdef TuneA715 : SubtargetFeature<"a715", "ARMProcFamily", "CortexA715", 845*d415bd75Srobert "Cortex-A715 ARM processors", [ 846*d415bd75Srobert FeatureFuseAES, 847*d415bd75Srobert FeaturePostRAScheduler, 848*d415bd75Srobert FeatureCmpBccFusion, 849*d415bd75Srobert FeatureLSLFast, 850*d415bd75Srobert FeatureFuseAdrpAdd, 851*d415bd75Srobert FeatureEnableSelectOptimize]>; 852*d415bd75Srobert 853*d415bd75Srobertdef TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily", 85473471bf0Spatrick "CortexR82", 855*d415bd75Srobert "Cortex-R82 ARM processors", [ 856*d415bd75Srobert FeaturePostRAScheduler]>; 85773471bf0Spatrick 858*d415bd75Srobertdef TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 859097a140dSpatrick "Cortex-X1 ARM processors", [ 86073471bf0Spatrick FeatureCmpBccFusion, 861097a140dSpatrick FeatureFuseAES, 862*d415bd75Srobert FeatureFuseAdrpAdd, 863*d415bd75Srobert FeatureLSLFast, 864097a140dSpatrick FeaturePostRAScheduler, 865*d415bd75Srobert FeatureEnableSelectOptimize]>; 866097a140dSpatrick 867*d415bd75Srobertdef TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2", 868*d415bd75Srobert "Cortex-X2 ARM processors", [ 869*d415bd75Srobert FeatureCmpBccFusion, 870*d415bd75Srobert FeatureFuseAES, 871*d415bd75Srobert FeatureFuseAdrpAdd, 872*d415bd75Srobert FeatureLSLFast, 873097a140dSpatrick FeaturePostRAScheduler, 874*d415bd75Srobert FeatureEnableSelectOptimize]>; 875*d415bd75Srobert 876*d415bd75Srobertdef TuneX3 : SubtargetFeature<"cortex-x3", "ARMProcFamily", "CortexX3", 877*d415bd75Srobert "Cortex-X3 ARM processors", [ 878*d415bd75Srobert FeatureLSLFast, 879*d415bd75Srobert FeatureFuseAdrpAdd, 880*d415bd75Srobert FeatureFuseAES, 881*d415bd75Srobert FeaturePostRAScheduler, 882*d415bd75Srobert FeatureEnableSelectOptimize]>; 883*d415bd75Srobert 884*d415bd75Srobertdef TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", 885*d415bd75Srobert "Fujitsu A64FX processors", [ 886*d415bd75Srobert FeaturePostRAScheduler, 88773471bf0Spatrick FeatureAggressiveFMA, 88873471bf0Spatrick FeatureArithmeticBccFusion, 88973471bf0Spatrick FeaturePredictableSelectIsExpensive 890097a140dSpatrick ]>; 891097a140dSpatrick 892*d415bd75Srobertdef TuneCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel", 893*d415bd75Srobert "Nvidia Carmel processors">; 894097a140dSpatrick 89509467b48Spatrick// Note that cyclone does not fuse AES instructions, but newer apple chips do 89609467b48Spatrick// perform the fusion and cyclone is used by default when targetting apple OSes. 897*d415bd75Srobertdef TuneAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", 89809467b48Spatrick "Apple A7 (the CPU formerly known as Cyclone)", [ 89909467b48Spatrick FeatureAlternateSExtLoadCVTF32Pattern, 90009467b48Spatrick FeatureArithmeticBccFusion, 90109467b48Spatrick FeatureArithmeticCbzFusion, 90209467b48Spatrick FeatureDisableLatencySchedHeuristic, 903*d415bd75Srobert FeatureFuseAES, FeatureFuseCryptoEOR, 90409467b48Spatrick FeatureZCRegMove, 90509467b48Spatrick FeatureZCZeroing, 906*d415bd75Srobert FeatureZCZeroingFPWorkaround] 907*d415bd75Srobert >; 90809467b48Spatrick 909*d415bd75Srobertdef TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", 91009467b48Spatrick "Apple A10", [ 91109467b48Spatrick FeatureAlternateSExtLoadCVTF32Pattern, 91209467b48Spatrick FeatureArithmeticBccFusion, 91309467b48Spatrick FeatureArithmeticCbzFusion, 91409467b48Spatrick FeatureDisableLatencySchedHeuristic, 91509467b48Spatrick FeatureFuseAES, 91609467b48Spatrick FeatureFuseCryptoEOR, 91709467b48Spatrick FeatureZCRegMove, 918*d415bd75Srobert FeatureZCZeroing] 919*d415bd75Srobert >; 92009467b48Spatrick 921*d415bd75Srobertdef TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", 92209467b48Spatrick "Apple A11", [ 92309467b48Spatrick FeatureAlternateSExtLoadCVTF32Pattern, 92409467b48Spatrick FeatureArithmeticBccFusion, 92509467b48Spatrick FeatureArithmeticCbzFusion, 92609467b48Spatrick FeatureDisableLatencySchedHeuristic, 92709467b48Spatrick FeatureFuseAES, 92809467b48Spatrick FeatureFuseCryptoEOR, 92909467b48Spatrick FeatureZCRegMove, 930*d415bd75Srobert FeatureZCZeroing] 931*d415bd75Srobert >; 93209467b48Spatrick 933*d415bd75Srobertdef TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", 93409467b48Spatrick "Apple A12", [ 93509467b48Spatrick FeatureAlternateSExtLoadCVTF32Pattern, 93609467b48Spatrick FeatureArithmeticBccFusion, 93709467b48Spatrick FeatureArithmeticCbzFusion, 93809467b48Spatrick FeatureDisableLatencySchedHeuristic, 93909467b48Spatrick FeatureFuseAES, 94009467b48Spatrick FeatureFuseCryptoEOR, 94109467b48Spatrick FeatureZCRegMove, 942*d415bd75Srobert FeatureZCZeroing] 943*d415bd75Srobert >; 94409467b48Spatrick 945*d415bd75Srobertdef TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", 94609467b48Spatrick "Apple A13", [ 94709467b48Spatrick FeatureAlternateSExtLoadCVTF32Pattern, 94809467b48Spatrick FeatureArithmeticBccFusion, 94909467b48Spatrick FeatureArithmeticCbzFusion, 95009467b48Spatrick FeatureDisableLatencySchedHeuristic, 95109467b48Spatrick FeatureFuseAES, 95209467b48Spatrick FeatureFuseCryptoEOR, 95309467b48Spatrick FeatureZCRegMove, 954*d415bd75Srobert FeatureZCZeroing] 955*d415bd75Srobert >; 95609467b48Spatrick 957*d415bd75Srobertdef TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14", 95873471bf0Spatrick "Apple A14", [ 95973471bf0Spatrick FeatureAggressiveFMA, 96073471bf0Spatrick FeatureAlternateSExtLoadCVTF32Pattern, 96173471bf0Spatrick FeatureArithmeticBccFusion, 96273471bf0Spatrick FeatureArithmeticCbzFusion, 96373471bf0Spatrick FeatureDisableLatencySchedHeuristic, 964*d415bd75Srobert FeatureFuseAddress, 965*d415bd75Srobert FeatureFuseAES, 966*d415bd75Srobert FeatureFuseArithmeticLogic, 967*d415bd75Srobert FeatureFuseCCSelect, 968*d415bd75Srobert FeatureFuseCryptoEOR, 969*d415bd75Srobert FeatureFuseAdrpAdd, 970*d415bd75Srobert FeatureFuseLiterals, 971*d415bd75Srobert FeatureZCRegMove, 972*d415bd75Srobert FeatureZCZeroing]>; 973*d415bd75Srobert 974*d415bd75Srobertdef TuneAppleA15 : SubtargetFeature<"apple-a15", "ARMProcFamily", "AppleA15", 975*d415bd75Srobert "Apple A15", [ 976*d415bd75Srobert FeatureAlternateSExtLoadCVTF32Pattern, 977*d415bd75Srobert FeatureArithmeticBccFusion, 978*d415bd75Srobert FeatureArithmeticCbzFusion, 979*d415bd75Srobert FeatureDisableLatencySchedHeuristic, 98073471bf0Spatrick FeatureFuseAddress, 98173471bf0Spatrick FeatureFuseAES, 98273471bf0Spatrick FeatureFuseArithmeticLogic, 98373471bf0Spatrick FeatureFuseCCSelect, 98473471bf0Spatrick FeatureFuseCryptoEOR, 98573471bf0Spatrick FeatureFuseLiterals, 98673471bf0Spatrick FeatureZCRegMove, 987*d415bd75Srobert FeatureZCZeroing 98873471bf0Spatrick ]>; 98973471bf0Spatrick 990*d415bd75Srobertdef TuneAppleA16 : SubtargetFeature<"apple-a16", "ARMProcFamily", "AppleA16", 991*d415bd75Srobert "Apple A16", [ 992*d415bd75Srobert FeatureAlternateSExtLoadCVTF32Pattern, 99309467b48Spatrick FeatureArithmeticBccFusion, 99409467b48Spatrick FeatureArithmeticCbzFusion, 995*d415bd75Srobert FeatureDisableLatencySchedHeuristic, 99609467b48Spatrick FeatureFuseAddress, 99709467b48Spatrick FeatureFuseAES, 99809467b48Spatrick FeatureFuseArithmeticLogic, 99909467b48Spatrick FeatureFuseCCSelect, 1000*d415bd75Srobert FeatureFuseCryptoEOR, 1001*d415bd75Srobert FeatureFuseLiterals, 1002*d415bd75Srobert FeatureZCRegMove, 1003*d415bd75Srobert FeatureZCZeroing 1004*d415bd75Srobert ]>; 1005*d415bd75Srobert 1006*d415bd75Srobertdef TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 1007*d415bd75Srobert "Samsung Exynos-M3 processors", 1008*d415bd75Srobert [FeatureExynosCheapAsMoveHandling, 1009*d415bd75Srobert FeatureForce32BitJumpTables, 1010*d415bd75Srobert FeatureFuseAddress, 1011*d415bd75Srobert FeatureFuseAES, 1012*d415bd75Srobert FeatureFuseCCSelect, 1013*d415bd75Srobert FeatureFuseAdrpAdd, 101409467b48Spatrick FeatureFuseLiterals, 101509467b48Spatrick FeatureLSLFast, 1016*d415bd75Srobert FeaturePostRAScheduler, 1017*d415bd75Srobert FeaturePredictableSelectIsExpensive]>; 1018*d415bd75Srobert 1019*d415bd75Srobert// Re-uses some scheduling and tunings from the ExynosM3 proc family. 1020*d415bd75Srobertdef TuneExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3", 1021*d415bd75Srobert "Samsung Exynos-M4 processors", 1022*d415bd75Srobert [FeatureArithmeticBccFusion, 1023*d415bd75Srobert FeatureArithmeticCbzFusion, 1024*d415bd75Srobert FeatureExynosCheapAsMoveHandling, 1025*d415bd75Srobert FeatureForce32BitJumpTables, 1026*d415bd75Srobert FeatureFuseAddress, 1027*d415bd75Srobert FeatureFuseAES, 1028*d415bd75Srobert FeatureFuseArithmeticLogic, 1029*d415bd75Srobert FeatureFuseCCSelect, 1030*d415bd75Srobert FeatureFuseAdrpAdd, 1031*d415bd75Srobert FeatureFuseLiterals, 1032*d415bd75Srobert FeatureLSLFast, 103309467b48Spatrick FeaturePostRAScheduler, 103409467b48Spatrick FeatureZCZeroing]>; 103509467b48Spatrick 1036*d415bd75Srobertdef TuneKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 103709467b48Spatrick "Qualcomm Kryo processors", [ 103809467b48Spatrick FeatureCustomCheapAsMoveHandling, 103909467b48Spatrick FeaturePostRAScheduler, 104009467b48Spatrick FeaturePredictableSelectIsExpensive, 104109467b48Spatrick FeatureZCZeroing, 1042*d415bd75Srobert FeatureLSLFast] 1043*d415bd75Srobert >; 104409467b48Spatrick 1045*d415bd75Srobertdef TuneFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 104609467b48Spatrick "Qualcomm Falkor processors", [ 104709467b48Spatrick FeatureCustomCheapAsMoveHandling, 104809467b48Spatrick FeaturePostRAScheduler, 104909467b48Spatrick FeaturePredictableSelectIsExpensive, 105009467b48Spatrick FeatureZCZeroing, 105109467b48Spatrick FeatureLSLFast, 105209467b48Spatrick FeatureSlowSTRQro 105309467b48Spatrick ]>; 105409467b48Spatrick 1055*d415bd75Srobertdef TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1", 105609467b48Spatrick "Neoverse E1 ARM processors", [ 105773471bf0Spatrick FeatureFuseAES, 1058*d415bd75Srobert FeatureFuseAdrpAdd, 1059*d415bd75Srobert FeaturePostRAScheduler]>; 106009467b48Spatrick 1061*d415bd75Srobertdef TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1", 106209467b48Spatrick "Neoverse N1 ARM processors", [ 106373471bf0Spatrick FeatureFuseAES, 1064*d415bd75Srobert FeatureFuseAdrpAdd, 1065*d415bd75Srobert FeatureLSLFast, 1066*d415bd75Srobert FeaturePostRAScheduler, 1067*d415bd75Srobert FeatureEnableSelectOptimize]>; 106809467b48Spatrick 1069*d415bd75Srobertdef TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2", 107073471bf0Spatrick "Neoverse N2 ARM processors", [ 107173471bf0Spatrick FeatureFuseAES, 1072*d415bd75Srobert FeatureFuseAdrpAdd, 1073*d415bd75Srobert FeatureLSLFast, 1074*d415bd75Srobert FeaturePostRAScheduler, 1075*d415bd75Srobert FeatureEnableSelectOptimize]>; 107673471bf0Spatrick 1077*d415bd75Srobertdef TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB", 1078*d415bd75Srobert "Neoverse 512-TVB ARM processors", [ 1079*d415bd75Srobert FeatureFuseAES, 1080*d415bd75Srobert FeatureFuseAdrpAdd, 1081*d415bd75Srobert FeatureLSLFast, 1082*d415bd75Srobert FeaturePostRAScheduler, 1083*d415bd75Srobert FeatureEnableSelectOptimize]>; 1084*d415bd75Srobert 1085*d415bd75Srobertdef TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1", 108673471bf0Spatrick "Neoverse V1 ARM processors", [ 108773471bf0Spatrick FeatureFuseAES, 1088*d415bd75Srobert FeatureFuseAdrpAdd, 1089*d415bd75Srobert FeatureLSLFast, 109073471bf0Spatrick FeaturePostRAScheduler, 1091*d415bd75Srobert FeatureEnableSelectOptimize]>; 109273471bf0Spatrick 1093*d415bd75Srobertdef TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2", 1094*d415bd75Srobert "Neoverse V2 ARM processors", [ 1095*d415bd75Srobert FeatureFuseAES, 1096*d415bd75Srobert FeatureLSLFast, 1097*d415bd75Srobert FeaturePostRAScheduler, 1098*d415bd75Srobert FeatureEnableSelectOptimize]>; 1099*d415bd75Srobert 1100*d415bd75Srobertdef TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 110109467b48Spatrick "Qualcomm Saphira processors", [ 110209467b48Spatrick FeatureCustomCheapAsMoveHandling, 110309467b48Spatrick FeaturePostRAScheduler, 110409467b48Spatrick FeaturePredictableSelectIsExpensive, 110509467b48Spatrick FeatureZCZeroing, 1106*d415bd75Srobert FeatureLSLFast]>; 110709467b48Spatrick 1108*d415bd75Srobertdef TuneThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99", 110909467b48Spatrick "Cavium ThunderX2 processors", [ 111009467b48Spatrick FeatureAggressiveFMA, 111109467b48Spatrick FeatureArithmeticBccFusion, 111209467b48Spatrick FeaturePostRAScheduler, 1113*d415bd75Srobert FeaturePredictableSelectIsExpensive]>; 111409467b48Spatrick 1115*d415bd75Srobertdef TuneThunderX3T110 : SubtargetFeature<"thunderx3t110", "ARMProcFamily", 11167299aa8dSpatrick "ThunderX3T110", 11177299aa8dSpatrick "Marvell ThunderX3 processors", [ 11187299aa8dSpatrick FeatureAggressiveFMA, 11197299aa8dSpatrick FeatureArithmeticBccFusion, 11207299aa8dSpatrick FeaturePostRAScheduler, 11217299aa8dSpatrick FeaturePredictableSelectIsExpensive, 11227299aa8dSpatrick FeatureBalanceFPOps, 1123*d415bd75Srobert FeatureStrictAlign]>; 11247299aa8dSpatrick 1125*d415bd75Srobertdef TuneThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 112609467b48Spatrick "Cavium ThunderX processors", [ 112709467b48Spatrick FeaturePostRAScheduler, 1128*d415bd75Srobert FeaturePredictableSelectIsExpensive]>; 112909467b48Spatrick 1130*d415bd75Srobertdef TuneThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 113109467b48Spatrick "ThunderXT88", 113209467b48Spatrick "Cavium ThunderX processors", [ 113309467b48Spatrick FeaturePostRAScheduler, 1134*d415bd75Srobert FeaturePredictableSelectIsExpensive]>; 113509467b48Spatrick 1136*d415bd75Srobertdef TuneThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 113709467b48Spatrick "ThunderXT81", 113809467b48Spatrick "Cavium ThunderX processors", [ 113909467b48Spatrick FeaturePostRAScheduler, 1140*d415bd75Srobert FeaturePredictableSelectIsExpensive]>; 114109467b48Spatrick 1142*d415bd75Srobertdef TuneThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 114309467b48Spatrick "ThunderXT83", 114409467b48Spatrick "Cavium ThunderX processors", [ 114509467b48Spatrick FeaturePostRAScheduler, 1146*d415bd75Srobert FeaturePredictableSelectIsExpensive]>; 114709467b48Spatrick 1148*d415bd75Srobertdef TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 114909467b48Spatrick "HiSilicon TS-V110 processors", [ 115009467b48Spatrick FeatureCustomCheapAsMoveHandling, 115109467b48Spatrick FeatureFuseAES, 1152*d415bd75Srobert FeaturePostRAScheduler]>; 115309467b48Spatrick 1154*d415bd75Srobertdef TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1", 1155*d415bd75Srobert "Ampere Computing Ampere-1 processors", [ 115609467b48Spatrick FeaturePostRAScheduler, 1157*d415bd75Srobert FeatureFuseAES, 1158*d415bd75Srobert FeatureLSLFast, 1159*d415bd75Srobert FeatureAggressiveFMA, 1160*d415bd75Srobert FeatureArithmeticBccFusion, 1161*d415bd75Srobert FeatureCmpBccFusion, 1162*d415bd75Srobert FeatureFuseAddress, 1163*d415bd75Srobert FeatureFuseLiterals]>; 1164*d415bd75Srobert 1165*d415bd75Srobertdef TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A", 1166*d415bd75Srobert "Ampere Computing Ampere-1A processors", [ 1167*d415bd75Srobert FeaturePostRAScheduler, 1168*d415bd75Srobert FeatureFuseAES, 1169*d415bd75Srobert FeatureLSLFast, 1170*d415bd75Srobert FeatureAggressiveFMA, 1171*d415bd75Srobert FeatureArithmeticBccFusion, 1172*d415bd75Srobert FeatureCmpBccFusion, 1173*d415bd75Srobert FeatureFuseAddress, 1174*d415bd75Srobert FeatureFuseLiterals, 1175*d415bd75Srobert FeatureFuseLiterals]>; 1176*d415bd75Srobert 1177*d415bd75Srobertdef ProcessorFeatures { 1178*d415bd75Srobert list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1179*d415bd75Srobert FeatureFPARMv8, FeatureNEON, FeaturePerfMon]; 1180*d415bd75Srobert list<SubtargetFeature> A55 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1181*d415bd75Srobert FeatureNEON, FeatureFullFP16, FeatureDotProd, 1182*d415bd75Srobert FeatureRCPC, FeaturePerfMon]; 1183*d415bd75Srobert list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1184*d415bd75Srobert FeatureMatMulInt8, FeatureBF16, FeatureAM, 1185*d415bd75Srobert FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1186*d415bd75Srobert FeatureFP16FML]; 1187*d415bd75Srobert list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1188*d415bd75Srobert FeatureNEON, FeatureFullFP16, FeatureDotProd, 1189*d415bd75Srobert FeatureRCPC, FeatureSSBS, FeatureRAS, 1190*d415bd75Srobert FeaturePerfMon]; 1191*d415bd75Srobert list<SubtargetFeature> A76 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1192*d415bd75Srobert FeatureNEON, FeatureFullFP16, FeatureDotProd, 1193*d415bd75Srobert FeatureRCPC, FeatureSSBS, FeaturePerfMon]; 1194*d415bd75Srobert list<SubtargetFeature> A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1195*d415bd75Srobert FeatureNEON, FeatureFullFP16, FeatureDotProd, 1196*d415bd75Srobert FeatureRCPC, FeaturePerfMon, FeatureSSBS]; 1197*d415bd75Srobert list<SubtargetFeature> A78 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1198*d415bd75Srobert FeatureNEON, FeatureFullFP16, FeatureDotProd, 1199*d415bd75Srobert FeatureRCPC, FeaturePerfMon, FeatureSPE, 1200*d415bd75Srobert FeatureSSBS]; 1201*d415bd75Srobert list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1202*d415bd75Srobert FeatureNEON, FeatureFullFP16, FeatureDotProd, 1203*d415bd75Srobert FeatureFlagM, FeatureFP16FML, FeaturePAuth, 1204*d415bd75Srobert FeaturePerfMon, FeatureRCPC, FeatureSPE, 1205*d415bd75Srobert FeatureSSBS]; 1206*d415bd75Srobert list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1207*d415bd75Srobert FeatureETE, FeatureMTE, FeatureFP16FML, 1208*d415bd75Srobert FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8]; 1209*d415bd75Srobert list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE, 1210*d415bd75Srobert FeatureFP16FML, FeatureSVE, FeatureTRBE, 1211*d415bd75Srobert FeatureSVE2BitPerm, FeatureBF16, FeatureETE, 1212*d415bd75Srobert FeaturePerfMon, FeatureMatMulInt8, FeatureSPE]; 1213*d415bd75Srobert list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16, 1214*d415bd75Srobert FeatureFP16FML, FeatureSSBS, FeaturePredRes, 1215*d415bd75Srobert FeatureSB]; 1216*d415bd75Srobert list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1217*d415bd75Srobert FeatureNEON, FeatureRCPC, FeaturePerfMon, 1218*d415bd75Srobert FeatureSPE, FeatureFullFP16, FeatureDotProd, 1219*d415bd75Srobert FeatureSSBS]; 1220*d415bd75Srobert list<SubtargetFeature> X1C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1221*d415bd75Srobert FeatureNEON, FeatureRCPC_IMMO, FeaturePerfMon, 1222*d415bd75Srobert FeatureSPE, FeatureFullFP16, FeatureDotProd, 1223*d415bd75Srobert FeaturePAuth, FeatureSSBS, FeatureFlagM, 1224*d415bd75Srobert FeatureLSE2]; 1225*d415bd75Srobert list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1226*d415bd75Srobert FeatureMatMulInt8, FeatureBF16, FeatureAM, 1227*d415bd75Srobert FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1228*d415bd75Srobert FeatureFP16FML]; 1229*d415bd75Srobert list<SubtargetFeature> X3 = [HasV9_0aOps, FeatureSVE, FeatureNEON, 1230*d415bd75Srobert FeaturePerfMon, FeatureETE, FeatureTRBE, 1231*d415bd75Srobert FeatureSPE, FeatureBF16, FeatureMatMulInt8, 1232*d415bd75Srobert FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16, 1233*d415bd75Srobert FeatureFP16FML]; 1234*d415bd75Srobert list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, 1235*d415bd75Srobert FeatureSHA2, FeaturePerfMon, FeatureFullFP16, 1236*d415bd75Srobert FeatureSVE, FeatureComplxNum]; 1237*d415bd75Srobert list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureCrypto, 1238*d415bd75Srobert FeatureFullFP16]; 1239*d415bd75Srobert list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 1240*d415bd75Srobert FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg]; 1241*d415bd75Srobert list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 1242*d415bd75Srobert FeatureNEON, FeaturePerfMon, FeatureCRC, 1243*d415bd75Srobert FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]; 1244*d415bd75Srobert list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1245*d415bd75Srobert FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1246*d415bd75Srobert list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8, 1247*d415bd75Srobert FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1248*d415bd75Srobert list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1249*d415bd75Srobert FeatureNEON, FeaturePerfMon, FeatureFullFP16, 1250*d415bd75Srobert FeatureFP16FML, FeatureSHA3]; 1251*d415bd75Srobert list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1252*d415bd75Srobert FeatureNEON, FeaturePerfMon, FeatureFRInt3264, 1253*d415bd75Srobert FeatureSpecRestrict, FeatureSSBS, FeatureSB, 1254*d415bd75Srobert FeaturePredRes, FeatureCacheDeepPersist, 1255*d415bd75Srobert FeatureFullFP16, FeatureFP16FML, FeatureSHA3, 1256*d415bd75Srobert FeatureAltFPCmp]; 1257*d415bd75Srobert list<SubtargetFeature> AppleA15 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1258*d415bd75Srobert FeatureNEON, FeaturePerfMon, FeatureSHA3, 1259*d415bd75Srobert FeatureFullFP16, FeatureFP16FML]; 1260*d415bd75Srobert list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1261*d415bd75Srobert FeatureNEON, FeaturePerfMon, FeatureSHA3, 1262*d415bd75Srobert FeatureFullFP16, FeatureFP16FML, 1263*d415bd75Srobert FeatureHCX]; 1264*d415bd75Srobert list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1265*d415bd75Srobert FeaturePerfMon]; 1266*d415bd75Srobert list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1267*d415bd75Srobert FeatureFullFP16, FeaturePerfMon]; 1268*d415bd75Srobert list<SubtargetFeature> Falkor = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1269*d415bd75Srobert FeatureFPARMv8, FeatureNEON, FeaturePerfMon, 1270*d415bd75Srobert FeatureRDM]; 1271*d415bd75Srobert list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1272*d415bd75Srobert FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1273*d415bd75Srobert FeatureRCPC, FeatureSSBS, FeaturePerfMon]; 1274*d415bd75Srobert list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1275*d415bd75Srobert FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1276*d415bd75Srobert FeatureRCPC, FeatureSPE, FeatureSSBS, 1277*d415bd75Srobert FeaturePerfMon]; 1278*d415bd75Srobert list<SubtargetFeature> NeoverseN2 = [HasV8_5aOps, FeatureBF16, FeatureETE, 1279*d415bd75Srobert FeatureMatMulInt8, FeatureMTE, FeatureSVE2, 1280*d415bd75Srobert FeatureSVE2BitPerm, FeatureTRBE, FeatureCrypto, 1281*d415bd75Srobert FeaturePerfMon]; 1282*d415bd75Srobert list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1283*d415bd75Srobert FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1284*d415bd75Srobert FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1285*d415bd75Srobert FeaturePerfMon, FeatureRandGen, FeatureSPE, 1286*d415bd75Srobert FeatureSSBS, FeatureSVE]; 1287*d415bd75Srobert list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1288*d415bd75Srobert FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1289*d415bd75Srobert FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1290*d415bd75Srobert FeaturePerfMon, FeatureRandGen, FeatureSPE, 1291*d415bd75Srobert FeatureSSBS, FeatureSVE]; 1292*d415bd75Srobert list<SubtargetFeature> NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE, 1293*d415bd75Srobert FeaturePerfMon, FeatureETE, FeatureMatMulInt8, 1294*d415bd75Srobert FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, 1295*d415bd75Srobert FeatureMTE, FeatureRandGen]; 1296*d415bd75Srobert list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1297*d415bd75Srobert FeatureNEON, FeatureSPE, FeaturePerfMon]; 1298*d415bd75Srobert list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1299*d415bd75Srobert FeatureFPARMv8, FeaturePerfMon, FeatureNEON]; 1300*d415bd75Srobert list<SubtargetFeature> ThunderX2T99 = [HasV8_1aOps, FeatureCRC, FeatureCrypto, 1301*d415bd75Srobert FeatureFPARMv8, FeatureNEON, FeatureLSE]; 1302*d415bd75Srobert list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto, 1303*d415bd75Srobert FeatureFPARMv8, FeatureNEON, FeatureLSE, 1304*d415bd75Srobert FeaturePAuth, FeaturePerfMon]; 1305*d415bd75Srobert list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1306*d415bd75Srobert FeatureNEON, FeaturePerfMon, FeatureSPE, 1307*d415bd75Srobert FeatureFullFP16, FeatureFP16FML, FeatureDotProd]; 1308*d415bd75Srobert list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, 1309*d415bd75Srobert FeatureSSBS, FeatureRandGen, FeatureSB, 1310*d415bd75Srobert FeatureSHA2, FeatureSHA3, FeatureAES]; 1311*d415bd75Srobert list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, 1312*d415bd75Srobert FeatureMTE, FeatureSSBS, FeatureRandGen, 1313*d415bd75Srobert FeatureSB, FeatureSM4, FeatureSHA2, 1314*d415bd75Srobert FeatureSHA3, FeatureAES]; 1315*d415bd75Srobert 1316097a140dSpatrick // ETE and TRBE are future architecture extensions. We temporarily enable them 1317*d415bd75Srobert // by default for users targeting generic AArch64. The extensions do not 131809467b48Spatrick // affect code generated by the compiler and can be used only by explicitly 131909467b48Spatrick // mentioning the new system register names in assembly. 1320*d415bd75Srobert list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE]; 1321*d415bd75Srobert} 132209467b48Spatrick 1323*d415bd75Srobert// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging 1324*d415bd75Srobert// optimizations. 1325*d415bd75Srobertdef : ProcessorModel<"generic", CortexA55Model, ProcessorFeatures.Generic, 1326*d415bd75Srobert [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, 1327*d415bd75Srobert FeatureEnableSelectOptimize]>; 1328*d415bd75Srobertdef : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53, 1329*d415bd75Srobert [TuneA35]>; 1330*d415bd75Srobertdef : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53, 1331*d415bd75Srobert [TuneA35]>; 1332*d415bd75Srobertdef : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53, 1333*d415bd75Srobert [TuneA53]>; 1334*d415bd75Srobertdef : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55, 1335*d415bd75Srobert [TuneA55]>; 1336*d415bd75Srobertdef : ProcessorModel<"cortex-a510", CortexA55Model, ProcessorFeatures.A510, 1337*d415bd75Srobert [TuneA510]>; 1338*d415bd75Srobertdef : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53, 1339*d415bd75Srobert [TuneA57]>; 1340*d415bd75Srobertdef : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65, 1341*d415bd75Srobert [TuneA65]>; 1342*d415bd75Srobertdef : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65, 1343*d415bd75Srobert [TuneA65]>; 1344*d415bd75Srobertdef : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53, 1345*d415bd75Srobert [TuneA72]>; 1346*d415bd75Srobertdef : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53, 1347*d415bd75Srobert [TuneA73]>; 1348*d415bd75Srobertdef : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55, 1349*d415bd75Srobert [TuneA75]>; 1350*d415bd75Srobertdef : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76, 1351*d415bd75Srobert [TuneA76]>; 1352*d415bd75Srobertdef : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76, 1353*d415bd75Srobert [TuneA76]>; 1354*d415bd75Srobertdef : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77, 1355*d415bd75Srobert [TuneA77]>; 1356*d415bd75Srobertdef : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78, 1357*d415bd75Srobert [TuneA78]>; 1358*d415bd75Srobertdef : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, 1359*d415bd75Srobert [TuneA78C]>; 1360*d415bd75Srobertdef : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710, 1361*d415bd75Srobert [TuneA710]>; 1362*d415bd75Srobertdef : ProcessorModel<"cortex-a715", NeoverseN2Model, ProcessorFeatures.A715, 1363*d415bd75Srobert [TuneA715]>; 1364*d415bd75Srobertdef : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, 1365*d415bd75Srobert [TuneR82]>; 1366*d415bd75Srobertdef : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, 1367*d415bd75Srobert [TuneX1]>; 1368*d415bd75Srobertdef : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C, 1369*d415bd75Srobert [TuneX1]>; 1370*d415bd75Srobertdef : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2, 1371*d415bd75Srobert [TuneX2]>; 1372*d415bd75Srobertdef : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3, 1373*d415bd75Srobert [TuneX3]>; 1374*d415bd75Srobertdef : ProcessorModel<"neoverse-e1", CortexA53Model, 1375*d415bd75Srobert ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; 1376*d415bd75Srobertdef : ProcessorModel<"neoverse-n1", CortexA57Model, 1377*d415bd75Srobert ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; 1378*d415bd75Srobertdef : ProcessorModel<"neoverse-n2", NeoverseN2Model, 1379*d415bd75Srobert ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; 1380*d415bd75Srobertdef : ProcessorModel<"neoverse-512tvb", NeoverseN2Model, 1381*d415bd75Srobert ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; 1382*d415bd75Srobertdef : ProcessorModel<"neoverse-v1", NeoverseN2Model, 1383*d415bd75Srobert ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; 1384*d415bd75Srobertdef : ProcessorModel<"neoverse-v2", NeoverseN2Model, 1385*d415bd75Srobert ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; 1386*d415bd75Srobertdef : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, 1387*d415bd75Srobert [TuneExynosM3]>; 1388*d415bd75Srobertdef : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, 1389*d415bd75Srobert [TuneExynosM4]>; 1390*d415bd75Srobertdef : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4, 1391*d415bd75Srobert [TuneExynosM4]>; 1392*d415bd75Srobertdef : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor, 1393*d415bd75Srobert [TuneFalkor]>; 1394*d415bd75Srobertdef : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira, 1395*d415bd75Srobert [TuneSaphira]>; 1396*d415bd75Srobertdef : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>; 1397*d415bd75Srobert 139809467b48Spatrick// Cavium ThunderX/ThunderX T8X Processors 1399*d415bd75Srobertdef : ProcessorModel<"thunderx", ThunderXT8XModel, ProcessorFeatures.ThunderX, 1400*d415bd75Srobert [TuneThunderX]>; 1401*d415bd75Srobertdef : ProcessorModel<"thunderxt88", ThunderXT8XModel, 1402*d415bd75Srobert ProcessorFeatures.ThunderX, [TuneThunderXT88]>; 1403*d415bd75Srobertdef : ProcessorModel<"thunderxt81", ThunderXT8XModel, 1404*d415bd75Srobert ProcessorFeatures.ThunderX, [TuneThunderXT81]>; 1405*d415bd75Srobertdef : ProcessorModel<"thunderxt83", ThunderXT8XModel, 1406*d415bd75Srobert ProcessorFeatures.ThunderX, [TuneThunderXT83]>; 140709467b48Spatrick// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 1408*d415bd75Srobertdef : ProcessorModel<"thunderx2t99", ThunderX2T99Model, 1409*d415bd75Srobert ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>; 14107299aa8dSpatrick// Marvell ThunderX3T110 Processors. 1411*d415bd75Srobertdef : ProcessorModel<"thunderx3t110", ThunderX3T110Model, 1412*d415bd75Srobert ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>; 1413*d415bd75Srobertdef : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, 1414*d415bd75Srobert [TuneTSV110]>; 141509467b48Spatrick 141609467b48Spatrick// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. 1417*d415bd75Srobertdef : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7, 1418*d415bd75Srobert [TuneAppleA7]>; 141909467b48Spatrick 142009467b48Spatrick// iPhone and iPad CPUs 1421*d415bd75Srobertdef : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7, 1422*d415bd75Srobert [TuneAppleA7]>; 1423*d415bd75Srobertdef : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7, 1424*d415bd75Srobert [TuneAppleA7]>; 1425*d415bd75Srobertdef : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7, 1426*d415bd75Srobert [TuneAppleA7]>; 1427*d415bd75Srobertdef : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10, 1428*d415bd75Srobert [TuneAppleA10]>; 1429*d415bd75Srobertdef : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11, 1430*d415bd75Srobert [TuneAppleA11]>; 1431*d415bd75Srobertdef : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12, 1432*d415bd75Srobert [TuneAppleA12]>; 1433*d415bd75Srobertdef : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13, 1434*d415bd75Srobert [TuneAppleA13]>; 1435*d415bd75Srobertdef : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14, 1436*d415bd75Srobert [TuneAppleA14]>; 1437*d415bd75Srobertdef : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15, 1438*d415bd75Srobert [TuneAppleA15]>; 1439*d415bd75Srobertdef : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, 1440*d415bd75Srobert [TuneAppleA16]>; 144173471bf0Spatrick 144273471bf0Spatrick// Mac CPUs 1443*d415bd75Srobertdef : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14, 1444*d415bd75Srobert [TuneAppleA14]>; 1445*d415bd75Srobertdef : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15, 1446*d415bd75Srobert [TuneAppleA15]>; 144709467b48Spatrick 144809467b48Spatrick// watch CPUs. 1449*d415bd75Srobertdef : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12, 1450*d415bd75Srobert [TuneAppleA12]>; 1451*d415bd75Srobertdef : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12, 1452*d415bd75Srobert [TuneAppleA12]>; 145309467b48Spatrick 145409467b48Spatrick// Alias for the latest Apple processor model supported by LLVM. 1455*d415bd75Srobertdef : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, 1456*d415bd75Srobert [TuneAppleA16]>; 145709467b48Spatrick 1458097a140dSpatrick// Fujitsu A64FX 1459*d415bd75Srobertdef : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX, 1460*d415bd75Srobert [TuneA64FX]>; 1461097a140dSpatrick 1462097a140dSpatrick// Nvidia Carmel 1463*d415bd75Srobertdef : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel, 1464*d415bd75Srobert [TuneCarmel]>; 1465*d415bd75Srobert 1466*d415bd75Srobert// Ampere Computing 1467*d415bd75Srobertdef : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1, 1468*d415bd75Srobert [TuneAmpere1]>; 1469*d415bd75Srobert 1470*d415bd75Srobertdef : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A, 1471*d415bd75Srobert [TuneAmpere1A]>; 1472097a140dSpatrick 147309467b48Spatrick//===----------------------------------------------------------------------===// 147409467b48Spatrick// Assembly parser 147509467b48Spatrick//===----------------------------------------------------------------------===// 147609467b48Spatrick 147709467b48Spatrickdef GenericAsmParserVariant : AsmParserVariant { 147809467b48Spatrick int Variant = 0; 147909467b48Spatrick string Name = "generic"; 148009467b48Spatrick string BreakCharacters = "."; 148109467b48Spatrick string TokenizingCharacters = "[]*!/"; 148209467b48Spatrick} 148309467b48Spatrick 148409467b48Spatrickdef AppleAsmParserVariant : AsmParserVariant { 148509467b48Spatrick int Variant = 1; 148609467b48Spatrick string Name = "apple-neon"; 148709467b48Spatrick string BreakCharacters = "."; 148809467b48Spatrick string TokenizingCharacters = "[]*!/"; 148909467b48Spatrick} 149009467b48Spatrick 149109467b48Spatrick//===----------------------------------------------------------------------===// 149209467b48Spatrick// Assembly printer 149309467b48Spatrick//===----------------------------------------------------------------------===// 149409467b48Spatrick// AArch64 Uses the MC printer for asm output, so make sure the TableGen 149509467b48Spatrick// AsmWriter bits get associated with the correct class. 149609467b48Spatrickdef GenericAsmWriter : AsmWriter { 149709467b48Spatrick string AsmWriterClassName = "InstPrinter"; 149809467b48Spatrick int PassSubtarget = 1; 149909467b48Spatrick int Variant = 0; 150009467b48Spatrick bit isMCAsmWriter = 1; 150109467b48Spatrick} 150209467b48Spatrick 150309467b48Spatrickdef AppleAsmWriter : AsmWriter { 150409467b48Spatrick let AsmWriterClassName = "AppleInstPrinter"; 150509467b48Spatrick int PassSubtarget = 1; 150609467b48Spatrick int Variant = 1; 150709467b48Spatrick int isMCAsmWriter = 1; 150809467b48Spatrick} 150909467b48Spatrick 151009467b48Spatrick//===----------------------------------------------------------------------===// 151109467b48Spatrick// Target Declaration 151209467b48Spatrick//===----------------------------------------------------------------------===// 151309467b48Spatrick 151409467b48Spatrickdef AArch64 : Target { 151509467b48Spatrick let InstructionSet = AArch64InstrInfo; 151609467b48Spatrick let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 151709467b48Spatrick let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 151809467b48Spatrick let AllowRegisterRenaming = 1; 151909467b48Spatrick} 152009467b48Spatrick 152109467b48Spatrick//===----------------------------------------------------------------------===// 152209467b48Spatrick// Pfm Counters 152309467b48Spatrick//===----------------------------------------------------------------------===// 152409467b48Spatrick 152509467b48Spatrickinclude "AArch64PfmCounters.td" 1526