109467b48Spatrick //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
209467b48Spatrick //
309467b48Spatrick // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
409467b48Spatrick // See https://llvm.org/LICENSE.txt for license information.
509467b48Spatrick // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
609467b48Spatrick //
709467b48Spatrick //===----------------------------------------------------------------------===//
809467b48Spatrick //
909467b48Spatrick // This class prints an AArch64 MCInst to a .s file.
1009467b48Spatrick //
1109467b48Spatrick //===----------------------------------------------------------------------===//
1209467b48Spatrick
1309467b48Spatrick #include "AArch64InstPrinter.h"
1409467b48Spatrick #include "MCTargetDesc/AArch64AddressingModes.h"
1509467b48Spatrick #include "Utils/AArch64BaseInfo.h"
1609467b48Spatrick #include "llvm/ADT/STLExtras.h"
1709467b48Spatrick #include "llvm/ADT/StringExtras.h"
1809467b48Spatrick #include "llvm/ADT/StringRef.h"
1909467b48Spatrick #include "llvm/MC/MCAsmInfo.h"
2009467b48Spatrick #include "llvm/MC/MCExpr.h"
2109467b48Spatrick #include "llvm/MC/MCInst.h"
2209467b48Spatrick #include "llvm/MC/MCRegisterInfo.h"
2309467b48Spatrick #include "llvm/MC/MCSubtargetInfo.h"
2409467b48Spatrick #include "llvm/Support/Casting.h"
2509467b48Spatrick #include "llvm/Support/ErrorHandling.h"
2609467b48Spatrick #include "llvm/Support/Format.h"
2709467b48Spatrick #include "llvm/Support/MathExtras.h"
2809467b48Spatrick #include "llvm/Support/raw_ostream.h"
2909467b48Spatrick #include <cassert>
3009467b48Spatrick #include <cstdint>
3109467b48Spatrick #include <string>
3209467b48Spatrick
3309467b48Spatrick using namespace llvm;
3409467b48Spatrick
3509467b48Spatrick #define DEBUG_TYPE "asm-printer"
3609467b48Spatrick
3709467b48Spatrick #define GET_INSTRUCTION_NAME
3809467b48Spatrick #define PRINT_ALIAS_INSTR
3909467b48Spatrick #include "AArch64GenAsmWriter.inc"
4009467b48Spatrick #define GET_INSTRUCTION_NAME
4109467b48Spatrick #define PRINT_ALIAS_INSTR
4209467b48Spatrick #include "AArch64GenAsmWriter1.inc"
4309467b48Spatrick
AArch64InstPrinter(const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)4409467b48Spatrick AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
4509467b48Spatrick const MCInstrInfo &MII,
4609467b48Spatrick const MCRegisterInfo &MRI)
4709467b48Spatrick : MCInstPrinter(MAI, MII, MRI) {}
4809467b48Spatrick
AArch64AppleInstPrinter(const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)4909467b48Spatrick AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI,
5009467b48Spatrick const MCInstrInfo &MII,
5109467b48Spatrick const MCRegisterInfo &MRI)
5209467b48Spatrick : AArch64InstPrinter(MAI, MII, MRI) {}
5309467b48Spatrick
applyTargetSpecificCLOption(StringRef Opt)5473471bf0Spatrick bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
5573471bf0Spatrick if (Opt == "no-aliases") {
5673471bf0Spatrick PrintAliases = false;
5773471bf0Spatrick return true;
5873471bf0Spatrick }
5973471bf0Spatrick return false;
6073471bf0Spatrick }
6173471bf0Spatrick
printRegName(raw_ostream & OS,MCRegister Reg) const62*d415bd75Srobert void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
63*d415bd75Srobert OS << markup("<reg:") << getRegisterName(Reg) << markup(">");
64*d415bd75Srobert }
65*d415bd75Srobert
printRegName(raw_ostream & OS,MCRegister Reg,unsigned AltIdx) const66*d415bd75Srobert void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg,
67*d415bd75Srobert unsigned AltIdx) const {
68*d415bd75Srobert OS << markup("<reg:") << getRegisterName(Reg, AltIdx) << markup(">");
69*d415bd75Srobert }
70*d415bd75Srobert
getRegName(MCRegister Reg) const71*d415bd75Srobert StringRef AArch64InstPrinter::getRegName(MCRegister Reg) const {
72*d415bd75Srobert return getRegisterName(Reg);
7309467b48Spatrick }
7409467b48Spatrick
printInst(const MCInst * MI,uint64_t Address,StringRef Annot,const MCSubtargetInfo & STI,raw_ostream & O)7509467b48Spatrick void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
7609467b48Spatrick StringRef Annot, const MCSubtargetInfo &STI,
7709467b48Spatrick raw_ostream &O) {
7809467b48Spatrick // Check for special encodings and print the canonical alias instead.
7909467b48Spatrick
8009467b48Spatrick unsigned Opcode = MI->getOpcode();
8109467b48Spatrick
8209467b48Spatrick if (Opcode == AArch64::SYSxt)
8309467b48Spatrick if (printSysAlias(MI, STI, O)) {
8409467b48Spatrick printAnnotation(O, Annot);
8509467b48Spatrick return;
8609467b48Spatrick }
8709467b48Spatrick
88*d415bd75Srobert if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR)
89*d415bd75Srobert if (printSyspAlias(MI, STI, O)) {
90*d415bd75Srobert printAnnotation(O, Annot);
91*d415bd75Srobert return;
92*d415bd75Srobert }
93*d415bd75Srobert
94*d415bd75Srobert // RPRFM overlaps PRFM (reg), so try to print it as RPRFM here.
95*d415bd75Srobert if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) {
96*d415bd75Srobert if (printRangePrefetchAlias(MI, STI, O, Annot))
97*d415bd75Srobert return;
98*d415bd75Srobert }
99*d415bd75Srobert
10009467b48Spatrick // SBFM/UBFM should print to a nicer aliased form if possible.
10109467b48Spatrick if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
10209467b48Spatrick Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
10309467b48Spatrick const MCOperand &Op0 = MI->getOperand(0);
10409467b48Spatrick const MCOperand &Op1 = MI->getOperand(1);
10509467b48Spatrick const MCOperand &Op2 = MI->getOperand(2);
10609467b48Spatrick const MCOperand &Op3 = MI->getOperand(3);
10709467b48Spatrick
10809467b48Spatrick bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
10909467b48Spatrick bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
11009467b48Spatrick if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
11109467b48Spatrick const char *AsmMnemonic = nullptr;
11209467b48Spatrick
11309467b48Spatrick switch (Op3.getImm()) {
11409467b48Spatrick default:
11509467b48Spatrick break;
11609467b48Spatrick case 7:
11709467b48Spatrick if (IsSigned)
11809467b48Spatrick AsmMnemonic = "sxtb";
11909467b48Spatrick else if (!Is64Bit)
12009467b48Spatrick AsmMnemonic = "uxtb";
12109467b48Spatrick break;
12209467b48Spatrick case 15:
12309467b48Spatrick if (IsSigned)
12409467b48Spatrick AsmMnemonic = "sxth";
12509467b48Spatrick else if (!Is64Bit)
12609467b48Spatrick AsmMnemonic = "uxth";
12709467b48Spatrick break;
12809467b48Spatrick case 31:
12909467b48Spatrick // *xtw is only valid for signed 64-bit operations.
13009467b48Spatrick if (Is64Bit && IsSigned)
13109467b48Spatrick AsmMnemonic = "sxtw";
13209467b48Spatrick break;
13309467b48Spatrick }
13409467b48Spatrick
13509467b48Spatrick if (AsmMnemonic) {
136*d415bd75Srobert O << '\t' << AsmMnemonic << '\t';
137*d415bd75Srobert printRegName(O, Op0.getReg());
138*d415bd75Srobert O << ", ";
139*d415bd75Srobert printRegName(O, getWRegFromXReg(Op1.getReg()));
14009467b48Spatrick printAnnotation(O, Annot);
14109467b48Spatrick return;
14209467b48Spatrick }
14309467b48Spatrick }
14409467b48Spatrick
14509467b48Spatrick // All immediate shifts are aliases, implemented using the Bitfield
14609467b48Spatrick // instruction. In all cases the immediate shift amount shift must be in
14709467b48Spatrick // the range 0 to (reg.size -1).
14809467b48Spatrick if (Op2.isImm() && Op3.isImm()) {
14909467b48Spatrick const char *AsmMnemonic = nullptr;
15009467b48Spatrick int shift = 0;
15109467b48Spatrick int64_t immr = Op2.getImm();
15209467b48Spatrick int64_t imms = Op3.getImm();
15309467b48Spatrick if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
15409467b48Spatrick AsmMnemonic = "lsl";
15509467b48Spatrick shift = 31 - imms;
15609467b48Spatrick } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
15709467b48Spatrick ((imms + 1 == immr))) {
15809467b48Spatrick AsmMnemonic = "lsl";
15909467b48Spatrick shift = 63 - imms;
16009467b48Spatrick } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
16109467b48Spatrick AsmMnemonic = "lsr";
16209467b48Spatrick shift = immr;
16309467b48Spatrick } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
16409467b48Spatrick AsmMnemonic = "lsr";
16509467b48Spatrick shift = immr;
16609467b48Spatrick } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
16709467b48Spatrick AsmMnemonic = "asr";
16809467b48Spatrick shift = immr;
16909467b48Spatrick } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
17009467b48Spatrick AsmMnemonic = "asr";
17109467b48Spatrick shift = immr;
17209467b48Spatrick }
17309467b48Spatrick if (AsmMnemonic) {
174*d415bd75Srobert O << '\t' << AsmMnemonic << '\t';
175*d415bd75Srobert printRegName(O, Op0.getReg());
176*d415bd75Srobert O << ", ";
177*d415bd75Srobert printRegName(O, Op1.getReg());
178*d415bd75Srobert O << ", " << markup("<imm:") << "#" << shift << markup(">");
17909467b48Spatrick printAnnotation(O, Annot);
18009467b48Spatrick return;
18109467b48Spatrick }
18209467b48Spatrick }
18309467b48Spatrick
18409467b48Spatrick // SBFIZ/UBFIZ aliases
18509467b48Spatrick if (Op2.getImm() > Op3.getImm()) {
186*d415bd75Srobert O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t';
187*d415bd75Srobert printRegName(O, Op0.getReg());
188*d415bd75Srobert O << ", ";
189*d415bd75Srobert printRegName(O, Op1.getReg());
190*d415bd75Srobert O << ", " << markup("<imm:") << "#" << (Is64Bit ? 64 : 32) - Op2.getImm()
191*d415bd75Srobert << markup(">") << ", " << markup("<imm:") << "#" << Op3.getImm() + 1
192*d415bd75Srobert << markup(">");
19309467b48Spatrick printAnnotation(O, Annot);
19409467b48Spatrick return;
19509467b48Spatrick }
19609467b48Spatrick
19709467b48Spatrick // Otherwise SBFX/UBFX is the preferred form
198*d415bd75Srobert O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t';
199*d415bd75Srobert printRegName(O, Op0.getReg());
200*d415bd75Srobert O << ", ";
201*d415bd75Srobert printRegName(O, Op1.getReg());
202*d415bd75Srobert O << ", " << markup("<imm:") << "#" << Op2.getImm() << markup(">") << ", "
203*d415bd75Srobert << markup("<imm:") << "#" << Op3.getImm() - Op2.getImm() + 1
204*d415bd75Srobert << markup(">");
20509467b48Spatrick printAnnotation(O, Annot);
20609467b48Spatrick return;
20709467b48Spatrick }
20809467b48Spatrick
20909467b48Spatrick if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
21009467b48Spatrick const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
21109467b48Spatrick const MCOperand &Op2 = MI->getOperand(2);
21209467b48Spatrick int ImmR = MI->getOperand(3).getImm();
21309467b48Spatrick int ImmS = MI->getOperand(4).getImm();
21409467b48Spatrick
21509467b48Spatrick if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
21609467b48Spatrick (ImmR == 0 || ImmS < ImmR) &&
21709467b48Spatrick STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
21809467b48Spatrick // BFC takes precedence over its entire range, sligtly differently to BFI.
21909467b48Spatrick int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
22009467b48Spatrick int LSB = (BitWidth - ImmR) % BitWidth;
22109467b48Spatrick int Width = ImmS + 1;
22209467b48Spatrick
223*d415bd75Srobert O << "\tbfc\t";
224*d415bd75Srobert printRegName(O, Op0.getReg());
225*d415bd75Srobert O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
226*d415bd75Srobert << markup("<imm:") << "#" << Width << markup(">");
22709467b48Spatrick printAnnotation(O, Annot);
22809467b48Spatrick return;
22909467b48Spatrick } else if (ImmS < ImmR) {
23009467b48Spatrick // BFI alias
23109467b48Spatrick int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
23209467b48Spatrick int LSB = (BitWidth - ImmR) % BitWidth;
23309467b48Spatrick int Width = ImmS + 1;
23409467b48Spatrick
235*d415bd75Srobert O << "\tbfi\t";
236*d415bd75Srobert printRegName(O, Op0.getReg());
237*d415bd75Srobert O << ", ";
238*d415bd75Srobert printRegName(O, Op2.getReg());
239*d415bd75Srobert O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
240*d415bd75Srobert << markup("<imm:") << "#" << Width << markup(">");
24109467b48Spatrick printAnnotation(O, Annot);
24209467b48Spatrick return;
24309467b48Spatrick }
24409467b48Spatrick
24509467b48Spatrick int LSB = ImmR;
24609467b48Spatrick int Width = ImmS - ImmR + 1;
24709467b48Spatrick // Otherwise BFXIL the preferred form
248*d415bd75Srobert O << "\tbfxil\t";
249*d415bd75Srobert printRegName(O, Op0.getReg());
250*d415bd75Srobert O << ", ";
251*d415bd75Srobert printRegName(O, Op2.getReg());
252*d415bd75Srobert O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
253*d415bd75Srobert << markup("<imm:") << "#" << Width << markup(">");
25409467b48Spatrick printAnnotation(O, Annot);
25509467b48Spatrick return;
25609467b48Spatrick }
25709467b48Spatrick
25809467b48Spatrick // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
25909467b48Spatrick // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
26009467b48Spatrick // printed.
26109467b48Spatrick if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
26209467b48Spatrick Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
26309467b48Spatrick MI->getOperand(1).isExpr()) {
26409467b48Spatrick if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
26509467b48Spatrick O << "\tmovz\t";
26609467b48Spatrick else
26709467b48Spatrick O << "\tmovn\t";
26809467b48Spatrick
269*d415bd75Srobert printRegName(O, MI->getOperand(0).getReg());
270*d415bd75Srobert O << ", " << markup("<imm:") << "#";
27109467b48Spatrick MI->getOperand(1).getExpr()->print(O, &MAI);
272*d415bd75Srobert O << markup(">");
27309467b48Spatrick return;
27409467b48Spatrick }
27509467b48Spatrick
27609467b48Spatrick if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
27709467b48Spatrick MI->getOperand(2).isExpr()) {
278*d415bd75Srobert O << "\tmovk\t";
279*d415bd75Srobert printRegName(O, MI->getOperand(0).getReg());
280*d415bd75Srobert O << ", " << markup("<imm:") << "#";
28109467b48Spatrick MI->getOperand(2).getExpr()->print(O, &MAI);
282*d415bd75Srobert O << markup(">");
28309467b48Spatrick return;
28409467b48Spatrick }
28509467b48Spatrick
28609467b48Spatrick // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
28709467b48Spatrick // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
28809467b48Spatrick // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
28909467b48Spatrick // that can represent the move is the MOV alias, and the rest get printed
29009467b48Spatrick // normally.
29109467b48Spatrick if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
29209467b48Spatrick MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
29309467b48Spatrick int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
29409467b48Spatrick int Shift = MI->getOperand(2).getImm();
29509467b48Spatrick uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
29609467b48Spatrick
29709467b48Spatrick if (AArch64_AM::isMOVZMovAlias(Value, Shift,
29809467b48Spatrick Opcode == AArch64::MOVZXi ? 64 : 32)) {
299*d415bd75Srobert O << "\tmov\t";
300*d415bd75Srobert printRegName(O, MI->getOperand(0).getReg());
301*d415bd75Srobert O << ", " << markup("<imm:") << "#"
302*d415bd75Srobert << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
30309467b48Spatrick return;
30409467b48Spatrick }
30509467b48Spatrick }
30609467b48Spatrick
30709467b48Spatrick if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
30809467b48Spatrick MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
30909467b48Spatrick int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
31009467b48Spatrick int Shift = MI->getOperand(2).getImm();
31109467b48Spatrick uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
31209467b48Spatrick if (RegWidth == 32)
31309467b48Spatrick Value = Value & 0xffffffff;
31409467b48Spatrick
31509467b48Spatrick if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
316*d415bd75Srobert O << "\tmov\t";
317*d415bd75Srobert printRegName(O, MI->getOperand(0).getReg());
318*d415bd75Srobert O << ", " << markup("<imm:") << "#"
319*d415bd75Srobert << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
32009467b48Spatrick return;
32109467b48Spatrick }
32209467b48Spatrick }
32309467b48Spatrick
32409467b48Spatrick if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
32509467b48Spatrick (MI->getOperand(1).getReg() == AArch64::XZR ||
32609467b48Spatrick MI->getOperand(1).getReg() == AArch64::WZR) &&
32709467b48Spatrick MI->getOperand(2).isImm()) {
32809467b48Spatrick int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
32909467b48Spatrick uint64_t Value = AArch64_AM::decodeLogicalImmediate(
33009467b48Spatrick MI->getOperand(2).getImm(), RegWidth);
33109467b48Spatrick if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
332*d415bd75Srobert O << "\tmov\t";
333*d415bd75Srobert printRegName(O, MI->getOperand(0).getReg());
334*d415bd75Srobert O << ", " << markup("<imm:") << "#"
335*d415bd75Srobert << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
33609467b48Spatrick return;
33709467b48Spatrick }
33809467b48Spatrick }
33909467b48Spatrick
34009467b48Spatrick if (Opcode == AArch64::SPACE) {
341097a140dSpatrick O << '\t' << MAI.getCommentString() << " SPACE "
342097a140dSpatrick << MI->getOperand(1).getImm();
34309467b48Spatrick printAnnotation(O, Annot);
34409467b48Spatrick return;
34509467b48Spatrick }
34609467b48Spatrick
34709467b48Spatrick // Instruction TSB is specified as a one operand instruction, but 'csync' is
34809467b48Spatrick // not encoded, so for printing it is treated as a special case here:
34909467b48Spatrick if (Opcode == AArch64::TSB) {
35009467b48Spatrick O << "\ttsb\tcsync";
35109467b48Spatrick return;
35209467b48Spatrick }
35309467b48Spatrick
35473471bf0Spatrick if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
35509467b48Spatrick printInstruction(MI, Address, STI, O);
35609467b48Spatrick
35709467b48Spatrick printAnnotation(O, Annot);
35809467b48Spatrick
35909467b48Spatrick if (atomicBarrierDroppedOnZero(Opcode) &&
36009467b48Spatrick (MI->getOperand(0).getReg() == AArch64::XZR ||
36109467b48Spatrick MI->getOperand(0).getReg() == AArch64::WZR)) {
36209467b48Spatrick printAnnotation(O, "acquire semantics dropped since destination is zero");
36309467b48Spatrick }
36409467b48Spatrick }
36509467b48Spatrick
isTblTbxInstruction(unsigned Opcode,StringRef & Layout,bool & IsTbx)36609467b48Spatrick static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
36709467b48Spatrick bool &IsTbx) {
36809467b48Spatrick switch (Opcode) {
36909467b48Spatrick case AArch64::TBXv8i8One:
37009467b48Spatrick case AArch64::TBXv8i8Two:
37109467b48Spatrick case AArch64::TBXv8i8Three:
37209467b48Spatrick case AArch64::TBXv8i8Four:
37309467b48Spatrick IsTbx = true;
37409467b48Spatrick Layout = ".8b";
37509467b48Spatrick return true;
37609467b48Spatrick case AArch64::TBLv8i8One:
37709467b48Spatrick case AArch64::TBLv8i8Two:
37809467b48Spatrick case AArch64::TBLv8i8Three:
37909467b48Spatrick case AArch64::TBLv8i8Four:
38009467b48Spatrick IsTbx = false;
38109467b48Spatrick Layout = ".8b";
38209467b48Spatrick return true;
38309467b48Spatrick case AArch64::TBXv16i8One:
38409467b48Spatrick case AArch64::TBXv16i8Two:
38509467b48Spatrick case AArch64::TBXv16i8Three:
38609467b48Spatrick case AArch64::TBXv16i8Four:
38709467b48Spatrick IsTbx = true;
38809467b48Spatrick Layout = ".16b";
38909467b48Spatrick return true;
39009467b48Spatrick case AArch64::TBLv16i8One:
39109467b48Spatrick case AArch64::TBLv16i8Two:
39209467b48Spatrick case AArch64::TBLv16i8Three:
39309467b48Spatrick case AArch64::TBLv16i8Four:
39409467b48Spatrick IsTbx = false;
39509467b48Spatrick Layout = ".16b";
39609467b48Spatrick return true;
39709467b48Spatrick default:
39809467b48Spatrick return false;
39909467b48Spatrick }
40009467b48Spatrick }
40109467b48Spatrick
40209467b48Spatrick struct LdStNInstrDesc {
40309467b48Spatrick unsigned Opcode;
40409467b48Spatrick const char *Mnemonic;
40509467b48Spatrick const char *Layout;
40609467b48Spatrick int ListOperand;
40709467b48Spatrick bool HasLane;
40809467b48Spatrick int NaturalOffset;
40909467b48Spatrick };
41009467b48Spatrick
41109467b48Spatrick static const LdStNInstrDesc LdStNInstInfo[] = {
41209467b48Spatrick { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
41309467b48Spatrick { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
41409467b48Spatrick { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
41509467b48Spatrick { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
41609467b48Spatrick { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
41709467b48Spatrick { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
41809467b48Spatrick { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
41909467b48Spatrick { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
42009467b48Spatrick { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
42109467b48Spatrick { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
42209467b48Spatrick { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
42309467b48Spatrick { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
42409467b48Spatrick { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
42509467b48Spatrick { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
42609467b48Spatrick { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
42709467b48Spatrick { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
42809467b48Spatrick { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
42909467b48Spatrick { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
43009467b48Spatrick { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
43109467b48Spatrick { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
43209467b48Spatrick { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
43309467b48Spatrick { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
43409467b48Spatrick { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
43509467b48Spatrick { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
43609467b48Spatrick { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
43709467b48Spatrick { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
43809467b48Spatrick { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
43909467b48Spatrick { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
44009467b48Spatrick { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
44109467b48Spatrick { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
44209467b48Spatrick { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
44309467b48Spatrick { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
44409467b48Spatrick { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
44509467b48Spatrick { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
44609467b48Spatrick { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
44709467b48Spatrick { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
44809467b48Spatrick { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
44909467b48Spatrick { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
45009467b48Spatrick { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
45109467b48Spatrick { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
45209467b48Spatrick { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
45309467b48Spatrick { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
45409467b48Spatrick { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
45509467b48Spatrick { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
45609467b48Spatrick { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
45709467b48Spatrick { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
45809467b48Spatrick { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
45909467b48Spatrick { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
46009467b48Spatrick { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
46109467b48Spatrick { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
46209467b48Spatrick { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
46309467b48Spatrick { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
46409467b48Spatrick { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
46509467b48Spatrick { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
46609467b48Spatrick { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
46709467b48Spatrick { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
46809467b48Spatrick { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
46909467b48Spatrick { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
47009467b48Spatrick { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
47109467b48Spatrick { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
47209467b48Spatrick { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
47309467b48Spatrick { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
47409467b48Spatrick { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
47509467b48Spatrick { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
47609467b48Spatrick { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
47709467b48Spatrick { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
47809467b48Spatrick { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
47909467b48Spatrick { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
48009467b48Spatrick { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
48109467b48Spatrick { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
48209467b48Spatrick { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
48309467b48Spatrick { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
48409467b48Spatrick { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
48509467b48Spatrick { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
48609467b48Spatrick { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
48709467b48Spatrick { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
48809467b48Spatrick { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
48909467b48Spatrick { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
49009467b48Spatrick { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
49109467b48Spatrick { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
49209467b48Spatrick { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
49309467b48Spatrick { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
49409467b48Spatrick { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
49509467b48Spatrick { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
49609467b48Spatrick { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
49709467b48Spatrick { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
49809467b48Spatrick { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
49909467b48Spatrick { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
50009467b48Spatrick { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
50109467b48Spatrick { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
50209467b48Spatrick { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
50309467b48Spatrick { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
50409467b48Spatrick { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
50509467b48Spatrick { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
50609467b48Spatrick { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
50709467b48Spatrick { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
50809467b48Spatrick { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
50909467b48Spatrick { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
51009467b48Spatrick { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
51109467b48Spatrick { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
51209467b48Spatrick { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
51309467b48Spatrick { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
51409467b48Spatrick { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
51509467b48Spatrick { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
51609467b48Spatrick { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
51709467b48Spatrick { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
51809467b48Spatrick { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
51909467b48Spatrick { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
52009467b48Spatrick { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
52109467b48Spatrick { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
52209467b48Spatrick { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
52309467b48Spatrick { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
52409467b48Spatrick { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
52509467b48Spatrick { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
52609467b48Spatrick { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
52709467b48Spatrick { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
52809467b48Spatrick { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
52909467b48Spatrick { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
53009467b48Spatrick { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
53109467b48Spatrick { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
53209467b48Spatrick { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
53309467b48Spatrick { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
53409467b48Spatrick { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
53509467b48Spatrick { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
53609467b48Spatrick { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
53709467b48Spatrick { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
53809467b48Spatrick { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
53909467b48Spatrick { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
54009467b48Spatrick { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
54109467b48Spatrick { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
54209467b48Spatrick { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
54309467b48Spatrick { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
54409467b48Spatrick { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
54509467b48Spatrick { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
54609467b48Spatrick { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
54709467b48Spatrick { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
54809467b48Spatrick { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
54909467b48Spatrick { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
55009467b48Spatrick { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
55109467b48Spatrick { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
55209467b48Spatrick { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
55309467b48Spatrick { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
55409467b48Spatrick { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
55509467b48Spatrick { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
55609467b48Spatrick { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
55709467b48Spatrick { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
55809467b48Spatrick { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
55909467b48Spatrick { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
56009467b48Spatrick { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
56109467b48Spatrick { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
56209467b48Spatrick { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
56309467b48Spatrick { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
56409467b48Spatrick { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
56509467b48Spatrick { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
56609467b48Spatrick { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
56709467b48Spatrick { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
56809467b48Spatrick { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
56909467b48Spatrick { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
57009467b48Spatrick { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
57109467b48Spatrick { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
57209467b48Spatrick { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
57309467b48Spatrick { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
57409467b48Spatrick { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
57509467b48Spatrick { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
57609467b48Spatrick { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
57709467b48Spatrick { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
57809467b48Spatrick { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
57909467b48Spatrick { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
58009467b48Spatrick { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
58109467b48Spatrick { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
58209467b48Spatrick { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
58309467b48Spatrick { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
58409467b48Spatrick { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
58509467b48Spatrick { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
58609467b48Spatrick { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
58709467b48Spatrick { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
58809467b48Spatrick { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
58909467b48Spatrick { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
59009467b48Spatrick { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
59109467b48Spatrick { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
59209467b48Spatrick { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
59309467b48Spatrick { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
59409467b48Spatrick { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
59509467b48Spatrick { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
59609467b48Spatrick { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
59709467b48Spatrick { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
59809467b48Spatrick { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
59909467b48Spatrick { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
60009467b48Spatrick { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
60109467b48Spatrick { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
60209467b48Spatrick { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
60309467b48Spatrick { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
60409467b48Spatrick { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
60509467b48Spatrick { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
60609467b48Spatrick { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
60709467b48Spatrick { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
60809467b48Spatrick { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
60909467b48Spatrick { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
61009467b48Spatrick { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
61109467b48Spatrick { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
61209467b48Spatrick { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
61309467b48Spatrick { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
61409467b48Spatrick { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
61509467b48Spatrick { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
61609467b48Spatrick { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
61709467b48Spatrick { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
61809467b48Spatrick { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
61909467b48Spatrick { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
62009467b48Spatrick { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
62109467b48Spatrick { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
62209467b48Spatrick { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
62309467b48Spatrick { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
62409467b48Spatrick { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
62509467b48Spatrick { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
62609467b48Spatrick { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
62709467b48Spatrick { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
62809467b48Spatrick { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
62909467b48Spatrick { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
63009467b48Spatrick { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
63109467b48Spatrick { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
63209467b48Spatrick { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
63309467b48Spatrick { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
63409467b48Spatrick { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
63509467b48Spatrick { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
63609467b48Spatrick { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
63709467b48Spatrick { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
63809467b48Spatrick { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
63909467b48Spatrick { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
64009467b48Spatrick { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
64109467b48Spatrick { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
64209467b48Spatrick { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
64309467b48Spatrick { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
64409467b48Spatrick { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
64509467b48Spatrick { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
64609467b48Spatrick { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
64709467b48Spatrick { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
64809467b48Spatrick { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
64909467b48Spatrick { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
65009467b48Spatrick { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
65109467b48Spatrick { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
65209467b48Spatrick { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
65309467b48Spatrick { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
65409467b48Spatrick { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
65509467b48Spatrick { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
65609467b48Spatrick { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
65709467b48Spatrick { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
65809467b48Spatrick { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
65909467b48Spatrick { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
66009467b48Spatrick { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
66109467b48Spatrick { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
66209467b48Spatrick { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
66309467b48Spatrick { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
66409467b48Spatrick { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
66509467b48Spatrick { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
66609467b48Spatrick { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
66709467b48Spatrick { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
66809467b48Spatrick { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
66909467b48Spatrick { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
67009467b48Spatrick { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
67109467b48Spatrick { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
67209467b48Spatrick { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
67309467b48Spatrick { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
67409467b48Spatrick { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
67509467b48Spatrick { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
67609467b48Spatrick { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
67709467b48Spatrick { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
67809467b48Spatrick { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
67909467b48Spatrick { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
68009467b48Spatrick { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
68109467b48Spatrick { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
68209467b48Spatrick { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
68309467b48Spatrick { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
68409467b48Spatrick { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
68509467b48Spatrick { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
68609467b48Spatrick { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
68709467b48Spatrick { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
68809467b48Spatrick { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
68909467b48Spatrick { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
69009467b48Spatrick { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
69109467b48Spatrick { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
69209467b48Spatrick { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
69309467b48Spatrick { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
69409467b48Spatrick { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
69509467b48Spatrick { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
69609467b48Spatrick { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
69709467b48Spatrick { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
69809467b48Spatrick { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
69909467b48Spatrick { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
70009467b48Spatrick { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
70109467b48Spatrick { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
70209467b48Spatrick { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
70309467b48Spatrick { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
70409467b48Spatrick { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
70509467b48Spatrick { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
70609467b48Spatrick { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
70709467b48Spatrick { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
70809467b48Spatrick { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
70909467b48Spatrick { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
71009467b48Spatrick { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
71109467b48Spatrick { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
71209467b48Spatrick { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
71309467b48Spatrick { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
71409467b48Spatrick { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
71509467b48Spatrick { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
71609467b48Spatrick { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
71709467b48Spatrick { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
71809467b48Spatrick { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
71909467b48Spatrick { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
72009467b48Spatrick { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
72109467b48Spatrick { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
72209467b48Spatrick { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
72309467b48Spatrick { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
72409467b48Spatrick { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
72509467b48Spatrick { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
72609467b48Spatrick { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
72709467b48Spatrick { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
72809467b48Spatrick { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
72909467b48Spatrick { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
73009467b48Spatrick { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
73109467b48Spatrick { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
73209467b48Spatrick { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
73309467b48Spatrick { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
73409467b48Spatrick { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
73509467b48Spatrick { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
73609467b48Spatrick { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
73709467b48Spatrick { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
73809467b48Spatrick { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
73909467b48Spatrick { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
74009467b48Spatrick { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
74109467b48Spatrick { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
74209467b48Spatrick { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
74309467b48Spatrick { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
74409467b48Spatrick { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
74509467b48Spatrick { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
74609467b48Spatrick { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
74709467b48Spatrick { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
74809467b48Spatrick { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
74909467b48Spatrick { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
75009467b48Spatrick { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
75109467b48Spatrick { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
75209467b48Spatrick };
75309467b48Spatrick
getLdStNInstrDesc(unsigned Opcode)75409467b48Spatrick static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
755*d415bd75Srobert for (const auto &Info : LdStNInstInfo)
756*d415bd75Srobert if (Info.Opcode == Opcode)
757*d415bd75Srobert return &Info;
75809467b48Spatrick
75909467b48Spatrick return nullptr;
76009467b48Spatrick }
76109467b48Spatrick
printInst(const MCInst * MI,uint64_t Address,StringRef Annot,const MCSubtargetInfo & STI,raw_ostream & O)76209467b48Spatrick void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
76309467b48Spatrick StringRef Annot,
76409467b48Spatrick const MCSubtargetInfo &STI,
76509467b48Spatrick raw_ostream &O) {
76609467b48Spatrick unsigned Opcode = MI->getOpcode();
76709467b48Spatrick StringRef Layout;
76809467b48Spatrick
76909467b48Spatrick bool IsTbx;
77009467b48Spatrick if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
771*d415bd75Srobert O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t';
772*d415bd75Srobert printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
773*d415bd75Srobert O << ", ";
77409467b48Spatrick
77509467b48Spatrick unsigned ListOpNum = IsTbx ? 2 : 1;
77609467b48Spatrick printVectorList(MI, ListOpNum, STI, O, "");
77709467b48Spatrick
778*d415bd75Srobert O << ", ";
779*d415bd75Srobert printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
78009467b48Spatrick printAnnotation(O, Annot);
78109467b48Spatrick return;
78209467b48Spatrick }
78309467b48Spatrick
78409467b48Spatrick if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
78509467b48Spatrick O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
78609467b48Spatrick
78709467b48Spatrick // Now onto the operands: first a vector list with possible lane
78809467b48Spatrick // specifier. E.g. { v0 }[2]
78909467b48Spatrick int OpNum = LdStDesc->ListOperand;
79009467b48Spatrick printVectorList(MI, OpNum++, STI, O, "");
79109467b48Spatrick
79209467b48Spatrick if (LdStDesc->HasLane)
79309467b48Spatrick O << '[' << MI->getOperand(OpNum++).getImm() << ']';
79409467b48Spatrick
79509467b48Spatrick // Next the address: [xN]
79609467b48Spatrick unsigned AddrReg = MI->getOperand(OpNum++).getReg();
797*d415bd75Srobert O << ", [";
798*d415bd75Srobert printRegName(O, AddrReg);
799*d415bd75Srobert O << ']';
80009467b48Spatrick
80109467b48Spatrick // Finally, there might be a post-indexed offset.
80209467b48Spatrick if (LdStDesc->NaturalOffset != 0) {
80309467b48Spatrick unsigned Reg = MI->getOperand(OpNum++).getReg();
804*d415bd75Srobert if (Reg != AArch64::XZR) {
805*d415bd75Srobert O << ", ";
806*d415bd75Srobert printRegName(O, Reg);
807*d415bd75Srobert } else {
80809467b48Spatrick assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
809*d415bd75Srobert O << ", " << markup("<imm:") << "#" << LdStDesc->NaturalOffset
810*d415bd75Srobert << markup(">");
81109467b48Spatrick }
81209467b48Spatrick }
81309467b48Spatrick
81409467b48Spatrick printAnnotation(O, Annot);
81509467b48Spatrick return;
81609467b48Spatrick }
81709467b48Spatrick
81809467b48Spatrick AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
81909467b48Spatrick }
82009467b48Spatrick
getRegName(MCRegister Reg) const821*d415bd75Srobert StringRef AArch64AppleInstPrinter::getRegName(MCRegister Reg) const {
822*d415bd75Srobert return getRegisterName(Reg);
823*d415bd75Srobert }
824*d415bd75Srobert
printRangePrefetchAlias(const MCInst * MI,const MCSubtargetInfo & STI,raw_ostream & O,StringRef Annot)825*d415bd75Srobert bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI,
826*d415bd75Srobert const MCSubtargetInfo &STI,
827*d415bd75Srobert raw_ostream &O,
828*d415bd75Srobert StringRef Annot) {
829*d415bd75Srobert unsigned Opcode = MI->getOpcode();
830*d415bd75Srobert
831*d415bd75Srobert #ifndef NDEBUG
832*d415bd75Srobert assert(((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) &&
833*d415bd75Srobert "Invalid opcode for RPRFM alias!");
834*d415bd75Srobert #endif
835*d415bd75Srobert
836*d415bd75Srobert unsigned PRFOp = MI->getOperand(0).getImm();
837*d415bd75Srobert unsigned Mask = 0x18; // 0b11000
838*d415bd75Srobert if ((PRFOp & Mask) != Mask)
839*d415bd75Srobert return false; // Rt != '11xxx', it's a PRFM instruction.
840*d415bd75Srobert
841*d415bd75Srobert unsigned Rm = MI->getOperand(2).getReg();
842*d415bd75Srobert
843*d415bd75Srobert // "Rm" must be a 64-bit GPR for RPRFM.
844*d415bd75Srobert if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm))
845*d415bd75Srobert Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32,
846*d415bd75Srobert &MRI.getRegClass(AArch64::GPR64RegClassID));
847*d415bd75Srobert
848*d415bd75Srobert unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>".
849*d415bd75Srobert unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S".
850*d415bd75Srobert
851*d415bd75Srobert assert((SignExtend <= 1) && "sign extend should be a single bit!");
852*d415bd75Srobert assert((Shift <= 1) && "Shift should be a single bit!");
853*d415bd75Srobert
854*d415bd75Srobert unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0;
855*d415bd75Srobert
856*d415bd75Srobert // encoded in "option<2>:option<0>:S:Rt<2:0>".
857*d415bd75Srobert unsigned RPRFOp =
858*d415bd75Srobert (SignExtend << 5) | (Option0 << 4) | (Shift << 3) | (PRFOp & 0x7);
859*d415bd75Srobert
860*d415bd75Srobert O << "\trprfm ";
861*d415bd75Srobert if (auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(RPRFOp))
862*d415bd75Srobert O << RPRFM->Name << ", ";
863*d415bd75Srobert else
864*d415bd75Srobert O << "#" << formatImm(RPRFOp) << ", ";
865*d415bd75Srobert O << getRegisterName(Rm);
866*d415bd75Srobert O << ", [";
867*d415bd75Srobert printOperand(MI, 1, STI, O); // "Rn".
868*d415bd75Srobert O << "]";
869*d415bd75Srobert
870*d415bd75Srobert printAnnotation(O, Annot);
871*d415bd75Srobert
872*d415bd75Srobert return true;
873*d415bd75Srobert }
874*d415bd75Srobert
printSysAlias(const MCInst * MI,const MCSubtargetInfo & STI,raw_ostream & O)87509467b48Spatrick bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
87609467b48Spatrick const MCSubtargetInfo &STI,
87709467b48Spatrick raw_ostream &O) {
87809467b48Spatrick #ifndef NDEBUG
87909467b48Spatrick unsigned Opcode = MI->getOpcode();
88009467b48Spatrick assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
88109467b48Spatrick #endif
88209467b48Spatrick
88309467b48Spatrick const MCOperand &Op1 = MI->getOperand(0);
88409467b48Spatrick const MCOperand &Cn = MI->getOperand(1);
88509467b48Spatrick const MCOperand &Cm = MI->getOperand(2);
88609467b48Spatrick const MCOperand &Op2 = MI->getOperand(3);
88709467b48Spatrick
88809467b48Spatrick unsigned Op1Val = Op1.getImm();
88909467b48Spatrick unsigned CnVal = Cn.getImm();
89009467b48Spatrick unsigned CmVal = Cm.getImm();
89109467b48Spatrick unsigned Op2Val = Op2.getImm();
89209467b48Spatrick
89309467b48Spatrick uint16_t Encoding = Op2Val;
89409467b48Spatrick Encoding |= CmVal << 3;
89509467b48Spatrick Encoding |= CnVal << 7;
89609467b48Spatrick Encoding |= Op1Val << 11;
89709467b48Spatrick
89809467b48Spatrick bool NeedsReg;
89909467b48Spatrick std::string Ins;
90009467b48Spatrick std::string Name;
90109467b48Spatrick
90209467b48Spatrick if (CnVal == 7) {
90309467b48Spatrick switch (CmVal) {
90409467b48Spatrick default: return false;
90509467b48Spatrick // Maybe IC, maybe Prediction Restriction
90609467b48Spatrick case 1:
90709467b48Spatrick switch (Op1Val) {
90809467b48Spatrick default: return false;
90909467b48Spatrick case 0: goto Search_IC;
91009467b48Spatrick case 3: goto Search_PRCTX;
91109467b48Spatrick }
91209467b48Spatrick // Prediction Restriction aliases
91309467b48Spatrick case 3: {
91409467b48Spatrick Search_PRCTX:
915*d415bd75Srobert if (Op1Val != 3 || CnVal != 7 || CmVal != 3)
91609467b48Spatrick return false;
91709467b48Spatrick
918*d415bd75Srobert const auto Requires =
919*d415bd75Srobert Op2Val == 6 ? AArch64::FeatureSPECRES2 : AArch64::FeaturePredRes;
920*d415bd75Srobert if (!(STI.hasFeature(AArch64::FeatureAll) || STI.hasFeature(Requires)))
921*d415bd75Srobert return false;
922*d415bd75Srobert
923*d415bd75Srobert NeedsReg = true;
92409467b48Spatrick switch (Op2Val) {
92509467b48Spatrick default: return false;
92609467b48Spatrick case 4: Ins = "cfp\t"; break;
92709467b48Spatrick case 5: Ins = "dvp\t"; break;
928*d415bd75Srobert case 6: Ins = "cosp\t"; break;
92909467b48Spatrick case 7: Ins = "cpp\t"; break;
93009467b48Spatrick }
931*d415bd75Srobert Name = "RCTX";
93209467b48Spatrick }
93309467b48Spatrick break;
93409467b48Spatrick // IC aliases
93509467b48Spatrick case 5: {
93609467b48Spatrick Search_IC:
93709467b48Spatrick const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
93809467b48Spatrick if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
93909467b48Spatrick return false;
94009467b48Spatrick
94109467b48Spatrick NeedsReg = IC->NeedsReg;
94209467b48Spatrick Ins = "ic\t";
94309467b48Spatrick Name = std::string(IC->Name);
94409467b48Spatrick }
94509467b48Spatrick break;
94609467b48Spatrick // DC aliases
94709467b48Spatrick case 4: case 6: case 10: case 11: case 12: case 13: case 14:
94809467b48Spatrick {
94909467b48Spatrick const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
95009467b48Spatrick if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
95109467b48Spatrick return false;
95209467b48Spatrick
95309467b48Spatrick NeedsReg = true;
95409467b48Spatrick Ins = "dc\t";
95509467b48Spatrick Name = std::string(DC->Name);
95609467b48Spatrick }
95709467b48Spatrick break;
95809467b48Spatrick // AT aliases
95909467b48Spatrick case 8: case 9: {
96009467b48Spatrick const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
96109467b48Spatrick if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
96209467b48Spatrick return false;
96309467b48Spatrick
96409467b48Spatrick NeedsReg = true;
96509467b48Spatrick Ins = "at\t";
96609467b48Spatrick Name = std::string(AT->Name);
96709467b48Spatrick }
96809467b48Spatrick break;
96909467b48Spatrick }
97073471bf0Spatrick } else if (CnVal == 8 || CnVal == 9) {
97109467b48Spatrick // TLBI aliases
97209467b48Spatrick const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
97309467b48Spatrick if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
97409467b48Spatrick return false;
97509467b48Spatrick
97609467b48Spatrick NeedsReg = TLBI->NeedsReg;
97709467b48Spatrick Ins = "tlbi\t";
97809467b48Spatrick Name = std::string(TLBI->Name);
97909467b48Spatrick }
98009467b48Spatrick else
98109467b48Spatrick return false;
98209467b48Spatrick
98309467b48Spatrick std::string Str = Ins + Name;
98409467b48Spatrick std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
98509467b48Spatrick
98609467b48Spatrick O << '\t' << Str;
987*d415bd75Srobert if (NeedsReg) {
988*d415bd75Srobert O << ", ";
989*d415bd75Srobert printRegName(O, MI->getOperand(4).getReg());
990*d415bd75Srobert }
991*d415bd75Srobert
992*d415bd75Srobert return true;
993*d415bd75Srobert }
994*d415bd75Srobert
printSyspAlias(const MCInst * MI,const MCSubtargetInfo & STI,raw_ostream & O)995*d415bd75Srobert bool AArch64InstPrinter::printSyspAlias(const MCInst *MI,
996*d415bd75Srobert const MCSubtargetInfo &STI,
997*d415bd75Srobert raw_ostream &O) {
998*d415bd75Srobert #ifndef NDEBUG
999*d415bd75Srobert unsigned Opcode = MI->getOpcode();
1000*d415bd75Srobert assert((Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) &&
1001*d415bd75Srobert "Invalid opcode for SYSP alias!");
1002*d415bd75Srobert #endif
1003*d415bd75Srobert
1004*d415bd75Srobert const MCOperand &Op1 = MI->getOperand(0);
1005*d415bd75Srobert const MCOperand &Cn = MI->getOperand(1);
1006*d415bd75Srobert const MCOperand &Cm = MI->getOperand(2);
1007*d415bd75Srobert const MCOperand &Op2 = MI->getOperand(3);
1008*d415bd75Srobert
1009*d415bd75Srobert unsigned Op1Val = Op1.getImm();
1010*d415bd75Srobert unsigned CnVal = Cn.getImm();
1011*d415bd75Srobert unsigned CmVal = Cm.getImm();
1012*d415bd75Srobert unsigned Op2Val = Op2.getImm();
1013*d415bd75Srobert
1014*d415bd75Srobert uint16_t Encoding = Op2Val;
1015*d415bd75Srobert Encoding |= CmVal << 3;
1016*d415bd75Srobert Encoding |= CnVal << 7;
1017*d415bd75Srobert Encoding |= Op1Val << 11;
1018*d415bd75Srobert
1019*d415bd75Srobert std::string Ins;
1020*d415bd75Srobert std::string Name;
1021*d415bd75Srobert
1022*d415bd75Srobert if (CnVal == 8 || CnVal == 9) {
1023*d415bd75Srobert // TLBIP aliases
1024*d415bd75Srobert
1025*d415bd75Srobert if (CnVal == 9) {
1026*d415bd75Srobert if (!STI.hasFeature(AArch64::FeatureXS))
1027*d415bd75Srobert return false;
1028*d415bd75Srobert Encoding &= ~(1 << 7);
1029*d415bd75Srobert }
1030*d415bd75Srobert
1031*d415bd75Srobert const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
1032*d415bd75Srobert if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
1033*d415bd75Srobert return false;
1034*d415bd75Srobert
1035*d415bd75Srobert Ins = "tlbip\t";
1036*d415bd75Srobert Name = std::string(TLBI->Name);
1037*d415bd75Srobert if (CnVal == 9)
1038*d415bd75Srobert Name += "nXS";
1039*d415bd75Srobert } else
1040*d415bd75Srobert return false;
1041*d415bd75Srobert
1042*d415bd75Srobert std::string Str = Ins + Name;
1043*d415bd75Srobert std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
1044*d415bd75Srobert
1045*d415bd75Srobert O << '\t' << Str;
1046*d415bd75Srobert O << ", ";
1047*d415bd75Srobert if (MI->getOperand(4).getReg() == AArch64::XZR)
1048*d415bd75Srobert printSyspXzrPair(MI, 4, STI, O);
1049*d415bd75Srobert else
1050*d415bd75Srobert printGPRSeqPairsClassOperand<64>(MI, 4, STI, O);
105109467b48Spatrick
105209467b48Spatrick return true;
105309467b48Spatrick }
105409467b48Spatrick
105573471bf0Spatrick template <int EltSize>
printMatrix(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)105673471bf0Spatrick void AArch64InstPrinter::printMatrix(const MCInst *MI, unsigned OpNum,
105773471bf0Spatrick const MCSubtargetInfo &STI,
105873471bf0Spatrick raw_ostream &O) {
105973471bf0Spatrick const MCOperand &RegOp = MI->getOperand(OpNum);
106073471bf0Spatrick assert(RegOp.isReg() && "Unexpected operand type!");
106173471bf0Spatrick
1062*d415bd75Srobert printRegName(O, RegOp.getReg());
106373471bf0Spatrick switch (EltSize) {
106473471bf0Spatrick case 0:
106573471bf0Spatrick break;
106673471bf0Spatrick case 8:
106773471bf0Spatrick O << ".b";
106873471bf0Spatrick break;
106973471bf0Spatrick case 16:
107073471bf0Spatrick O << ".h";
107173471bf0Spatrick break;
107273471bf0Spatrick case 32:
107373471bf0Spatrick O << ".s";
107473471bf0Spatrick break;
107573471bf0Spatrick case 64:
107673471bf0Spatrick O << ".d";
107773471bf0Spatrick break;
107873471bf0Spatrick case 128:
107973471bf0Spatrick O << ".q";
108073471bf0Spatrick break;
108173471bf0Spatrick default:
108273471bf0Spatrick llvm_unreachable("Unsupported element size");
108373471bf0Spatrick }
108473471bf0Spatrick }
108573471bf0Spatrick
108673471bf0Spatrick template <bool IsVertical>
printMatrixTileVector(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)108773471bf0Spatrick void AArch64InstPrinter::printMatrixTileVector(const MCInst *MI, unsigned OpNum,
108873471bf0Spatrick const MCSubtargetInfo &STI,
108973471bf0Spatrick raw_ostream &O) {
109073471bf0Spatrick const MCOperand &RegOp = MI->getOperand(OpNum);
109173471bf0Spatrick assert(RegOp.isReg() && "Unexpected operand type!");
109273471bf0Spatrick StringRef RegName = getRegisterName(RegOp.getReg());
109373471bf0Spatrick
109473471bf0Spatrick // Insert the horizontal/vertical flag before the suffix.
109573471bf0Spatrick StringRef Base, Suffix;
109673471bf0Spatrick std::tie(Base, Suffix) = RegName.split('.');
109773471bf0Spatrick O << Base << (IsVertical ? "v" : "h") << '.' << Suffix;
109873471bf0Spatrick }
109973471bf0Spatrick
printMatrixTile(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)110073471bf0Spatrick void AArch64InstPrinter::printMatrixTile(const MCInst *MI, unsigned OpNum,
110173471bf0Spatrick const MCSubtargetInfo &STI,
110273471bf0Spatrick raw_ostream &O) {
110373471bf0Spatrick const MCOperand &RegOp = MI->getOperand(OpNum);
110473471bf0Spatrick assert(RegOp.isReg() && "Unexpected operand type!");
1105*d415bd75Srobert printRegName(O, RegOp.getReg());
110673471bf0Spatrick }
110773471bf0Spatrick
printSVCROp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)110873471bf0Spatrick void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum,
110973471bf0Spatrick const MCSubtargetInfo &STI,
111073471bf0Spatrick raw_ostream &O) {
111173471bf0Spatrick const MCOperand &MO = MI->getOperand(OpNum);
111273471bf0Spatrick assert(MO.isImm() && "Unexpected operand type!");
111373471bf0Spatrick unsigned svcrop = MO.getImm();
111473471bf0Spatrick const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
111573471bf0Spatrick assert(SVCR && "Unexpected SVCR operand!");
111673471bf0Spatrick O << SVCR->Name;
111773471bf0Spatrick }
111873471bf0Spatrick
printOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)111909467b48Spatrick void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
112009467b48Spatrick const MCSubtargetInfo &STI,
112109467b48Spatrick raw_ostream &O) {
112209467b48Spatrick const MCOperand &Op = MI->getOperand(OpNo);
112309467b48Spatrick if (Op.isReg()) {
112409467b48Spatrick unsigned Reg = Op.getReg();
1125*d415bd75Srobert printRegName(O, Reg);
112609467b48Spatrick } else if (Op.isImm()) {
112709467b48Spatrick printImm(MI, OpNo, STI, O);
112809467b48Spatrick } else {
112909467b48Spatrick assert(Op.isExpr() && "unknown operand kind in printOperand");
113009467b48Spatrick Op.getExpr()->print(O, &MAI);
113109467b48Spatrick }
113209467b48Spatrick }
113309467b48Spatrick
printImm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)113409467b48Spatrick void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
113509467b48Spatrick const MCSubtargetInfo &STI,
113609467b48Spatrick raw_ostream &O) {
113709467b48Spatrick const MCOperand &Op = MI->getOperand(OpNo);
1138*d415bd75Srobert O << markup("<imm:") << "#" << formatImm(Op.getImm()) << markup(">");
113909467b48Spatrick }
114009467b48Spatrick
printImmHex(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)114109467b48Spatrick void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
114209467b48Spatrick const MCSubtargetInfo &STI,
114309467b48Spatrick raw_ostream &O) {
114409467b48Spatrick const MCOperand &Op = MI->getOperand(OpNo);
1145*d415bd75Srobert O << markup("<imm:") << format("#%#llx", Op.getImm()) << markup(">");
114609467b48Spatrick }
114709467b48Spatrick
1148097a140dSpatrick template<int Size>
printSImm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)1149097a140dSpatrick void AArch64InstPrinter::printSImm(const MCInst *MI, unsigned OpNo,
1150097a140dSpatrick const MCSubtargetInfo &STI,
1151097a140dSpatrick raw_ostream &O) {
1152097a140dSpatrick const MCOperand &Op = MI->getOperand(OpNo);
1153097a140dSpatrick if (Size == 8)
1154*d415bd75Srobert O << markup("<imm:") << "#" << formatImm((signed char)Op.getImm())
1155*d415bd75Srobert << markup(">");
1156097a140dSpatrick else if (Size == 16)
1157*d415bd75Srobert O << markup("<imm:") << "#" << formatImm((signed short)Op.getImm())
1158*d415bd75Srobert << markup(">");
1159097a140dSpatrick else
1160*d415bd75Srobert O << markup("<imm:") << "#" << formatImm(Op.getImm()) << markup(">");
1161097a140dSpatrick }
1162097a140dSpatrick
printPostIncOperand(const MCInst * MI,unsigned OpNo,unsigned Imm,raw_ostream & O)116309467b48Spatrick void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
116409467b48Spatrick unsigned Imm, raw_ostream &O) {
116509467b48Spatrick const MCOperand &Op = MI->getOperand(OpNo);
116609467b48Spatrick if (Op.isReg()) {
116709467b48Spatrick unsigned Reg = Op.getReg();
116809467b48Spatrick if (Reg == AArch64::XZR)
1169*d415bd75Srobert O << markup("<imm:") << "#" << Imm << markup(">");
117009467b48Spatrick else
1171*d415bd75Srobert printRegName(O, Reg);
117209467b48Spatrick } else
117309467b48Spatrick llvm_unreachable("unknown operand kind in printPostIncOperand64");
117409467b48Spatrick }
117509467b48Spatrick
printVRegOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)117609467b48Spatrick void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
117709467b48Spatrick const MCSubtargetInfo &STI,
117809467b48Spatrick raw_ostream &O) {
117909467b48Spatrick const MCOperand &Op = MI->getOperand(OpNo);
118009467b48Spatrick assert(Op.isReg() && "Non-register vreg operand!");
118109467b48Spatrick unsigned Reg = Op.getReg();
1182*d415bd75Srobert printRegName(O, Reg, AArch64::vreg);
118309467b48Spatrick }
118409467b48Spatrick
printSysCROperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)118509467b48Spatrick void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
118609467b48Spatrick const MCSubtargetInfo &STI,
118709467b48Spatrick raw_ostream &O) {
118809467b48Spatrick const MCOperand &Op = MI->getOperand(OpNo);
118909467b48Spatrick assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
119009467b48Spatrick O << "c" << Op.getImm();
119109467b48Spatrick }
119209467b48Spatrick
printAddSubImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)119309467b48Spatrick void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
119409467b48Spatrick const MCSubtargetInfo &STI,
119509467b48Spatrick raw_ostream &O) {
119609467b48Spatrick const MCOperand &MO = MI->getOperand(OpNum);
119709467b48Spatrick if (MO.isImm()) {
119809467b48Spatrick unsigned Val = (MO.getImm() & 0xfff);
119909467b48Spatrick assert(Val == MO.getImm() && "Add/sub immediate out of range!");
120009467b48Spatrick unsigned Shift =
120109467b48Spatrick AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
1202*d415bd75Srobert O << markup("<imm:") << '#' << formatImm(Val) << markup(">");
1203*d415bd75Srobert if (Shift != 0) {
120409467b48Spatrick printShifter(MI, OpNum + 1, STI, O);
120509467b48Spatrick if (CommentStream)
120609467b48Spatrick *CommentStream << '=' << formatImm(Val << Shift) << '\n';
1207*d415bd75Srobert }
120809467b48Spatrick } else {
120909467b48Spatrick assert(MO.isExpr() && "Unexpected operand type!");
121009467b48Spatrick MO.getExpr()->print(O, &MAI);
121109467b48Spatrick printShifter(MI, OpNum + 1, STI, O);
121209467b48Spatrick }
121309467b48Spatrick }
121409467b48Spatrick
121509467b48Spatrick template <typename T>
printLogicalImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)121609467b48Spatrick void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
121709467b48Spatrick const MCSubtargetInfo &STI,
121809467b48Spatrick raw_ostream &O) {
121909467b48Spatrick uint64_t Val = MI->getOperand(OpNum).getImm();
1220*d415bd75Srobert O << markup("<imm:") << "#0x";
122109467b48Spatrick O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
1222*d415bd75Srobert O << markup(">");
122309467b48Spatrick }
122409467b48Spatrick
printShifter(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)122509467b48Spatrick void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
122609467b48Spatrick const MCSubtargetInfo &STI,
122709467b48Spatrick raw_ostream &O) {
122809467b48Spatrick unsigned Val = MI->getOperand(OpNum).getImm();
122909467b48Spatrick // LSL #0 should not be printed.
123009467b48Spatrick if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
123109467b48Spatrick AArch64_AM::getShiftValue(Val) == 0)
123209467b48Spatrick return;
123309467b48Spatrick O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
1234*d415bd75Srobert << " " << markup("<imm:") << "#" << AArch64_AM::getShiftValue(Val)
1235*d415bd75Srobert << markup(">");
123609467b48Spatrick }
123709467b48Spatrick
printShiftedRegister(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)123809467b48Spatrick void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
123909467b48Spatrick const MCSubtargetInfo &STI,
124009467b48Spatrick raw_ostream &O) {
1241*d415bd75Srobert printRegName(O, MI->getOperand(OpNum).getReg());
124209467b48Spatrick printShifter(MI, OpNum + 1, STI, O);
124309467b48Spatrick }
124409467b48Spatrick
printExtendedRegister(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)124509467b48Spatrick void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
124609467b48Spatrick const MCSubtargetInfo &STI,
124709467b48Spatrick raw_ostream &O) {
1248*d415bd75Srobert printRegName(O, MI->getOperand(OpNum).getReg());
124909467b48Spatrick printArithExtend(MI, OpNum + 1, STI, O);
125009467b48Spatrick }
125109467b48Spatrick
printArithExtend(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)125209467b48Spatrick void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
125309467b48Spatrick const MCSubtargetInfo &STI,
125409467b48Spatrick raw_ostream &O) {
125509467b48Spatrick unsigned Val = MI->getOperand(OpNum).getImm();
125609467b48Spatrick AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
125709467b48Spatrick unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
125809467b48Spatrick
125909467b48Spatrick // If the destination or first source register operand is [W]SP, print
126009467b48Spatrick // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
126109467b48Spatrick // all.
126209467b48Spatrick if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
126309467b48Spatrick unsigned Dest = MI->getOperand(0).getReg();
126409467b48Spatrick unsigned Src1 = MI->getOperand(1).getReg();
126509467b48Spatrick if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
126609467b48Spatrick ExtType == AArch64_AM::UXTX) ||
126709467b48Spatrick ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
126809467b48Spatrick ExtType == AArch64_AM::UXTW) ) {
126909467b48Spatrick if (ShiftVal != 0)
1270*d415bd75Srobert O << ", lsl " << markup("<imm:") << "#" << ShiftVal << markup(">");
127109467b48Spatrick return;
127209467b48Spatrick }
127309467b48Spatrick }
127409467b48Spatrick O << ", " << AArch64_AM::getShiftExtendName(ExtType);
127509467b48Spatrick if (ShiftVal != 0)
1276*d415bd75Srobert O << " " << markup("<imm:") << "#" << ShiftVal << markup(">");
127709467b48Spatrick }
127809467b48Spatrick
printMemExtendImpl(bool SignExtend,bool DoShift,unsigned Width,char SrcRegKind,raw_ostream & O,bool UseMarkup)1279*d415bd75Srobert static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width,
1280*d415bd75Srobert char SrcRegKind, raw_ostream &O,
1281*d415bd75Srobert bool UseMarkup) {
128209467b48Spatrick // sxtw, sxtx, uxtw or lsl (== uxtx)
128309467b48Spatrick bool IsLSL = !SignExtend && SrcRegKind == 'x';
128409467b48Spatrick if (IsLSL)
128509467b48Spatrick O << "lsl";
128609467b48Spatrick else
128709467b48Spatrick O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
128809467b48Spatrick
1289*d415bd75Srobert if (DoShift || IsLSL) {
1290*d415bd75Srobert O << " ";
1291*d415bd75Srobert if (UseMarkup)
1292*d415bd75Srobert O << "<imm:";
129309467b48Spatrick O << "#" << Log2_32(Width / 8);
1294*d415bd75Srobert if (UseMarkup)
1295*d415bd75Srobert O << ">";
1296*d415bd75Srobert }
129709467b48Spatrick }
129809467b48Spatrick
printMemExtend(const MCInst * MI,unsigned OpNum,raw_ostream & O,char SrcRegKind,unsigned Width)129909467b48Spatrick void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
130009467b48Spatrick raw_ostream &O, char SrcRegKind,
130109467b48Spatrick unsigned Width) {
130209467b48Spatrick bool SignExtend = MI->getOperand(OpNum).getImm();
130309467b48Spatrick bool DoShift = MI->getOperand(OpNum + 1).getImm();
1304*d415bd75Srobert printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O, UseMarkup);
130509467b48Spatrick }
130609467b48Spatrick
130709467b48Spatrick template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
printRegWithShiftExtend(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)130809467b48Spatrick void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
130909467b48Spatrick unsigned OpNum,
131009467b48Spatrick const MCSubtargetInfo &STI,
131109467b48Spatrick raw_ostream &O) {
131209467b48Spatrick printOperand(MI, OpNum, STI, O);
131309467b48Spatrick if (Suffix == 's' || Suffix == 'd')
131409467b48Spatrick O << '.' << Suffix;
131509467b48Spatrick else
131609467b48Spatrick assert(Suffix == 0 && "Unsupported suffix size");
131709467b48Spatrick
131809467b48Spatrick bool DoShift = ExtWidth != 8;
131909467b48Spatrick if (SignExtend || DoShift || SrcRegKind == 'w') {
132009467b48Spatrick O << ", ";
1321*d415bd75Srobert printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O, UseMarkup);
1322*d415bd75Srobert }
1323*d415bd75Srobert }
1324*d415bd75Srobert
1325*d415bd75Srobert template <int EltSize>
printPredicateAsCounter(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1326*d415bd75Srobert void AArch64InstPrinter::printPredicateAsCounter(const MCInst *MI,
1327*d415bd75Srobert unsigned OpNum,
1328*d415bd75Srobert const MCSubtargetInfo &STI,
1329*d415bd75Srobert raw_ostream &O) {
1330*d415bd75Srobert unsigned Reg = MI->getOperand(OpNum).getReg();
1331*d415bd75Srobert
1332*d415bd75Srobert assert(Reg <= AArch64::P15 && "Unsupported predicate register");
1333*d415bd75Srobert O << "pn" << (Reg - AArch64::P0);
1334*d415bd75Srobert switch (EltSize) {
1335*d415bd75Srobert case 0:
1336*d415bd75Srobert break;
1337*d415bd75Srobert case 8:
1338*d415bd75Srobert O << ".b";
1339*d415bd75Srobert break;
1340*d415bd75Srobert case 16:
1341*d415bd75Srobert O << ".h";
1342*d415bd75Srobert break;
1343*d415bd75Srobert case 32:
1344*d415bd75Srobert O << ".s";
1345*d415bd75Srobert break;
1346*d415bd75Srobert case 64:
1347*d415bd75Srobert O << ".d";
1348*d415bd75Srobert break;
1349*d415bd75Srobert default:
1350*d415bd75Srobert llvm_unreachable("Unsupported element size");
135109467b48Spatrick }
135209467b48Spatrick }
135309467b48Spatrick
printCondCode(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)135409467b48Spatrick void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
135509467b48Spatrick const MCSubtargetInfo &STI,
135609467b48Spatrick raw_ostream &O) {
135709467b48Spatrick AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
135809467b48Spatrick O << AArch64CC::getCondCodeName(CC);
135909467b48Spatrick }
136009467b48Spatrick
printInverseCondCode(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)136109467b48Spatrick void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
136209467b48Spatrick const MCSubtargetInfo &STI,
136309467b48Spatrick raw_ostream &O) {
136409467b48Spatrick AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
136509467b48Spatrick O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
136609467b48Spatrick }
136709467b48Spatrick
printAMNoIndex(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)136809467b48Spatrick void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
136909467b48Spatrick const MCSubtargetInfo &STI,
137009467b48Spatrick raw_ostream &O) {
1371*d415bd75Srobert O << '[';
1372*d415bd75Srobert printRegName(O, MI->getOperand(OpNum).getReg());
1373*d415bd75Srobert O << ']';
137409467b48Spatrick }
137509467b48Spatrick
137609467b48Spatrick template <int Scale>
printImmScale(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)137709467b48Spatrick void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
137809467b48Spatrick const MCSubtargetInfo &STI,
137909467b48Spatrick raw_ostream &O) {
1380*d415bd75Srobert O << markup("<imm:") << '#'
1381*d415bd75Srobert << formatImm(Scale * MI->getOperand(OpNum).getImm()) << markup(">");
1382*d415bd75Srobert }
1383*d415bd75Srobert
1384*d415bd75Srobert template <int Scale, int Offset>
printImmRangeScale(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1385*d415bd75Srobert void AArch64InstPrinter::printImmRangeScale(const MCInst *MI, unsigned OpNum,
1386*d415bd75Srobert const MCSubtargetInfo &STI,
1387*d415bd75Srobert raw_ostream &O) {
1388*d415bd75Srobert unsigned FirstImm = Scale * MI->getOperand(OpNum).getImm();
1389*d415bd75Srobert O << formatImm(FirstImm);
1390*d415bd75Srobert O << ":" << formatImm(FirstImm + Offset);
139109467b48Spatrick }
139209467b48Spatrick
printUImm12Offset(const MCInst * MI,unsigned OpNum,unsigned Scale,raw_ostream & O)139309467b48Spatrick void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
139409467b48Spatrick unsigned Scale, raw_ostream &O) {
139509467b48Spatrick const MCOperand MO = MI->getOperand(OpNum);
139609467b48Spatrick if (MO.isImm()) {
1397*d415bd75Srobert O << markup("<imm:") << '#' << formatImm(MO.getImm() * Scale)
1398*d415bd75Srobert << markup(">");
139909467b48Spatrick } else {
140009467b48Spatrick assert(MO.isExpr() && "Unexpected operand type!");
140109467b48Spatrick MO.getExpr()->print(O, &MAI);
140209467b48Spatrick }
140309467b48Spatrick }
140409467b48Spatrick
printAMIndexedWB(const MCInst * MI,unsigned OpNum,unsigned Scale,raw_ostream & O)140509467b48Spatrick void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
140609467b48Spatrick unsigned Scale, raw_ostream &O) {
140709467b48Spatrick const MCOperand MO1 = MI->getOperand(OpNum + 1);
1408*d415bd75Srobert O << '[';
1409*d415bd75Srobert printRegName(O, MI->getOperand(OpNum).getReg());
141009467b48Spatrick if (MO1.isImm()) {
1411*d415bd75Srobert O << ", " << markup("<imm:") << "#" << formatImm(MO1.getImm() * Scale)
1412*d415bd75Srobert << markup(">");
141309467b48Spatrick } else {
141409467b48Spatrick assert(MO1.isExpr() && "Unexpected operand type!");
141509467b48Spatrick O << ", ";
141609467b48Spatrick MO1.getExpr()->print(O, &MAI);
141709467b48Spatrick }
141809467b48Spatrick O << ']';
141909467b48Spatrick }
142009467b48Spatrick
printRPRFMOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1421*d415bd75Srobert void AArch64InstPrinter::printRPRFMOperand(const MCInst *MI, unsigned OpNum,
1422*d415bd75Srobert const MCSubtargetInfo &STI,
1423*d415bd75Srobert raw_ostream &O) {
1424*d415bd75Srobert unsigned prfop = MI->getOperand(OpNum).getImm();
1425*d415bd75Srobert if (auto PRFM = AArch64RPRFM::lookupRPRFMByEncoding(prfop)) {
1426*d415bd75Srobert O << PRFM->Name;
1427*d415bd75Srobert return;
1428*d415bd75Srobert }
1429*d415bd75Srobert
1430*d415bd75Srobert O << '#' << formatImm(prfop);
1431*d415bd75Srobert }
1432*d415bd75Srobert
143309467b48Spatrick template <bool IsSVEPrefetch>
printPrefetchOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)143409467b48Spatrick void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
143509467b48Spatrick const MCSubtargetInfo &STI,
143609467b48Spatrick raw_ostream &O) {
143709467b48Spatrick unsigned prfop = MI->getOperand(OpNum).getImm();
143809467b48Spatrick if (IsSVEPrefetch) {
143909467b48Spatrick if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
144009467b48Spatrick O << PRFM->Name;
144109467b48Spatrick return;
144209467b48Spatrick }
1443*d415bd75Srobert } else {
1444*d415bd75Srobert auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
1445*d415bd75Srobert if (PRFM && PRFM->haveFeatures(STI.getFeatureBits())) {
144609467b48Spatrick O << PRFM->Name;
144709467b48Spatrick return;
144809467b48Spatrick }
1449*d415bd75Srobert }
145009467b48Spatrick
1451*d415bd75Srobert O << markup("<imm:") << '#' << formatImm(prfop) << markup(">");
145209467b48Spatrick }
145309467b48Spatrick
printPSBHintOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)145409467b48Spatrick void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
145509467b48Spatrick const MCSubtargetInfo &STI,
145609467b48Spatrick raw_ostream &O) {
145709467b48Spatrick unsigned psbhintop = MI->getOperand(OpNum).getImm();
145809467b48Spatrick auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
145909467b48Spatrick if (PSB)
146009467b48Spatrick O << PSB->Name;
146109467b48Spatrick else
1462*d415bd75Srobert O << markup("<imm:") << '#' << formatImm(psbhintop) << markup(">");
146309467b48Spatrick }
146409467b48Spatrick
printBTIHintOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)146509467b48Spatrick void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
146609467b48Spatrick const MCSubtargetInfo &STI,
146709467b48Spatrick raw_ostream &O) {
146873471bf0Spatrick unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32;
146909467b48Spatrick auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
147009467b48Spatrick if (BTI)
147109467b48Spatrick O << BTI->Name;
147209467b48Spatrick else
1473*d415bd75Srobert O << markup("<imm:") << '#' << formatImm(btihintop) << markup(">");
147409467b48Spatrick }
147509467b48Spatrick
printFPImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)147609467b48Spatrick void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
147709467b48Spatrick const MCSubtargetInfo &STI,
147809467b48Spatrick raw_ostream &O) {
147909467b48Spatrick const MCOperand &MO = MI->getOperand(OpNum);
148073471bf0Spatrick float FPImm = MO.isDFPImm() ? bit_cast<double>(MO.getDFPImm())
148173471bf0Spatrick : AArch64_AM::getFPImmFloat(MO.getImm());
148209467b48Spatrick
148309467b48Spatrick // 8 decimal places are enough to perfectly represent permitted floats.
1484*d415bd75Srobert O << markup("<imm:") << format("#%.8f", FPImm) << markup(">");
148509467b48Spatrick }
148609467b48Spatrick
getNextVectorRegister(unsigned Reg,unsigned Stride=1)148709467b48Spatrick static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
148809467b48Spatrick while (Stride--) {
148909467b48Spatrick switch (Reg) {
149009467b48Spatrick default:
149109467b48Spatrick llvm_unreachable("Vector register expected!");
149209467b48Spatrick case AArch64::Q0: Reg = AArch64::Q1; break;
149309467b48Spatrick case AArch64::Q1: Reg = AArch64::Q2; break;
149409467b48Spatrick case AArch64::Q2: Reg = AArch64::Q3; break;
149509467b48Spatrick case AArch64::Q3: Reg = AArch64::Q4; break;
149609467b48Spatrick case AArch64::Q4: Reg = AArch64::Q5; break;
149709467b48Spatrick case AArch64::Q5: Reg = AArch64::Q6; break;
149809467b48Spatrick case AArch64::Q6: Reg = AArch64::Q7; break;
149909467b48Spatrick case AArch64::Q7: Reg = AArch64::Q8; break;
150009467b48Spatrick case AArch64::Q8: Reg = AArch64::Q9; break;
150109467b48Spatrick case AArch64::Q9: Reg = AArch64::Q10; break;
150209467b48Spatrick case AArch64::Q10: Reg = AArch64::Q11; break;
150309467b48Spatrick case AArch64::Q11: Reg = AArch64::Q12; break;
150409467b48Spatrick case AArch64::Q12: Reg = AArch64::Q13; break;
150509467b48Spatrick case AArch64::Q13: Reg = AArch64::Q14; break;
150609467b48Spatrick case AArch64::Q14: Reg = AArch64::Q15; break;
150709467b48Spatrick case AArch64::Q15: Reg = AArch64::Q16; break;
150809467b48Spatrick case AArch64::Q16: Reg = AArch64::Q17; break;
150909467b48Spatrick case AArch64::Q17: Reg = AArch64::Q18; break;
151009467b48Spatrick case AArch64::Q18: Reg = AArch64::Q19; break;
151109467b48Spatrick case AArch64::Q19: Reg = AArch64::Q20; break;
151209467b48Spatrick case AArch64::Q20: Reg = AArch64::Q21; break;
151309467b48Spatrick case AArch64::Q21: Reg = AArch64::Q22; break;
151409467b48Spatrick case AArch64::Q22: Reg = AArch64::Q23; break;
151509467b48Spatrick case AArch64::Q23: Reg = AArch64::Q24; break;
151609467b48Spatrick case AArch64::Q24: Reg = AArch64::Q25; break;
151709467b48Spatrick case AArch64::Q25: Reg = AArch64::Q26; break;
151809467b48Spatrick case AArch64::Q26: Reg = AArch64::Q27; break;
151909467b48Spatrick case AArch64::Q27: Reg = AArch64::Q28; break;
152009467b48Spatrick case AArch64::Q28: Reg = AArch64::Q29; break;
152109467b48Spatrick case AArch64::Q29: Reg = AArch64::Q30; break;
152209467b48Spatrick case AArch64::Q30: Reg = AArch64::Q31; break;
152309467b48Spatrick // Vector lists can wrap around.
152409467b48Spatrick case AArch64::Q31:
152509467b48Spatrick Reg = AArch64::Q0;
152609467b48Spatrick break;
152709467b48Spatrick case AArch64::Z0: Reg = AArch64::Z1; break;
152809467b48Spatrick case AArch64::Z1: Reg = AArch64::Z2; break;
152909467b48Spatrick case AArch64::Z2: Reg = AArch64::Z3; break;
153009467b48Spatrick case AArch64::Z3: Reg = AArch64::Z4; break;
153109467b48Spatrick case AArch64::Z4: Reg = AArch64::Z5; break;
153209467b48Spatrick case AArch64::Z5: Reg = AArch64::Z6; break;
153309467b48Spatrick case AArch64::Z6: Reg = AArch64::Z7; break;
153409467b48Spatrick case AArch64::Z7: Reg = AArch64::Z8; break;
153509467b48Spatrick case AArch64::Z8: Reg = AArch64::Z9; break;
153609467b48Spatrick case AArch64::Z9: Reg = AArch64::Z10; break;
153709467b48Spatrick case AArch64::Z10: Reg = AArch64::Z11; break;
153809467b48Spatrick case AArch64::Z11: Reg = AArch64::Z12; break;
153909467b48Spatrick case AArch64::Z12: Reg = AArch64::Z13; break;
154009467b48Spatrick case AArch64::Z13: Reg = AArch64::Z14; break;
154109467b48Spatrick case AArch64::Z14: Reg = AArch64::Z15; break;
154209467b48Spatrick case AArch64::Z15: Reg = AArch64::Z16; break;
154309467b48Spatrick case AArch64::Z16: Reg = AArch64::Z17; break;
154409467b48Spatrick case AArch64::Z17: Reg = AArch64::Z18; break;
154509467b48Spatrick case AArch64::Z18: Reg = AArch64::Z19; break;
154609467b48Spatrick case AArch64::Z19: Reg = AArch64::Z20; break;
154709467b48Spatrick case AArch64::Z20: Reg = AArch64::Z21; break;
154809467b48Spatrick case AArch64::Z21: Reg = AArch64::Z22; break;
154909467b48Spatrick case AArch64::Z22: Reg = AArch64::Z23; break;
155009467b48Spatrick case AArch64::Z23: Reg = AArch64::Z24; break;
155109467b48Spatrick case AArch64::Z24: Reg = AArch64::Z25; break;
155209467b48Spatrick case AArch64::Z25: Reg = AArch64::Z26; break;
155309467b48Spatrick case AArch64::Z26: Reg = AArch64::Z27; break;
155409467b48Spatrick case AArch64::Z27: Reg = AArch64::Z28; break;
155509467b48Spatrick case AArch64::Z28: Reg = AArch64::Z29; break;
155609467b48Spatrick case AArch64::Z29: Reg = AArch64::Z30; break;
155709467b48Spatrick case AArch64::Z30: Reg = AArch64::Z31; break;
155809467b48Spatrick // Vector lists can wrap around.
155909467b48Spatrick case AArch64::Z31:
156009467b48Spatrick Reg = AArch64::Z0;
156109467b48Spatrick break;
1562*d415bd75Srobert case AArch64::P0: Reg = AArch64::P1; break;
1563*d415bd75Srobert case AArch64::P1: Reg = AArch64::P2; break;
1564*d415bd75Srobert case AArch64::P2: Reg = AArch64::P3; break;
1565*d415bd75Srobert case AArch64::P3: Reg = AArch64::P4; break;
1566*d415bd75Srobert case AArch64::P4: Reg = AArch64::P5; break;
1567*d415bd75Srobert case AArch64::P5: Reg = AArch64::P6; break;
1568*d415bd75Srobert case AArch64::P6: Reg = AArch64::P7; break;
1569*d415bd75Srobert case AArch64::P7: Reg = AArch64::P8; break;
1570*d415bd75Srobert case AArch64::P8: Reg = AArch64::P9; break;
1571*d415bd75Srobert case AArch64::P9: Reg = AArch64::P10; break;
1572*d415bd75Srobert case AArch64::P10: Reg = AArch64::P11; break;
1573*d415bd75Srobert case AArch64::P11: Reg = AArch64::P12; break;
1574*d415bd75Srobert case AArch64::P12: Reg = AArch64::P13; break;
1575*d415bd75Srobert case AArch64::P13: Reg = AArch64::P14; break;
1576*d415bd75Srobert case AArch64::P14: Reg = AArch64::P15; break;
1577*d415bd75Srobert // Vector lists can wrap around.
1578*d415bd75Srobert case AArch64::P15: Reg = AArch64::P0; break;
157909467b48Spatrick }
158009467b48Spatrick }
158109467b48Spatrick return Reg;
158209467b48Spatrick }
158309467b48Spatrick
158409467b48Spatrick template<unsigned size>
printGPRSeqPairsClassOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)158509467b48Spatrick void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
158609467b48Spatrick unsigned OpNum,
158709467b48Spatrick const MCSubtargetInfo &STI,
158809467b48Spatrick raw_ostream &O) {
158909467b48Spatrick static_assert(size == 64 || size == 32,
159009467b48Spatrick "Template parameter must be either 32 or 64");
159109467b48Spatrick unsigned Reg = MI->getOperand(OpNum).getReg();
159209467b48Spatrick
159309467b48Spatrick unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
159409467b48Spatrick unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
159509467b48Spatrick
159609467b48Spatrick unsigned Even = MRI.getSubReg(Reg, Sube);
159709467b48Spatrick unsigned Odd = MRI.getSubReg(Reg, Subo);
1598*d415bd75Srobert printRegName(O, Even);
1599*d415bd75Srobert O << ", ";
1600*d415bd75Srobert printRegName(O, Odd);
160109467b48Spatrick }
160209467b48Spatrick
printMatrixTileList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)160373471bf0Spatrick void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum,
160473471bf0Spatrick const MCSubtargetInfo &STI,
160573471bf0Spatrick raw_ostream &O) {
160673471bf0Spatrick unsigned MaxRegs = 8;
160773471bf0Spatrick unsigned RegMask = MI->getOperand(OpNum).getImm();
160873471bf0Spatrick
160973471bf0Spatrick unsigned NumRegs = 0;
161073471bf0Spatrick for (unsigned I = 0; I < MaxRegs; ++I)
161173471bf0Spatrick if ((RegMask & (1 << I)) != 0)
161273471bf0Spatrick ++NumRegs;
161373471bf0Spatrick
161473471bf0Spatrick O << "{";
161573471bf0Spatrick unsigned Printed = 0;
161673471bf0Spatrick for (unsigned I = 0; I < MaxRegs; ++I) {
161773471bf0Spatrick unsigned Reg = RegMask & (1 << I);
161873471bf0Spatrick if (Reg == 0)
161973471bf0Spatrick continue;
1620*d415bd75Srobert printRegName(O, AArch64::ZAD0 + I);
162173471bf0Spatrick if (Printed + 1 != NumRegs)
162273471bf0Spatrick O << ", ";
162373471bf0Spatrick ++Printed;
162473471bf0Spatrick }
162573471bf0Spatrick O << "}";
162673471bf0Spatrick }
162773471bf0Spatrick
printVectorList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O,StringRef LayoutSuffix)162809467b48Spatrick void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
162909467b48Spatrick const MCSubtargetInfo &STI,
163009467b48Spatrick raw_ostream &O,
163109467b48Spatrick StringRef LayoutSuffix) {
163209467b48Spatrick unsigned Reg = MI->getOperand(OpNum).getReg();
163309467b48Spatrick
163409467b48Spatrick O << "{ ";
163509467b48Spatrick
163609467b48Spatrick // Work out how many registers there are in the list (if there is an actual
163709467b48Spatrick // list).
163809467b48Spatrick unsigned NumRegs = 1;
163909467b48Spatrick if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
164009467b48Spatrick MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1641*d415bd75Srobert MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) ||
1642*d415bd75Srobert MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) ||
1643*d415bd75Srobert MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
164409467b48Spatrick NumRegs = 2;
164509467b48Spatrick else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
164609467b48Spatrick MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
164709467b48Spatrick MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
164809467b48Spatrick NumRegs = 3;
164909467b48Spatrick else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
165009467b48Spatrick MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1651*d415bd75Srobert MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) ||
1652*d415bd75Srobert MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
165309467b48Spatrick NumRegs = 4;
165409467b48Spatrick
1655*d415bd75Srobert unsigned Stride = 1;
1656*d415bd75Srobert if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1657*d415bd75Srobert Stride = 8;
1658*d415bd75Srobert else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1659*d415bd75Srobert Stride = 4;
1660*d415bd75Srobert
166109467b48Spatrick // Now forget about the list and find out what the first register is.
166209467b48Spatrick if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
166309467b48Spatrick Reg = FirstReg;
166409467b48Spatrick else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
166509467b48Spatrick Reg = FirstReg;
166609467b48Spatrick else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
166709467b48Spatrick Reg = FirstReg;
1668*d415bd75Srobert else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0))
1669*d415bd75Srobert Reg = FirstReg;
167009467b48Spatrick
167109467b48Spatrick // If it's a D-reg, we need to promote it to the equivalent Q-reg before
167209467b48Spatrick // printing (otherwise getRegisterName fails).
167309467b48Spatrick if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
167409467b48Spatrick const MCRegisterClass &FPR128RC =
167509467b48Spatrick MRI.getRegClass(AArch64::FPR128RegClassID);
167609467b48Spatrick Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
167709467b48Spatrick }
167809467b48Spatrick
1679*d415bd75Srobert if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1680*d415bd75Srobert MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) &&
1681*d415bd75Srobert NumRegs > 1 && Stride == 1 &&
1682*d415bd75Srobert // Do not print the range when the last register is lower than the first.
1683*d415bd75Srobert // Because it is a wrap-around register.
1684*d415bd75Srobert Reg < getNextVectorRegister(Reg, NumRegs - 1)) {
1685*d415bd75Srobert printRegName(O, Reg);
1686*d415bd75Srobert O << LayoutSuffix;
1687*d415bd75Srobert if (NumRegs > 1) {
1688*d415bd75Srobert // Set of two sve registers should be separated by ','
1689*d415bd75Srobert StringRef split_char = NumRegs == 2 ? ", " : " - ";
1690*d415bd75Srobert O << split_char;
1691*d415bd75Srobert printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1)));
1692*d415bd75Srobert O << LayoutSuffix;
1693*d415bd75Srobert }
1694*d415bd75Srobert } else {
1695*d415bd75Srobert for (unsigned i = 0; i < NumRegs;
1696*d415bd75Srobert ++i, Reg = getNextVectorRegister(Reg, Stride)) {
1697*d415bd75Srobert // wrap-around sve register
1698*d415bd75Srobert if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1699*d415bd75Srobert MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg))
1700*d415bd75Srobert printRegName(O, Reg);
170109467b48Spatrick else
1702*d415bd75Srobert printRegName(O, Reg, AArch64::vreg);
1703*d415bd75Srobert O << LayoutSuffix;
170409467b48Spatrick if (i + 1 != NumRegs)
170509467b48Spatrick O << ", ";
170609467b48Spatrick }
1707*d415bd75Srobert }
170809467b48Spatrick O << " }";
170909467b48Spatrick }
171009467b48Spatrick
171109467b48Spatrick void
printImplicitlyTypedVectorList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)171209467b48Spatrick AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
171309467b48Spatrick unsigned OpNum,
171409467b48Spatrick const MCSubtargetInfo &STI,
171509467b48Spatrick raw_ostream &O) {
171609467b48Spatrick printVectorList(MI, OpNum, STI, O, "");
171709467b48Spatrick }
171809467b48Spatrick
171909467b48Spatrick template <unsigned NumLanes, char LaneKind>
printTypedVectorList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)172009467b48Spatrick void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
172109467b48Spatrick const MCSubtargetInfo &STI,
172209467b48Spatrick raw_ostream &O) {
172309467b48Spatrick std::string Suffix(".");
172409467b48Spatrick if (NumLanes)
172509467b48Spatrick Suffix += itostr(NumLanes) + LaneKind;
172609467b48Spatrick else
172709467b48Spatrick Suffix += LaneKind;
172809467b48Spatrick
172909467b48Spatrick printVectorList(MI, OpNum, STI, O, Suffix);
173009467b48Spatrick }
173109467b48Spatrick
1732*d415bd75Srobert template <unsigned Scale>
printVectorIndex(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)173309467b48Spatrick void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
173409467b48Spatrick const MCSubtargetInfo &STI,
173509467b48Spatrick raw_ostream &O) {
1736*d415bd75Srobert O << "[" << Scale * MI->getOperand(OpNum).getImm() << "]";
1737*d415bd75Srobert }
1738*d415bd75Srobert
printMatrixIndex(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1739*d415bd75Srobert void AArch64InstPrinter::printMatrixIndex(const MCInst *MI, unsigned OpNum,
1740*d415bd75Srobert const MCSubtargetInfo &STI,
1741*d415bd75Srobert raw_ostream &O) {
1742*d415bd75Srobert O << MI->getOperand(OpNum).getImm();
174309467b48Spatrick }
174409467b48Spatrick
printAlignedLabel(const MCInst * MI,uint64_t Address,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1745097a140dSpatrick void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, uint64_t Address,
1746097a140dSpatrick unsigned OpNum,
174709467b48Spatrick const MCSubtargetInfo &STI,
174809467b48Spatrick raw_ostream &O) {
174909467b48Spatrick const MCOperand &Op = MI->getOperand(OpNum);
175009467b48Spatrick
175109467b48Spatrick // If the label has already been resolved to an immediate offset (say, when
175209467b48Spatrick // we're running the disassembler), just print the immediate.
175309467b48Spatrick if (Op.isImm()) {
1754*d415bd75Srobert O << markup("<imm:");
1755097a140dSpatrick int64_t Offset = Op.getImm() * 4;
1756097a140dSpatrick if (PrintBranchImmAsAddress)
1757097a140dSpatrick O << formatHex(Address + Offset);
1758097a140dSpatrick else
1759097a140dSpatrick O << "#" << formatImm(Offset);
1760*d415bd75Srobert O << markup(">");
176109467b48Spatrick return;
176209467b48Spatrick }
176309467b48Spatrick
176409467b48Spatrick // If the branch target is simply an address then print it in hex.
176509467b48Spatrick const MCConstantExpr *BranchTarget =
176609467b48Spatrick dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1767097a140dSpatrick int64_t TargetAddress;
1768097a140dSpatrick if (BranchTarget && BranchTarget->evaluateAsAbsolute(TargetAddress)) {
1769*d415bd75Srobert O << formatHex((uint64_t)TargetAddress);
177009467b48Spatrick } else {
177109467b48Spatrick // Otherwise, just print the expression.
177209467b48Spatrick MI->getOperand(OpNum).getExpr()->print(O, &MAI);
177309467b48Spatrick }
177409467b48Spatrick }
177509467b48Spatrick
printAdrpLabel(const MCInst * MI,uint64_t Address,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)177673471bf0Spatrick void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, uint64_t Address,
177773471bf0Spatrick unsigned OpNum,
177809467b48Spatrick const MCSubtargetInfo &STI,
177909467b48Spatrick raw_ostream &O) {
178009467b48Spatrick const MCOperand &Op = MI->getOperand(OpNum);
178109467b48Spatrick
178209467b48Spatrick // If the label has already been resolved to an immediate offset (say, when
178309467b48Spatrick // we're running the disassembler), just print the immediate.
178409467b48Spatrick if (Op.isImm()) {
178573471bf0Spatrick const int64_t Offset = Op.getImm() * 4096;
1786*d415bd75Srobert O << markup("<imm:");
178773471bf0Spatrick if (PrintBranchImmAsAddress)
178873471bf0Spatrick O << formatHex((Address & -4096) + Offset);
178973471bf0Spatrick else
179073471bf0Spatrick O << "#" << Offset;
1791*d415bd75Srobert O << markup(">");
179209467b48Spatrick return;
179309467b48Spatrick }
179409467b48Spatrick
179509467b48Spatrick // Otherwise, just print the expression.
179609467b48Spatrick MI->getOperand(OpNum).getExpr()->print(O, &MAI);
179709467b48Spatrick }
179809467b48Spatrick
printBarrierOption(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)179909467b48Spatrick void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
180009467b48Spatrick const MCSubtargetInfo &STI,
180109467b48Spatrick raw_ostream &O) {
180209467b48Spatrick unsigned Val = MI->getOperand(OpNo).getImm();
180309467b48Spatrick unsigned Opcode = MI->getOpcode();
180409467b48Spatrick
180509467b48Spatrick StringRef Name;
180609467b48Spatrick if (Opcode == AArch64::ISB) {
180709467b48Spatrick auto ISB = AArch64ISB::lookupISBByEncoding(Val);
180809467b48Spatrick Name = ISB ? ISB->Name : "";
180909467b48Spatrick } else if (Opcode == AArch64::TSB) {
181009467b48Spatrick auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
181109467b48Spatrick Name = TSB ? TSB->Name : "";
181209467b48Spatrick } else {
181309467b48Spatrick auto DB = AArch64DB::lookupDBByEncoding(Val);
181409467b48Spatrick Name = DB ? DB->Name : "";
181509467b48Spatrick }
181609467b48Spatrick if (!Name.empty())
181709467b48Spatrick O << Name;
181809467b48Spatrick else
1819*d415bd75Srobert O << markup("<imm:") << "#" << Val << markup(">");
182009467b48Spatrick }
182109467b48Spatrick
printBarriernXSOption(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)182273471bf0Spatrick void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo,
182373471bf0Spatrick const MCSubtargetInfo &STI,
182473471bf0Spatrick raw_ostream &O) {
182573471bf0Spatrick unsigned Val = MI->getOperand(OpNo).getImm();
182673471bf0Spatrick assert(MI->getOpcode() == AArch64::DSBnXS);
182773471bf0Spatrick
182873471bf0Spatrick StringRef Name;
182973471bf0Spatrick auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
183073471bf0Spatrick Name = DB ? DB->Name : "";
183173471bf0Spatrick
183273471bf0Spatrick if (!Name.empty())
183373471bf0Spatrick O << Name;
183473471bf0Spatrick else
1835*d415bd75Srobert O << markup("<imm:") << "#" << Val << markup(">");
1836*d415bd75Srobert }
1837*d415bd75Srobert
isValidSysReg(const AArch64SysReg::SysReg * Reg,bool Read,const MCSubtargetInfo & STI)1838*d415bd75Srobert static bool isValidSysReg(const AArch64SysReg::SysReg *Reg, bool Read,
1839*d415bd75Srobert const MCSubtargetInfo &STI) {
1840*d415bd75Srobert return (Reg && (Read ? Reg->Readable : Reg->Writeable) &&
1841*d415bd75Srobert Reg->haveFeatures(STI.getFeatureBits()));
1842*d415bd75Srobert }
1843*d415bd75Srobert
1844*d415bd75Srobert // Looks up a system register either by encoding or by name. Some system
1845*d415bd75Srobert // registers share the same encoding between different architectures,
1846*d415bd75Srobert // therefore a tablegen lookup by encoding will return an entry regardless
1847*d415bd75Srobert // of the register's predication on a specific subtarget feature. To work
1848*d415bd75Srobert // around this problem we keep an alternative name for such registers and
1849*d415bd75Srobert // look them up by that name if the first lookup was unsuccessful.
lookupSysReg(unsigned Val,bool Read,const MCSubtargetInfo & STI)1850*d415bd75Srobert static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read,
1851*d415bd75Srobert const MCSubtargetInfo &STI) {
1852*d415bd75Srobert const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
1853*d415bd75Srobert
1854*d415bd75Srobert if (Reg && !isValidSysReg(Reg, Read, STI))
1855*d415bd75Srobert Reg = AArch64SysReg::lookupSysRegByName(Reg->AltName);
1856*d415bd75Srobert
1857*d415bd75Srobert return Reg;
185873471bf0Spatrick }
185973471bf0Spatrick
printMRSSystemRegister(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)186009467b48Spatrick void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
186109467b48Spatrick const MCSubtargetInfo &STI,
186209467b48Spatrick raw_ostream &O) {
186309467b48Spatrick unsigned Val = MI->getOperand(OpNo).getImm();
186409467b48Spatrick
186509467b48Spatrick // Horrible hack for the one register that has identical encodings but
186609467b48Spatrick // different names in MSR and MRS. Because of this, one of MRS and MSR is
186709467b48Spatrick // going to get the wrong entry
186809467b48Spatrick if (Val == AArch64SysReg::DBGDTRRX_EL0) {
186909467b48Spatrick O << "DBGDTRRX_EL0";
187009467b48Spatrick return;
187109467b48Spatrick }
187209467b48Spatrick
1873097a140dSpatrick // Horrible hack for two different registers having the same encoding.
1874097a140dSpatrick if (Val == AArch64SysReg::TRCEXTINSELR) {
1875097a140dSpatrick O << "TRCEXTINSELR";
1876097a140dSpatrick return;
1877097a140dSpatrick }
1878097a140dSpatrick
1879*d415bd75Srobert const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI);
1880*d415bd75Srobert
1881*d415bd75Srobert if (isValidSysReg(Reg, true /*Read*/, STI))
188209467b48Spatrick O << Reg->Name;
188309467b48Spatrick else
188409467b48Spatrick O << AArch64SysReg::genericRegisterString(Val);
188509467b48Spatrick }
188609467b48Spatrick
printMSRSystemRegister(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)188709467b48Spatrick void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
188809467b48Spatrick const MCSubtargetInfo &STI,
188909467b48Spatrick raw_ostream &O) {
189009467b48Spatrick unsigned Val = MI->getOperand(OpNo).getImm();
189109467b48Spatrick
189209467b48Spatrick // Horrible hack for the one register that has identical encodings but
189309467b48Spatrick // different names in MSR and MRS. Because of this, one of MRS and MSR is
189409467b48Spatrick // going to get the wrong entry
189509467b48Spatrick if (Val == AArch64SysReg::DBGDTRTX_EL0) {
189609467b48Spatrick O << "DBGDTRTX_EL0";
189709467b48Spatrick return;
189809467b48Spatrick }
189909467b48Spatrick
1900097a140dSpatrick // Horrible hack for two different registers having the same encoding.
1901097a140dSpatrick if (Val == AArch64SysReg::TRCEXTINSELR) {
1902097a140dSpatrick O << "TRCEXTINSELR";
1903097a140dSpatrick return;
1904097a140dSpatrick }
1905097a140dSpatrick
1906*d415bd75Srobert const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI);
1907*d415bd75Srobert
1908*d415bd75Srobert if (isValidSysReg(Reg, false /*Read*/, STI))
190909467b48Spatrick O << Reg->Name;
191009467b48Spatrick else
191109467b48Spatrick O << AArch64SysReg::genericRegisterString(Val);
191209467b48Spatrick }
191309467b48Spatrick
printSystemPStateField(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)191409467b48Spatrick void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
191509467b48Spatrick const MCSubtargetInfo &STI,
191609467b48Spatrick raw_ostream &O) {
191709467b48Spatrick unsigned Val = MI->getOperand(OpNo).getImm();
191809467b48Spatrick
1919*d415bd75Srobert auto PStateImm15 = AArch64PState::lookupPStateImm0_15ByEncoding(Val);
1920*d415bd75Srobert auto PStateImm1 = AArch64PState::lookupPStateImm0_1ByEncoding(Val);
1921*d415bd75Srobert if (PStateImm15 && PStateImm15->haveFeatures(STI.getFeatureBits()))
1922*d415bd75Srobert O << PStateImm15->Name;
1923*d415bd75Srobert else if (PStateImm1 && PStateImm1->haveFeatures(STI.getFeatureBits()))
1924*d415bd75Srobert O << PStateImm1->Name;
192509467b48Spatrick else
192609467b48Spatrick O << "#" << formatImm(Val);
192709467b48Spatrick }
192809467b48Spatrick
printSIMDType10Operand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)192909467b48Spatrick void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
193009467b48Spatrick const MCSubtargetInfo &STI,
193109467b48Spatrick raw_ostream &O) {
193209467b48Spatrick unsigned RawVal = MI->getOperand(OpNo).getImm();
193309467b48Spatrick uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
1934*d415bd75Srobert O << markup("<imm:") << format("#%#016llx", Val) << markup(">");
193509467b48Spatrick }
193609467b48Spatrick
193709467b48Spatrick template<int64_t Angle, int64_t Remainder>
printComplexRotationOp(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)193809467b48Spatrick void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
193909467b48Spatrick const MCSubtargetInfo &STI,
194009467b48Spatrick raw_ostream &O) {
194109467b48Spatrick unsigned Val = MI->getOperand(OpNo).getImm();
1942*d415bd75Srobert O << markup("<imm:") << "#" << (Val * Angle) + Remainder << markup(">");
194309467b48Spatrick }
194409467b48Spatrick
printSVEPattern(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)194509467b48Spatrick void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
194609467b48Spatrick const MCSubtargetInfo &STI,
194709467b48Spatrick raw_ostream &O) {
194809467b48Spatrick unsigned Val = MI->getOperand(OpNum).getImm();
194909467b48Spatrick if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
195009467b48Spatrick O << Pat->Name;
195109467b48Spatrick else
1952*d415bd75Srobert O << markup("<imm:") << '#' << formatImm(Val) << markup(">");
1953*d415bd75Srobert }
1954*d415bd75Srobert
printSVEVecLenSpecifier(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1955*d415bd75Srobert void AArch64InstPrinter::printSVEVecLenSpecifier(const MCInst *MI,
1956*d415bd75Srobert unsigned OpNum,
1957*d415bd75Srobert const MCSubtargetInfo &STI,
1958*d415bd75Srobert raw_ostream &O) {
1959*d415bd75Srobert unsigned Val = MI->getOperand(OpNum).getImm();
1960*d415bd75Srobert // Pattern has only 1 bit
1961*d415bd75Srobert if (Val > 1)
1962*d415bd75Srobert llvm_unreachable("Invalid vector length specifier");
1963*d415bd75Srobert if (auto Pat =
1964*d415bd75Srobert AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByEncoding(Val))
1965*d415bd75Srobert O << Pat->Name;
1966*d415bd75Srobert else
1967*d415bd75Srobert llvm_unreachable("Invalid vector length specifier");
196809467b48Spatrick }
196909467b48Spatrick
197009467b48Spatrick template <char suffix>
printSVERegOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)197109467b48Spatrick void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
197209467b48Spatrick const MCSubtargetInfo &STI,
197309467b48Spatrick raw_ostream &O) {
197409467b48Spatrick switch (suffix) {
197509467b48Spatrick case 0:
197609467b48Spatrick case 'b':
197709467b48Spatrick case 'h':
197809467b48Spatrick case 's':
197909467b48Spatrick case 'd':
198009467b48Spatrick case 'q':
198109467b48Spatrick break;
198209467b48Spatrick default: llvm_unreachable("Invalid kind specifier.");
198309467b48Spatrick }
198409467b48Spatrick
198509467b48Spatrick unsigned Reg = MI->getOperand(OpNum).getReg();
1986*d415bd75Srobert printRegName(O, Reg);
198709467b48Spatrick if (suffix != 0)
198809467b48Spatrick O << '.' << suffix;
198909467b48Spatrick }
199009467b48Spatrick
199109467b48Spatrick template <typename T>
printImmSVE(T Value,raw_ostream & O)199209467b48Spatrick void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) {
1993097a140dSpatrick std::make_unsigned_t<T> HexValue = Value;
199409467b48Spatrick
199509467b48Spatrick if (getPrintImmHex())
1996*d415bd75Srobert O << markup("<imm:") << '#' << formatHex((uint64_t)HexValue) << markup(">");
199709467b48Spatrick else
1998*d415bd75Srobert O << markup("<imm:") << '#' << formatDec(Value) << markup(">");
199909467b48Spatrick
200009467b48Spatrick if (CommentStream) {
200109467b48Spatrick // Do the opposite to that used for instruction operands.
200209467b48Spatrick if (getPrintImmHex())
200309467b48Spatrick *CommentStream << '=' << formatDec(HexValue) << '\n';
200409467b48Spatrick else
200509467b48Spatrick *CommentStream << '=' << formatHex((uint64_t)Value) << '\n';
200609467b48Spatrick }
200709467b48Spatrick }
200809467b48Spatrick
200909467b48Spatrick template <typename T>
printImm8OptLsl(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)201009467b48Spatrick void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
201109467b48Spatrick const MCSubtargetInfo &STI,
201209467b48Spatrick raw_ostream &O) {
201309467b48Spatrick unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
201409467b48Spatrick unsigned Shift = MI->getOperand(OpNum + 1).getImm();
201509467b48Spatrick assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
201609467b48Spatrick "Unexepected shift type!");
201709467b48Spatrick
201809467b48Spatrick // #0 lsl #8 is never pretty printed
201909467b48Spatrick if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
2020*d415bd75Srobert O << markup("<imm:") << '#' << formatImm(UnscaledVal) << markup(">");
202109467b48Spatrick printShifter(MI, OpNum + 1, STI, O);
202209467b48Spatrick return;
202309467b48Spatrick }
202409467b48Spatrick
202509467b48Spatrick T Val;
202609467b48Spatrick if (std::is_signed<T>())
202709467b48Spatrick Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
202809467b48Spatrick else
202909467b48Spatrick Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
203009467b48Spatrick
203109467b48Spatrick printImmSVE(Val, O);
203209467b48Spatrick }
203309467b48Spatrick
203409467b48Spatrick template <typename T>
printSVELogicalImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)203509467b48Spatrick void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
203609467b48Spatrick const MCSubtargetInfo &STI,
203709467b48Spatrick raw_ostream &O) {
2038097a140dSpatrick typedef std::make_signed_t<T> SignedT;
2039097a140dSpatrick typedef std::make_unsigned_t<T> UnsignedT;
204009467b48Spatrick
204109467b48Spatrick uint64_t Val = MI->getOperand(OpNum).getImm();
204209467b48Spatrick UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64);
204309467b48Spatrick
204409467b48Spatrick // Prefer the default format for 16bit values, hex otherwise.
204509467b48Spatrick if ((int16_t)PrintVal == (SignedT)PrintVal)
204609467b48Spatrick printImmSVE((T)PrintVal, O);
204709467b48Spatrick else if ((uint16_t)PrintVal == PrintVal)
204809467b48Spatrick printImmSVE(PrintVal, O);
204909467b48Spatrick else
2050*d415bd75Srobert O << markup("<imm:") << '#' << formatHex((uint64_t)PrintVal) << markup(">");
205109467b48Spatrick }
205209467b48Spatrick
205309467b48Spatrick template <int Width>
printZPRasFPR(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)205409467b48Spatrick void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
205509467b48Spatrick const MCSubtargetInfo &STI,
205609467b48Spatrick raw_ostream &O) {
205709467b48Spatrick unsigned Base;
205809467b48Spatrick switch (Width) {
205909467b48Spatrick case 8: Base = AArch64::B0; break;
206009467b48Spatrick case 16: Base = AArch64::H0; break;
206109467b48Spatrick case 32: Base = AArch64::S0; break;
206209467b48Spatrick case 64: Base = AArch64::D0; break;
206309467b48Spatrick case 128: Base = AArch64::Q0; break;
206409467b48Spatrick default:
206509467b48Spatrick llvm_unreachable("Unsupported width");
206609467b48Spatrick }
206709467b48Spatrick unsigned Reg = MI->getOperand(OpNum).getReg();
2068*d415bd75Srobert printRegName(O, Reg - AArch64::Z0 + Base);
206909467b48Spatrick }
207009467b48Spatrick
207109467b48Spatrick template <unsigned ImmIs0, unsigned ImmIs1>
printExactFPImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)207209467b48Spatrick void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
207309467b48Spatrick const MCSubtargetInfo &STI,
207409467b48Spatrick raw_ostream &O) {
207509467b48Spatrick auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
207609467b48Spatrick auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
207709467b48Spatrick unsigned Val = MI->getOperand(OpNum).getImm();
2078*d415bd75Srobert O << markup("<imm:") << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr)
2079*d415bd75Srobert << markup(">");
208009467b48Spatrick }
208109467b48Spatrick
printGPR64as32(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)208209467b48Spatrick void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
208309467b48Spatrick const MCSubtargetInfo &STI,
208409467b48Spatrick raw_ostream &O) {
208509467b48Spatrick unsigned Reg = MI->getOperand(OpNum).getReg();
2086*d415bd75Srobert printRegName(O, getWRegFromXReg(Reg));
208709467b48Spatrick }
208873471bf0Spatrick
printGPR64x8(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)208973471bf0Spatrick void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
209073471bf0Spatrick const MCSubtargetInfo &STI,
209173471bf0Spatrick raw_ostream &O) {
209273471bf0Spatrick unsigned Reg = MI->getOperand(OpNum).getReg();
2093*d415bd75Srobert printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0));
2094*d415bd75Srobert }
2095*d415bd75Srobert
printSyspXzrPair(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)2096*d415bd75Srobert void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum,
2097*d415bd75Srobert const MCSubtargetInfo &STI,
2098*d415bd75Srobert raw_ostream &O) {
2099*d415bd75Srobert unsigned Reg = MI->getOperand(OpNum).getReg();
2100*d415bd75Srobert assert(Reg == AArch64::XZR &&
2101*d415bd75Srobert "MC representation of SyspXzrPair should be XZR");
2102*d415bd75Srobert O << getRegisterName(Reg) << ", " << getRegisterName(Reg);
210373471bf0Spatrick }
2104