109467b48Spatrick 209467b48Spatrickclass R600Reg <string name, bits<16> encoding> : Register<name> { 309467b48Spatrick let Namespace = "AMDGPU"; 409467b48Spatrick let HWEncoding = encoding; 509467b48Spatrick} 609467b48Spatrick 709467b48Spatrickclass R600RegWithChan <string name, bits<9> sel, string chan> : 809467b48Spatrick Register <name> { 909467b48Spatrick 1009467b48Spatrick field bits<2> chan_encoding = !if(!eq(chan, "X"), 0, 1109467b48Spatrick !if(!eq(chan, "Y"), 1, 1209467b48Spatrick !if(!eq(chan, "Z"), 2, 1309467b48Spatrick !if(!eq(chan, "W"), 3, 0)))); 1409467b48Spatrick let HWEncoding{8-0} = sel; 1509467b48Spatrick let HWEncoding{10-9} = chan_encoding; 1609467b48Spatrick let Namespace = "AMDGPU"; 1709467b48Spatrick} 1809467b48Spatrick 1909467b48Spatrickclass R600Reg_128<string n, list<Register> subregs, bits<16> encoding> : 2009467b48Spatrick RegisterWithSubRegs<n, subregs> { 2109467b48Spatrick field bits<2> chan_encoding = 0; 2209467b48Spatrick let Namespace = "AMDGPU"; 2309467b48Spatrick let SubRegIndices = [sub0, sub1, sub2, sub3]; 2409467b48Spatrick let HWEncoding{8-0} = encoding{8-0}; 2509467b48Spatrick let HWEncoding{10-9} = chan_encoding; 2609467b48Spatrick} 2709467b48Spatrick 2809467b48Spatrickclass R600Reg_64<string n, list<Register> subregs, bits<16> encoding> : 2909467b48Spatrick RegisterWithSubRegs<n, subregs> { 3009467b48Spatrick field bits<2> chan_encoding = 0; 3109467b48Spatrick let Namespace = "AMDGPU"; 3209467b48Spatrick let SubRegIndices = [sub0, sub1]; 3309467b48Spatrick let HWEncoding = encoding; 3409467b48Spatrick let HWEncoding{8-0} = encoding{8-0}; 3509467b48Spatrick let HWEncoding{10-9} = chan_encoding; 3609467b48Spatrick} 3709467b48Spatrick 3809467b48Spatrickclass R600Reg_64Vertical<int lo, int hi, string chan> : R600Reg_64 < 3909467b48Spatrick "V"#lo#hi#"_"#chan, 4009467b48Spatrick [!cast<Register>("T"#lo#"_"#chan), !cast<Register>("T"#hi#"_"#chan)], 4109467b48Spatrick lo 4209467b48Spatrick>; 4309467b48Spatrick 4409467b48Spatrickforeach Index = 0-127 in { 4509467b48Spatrick foreach Chan = [ "X", "Y", "Z", "W" ] in { 4609467b48Spatrick // 32-bit Temporary Registers 4709467b48Spatrick def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>; 4809467b48Spatrick 4909467b48Spatrick // Indirect addressing offset registers 5009467b48Spatrick def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan, 5109467b48Spatrick Index, Chan>; 5209467b48Spatrick } 5309467b48Spatrick // 128-bit Temporary Registers 5409467b48Spatrick def T#Index#_XYZW : R600Reg_128 <"T"#Index#"", 5509467b48Spatrick [!cast<Register>("T"#Index#"_X"), 5609467b48Spatrick !cast<Register>("T"#Index#"_Y"), 5709467b48Spatrick !cast<Register>("T"#Index#"_Z"), 5809467b48Spatrick !cast<Register>("T"#Index#"_W")], 5909467b48Spatrick Index>; 6009467b48Spatrick 6109467b48Spatrick def T#Index#_XY : R600Reg_64 <"T"#Index#"", 6209467b48Spatrick [!cast<Register>("T"#Index#"_X"), 6309467b48Spatrick !cast<Register>("T"#Index#"_Y")], 6409467b48Spatrick Index>; 6509467b48Spatrick} 6609467b48Spatrick 6709467b48Spatrickforeach Chan = [ "X", "Y", "Z", "W"] in { 6809467b48Spatrick 6909467b48Spatrick let chan_encoding = !if(!eq(Chan, "X"), 0, 7009467b48Spatrick !if(!eq(Chan, "Y"), 1, 7109467b48Spatrick !if(!eq(Chan, "Z"), 2, 7209467b48Spatrick !if(!eq(Chan, "W"), 3, 0)))) in { 7309467b48Spatrick def V0123_#Chan : R600Reg_128 <"V0123_"#Chan, 7409467b48Spatrick [!cast<Register>("T0_"#Chan), 7509467b48Spatrick !cast<Register>("T1_"#Chan), 7609467b48Spatrick !cast<Register>("T2_"#Chan), 7709467b48Spatrick !cast<Register>("T3_"#Chan)], 7809467b48Spatrick 0>; 7909467b48Spatrick def V01_#Chan : R600Reg_64Vertical<0, 1, Chan>; 8009467b48Spatrick def V23_#Chan : R600Reg_64Vertical<2, 3, Chan>; 8109467b48Spatrick } 8209467b48Spatrick} 8309467b48Spatrick 8409467b48Spatrick 8509467b48Spatrick// KCACHE_BANK0 8609467b48Spatrickforeach Index = 159-128 in { 8709467b48Spatrick foreach Chan = [ "X", "Y", "Z", "W" ] in { 8809467b48Spatrick // 32-bit Temporary Registers 8909467b48Spatrick def KC0_#Index#_#Chan : R600RegWithChan <"KC0["#!add(Index,-128)#"]."#Chan, Index, Chan>; 9009467b48Spatrick } 9109467b48Spatrick // 128-bit Temporary Registers 9209467b48Spatrick def KC0_#Index#_XYZW : R600Reg_128 <"KC0["#!add(Index, -128)#"].XYZW", 9309467b48Spatrick [!cast<Register>("KC0_"#Index#"_X"), 9409467b48Spatrick !cast<Register>("KC0_"#Index#"_Y"), 9509467b48Spatrick !cast<Register>("KC0_"#Index#"_Z"), 9609467b48Spatrick !cast<Register>("KC0_"#Index#"_W")], 9709467b48Spatrick Index>; 9809467b48Spatrick} 9909467b48Spatrick 10009467b48Spatrick// KCACHE_BANK1 10109467b48Spatrickforeach Index = 191-160 in { 10209467b48Spatrick foreach Chan = [ "X", "Y", "Z", "W" ] in { 10309467b48Spatrick // 32-bit Temporary Registers 10409467b48Spatrick def KC1_#Index#_#Chan : R600RegWithChan <"KC1["#!add(Index,-160)#"]."#Chan, Index, Chan>; 10509467b48Spatrick } 10609467b48Spatrick // 128-bit Temporary Registers 10709467b48Spatrick def KC1_#Index#_XYZW : R600Reg_128 <"KC1["#!add(Index, -160)#"].XYZW", 10809467b48Spatrick [!cast<Register>("KC1_"#Index#"_X"), 10909467b48Spatrick !cast<Register>("KC1_"#Index#"_Y"), 11009467b48Spatrick !cast<Register>("KC1_"#Index#"_Z"), 11109467b48Spatrick !cast<Register>("KC1_"#Index#"_W")], 11209467b48Spatrick Index>; 11309467b48Spatrick} 11409467b48Spatrick 11509467b48Spatrick 11609467b48Spatrick// Array Base Register holding input in FS 11709467b48Spatrickforeach Index = 448-480 in { 11809467b48Spatrick def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>; 11909467b48Spatrick} 12009467b48Spatrick 12109467b48Spatrick 12209467b48Spatrick// Special Registers 12309467b48Spatrick 12409467b48Spatrickdef OQA : R600Reg<"OQA", 219>; 12509467b48Spatrickdef OQB : R600Reg<"OQB", 220>; 12609467b48Spatrickdef OQAP : R600Reg<"OQAP", 221>; 12709467b48Spatrickdef OQBP : R600Reg<"OQAP", 222>; 12809467b48Spatrickdef LDS_DIRECT_A : R600Reg<"LDS_DIRECT_A", 223>; 12909467b48Spatrickdef LDS_DIRECT_B : R600Reg<"LDS_DIRECT_B", 224>; 13009467b48Spatrickdef ZERO : R600Reg<"0.0", 248>; 13109467b48Spatrickdef ONE : R600Reg<"1.0", 249>; 13209467b48Spatrickdef NEG_ONE : R600Reg<"-1.0", 249>; 13309467b48Spatrickdef ONE_INT : R600Reg<"1", 250>; 13409467b48Spatrickdef HALF : R600Reg<"0.5", 252>; 13509467b48Spatrickdef NEG_HALF : R600Reg<"-0.5", 252>; 13609467b48Spatrickdef ALU_LITERAL_X : R600RegWithChan<"literal.x", 253, "X">; 13709467b48Spatrickdef ALU_LITERAL_Y : R600RegWithChan<"literal.y", 253, "Y">; 13809467b48Spatrickdef ALU_LITERAL_Z : R600RegWithChan<"literal.z", 253, "Z">; 13909467b48Spatrickdef ALU_LITERAL_W : R600RegWithChan<"literal.w", 253, "W">; 14009467b48Spatrickdef PV_X : R600RegWithChan<"PV.X", 254, "X">; 14109467b48Spatrickdef PV_Y : R600RegWithChan<"PV.Y", 254, "Y">; 14209467b48Spatrickdef PV_Z : R600RegWithChan<"PV.Z", 254, "Z">; 14309467b48Spatrickdef PV_W : R600RegWithChan<"PV.W", 254, "W">; 14409467b48Spatrickdef PS: R600Reg<"PS", 255>; 14509467b48Spatrickdef PREDICATE_BIT : R600Reg<"PredicateBit", 0>; 14609467b48Spatrickdef PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>; 14709467b48Spatrickdef PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>; 14809467b48Spatrickdef PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>; 14909467b48Spatrickdef AR_X : R600Reg<"AR.x", 0>; 15009467b48Spatrickdef INDIRECT_BASE_ADDR : R600Reg <"INDIRECT_BASE_ADDR", 0>; 15109467b48Spatrick 15209467b48Spatrickdef R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32, 153*097a140dSpatrick (add (sequence "ArrayBase%u", 448, 480))> { 154*097a140dSpatrick let Weight = 0; 155*097a140dSpatrick} 15609467b48Spatrick// special registers for ALU src operands 15709467b48Spatrick// const buffer reference, SRCx_SEL contains index 15809467b48Spatrickdef ALU_CONST : R600Reg<"CBuf", 0>; 15909467b48Spatrick// interpolation param reference, SRCx_SEL contains index 16009467b48Spatrickdef ALU_PARAM : R600Reg<"Param", 0>; 16109467b48Spatrick 162*097a140dSpatricklet Weight = 0 in { 16309467b48Spatricklet isAllocatable = 0 in { 16409467b48Spatrick 16509467b48Spatrickdef R600_Addr : RegisterClass <"AMDGPU", [i32], 32, (add (sequence "Addr%u_X", 0, 127))>; 16609467b48Spatrick 16709467b48Spatrick// We only use Addr_[YZW] for vertical vectors. 16809467b48Spatrick// FIXME if we add more vertical vector registers we will need to ad more 16909467b48Spatrick// registers to these classes. 17009467b48Spatrickdef R600_Addr_Y : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Y)>; 17109467b48Spatrickdef R600_Addr_Z : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Z)>; 17209467b48Spatrickdef R600_Addr_W : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_W)>; 17309467b48Spatrick 17409467b48Spatrickdef R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32, 17509467b48Spatrick (add OQA, OQB, OQAP, OQBP, LDS_DIRECT_A, LDS_DIRECT_B)>; 17609467b48Spatrick 17709467b48Spatrickdef R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32, 17809467b48Spatrick (add (sequence "KC0_%u_X", 128, 159))>; 17909467b48Spatrick 18009467b48Spatrickdef R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32, 18109467b48Spatrick (add (sequence "KC0_%u_Y", 128, 159))>; 18209467b48Spatrick 18309467b48Spatrickdef R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32, 18409467b48Spatrick (add (sequence "KC0_%u_Z", 128, 159))>; 18509467b48Spatrick 18609467b48Spatrickdef R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32, 18709467b48Spatrick (add (sequence "KC0_%u_W", 128, 159))>; 18809467b48Spatrick 18909467b48Spatrickdef R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32, 19009467b48Spatrick (interleave R600_KC0_X, R600_KC0_Y, 19109467b48Spatrick R600_KC0_Z, R600_KC0_W)>; 19209467b48Spatrick 19309467b48Spatrickdef R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32, 19409467b48Spatrick (add (sequence "KC1_%u_X", 160, 191))>; 19509467b48Spatrick 19609467b48Spatrickdef R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32, 19709467b48Spatrick (add (sequence "KC1_%u_Y", 160, 191))>; 19809467b48Spatrick 19909467b48Spatrickdef R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32, 20009467b48Spatrick (add (sequence "KC1_%u_Z", 160, 191))>; 20109467b48Spatrick 20209467b48Spatrickdef R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32, 20309467b48Spatrick (add (sequence "KC1_%u_W", 160, 191))>; 20409467b48Spatrick 20509467b48Spatrickdef R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32, 20609467b48Spatrick (interleave R600_KC1_X, R600_KC1_Y, 20709467b48Spatrick R600_KC1_Z, R600_KC1_W)>; 20809467b48Spatrick 20909467b48Spatrick} // End isAllocatable = 0 21009467b48Spatrick 21109467b48Spatrickdef R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, 21209467b48Spatrick (add (sequence "T%u_X", 0, 127), AR_X)>; 21309467b48Spatrick 21409467b48Spatrickdef R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32, 21509467b48Spatrick (add (sequence "T%u_Y", 0, 127))>; 21609467b48Spatrick 21709467b48Spatrickdef R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32, 21809467b48Spatrick (add (sequence "T%u_Z", 0, 127))>; 21909467b48Spatrick 22009467b48Spatrickdef R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32, 22109467b48Spatrick (add (sequence "T%u_W", 0, 127))>; 22209467b48Spatrick 22309467b48Spatrickdef R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, 22409467b48Spatrick (interleave R600_TReg32_X, R600_TReg32_Y, 22509467b48Spatrick R600_TReg32_Z, R600_TReg32_W)>; 22609467b48Spatrick 22709467b48Spatrickdef R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add 22809467b48Spatrick R600_TReg32, 22909467b48Spatrick R600_ArrayBase, 23009467b48Spatrick R600_Addr, 23109467b48Spatrick R600_KC0, R600_KC1, 23209467b48Spatrick ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF, 23309467b48Spatrick ALU_CONST, ALU_PARAM, OQAP, INDIRECT_BASE_ADDR 23409467b48Spatrick )>; 23509467b48Spatrick 23609467b48Spatrickdef R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add 23709467b48Spatrick PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>; 23809467b48Spatrick 23909467b48Spatrickdef R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add 24009467b48Spatrick PREDICATE_BIT)>; 24109467b48Spatrick 24209467b48Spatrickdef R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, 24309467b48Spatrick (add (sequence "T%u_XYZW", 0, 127))> { 24409467b48Spatrick let CopyCost = -1; 24509467b48Spatrick} 24609467b48Spatrick 24709467b48Spatrickdef R600_Reg128Vertical : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, 24809467b48Spatrick (add V0123_W, V0123_Z, V0123_Y, V0123_X) 24909467b48Spatrick>; 25009467b48Spatrick 25109467b48Spatrickdef R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32, i64, f64], 64, 25209467b48Spatrick (add (sequence "T%u_XY", 0, 63))>; 25309467b48Spatrick 25409467b48Spatrickdef R600_Reg64Vertical : RegisterClass<"AMDGPU", [v2f32, v2i32], 64, 25509467b48Spatrick (add V01_X, V01_Y, V01_Z, V01_W, 25609467b48Spatrick V23_X, V23_Y, V23_Z, V23_W)>; 257*097a140dSpatrick} // End let Weight = 0 258