1//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the Hexagon target. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// Hexagon Subtarget features. 21//===----------------------------------------------------------------------===// 22 23// Hexagon Architectures 24include "HexagonDepArch.td" 25 26def ProcTinyCore: SubtargetFeature<"tinycore", "HexagonProcFamily", 27 "TinyCore", "Hexagon Tiny Core">; 28 29// Hexagon ISA Extensions 30def ExtensionZReg: SubtargetFeature<"zreg", "UseZRegOps", "true", 31 "Hexagon ZReg extension instructions">; 32 33def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion", 34 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">; 35def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion", 36 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions", 37 [ExtensionHVX]>; 38def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion", 39 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions", 40 [ExtensionHVX, ExtensionHVXV60]>; 41def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion", 42 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions", 43 [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62]>; 44def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion", 45 "Hexagon::ArchEnum::V66", "Hexagon HVX instructions", 46 [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, 47 ExtensionZReg]>; 48def ExtensionHVXV67: SubtargetFeature<"hvxv67", "HexagonHVXVersion", 49 "Hexagon::ArchEnum::V67", "Hexagon HVX instructions", 50 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66]>; 51def ExtensionHVXV68: SubtargetFeature<"hvxv68", "HexagonHVXVersion", 52 "Hexagon::ArchEnum::V68", "Hexagon HVX instructions", 53 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66, 54 ExtensionHVXV67]>; 55 56def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps", 57 "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>; 58def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps", 59 "true", "Hexagon HVX 128B instructions", [ExtensionHVX]>; 60 61def ExtensionAudio: SubtargetFeature<"audio", "UseAudioOps", "true", 62 "Hexagon Audio extension instructions">; 63 64def FeatureCompound: SubtargetFeature<"compound", "UseCompound", "true", 65 "Use compound instructions">; 66def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true", 67 "Support for instruction packets">; 68def FeaturePreV65: SubtargetFeature<"prev65", "HasPreV65", "true", 69 "Support features deprecated in v65">; 70def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", 71 "Use constant-extended calls">; 72def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false", 73 "Supports mem_noshuf feature">; 74def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true", 75 "Use memop instructions">; 76def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true", 77 "Support for new-value jumps", [FeaturePackets]>; 78def FeatureNVS: SubtargetFeature<"nvs", "UseNewValueStores", "true", 79 "Support for new-value stores", [FeaturePackets]>; 80def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true", 81 "Allow GP-relative addressing of global variables">; 82def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true", 83 "Enable generation of duplex instruction">; 84def FeatureUnsafeFP: SubtargetFeature<"unsafe-fp", "UseUnsafeMath", "true", 85 "Use unsafe FP math">; 86def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19", 87 "true", "Reserve register R19">; 88def FeatureNoreturnStackElim: SubtargetFeature<"noreturn-stack-elim", 89 "NoreturnStackElim", "true", 90 "Eliminate stack allocation in a noreturn function when possible">; 91 92//===----------------------------------------------------------------------===// 93// Hexagon Instruction Predicate Definitions. 94//===----------------------------------------------------------------------===// 95 96def UseMEMOPS : Predicate<"HST->useMemops()">; 97def UseHVX64B : Predicate<"HST->useHVX64BOps()">, 98 AssemblerPredicate<(all_of ExtensionHVX64B)>; 99def UseHVX128B : Predicate<"HST->useHVX128BOps()">, 100 AssemblerPredicate<(all_of ExtensionHVX128B)>; 101def UseHVX : Predicate<"HST->useHVXOps()">, 102 AssemblerPredicate<(all_of ExtensionHVXV60)>; 103def UseHVXV60 : Predicate<"HST->useHVXV60Ops()">, 104 AssemblerPredicate<(all_of ExtensionHVXV60)>; 105def UseHVXV62 : Predicate<"HST->useHVXV62Ops()">, 106 AssemblerPredicate<(all_of ExtensionHVXV62)>; 107def UseHVXV65 : Predicate<"HST->useHVXV65Ops()">, 108 AssemblerPredicate<(all_of ExtensionHVXV65)>; 109def UseHVXV66 : Predicate<"HST->useHVXV66Ops()">, 110 AssemblerPredicate<(all_of ExtensionHVXV66)>; 111def UseHVXV67 : Predicate<"HST->useHVXV67Ops()">, 112 AssemblerPredicate<(all_of ExtensionHVXV67)>; 113def UseHVXV68 : Predicate<"HST->useHVXV68Ops()">, 114 AssemblerPredicate<(all_of ExtensionHVXV68)>; 115def UseAudio : Predicate<"HST->useAudioOps()">, 116 AssemblerPredicate<(all_of ExtensionAudio)>; 117def UseZReg : Predicate<"HST->useZRegOps()">, 118 AssemblerPredicate<(all_of ExtensionZReg)>; 119def UseCompound : Predicate<"HST->useCompound()">; 120def HasPreV65 : Predicate<"HST->hasPreV65()">, 121 AssemblerPredicate<(all_of FeaturePreV65)>; 122def HasMemNoShuf : Predicate<"HST->hasMemNoShuf()">, 123 AssemblerPredicate<(all_of FeatureMemNoShuf)>; 124def UseUnsafeMath : Predicate<"HST->useUnsafeMath()">; 125def NotOptTinyCore : Predicate<"!HST->isTinyCore() ||" 126 "MF->getFunction().hasOptSize()"> { 127 let RecomputePerFunction = 1; 128} 129def UseSmallData : Predicate<"HST->useSmallData()">; 130 131def Hvx64: HwMode<"+hvx-length64b">; 132def Hvx128: HwMode<"+hvx-length128b">; 133 134//===----------------------------------------------------------------------===// 135// Classes used for relation maps. 136//===----------------------------------------------------------------------===// 137 138// The classes below should remain in hierarchical order... 139class ImmRegShl; 140// ImmRegRel - Filter class used to relate instructions having reg-reg form 141// with their reg-imm counterparts. 142class ImmRegRel; 143// PredRel - Filter class used to relate non-predicated instructions with their 144// predicated forms. 145class PredRel; 146class PredNewRel: PredRel; 147// NewValueRel - Filter class used to relate regular store instructions with 148// their new-value store form. 149class NewValueRel: PredNewRel; 150class AddrModeRel: NewValueRel; 151class PostInc_BaseImm; 152class IntrinsicsRel; 153// ... through here. 154 155//===----------------------------------------------------------------------===// 156// Generate mapping table to relate non-predicate instructions with their 157// predicated formats - true and false. 158// 159 160def getPredOpcode : InstrMapping { 161 let FilterClass = "PredRel"; 162 // Instructions with the same BaseOpcode and isNVStore values form a row. 163 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"]; 164 // Instructions with the same predicate sense form a column. 165 let ColFields = ["PredSense"]; 166 // The key column is the unpredicated instructions. 167 let KeyCol = [""]; 168 // Value columns are PredSense=true and PredSense=false 169 let ValueCols = [["true"], ["false"]]; 170} 171 172//===----------------------------------------------------------------------===// 173// Generate mapping table to relate predicate-true instructions with their 174// predicate-false forms 175// 176def getFalsePredOpcode : InstrMapping { 177 let FilterClass = "PredRel"; 178 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"]; 179 let ColFields = ["PredSense"]; 180 let KeyCol = ["true"]; 181 let ValueCols = [["false"]]; 182} 183 184//===----------------------------------------------------------------------===// 185// Generate mapping table to relate predicate-false instructions with their 186// predicate-true forms 187// 188def getTruePredOpcode : InstrMapping { 189 let FilterClass = "PredRel"; 190 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"]; 191 let ColFields = ["PredSense"]; 192 let KeyCol = ["false"]; 193 let ValueCols = [["true"]]; 194} 195 196//===----------------------------------------------------------------------===// 197// Generate mapping table to relate predicated instructions with their .new 198// format. 199// 200def getPredNewOpcode : InstrMapping { 201 let FilterClass = "PredNewRel"; 202 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; 203 let ColFields = ["PNewValue"]; 204 let KeyCol = [""]; 205 let ValueCols = [["new"]]; 206} 207 208//===----------------------------------------------------------------------===// 209// Generate mapping table to relate .new predicated instructions with their old 210// format. 211// 212def getPredOldOpcode : InstrMapping { 213 let FilterClass = "PredNewRel"; 214 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; 215 let ColFields = ["PNewValue"]; 216 let KeyCol = ["new"]; 217 let ValueCols = [[""]]; 218} 219 220//===----------------------------------------------------------------------===// 221// Generate mapping table to relate store instructions with their new-value 222// format. 223// 224def getNewValueOpcode : InstrMapping { 225 let FilterClass = "NewValueRel"; 226 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"]; 227 let ColFields = ["NValueST"]; 228 let KeyCol = ["false"]; 229 let ValueCols = [["true"]]; 230} 231 232//===----------------------------------------------------------------------===// 233// Generate mapping table to relate new-value store instructions with their old 234// format. 235// 236def getNonNVStore : InstrMapping { 237 let FilterClass = "NewValueRel"; 238 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"]; 239 let ColFields = ["NValueST"]; 240 let KeyCol = ["true"]; 241 let ValueCols = [["false"]]; 242} 243 244def changeAddrMode_abs_io: InstrMapping { 245 let FilterClass = "AddrModeRel"; 246 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", 247 "isFloat"]; 248 let ColFields = ["addrMode"]; 249 let KeyCol = ["Absolute"]; 250 let ValueCols = [["BaseImmOffset"]]; 251} 252 253def changeAddrMode_io_abs: InstrMapping { 254 let FilterClass = "AddrModeRel"; 255 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", 256 "isFloat"]; 257 let ColFields = ["addrMode"]; 258 let KeyCol = ["BaseImmOffset"]; 259 let ValueCols = [["Absolute"]]; 260} 261 262def changeAddrMode_io_rr: InstrMapping { 263 let FilterClass = "AddrModeRel"; 264 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 265 let ColFields = ["addrMode"]; 266 let KeyCol = ["BaseImmOffset"]; 267 let ValueCols = [["BaseRegOffset"]]; 268} 269 270def changeAddrMode_rr_io: InstrMapping { 271 let FilterClass = "AddrModeRel"; 272 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 273 let ColFields = ["addrMode"]; 274 let KeyCol = ["BaseRegOffset"]; 275 let ValueCols = [["BaseImmOffset"]]; 276} 277 278def changeAddrMode_pi_io: InstrMapping { 279 let FilterClass = "PostInc_BaseImm"; 280 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 281 let ColFields = ["addrMode"]; 282 let KeyCol = ["PostInc"]; 283 let ValueCols = [["BaseImmOffset"]]; 284} 285 286def changeAddrMode_io_pi: InstrMapping { 287 let FilterClass = "PostInc_BaseImm"; 288 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 289 let ColFields = ["addrMode"]; 290 let KeyCol = ["BaseImmOffset"]; 291 let ValueCols = [["PostInc"]]; 292} 293 294def changeAddrMode_rr_ur: InstrMapping { 295 let FilterClass = "ImmRegShl"; 296 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 297 let ColFields = ["addrMode"]; 298 let KeyCol = ["BaseRegOffset"]; 299 let ValueCols = [["BaseLongOffset"]]; 300} 301 302def changeAddrMode_ur_rr : InstrMapping { 303 let FilterClass = "ImmRegShl"; 304 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 305 let ColFields = ["addrMode"]; 306 let KeyCol = ["BaseLongOffset"]; 307 let ValueCols = [["BaseRegOffset"]]; 308} 309 310def getRegForm : InstrMapping { 311 let FilterClass = "ImmRegRel"; 312 let RowFields = ["CextOpcode", "PredSense", "PNewValue"]; 313 let ColFields = ["InputType"]; 314 let KeyCol = ["imm"]; 315 let ValueCols = [["reg"]]; 316} 317 318def notTakenBranchPrediction : InstrMapping { 319 let FilterClass = "PredRel"; 320 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"]; 321 let ColFields = ["isBrTaken"]; 322 let KeyCol = ["true"]; 323 let ValueCols = [["false"]]; 324} 325 326def takenBranchPrediction : InstrMapping { 327 let FilterClass = "PredRel"; 328 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"]; 329 let ColFields = ["isBrTaken"]; 330 let KeyCol = ["false"]; 331 let ValueCols = [["true"]]; 332} 333 334def getRealHWInstr : InstrMapping { 335 let FilterClass = "IntrinsicsRel"; 336 let RowFields = ["BaseOpcode"]; 337 let ColFields = ["InstrType"]; 338 let KeyCol = ["Pseudo"]; 339 let ValueCols = [["Pseudo"], ["Real"]]; 340} 341//===----------------------------------------------------------------------===// 342// Register File, Instruction Descriptions 343//===----------------------------------------------------------------------===// 344include "HexagonSchedule.td" 345include "HexagonRegisterInfo.td" 346include "HexagonOperands.td" 347include "HexagonDepOperands.td" 348include "HexagonDepITypes.td" 349include "HexagonInstrFormats.td" 350include "HexagonDepInstrFormats.td" 351include "HexagonDepInstrInfo.td" 352include "HexagonCallingConv.td" 353include "HexagonPseudo.td" 354include "HexagonPatterns.td" 355include "HexagonPatternsHVX.td" 356include "HexagonPatternsV65.td" 357include "HexagonDepMappings.td" 358include "HexagonIntrinsics.td" 359 360def HexagonInstrInfo : InstrInfo; 361 362//===----------------------------------------------------------------------===// 363// Hexagon processors supported. 364//===----------------------------------------------------------------------===// 365 366class Proc<string Name, SchedMachineModel Model, 367 list<SubtargetFeature> Features> 368 : ProcessorModel<Name, Model, Features>; 369 370def : Proc<"generic", HexagonModelV60, 371 [ArchV5, ArchV55, ArchV60, 372 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, 373 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; 374def : Proc<"hexagonv5", HexagonModelV5, 375 [ArchV5, 376 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, 377 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; 378def : Proc<"hexagonv55", HexagonModelV55, 379 [ArchV5, ArchV55, 380 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, 381 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; 382def : Proc<"hexagonv60", HexagonModelV60, 383 [ArchV5, ArchV55, ArchV60, 384 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, 385 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; 386def : Proc<"hexagonv62", HexagonModelV62, 387 [ArchV5, ArchV55, ArchV60, ArchV62, 388 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, 389 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; 390def : Proc<"hexagonv65", HexagonModelV65, 391 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, 392 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, 393 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; 394def : Proc<"hexagonv66", HexagonModelV66, 395 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, 396 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, 397 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; 398def : Proc<"hexagonv67", HexagonModelV67, 399 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, 400 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, 401 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; 402def : Proc<"hexagonv68", HexagonModelV68, 403 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, 404 ArchV68, 405 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, 406 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; 407// Need to update the correct features for tiny core. 408// Disable NewValueJumps since the packetizer is unable to handle a packet with 409// a new value jump and another SLOT0 instruction. 410def : Proc<"hexagonv67t", HexagonModelV67T, 411 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, 412 ProcTinyCore, ExtensionAudio, 413 FeatureCompound, FeatureMemNoShuf, FeatureMemops, 414 FeatureNVS, FeaturePackets, FeatureSmallData]>; 415 416//===----------------------------------------------------------------------===// 417// Declare the target which we are implementing 418//===----------------------------------------------------------------------===// 419 420def HexagonAsmParser : AsmParser { 421 let ShouldEmitMatchRegisterAltName = 1; 422 bit HasMnemonicFirst = 0; 423} 424 425def HexagonAsmParserVariant : AsmParserVariant { 426 int Variant = 0; 427 string TokenizingCharacters = "#()=:.<>!+*-|^&"; 428 string BreakCharacters = ""; 429} 430 431def HexagonAsmWriter : AsmWriter { 432 string AsmWriterClassName = "InstPrinter"; 433 bit isMCAsmWriter = 1; 434} 435 436def Hexagon : Target { 437 let InstructionSet = HexagonInstrInfo; 438 let AssemblyParsers = [HexagonAsmParser]; 439 let AssemblyParserVariants = [HexagonAsmParserVariant]; 440 let AssemblyWriters = [HexagonAsmWriter]; 441 let AllowRegisterRenaming = 1; 442} 443