109467b48Spatrick//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 209467b48Spatrick// 309467b48Spatrick// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 409467b48Spatrick// See https://llvm.org/LICENSE.txt for license information. 509467b48Spatrick// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 609467b48Spatrick// 709467b48Spatrick//===----------------------------------------------------------------------===// 809467b48Spatrick// 909467b48Spatrick// This file contains the Mips implementation of the TargetInstrInfo class. 1009467b48Spatrick// 1109467b48Spatrick//===----------------------------------------------------------------------===// 1209467b48Spatrick 1309467b48Spatrick 1409467b48Spatrick//===----------------------------------------------------------------------===// 1509467b48Spatrick// Mips profiles and nodes 1609467b48Spatrick//===----------------------------------------------------------------------===// 1709467b48Spatrick 1809467b48Spatrickdef SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 1909467b48Spatrickdef SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 2009467b48Spatrick SDTCisSameAs<1, 2>, 2109467b48Spatrick SDTCisSameAs<3, 4>, 2209467b48Spatrick SDTCisInt<4>]>; 2309467b48Spatrickdef SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 2409467b48Spatrickdef SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 2509467b48Spatrickdef SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>; 2609467b48Spatrickdef SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 2709467b48Spatrick SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 2809467b48Spatrickdef SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 2909467b48Spatrick SDTCisSameAs<1, 2>]>; 3009467b48Spatrickdef SDT_MipsMAddMSub : SDTypeProfile<1, 3, 3109467b48Spatrick [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 3209467b48Spatrick SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 3309467b48Spatrickdef SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 3409467b48Spatrick 3509467b48Spatrickdef SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 3609467b48Spatrick 3709467b48Spatrickdef SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 3809467b48Spatrick 3909467b48Spatrickdef SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 4009467b48Spatrick SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 4109467b48Spatrickdef SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 4209467b48Spatrick SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 4309467b48Spatrick SDTCisSameAs<0, 4>]>; 4409467b48Spatrick 4509467b48Spatrickdef SDTMipsLoadLR : SDTypeProfile<1, 2, 4609467b48Spatrick [SDTCisInt<0>, SDTCisPtrTy<1>, 4709467b48Spatrick SDTCisSameAs<0, 2>]>; 4809467b48Spatrick 4909467b48Spatrick// Call 5009467b48Spatrickdef MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 5109467b48Spatrick [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 5209467b48Spatrick SDNPVariadic]>; 5309467b48Spatrick 5409467b48Spatrick// Tail call 5509467b48Spatrickdef MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 5609467b48Spatrick [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 5709467b48Spatrick 5809467b48Spatrick// Hi and Lo nodes are used to handle global addresses. Used on 5909467b48Spatrick// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 6009467b48Spatrick// static model. (nothing to do with Mips Registers Hi and Lo) 6109467b48Spatrick 6209467b48Spatrick// Hi is the odd node out, on MIPS64 it can expand to either daddiu when 6309467b48Spatrick// using static relocations with 64 bit symbols, or lui when using 32 bit 6409467b48Spatrick// symbols. 6509467b48Spatrickdef MipsHigher : SDNode<"MipsISD::Higher", SDTIntUnaryOp>; 6609467b48Spatrickdef MipsHighest : SDNode<"MipsISD::Highest", SDTIntUnaryOp>; 6709467b48Spatrickdef MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 6809467b48Spatrickdef MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 6909467b48Spatrick 7009467b48Spatrickdef MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 7109467b48Spatrick 7209467b48Spatrick// Hi node for accessing the GOT. 7309467b48Spatrickdef MipsGotHi : SDNode<"MipsISD::GotHi", SDTIntUnaryOp>; 7409467b48Spatrick 7509467b48Spatrick// Hi node for handling TLS offsets 7609467b48Spatrickdef MipsTlsHi : SDNode<"MipsISD::TlsHi", SDTIntUnaryOp>; 7709467b48Spatrick 7809467b48Spatrick// Thread pointer 7909467b48Spatrickdef MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 8009467b48Spatrick 8109467b48Spatrick// Return 8209467b48Spatrickdef MipsRet : SDNode<"MipsISD::Ret", SDTNone, 8309467b48Spatrick [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 8409467b48Spatrick 8509467b48Spatrickdef MipsERet : SDNode<"MipsISD::ERet", SDTNone, 8609467b48Spatrick [SDNPHasChain, SDNPOptInGlue, SDNPSideEffect]>; 8709467b48Spatrick 8809467b48Spatrick// These are target-independent nodes, but have target-specific formats. 8909467b48Spatrickdef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 9009467b48Spatrick [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 9109467b48Spatrickdef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 9209467b48Spatrick [SDNPHasChain, SDNPSideEffect, 9309467b48Spatrick SDNPOptInGlue, SDNPOutGlue]>; 9409467b48Spatrick 9509467b48Spatrick// Nodes used to extract LO/HI registers. 9609467b48Spatrickdef MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>; 9709467b48Spatrickdef MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>; 9809467b48Spatrick 9909467b48Spatrick// Node used to insert 32-bit integers to LOHI register pair. 10009467b48Spatrickdef MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>; 10109467b48Spatrick 10209467b48Spatrick// Mult nodes. 10309467b48Spatrickdef MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 10409467b48Spatrickdef MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 10509467b48Spatrick 10609467b48Spatrick// MAdd*/MSub* nodes 10709467b48Spatrickdef MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 10809467b48Spatrickdef MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 10909467b48Spatrickdef MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 11009467b48Spatrickdef MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 11109467b48Spatrick 11209467b48Spatrick// DivRem(u) nodes 11309467b48Spatrickdef MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 11409467b48Spatrickdef MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 11509467b48Spatrickdef MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 11609467b48Spatrick [SDNPOutGlue]>; 11709467b48Spatrickdef MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 11809467b48Spatrick [SDNPOutGlue]>; 11909467b48Spatrick 12009467b48Spatrick// Target constant nodes that are not part of any isel patterns and remain 12109467b48Spatrick// unchanged can cause instructions with illegal operands to be emitted. 12209467b48Spatrick// Wrapper node patterns give the instruction selector a chance to replace 12309467b48Spatrick// target constant nodes that would otherwise remain unchanged with ADDiu 12409467b48Spatrick// nodes. Without these wrapper node patterns, the following conditional move 12509467b48Spatrick// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 12609467b48Spatrick// compiled: 12709467b48Spatrick// movn %got(d)($gp), %got(c)($gp), $4 12809467b48Spatrick// This instruction is illegal since movn can take only register operands. 12909467b48Spatrick 13009467b48Spatrickdef MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 13109467b48Spatrick 13209467b48Spatrickdef MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 13309467b48Spatrick 13409467b48Spatrickdef MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 13509467b48Spatrickdef MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 13609467b48Spatrickdef MipsCIns : SDNode<"MipsISD::CIns", SDT_Ext>; 13709467b48Spatrick 13809467b48Spatrickdef MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 13909467b48Spatrick [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 14009467b48Spatrickdef MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 14109467b48Spatrick [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 14209467b48Spatrickdef MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 14309467b48Spatrick [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 14409467b48Spatrickdef MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 14509467b48Spatrick [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 14609467b48Spatrickdef MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 14709467b48Spatrick [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 14809467b48Spatrickdef MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 14909467b48Spatrick [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 15009467b48Spatrickdef MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 15109467b48Spatrick [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 15209467b48Spatrickdef MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 15309467b48Spatrick [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 15409467b48Spatrick 15509467b48Spatrick//===----------------------------------------------------------------------===// 15609467b48Spatrick// Mips Instruction Predicate Definitions. 15709467b48Spatrick//===----------------------------------------------------------------------===// 15809467b48Spatrickdef HasMips2 : Predicate<"Subtarget->hasMips2()">, 159097a140dSpatrick AssemblerPredicate<(all_of FeatureMips2)>; 16009467b48Spatrickdef HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">, 161097a140dSpatrick AssemblerPredicate<(all_of FeatureMips3_32)>; 16209467b48Spatrickdef HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">, 163097a140dSpatrick AssemblerPredicate<(all_of FeatureMips3_32r2)>; 16409467b48Spatrickdef HasMips3 : Predicate<"Subtarget->hasMips3()">, 165097a140dSpatrick AssemblerPredicate<(all_of FeatureMips3)>; 16609467b48Spatrickdef NotMips3 : Predicate<"!Subtarget->hasMips3()">, 167097a140dSpatrick AssemblerPredicate<(all_of (not FeatureMips3))>; 16809467b48Spatrickdef HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">, 169097a140dSpatrick AssemblerPredicate<(all_of FeatureMips4_32)>; 17009467b48Spatrickdef NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">, 171097a140dSpatrick AssemblerPredicate<(all_of (not FeatureMips4_32))>; 17209467b48Spatrickdef HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">, 173097a140dSpatrick AssemblerPredicate<(all_of FeatureMips4_32r2)>; 17409467b48Spatrickdef HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">, 175097a140dSpatrick AssemblerPredicate<(all_of FeatureMips5_32r2)>; 17609467b48Spatrickdef HasMips32 : Predicate<"Subtarget->hasMips32()">, 177097a140dSpatrick AssemblerPredicate<(all_of FeatureMips32)>; 17809467b48Spatrickdef HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">, 179097a140dSpatrick AssemblerPredicate<(all_of FeatureMips32r2)>; 18009467b48Spatrickdef HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">, 181097a140dSpatrick AssemblerPredicate<(all_of FeatureMips32r5)>; 18209467b48Spatrickdef HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">, 183097a140dSpatrick AssemblerPredicate<(all_of FeatureMips32r6)>; 18409467b48Spatrickdef NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">, 185097a140dSpatrick AssemblerPredicate<(all_of (not FeatureMips32r6))>; 18609467b48Spatrickdef IsGP64bit : Predicate<"Subtarget->isGP64bit()">, 187097a140dSpatrick AssemblerPredicate<(all_of FeatureGP64Bit)>; 18809467b48Spatrickdef IsGP32bit : Predicate<"!Subtarget->isGP64bit()">, 189097a140dSpatrick AssemblerPredicate<(all_of (not FeatureGP64Bit))>; 19009467b48Spatrickdef IsPTR64bit : Predicate<"Subtarget->isABI_N64()">, 191097a140dSpatrick AssemblerPredicate<(all_of FeaturePTR64Bit)>; 19209467b48Spatrickdef IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">, 193097a140dSpatrick AssemblerPredicate<(all_of (not FeaturePTR64Bit))>; 19409467b48Spatrickdef HasMips64 : Predicate<"Subtarget->hasMips64()">, 195097a140dSpatrick AssemblerPredicate<(all_of FeatureMips64)>; 19609467b48Spatrickdef NotMips64 : Predicate<"!Subtarget->hasMips64()">, 197097a140dSpatrick AssemblerPredicate<(all_of (not FeatureMips64))>; 19809467b48Spatrickdef HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">, 199097a140dSpatrick AssemblerPredicate<(all_of FeatureMips64r2)>; 20009467b48Spatrickdef HasMips64r5 : Predicate<"Subtarget->hasMips64r5()">, 201097a140dSpatrick AssemblerPredicate<(all_of FeatureMips64r5)>; 20209467b48Spatrickdef HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">, 203097a140dSpatrick AssemblerPredicate<(all_of FeatureMips64r6)>; 20409467b48Spatrickdef NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">, 205097a140dSpatrick AssemblerPredicate<(all_of (not FeatureMips64r6))>; 20609467b48Spatrickdef InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, 207097a140dSpatrick AssemblerPredicate<(all_of FeatureMips16)>; 20809467b48Spatrickdef NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">, 209097a140dSpatrick AssemblerPredicate<(all_of (not FeatureMips16))>; 21009467b48Spatrickdef HasCnMips : Predicate<"Subtarget->hasCnMips()">, 211097a140dSpatrick AssemblerPredicate<(all_of FeatureCnMips)>; 21209467b48Spatrickdef NotCnMips : Predicate<"!Subtarget->hasCnMips()">, 213097a140dSpatrick AssemblerPredicate<(all_of (not FeatureCnMips))>; 21409467b48Spatrickdef HasCnMipsP : Predicate<"Subtarget->hasCnMipsP()">, 215097a140dSpatrick AssemblerPredicate<(all_of FeatureCnMipsP)>; 21609467b48Spatrickdef NotCnMipsP : Predicate<"!Subtarget->hasCnMipsP()">, 217097a140dSpatrick AssemblerPredicate<(all_of (not FeatureCnMipsP))>; 21809467b48Spatrickdef IsSym32 : Predicate<"Subtarget->hasSym32()">, 219097a140dSpatrick AssemblerPredicate<(all_of FeatureSym32)>; 22009467b48Spatrickdef IsSym64 : Predicate<"!Subtarget->hasSym32()">, 221097a140dSpatrick AssemblerPredicate<(all_of (not FeatureSym32))>; 22209467b48Spatrickdef IsN64 : Predicate<"Subtarget->isABI_N64()">; 22309467b48Spatrickdef IsNotN64 : Predicate<"!Subtarget->isABI_N64()">; 22409467b48Spatrickdef RelocNotPIC : Predicate<"!TM.isPositionIndependent()">; 22509467b48Spatrickdef RelocPIC : Predicate<"TM.isPositionIndependent()">; 22609467b48Spatrickdef NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; 22709467b48Spatrickdef UseAbs : Predicate<"Subtarget->inAbs2008Mode() ||" 22809467b48Spatrick "TM.Options.NoNaNsFPMath">; 22909467b48Spatrickdef HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">, 230097a140dSpatrick AssemblerPredicate<(all_of (not FeatureMips16))>; 23109467b48Spatrickdef NotDSP : Predicate<"!Subtarget->hasDSP()">; 23209467b48Spatrickdef InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">, 233097a140dSpatrick AssemblerPredicate<(all_of FeatureMicroMips)>; 23409467b48Spatrickdef NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">, 235097a140dSpatrick AssemblerPredicate<(all_of (not FeatureMicroMips))>; 23609467b48Spatrickdef IsLE : Predicate<"Subtarget->isLittle()">; 23709467b48Spatrickdef IsBE : Predicate<"!Subtarget->isLittle()">; 23809467b48Spatrickdef IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 239097a140dSpatrickdef UseTCCInDIV : AssemblerPredicate<(all_of FeatureUseTCCInDIV)>; 24009467b48Spatrickdef HasEVA : Predicate<"Subtarget->hasEVA()">, 241097a140dSpatrick AssemblerPredicate<(all_of FeatureEVA)>; 24209467b48Spatrickdef HasMSA : Predicate<"Subtarget->hasMSA()">, 243097a140dSpatrick AssemblerPredicate<(all_of FeatureMSA)>; 24409467b48Spatrickdef HasMadd4 : Predicate<"!Subtarget->disableMadd4()">, 245a0747c9fSpatrick AssemblerPredicate<(all_of (not FeatureNoMadd4))>; 24609467b48Spatrickdef HasMT : Predicate<"Subtarget->hasMT()">, 247097a140dSpatrick AssemblerPredicate<(all_of FeatureMT)>; 24809467b48Spatrickdef UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">, 249097a140dSpatrick AssemblerPredicate<(all_of FeatureUseIndirectJumpsHazard)>; 25009467b48Spatrickdef NoIndirectJumpGuards : Predicate<"!Subtarget->useIndirectJumpsHazard()">, 251097a140dSpatrick AssemblerPredicate<(all_of (not FeatureUseIndirectJumpsHazard))>; 25209467b48Spatrickdef HasCRC : Predicate<"Subtarget->hasCRC()">, 253097a140dSpatrick AssemblerPredicate<(all_of FeatureCRC)>; 25409467b48Spatrickdef HasVirt : Predicate<"Subtarget->hasVirt()">, 255097a140dSpatrick AssemblerPredicate<(all_of FeatureVirt)>; 25609467b48Spatrickdef HasGINV : Predicate<"Subtarget->hasGINV()">, 257097a140dSpatrick AssemblerPredicate<(all_of FeatureGINV)>; 25809467b48Spatrick// TODO: Add support for FPOpFusion::Standard 25909467b48Spatrickdef AllowFPOpFusion : Predicate<"TM.Options.AllowFPOpFusion ==" 26009467b48Spatrick " FPOpFusion::Fast">; 26109467b48Spatrick//===----------------------------------------------------------------------===// 26209467b48Spatrick// Mips GPR size adjectives. 26309467b48Spatrick// They are mutually exclusive. 26409467b48Spatrick//===----------------------------------------------------------------------===// 26509467b48Spatrick 26609467b48Spatrickclass GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; } 26709467b48Spatrickclass GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; } 26809467b48Spatrick 26909467b48Spatrickclass PTR_32 { list<Predicate> PTRPredicates = [IsPTR32bit]; } 27009467b48Spatrickclass PTR_64 { list<Predicate> PTRPredicates = [IsPTR64bit]; } 27109467b48Spatrick 27209467b48Spatrick//===----------------------------------------------------------------------===// 27309467b48Spatrick// Mips Symbol size adjectives. 27409467b48Spatrick// They are mutally exculsive. 27509467b48Spatrick//===----------------------------------------------------------------------===// 27609467b48Spatrick 27709467b48Spatrickclass SYM_32 { list<Predicate> SYMPredicates = [IsSym32]; } 27809467b48Spatrickclass SYM_64 { list<Predicate> SYMPredicates = [IsSym64]; } 27909467b48Spatrick 28009467b48Spatrick//===----------------------------------------------------------------------===// 28109467b48Spatrick// Mips ISA/ASE membership and instruction group membership adjectives. 28209467b48Spatrick// They are mutually exclusive. 28309467b48Spatrick//===----------------------------------------------------------------------===// 28409467b48Spatrick 28509467b48Spatrick// FIXME: I'd prefer to use additive predicates to build the instruction sets 28609467b48Spatrick// but we are short on assembler feature bits at the moment. Using a 28709467b48Spatrick// subtractive predicate will hopefully keep us under the 32 predicate 28809467b48Spatrick// limit long enough to develop an alternative way to handle P1||P2 28909467b48Spatrick// predicates. 29009467b48Spatrickclass ISA_MIPS1 { 29109467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 29209467b48Spatrick} 29309467b48Spatrickclass ISA_MIPS1_NOT_MIPS3 { 29409467b48Spatrick list<Predicate> InsnPredicates = [NotMips3]; 29509467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 29609467b48Spatrick} 29709467b48Spatrickclass ISA_MIPS1_NOT_4_32 { 29809467b48Spatrick list<Predicate> InsnPredicates = [NotMips4_32]; 29909467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 30009467b48Spatrick} 30109467b48Spatrickclass ISA_MIPS1_NOT_32R6_64R6 { 30209467b48Spatrick list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6]; 30309467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 30409467b48Spatrick} 30509467b48Spatrickclass ISA_MIPS2 { 30609467b48Spatrick list<Predicate> InsnPredicates = [HasMips2]; 30709467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 30809467b48Spatrick} 30909467b48Spatrickclass ISA_MIPS2_NOT_32R6_64R6 { 31009467b48Spatrick list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6]; 31109467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 31209467b48Spatrick} 31309467b48Spatrickclass ISA_MIPS3 { 31409467b48Spatrick list<Predicate> InsnPredicates = [HasMips3]; 31509467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 31609467b48Spatrick} 31709467b48Spatrickclass ISA_MIPS3_NOT_32R6_64R6 { 31809467b48Spatrick list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6]; 31909467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 32009467b48Spatrick} 32109467b48Spatrickclass ISA_MIPS32 { 32209467b48Spatrick list<Predicate> InsnPredicates = [HasMips32]; 32309467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 32409467b48Spatrick} 32509467b48Spatrickclass ISA_MIPS32_NOT_32R6_64R6 { 32609467b48Spatrick list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6]; 32709467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 32809467b48Spatrick} 32909467b48Spatrickclass ISA_MIPS32R2 { 33009467b48Spatrick list<Predicate> InsnPredicates = [HasMips32r2]; 33109467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 33209467b48Spatrick} 33309467b48Spatrickclass ISA_MIPS32R2_NOT_32R6_64R6 { 33409467b48Spatrick list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6]; 33509467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 33609467b48Spatrick} 33709467b48Spatrickclass ISA_MIPS32R5 { 33809467b48Spatrick list<Predicate> InsnPredicates = [HasMips32r5]; 33909467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 34009467b48Spatrick} 34109467b48Spatrickclass ISA_MIPS64 { 34209467b48Spatrick list<Predicate> InsnPredicates = [HasMips64]; 34309467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 34409467b48Spatrick} 34509467b48Spatrickclass ISA_MIPS64_NOT_64R6 { 34609467b48Spatrick list<Predicate> InsnPredicates = [HasMips64, NotMips64r6]; 34709467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 34809467b48Spatrick} 34909467b48Spatrickclass ISA_MIPS64R2 { 35009467b48Spatrick list<Predicate> InsnPredicates = [HasMips64r2]; 35109467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 35209467b48Spatrick} 35309467b48Spatrickclass ISA_MIPS64R5 { 35409467b48Spatrick list<Predicate> InsnPredicates = [HasMips64r5]; 35509467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 35609467b48Spatrick} 35709467b48Spatrickclass ISA_MIPS32R6 { 35809467b48Spatrick list<Predicate> InsnPredicates = [HasMips32r6]; 35909467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 36009467b48Spatrick} 36109467b48Spatrickclass ISA_MIPS64R6 { 36209467b48Spatrick list<Predicate> InsnPredicates = [HasMips64r6]; 36309467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 36409467b48Spatrick} 36509467b48Spatrickclass ISA_MICROMIPS { 36609467b48Spatrick list<Predicate> EncodingPredicates = [InMicroMips]; 36709467b48Spatrick} 36809467b48Spatrickclass ISA_MICROMIPS32R5 { 36909467b48Spatrick list<Predicate> InsnPredicates = [HasMips32r5]; 37009467b48Spatrick list<Predicate> EncodingPredicates = [InMicroMips]; 37109467b48Spatrick} 37209467b48Spatrickclass ISA_MICROMIPS32R6 { 37309467b48Spatrick list<Predicate> InsnPredicates = [HasMips32r6]; 37409467b48Spatrick list<Predicate> EncodingPredicates = [InMicroMips]; 37509467b48Spatrick} 37609467b48Spatrickclass ISA_MICROMIPS64R6 { 37709467b48Spatrick list<Predicate> InsnPredicates = [HasMips64r6]; 37809467b48Spatrick list<Predicate> EncodingPredicates = [InMicroMips]; 37909467b48Spatrick} 38009467b48Spatrickclass ISA_MICROMIPS32_NOT_MIPS32R6 { 38109467b48Spatrick list<Predicate> InsnPredicates = [NotMips32r6]; 38209467b48Spatrick list<Predicate> EncodingPredicates = [InMicroMips]; 38309467b48Spatrick} 38409467b48Spatrickclass ASE_EVA { list<Predicate> ASEPredicate = [HasEVA]; } 38509467b48Spatrick 38609467b48Spatrick// The portions of MIPS-III that were also added to MIPS32 38709467b48Spatrickclass INSN_MIPS3_32 { 38809467b48Spatrick list<Predicate> InsnPredicates = [HasMips3_32]; 38909467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 39009467b48Spatrick} 39109467b48Spatrick 39209467b48Spatrick// The portions of MIPS-III that were also added to MIPS32 but were removed in 39309467b48Spatrick// MIPS32r6 and MIPS64r6. 39409467b48Spatrickclass INSN_MIPS3_32_NOT_32R6_64R6 { 39509467b48Spatrick list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6]; 39609467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 39709467b48Spatrick} 39809467b48Spatrick 39909467b48Spatrick// The portions of MIPS-III that were also added to MIPS32 40009467b48Spatrickclass INSN_MIPS3_32R2 { 40109467b48Spatrick list<Predicate> InsnPredicates = [HasMips3_32r2]; 40209467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 40309467b48Spatrick} 40409467b48Spatrick 40509467b48Spatrick// The portions of MIPS-IV that were also added to MIPS32. 40609467b48Spatrickclass INSN_MIPS4_32 { 40709467b48Spatrick list <Predicate> InsnPredicates = [HasMips4_32]; 40809467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 40909467b48Spatrick} 41009467b48Spatrick 41109467b48Spatrick// The portions of MIPS-IV that were also added to MIPS32 but were removed in 41209467b48Spatrick// MIPS32r6 and MIPS64r6. 41309467b48Spatrickclass INSN_MIPS4_32_NOT_32R6_64R6 { 41409467b48Spatrick list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6]; 41509467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 41609467b48Spatrick} 41709467b48Spatrick 41809467b48Spatrick// The portions of MIPS-IV that were also added to MIPS32r2 but were removed in 41909467b48Spatrick// MIPS32r6 and MIPS64r6. 42009467b48Spatrickclass INSN_MIPS4_32R2_NOT_32R6_64R6 { 42109467b48Spatrick list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6]; 42209467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 42309467b48Spatrick} 42409467b48Spatrick 42509467b48Spatrick// The portions of MIPS-IV that were also added to MIPS32r2. 42609467b48Spatrickclass INSN_MIPS4_32R2 { 42709467b48Spatrick list<Predicate> InsnPredicates = [HasMips4_32r2]; 42809467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 42909467b48Spatrick} 43009467b48Spatrick 43109467b48Spatrick// The portions of MIPS-V that were also added to MIPS32r2 but were removed in 43209467b48Spatrick// MIPS32r6 and MIPS64r6. 43309467b48Spatrickclass INSN_MIPS5_32R2_NOT_32R6_64R6 { 43409467b48Spatrick list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6]; 43509467b48Spatrick list<Predicate> EncodingPredicates = [HasStdEnc]; 43609467b48Spatrick} 43709467b48Spatrick 43809467b48Spatrickclass ASE_CNMIPS { 43909467b48Spatrick list<Predicate> ASEPredicate = [HasCnMips]; 44009467b48Spatrick} 44109467b48Spatrick 44209467b48Spatrickclass NOT_ASE_CNMIPS { 44309467b48Spatrick list<Predicate> ASEPredicate = [NotCnMips]; 44409467b48Spatrick} 44509467b48Spatrick 44609467b48Spatrickclass ASE_CNMIPSP { 44709467b48Spatrick list<Predicate> ASEPredicate = [HasCnMipsP]; 44809467b48Spatrick} 44909467b48Spatrick 45009467b48Spatrickclass NOT_ASE_CNMIPSP { 45109467b48Spatrick list<Predicate> ASEPredicate = [NotCnMipsP]; 45209467b48Spatrick} 45309467b48Spatrick 45409467b48Spatrickclass ASE_MIPS64_CNMIPS { 45509467b48Spatrick list<Predicate> ASEPredicate = [HasMips64, HasCnMips]; 45609467b48Spatrick} 45709467b48Spatrick 45809467b48Spatrickclass ASE_MSA { 45909467b48Spatrick list<Predicate> ASEPredicate = [HasMSA]; 46009467b48Spatrick} 46109467b48Spatrick 46209467b48Spatrickclass ASE_MSA_NOT_MSA64 { 46309467b48Spatrick list<Predicate> ASEPredicate = [HasMSA, NotMips64]; 46409467b48Spatrick} 46509467b48Spatrick 46609467b48Spatrickclass ASE_MSA64 { 46709467b48Spatrick list<Predicate> ASEPredicate = [HasMSA, HasMips64]; 46809467b48Spatrick} 46909467b48Spatrick 47009467b48Spatrickclass ASE_MT { 47109467b48Spatrick list <Predicate> ASEPredicate = [HasMT]; 47209467b48Spatrick} 47309467b48Spatrick 47409467b48Spatrickclass ASE_CRC { 47509467b48Spatrick list <Predicate> ASEPredicate = [HasCRC]; 47609467b48Spatrick} 47709467b48Spatrick 47809467b48Spatrickclass ASE_VIRT { 47909467b48Spatrick list <Predicate> ASEPredicate = [HasVirt]; 48009467b48Spatrick} 48109467b48Spatrick 48209467b48Spatrickclass ASE_GINV { 48309467b48Spatrick list <Predicate> ASEPredicate = [HasGINV]; 48409467b48Spatrick} 48509467b48Spatrick 48609467b48Spatrick// Class used for separating microMIPSr6 and microMIPS (r3) instruction. 48709467b48Spatrick// It can be used only on instructions that doesn't inherit PredicateControl. 48809467b48Spatrickclass ISA_MICROMIPS_NOT_32R6 : PredicateControl { 48909467b48Spatrick let InsnPredicates = [NotMips32r6]; 49009467b48Spatrick let EncodingPredicates = [InMicroMips]; 49109467b48Spatrick} 49209467b48Spatrick 49309467b48Spatrickclass ASE_NOT_DSP { 49409467b48Spatrick list<Predicate> ASEPredicate = [NotDSP]; 49509467b48Spatrick} 49609467b48Spatrick 49709467b48Spatrickclass MADD4 { 49809467b48Spatrick list<Predicate> AdditionalPredicates = [HasMadd4]; 49909467b48Spatrick} 50009467b48Spatrick 501097a140dSpatrick// Classes used for separating expansions that differ based on the ABI in 50209467b48Spatrick// use. 50309467b48Spatrickclass ABI_N64 { 50409467b48Spatrick list<Predicate> AdditionalPredicates = [IsN64]; 50509467b48Spatrick} 50609467b48Spatrick 50709467b48Spatrickclass ABI_NOT_N64 { 50809467b48Spatrick list<Predicate> AdditionalPredicates = [IsNotN64]; 50909467b48Spatrick} 51009467b48Spatrick 51109467b48Spatrickclass FPOP_FUSION_FAST { 51209467b48Spatrick list <Predicate> AdditionalPredicates = [AllowFPOpFusion]; 51309467b48Spatrick} 51409467b48Spatrick 51509467b48Spatrick//===----------------------------------------------------------------------===// 51609467b48Spatrick 51709467b48Spatrickclass MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl; 51809467b48Spatrick 51909467b48Spatrickclass MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> : 52009467b48Spatrick InstAlias<Asm, Result, Emit>, PredicateControl; 52109467b48Spatrick 52209467b48Spatrickclass IsCommutable { 52309467b48Spatrick bit isCommutable = 1; 52409467b48Spatrick} 52509467b48Spatrick 52609467b48Spatrickclass IsBranch { 52709467b48Spatrick bit isBranch = 1; 52809467b48Spatrick bit isCTI = 1; 52909467b48Spatrick} 53009467b48Spatrick 53109467b48Spatrickclass IsReturn { 53209467b48Spatrick bit isReturn = 1; 53309467b48Spatrick bit isCTI = 1; 53409467b48Spatrick} 53509467b48Spatrick 53609467b48Spatrickclass IsCall { 53709467b48Spatrick bit isCall = 1; 53809467b48Spatrick bit isCTI = 1; 53909467b48Spatrick} 54009467b48Spatrick 54109467b48Spatrickclass IsTailCall { 54209467b48Spatrick bit isCall = 1; 54309467b48Spatrick bit isTerminator = 1; 54409467b48Spatrick bit isReturn = 1; 54509467b48Spatrick bit isBarrier = 1; 54609467b48Spatrick bit hasExtraSrcRegAllocReq = 1; 54709467b48Spatrick bit isCodeGenOnly = 1; 54809467b48Spatrick bit isCTI = 1; 54909467b48Spatrick} 55009467b48Spatrick 55109467b48Spatrickclass IsAsCheapAsAMove { 55209467b48Spatrick bit isAsCheapAsAMove = 1; 55309467b48Spatrick} 55409467b48Spatrick 55509467b48Spatrickclass NeverHasSideEffects { 55609467b48Spatrick bit hasSideEffects = 0; 55709467b48Spatrick} 55809467b48Spatrick 55909467b48Spatrick//===----------------------------------------------------------------------===// 56009467b48Spatrick// Instruction format superclass 56109467b48Spatrick//===----------------------------------------------------------------------===// 56209467b48Spatrick 56309467b48Spatrickinclude "MipsInstrFormats.td" 56409467b48Spatrick 56509467b48Spatrick//===----------------------------------------------------------------------===// 56609467b48Spatrick// Mips Operand, Complex Patterns and Transformations Definitions. 56709467b48Spatrick//===----------------------------------------------------------------------===// 56809467b48Spatrick 56909467b48Spatrickclass ConstantSImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [], 57009467b48Spatrick int Offset = 0> : AsmOperandClass { 57109467b48Spatrick let Name = "ConstantSImm" # Bits # "_" # Offset; 57209467b48Spatrick let RenderMethod = "addConstantSImmOperands<" # Bits # ", " # Offset # ">"; 57309467b48Spatrick let PredicateMethod = "isConstantSImm<" # Bits # ", " # Offset # ">"; 57409467b48Spatrick let SuperClasses = Supers; 57509467b48Spatrick let DiagnosticType = "SImm" # Bits # "_" # Offset; 57609467b48Spatrick} 57709467b48Spatrick 57809467b48Spatrickclass SimmLslAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [], 57909467b48Spatrick int Shift = 0> : AsmOperandClass { 58009467b48Spatrick let Name = "Simm" # Bits # "_Lsl" # Shift; 58109467b48Spatrick let RenderMethod = "addImmOperands"; 58209467b48Spatrick let PredicateMethod = "isScaledSImm<" # Bits # ", " # Shift # ">"; 58309467b48Spatrick let SuperClasses = Supers; 58409467b48Spatrick let DiagnosticType = "SImm" # Bits # "_Lsl" # Shift; 58509467b48Spatrick} 58609467b48Spatrick 58709467b48Spatrickclass ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [], 58809467b48Spatrick int Offset = 0> : AsmOperandClass { 58909467b48Spatrick let Name = "ConstantUImm" # Bits # "_" # Offset; 59009467b48Spatrick let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">"; 59109467b48Spatrick let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">"; 59209467b48Spatrick let SuperClasses = Supers; 59309467b48Spatrick let DiagnosticType = "UImm" # Bits # "_" # Offset; 59409467b48Spatrick} 59509467b48Spatrick 59609467b48Spatrickclass ConstantUImmRangeAsmOperandClass<int Bottom, int Top, 59709467b48Spatrick list<AsmOperandClass> Supers = []> 59809467b48Spatrick : AsmOperandClass { 59909467b48Spatrick let Name = "ConstantUImmRange" # Bottom # "_" # Top; 60009467b48Spatrick let RenderMethod = "addImmOperands"; 60109467b48Spatrick let PredicateMethod = "isConstantUImmRange<" # Bottom # ", " # Top # ">"; 60209467b48Spatrick let SuperClasses = Supers; 60309467b48Spatrick let DiagnosticType = "UImmRange" # Bottom # "_" # Top; 60409467b48Spatrick} 60509467b48Spatrick 60609467b48Spatrickclass SImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []> 60709467b48Spatrick : AsmOperandClass { 60809467b48Spatrick let Name = "SImm" # Bits; 60909467b48Spatrick let RenderMethod = "addSImmOperands<" # Bits # ">"; 61009467b48Spatrick let PredicateMethod = "isSImm<" # Bits # ">"; 61109467b48Spatrick let SuperClasses = Supers; 61209467b48Spatrick let DiagnosticType = "SImm" # Bits; 61309467b48Spatrick} 61409467b48Spatrick 61509467b48Spatrickclass UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []> 61609467b48Spatrick : AsmOperandClass { 61709467b48Spatrick let Name = "UImm" # Bits; 61809467b48Spatrick let RenderMethod = "addUImmOperands<" # Bits # ">"; 61909467b48Spatrick let PredicateMethod = "isUImm<" # Bits # ">"; 62009467b48Spatrick let SuperClasses = Supers; 62109467b48Spatrick let DiagnosticType = "UImm" # Bits; 62209467b48Spatrick} 62309467b48Spatrick 62409467b48Spatrick// Generic case - only to support certain assembly pseudo instructions. 62509467b48Spatrickclass UImmAnyAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []> 62609467b48Spatrick : AsmOperandClass { 62709467b48Spatrick let Name = "ImmAny"; 62809467b48Spatrick let RenderMethod = "addConstantUImmOperands<32>"; 62909467b48Spatrick let PredicateMethod = "isSImm<" # Bits # ">"; 63009467b48Spatrick let SuperClasses = Supers; 63109467b48Spatrick let DiagnosticType = "ImmAny"; 63209467b48Spatrick} 63309467b48Spatrick 63409467b48Spatrick// AsmOperandClasses require a strict ordering which is difficult to manage 63509467b48Spatrick// as a hierarchy. Instead, we use a linear ordering and impose an order that 63609467b48Spatrick// is in some places arbitrary. 63709467b48Spatrick// 63809467b48Spatrick// Here the rules that are in use: 63909467b48Spatrick// * Wider immediates are a superset of narrower immediates: 64009467b48Spatrick// uimm4 < uimm5 < uimm6 64109467b48Spatrick// * For the same bit-width, unsigned immediates are a superset of signed 64209467b48Spatrick// immediates:: 64309467b48Spatrick// simm4 < uimm4 < simm5 < uimm5 64409467b48Spatrick// * For the same upper-bound, signed immediates are a superset of unsigned 64509467b48Spatrick// immediates: 64609467b48Spatrick// uimm3 < simm4 < uimm4 < simm4 64709467b48Spatrick// * Modified immediates are a superset of ordinary immediates: 64809467b48Spatrick// uimm5 < uimm5_plus1 (1..32) < uimm5_plus32 (32..63) < uimm6 64909467b48Spatrick// The term 'superset' starts to break down here since the uimm5_plus* classes 65009467b48Spatrick// are not true supersets of uimm5 (but they are still subsets of uimm6). 65109467b48Spatrick// * 'Relaxed' immediates are supersets of the corresponding unsigned immediate. 65209467b48Spatrick// uimm16 < uimm16_relaxed 65309467b48Spatrick// * The codeGen pattern type is arbitrarily ordered. 65409467b48Spatrick// uimm5 < uimm5_64, and uimm5 < vsplat_uimm5 65509467b48Spatrick// This is entirely arbitrary. We need an ordering and what we pick is 65609467b48Spatrick// unimportant since only one is possible for a given mnemonic. 65709467b48Spatrick 65809467b48Spatrickdef UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> { 65909467b48Spatrick let Name = "UImm32_Coerced"; 66009467b48Spatrick let DiagnosticType = "UImm32_Coerced"; 66109467b48Spatrick} 66209467b48Spatrickdef SImm32RelaxedAsmOperandClass 66309467b48Spatrick : SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> { 66409467b48Spatrick let Name = "SImm32_Relaxed"; 66509467b48Spatrick let PredicateMethod = "isAnyImm<33>"; 66609467b48Spatrick let DiagnosticType = "SImm32_Relaxed"; 66709467b48Spatrick} 66809467b48Spatrickdef SImm32AsmOperandClass 66909467b48Spatrick : SImmAsmOperandClass<32, [SImm32RelaxedAsmOperandClass]>; 67009467b48Spatrickdef ConstantUImm26AsmOperandClass 67109467b48Spatrick : ConstantUImmAsmOperandClass<26, [SImm32AsmOperandClass]>; 67209467b48Spatrickdef ConstantUImm20AsmOperandClass 67309467b48Spatrick : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>; 67409467b48Spatrickdef ConstantSImm19Lsl2AsmOperandClass : AsmOperandClass { 67509467b48Spatrick let Name = "SImm19Lsl2"; 67609467b48Spatrick let RenderMethod = "addImmOperands"; 67709467b48Spatrick let PredicateMethod = "isScaledSImm<19, 2>"; 67809467b48Spatrick let SuperClasses = [ConstantUImm20AsmOperandClass]; 67909467b48Spatrick let DiagnosticType = "SImm19_Lsl2"; 68009467b48Spatrick} 68109467b48Spatrickdef UImm16RelaxedAsmOperandClass 68209467b48Spatrick : UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> { 68309467b48Spatrick let Name = "UImm16_Relaxed"; 68409467b48Spatrick let PredicateMethod = "isAnyImm<16>"; 68509467b48Spatrick let DiagnosticType = "UImm16_Relaxed"; 68609467b48Spatrick} 68709467b48Spatrick// Similar to the relaxed classes which take an SImm and render it as 68809467b48Spatrick// an UImm, this takes a UImm and renders it as an SImm. 68909467b48Spatrickdef UImm16AltRelaxedAsmOperandClass 69009467b48Spatrick : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> { 69109467b48Spatrick let Name = "UImm16_AltRelaxed"; 69209467b48Spatrick let PredicateMethod = "isUImm<16>"; 69309467b48Spatrick let DiagnosticType = "UImm16_AltRelaxed"; 69409467b48Spatrick} 69509467b48Spatrick// FIXME: One of these should probably have UImm16AsmOperandClass as the 69609467b48Spatrick// superclass instead of UImm16RelaxedasmOPerandClass. 69709467b48Spatrickdef UImm16AsmOperandClass 69809467b48Spatrick : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>; 69909467b48Spatrickdef SImm16RelaxedAsmOperandClass 70009467b48Spatrick : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> { 70109467b48Spatrick let Name = "SImm16_Relaxed"; 70209467b48Spatrick let PredicateMethod = "isAnyImm<16>"; 70309467b48Spatrick let DiagnosticType = "SImm16_Relaxed"; 70409467b48Spatrick} 70509467b48Spatrickdef SImm16AsmOperandClass 70609467b48Spatrick : SImmAsmOperandClass<16, [SImm16RelaxedAsmOperandClass]>; 70709467b48Spatrickdef ConstantSImm10Lsl3AsmOperandClass : AsmOperandClass { 70809467b48Spatrick let Name = "SImm10Lsl3"; 70909467b48Spatrick let RenderMethod = "addImmOperands"; 71009467b48Spatrick let PredicateMethod = "isScaledSImm<10, 3>"; 71109467b48Spatrick let SuperClasses = [SImm16AsmOperandClass]; 71209467b48Spatrick let DiagnosticType = "SImm10_Lsl3"; 71309467b48Spatrick} 71409467b48Spatrickdef ConstantSImm10Lsl2AsmOperandClass : AsmOperandClass { 71509467b48Spatrick let Name = "SImm10Lsl2"; 71609467b48Spatrick let RenderMethod = "addImmOperands"; 71709467b48Spatrick let PredicateMethod = "isScaledSImm<10, 2>"; 71809467b48Spatrick let SuperClasses = [ConstantSImm10Lsl3AsmOperandClass]; 71909467b48Spatrick let DiagnosticType = "SImm10_Lsl2"; 72009467b48Spatrick} 72109467b48Spatrickdef ConstantSImm11AsmOperandClass 72209467b48Spatrick : ConstantSImmAsmOperandClass<11, [ConstantSImm10Lsl2AsmOperandClass]>; 72309467b48Spatrickdef ConstantSImm10Lsl1AsmOperandClass : AsmOperandClass { 72409467b48Spatrick let Name = "SImm10Lsl1"; 72509467b48Spatrick let RenderMethod = "addImmOperands"; 72609467b48Spatrick let PredicateMethod = "isScaledSImm<10, 1>"; 72709467b48Spatrick let SuperClasses = [ConstantSImm11AsmOperandClass]; 72809467b48Spatrick let DiagnosticType = "SImm10_Lsl1"; 72909467b48Spatrick} 73009467b48Spatrickdef ConstantUImm10AsmOperandClass 73109467b48Spatrick : ConstantUImmAsmOperandClass<10, [ConstantSImm10Lsl1AsmOperandClass]>; 73209467b48Spatrickdef ConstantSImm10AsmOperandClass 73309467b48Spatrick : ConstantSImmAsmOperandClass<10, [ConstantUImm10AsmOperandClass]>; 73409467b48Spatrickdef ConstantSImm9AsmOperandClass 73509467b48Spatrick : ConstantSImmAsmOperandClass<9, [ConstantSImm10AsmOperandClass]>; 73609467b48Spatrickdef ConstantSImm7Lsl2AsmOperandClass : AsmOperandClass { 73709467b48Spatrick let Name = "SImm7Lsl2"; 73809467b48Spatrick let RenderMethod = "addImmOperands"; 73909467b48Spatrick let PredicateMethod = "isScaledSImm<7, 2>"; 74009467b48Spatrick let SuperClasses = [ConstantSImm9AsmOperandClass]; 74109467b48Spatrick let DiagnosticType = "SImm7_Lsl2"; 74209467b48Spatrick} 74309467b48Spatrickdef ConstantUImm8AsmOperandClass 74409467b48Spatrick : ConstantUImmAsmOperandClass<8, [ConstantSImm7Lsl2AsmOperandClass]>; 74509467b48Spatrickdef ConstantUImm7Sub1AsmOperandClass 74609467b48Spatrick : ConstantUImmAsmOperandClass<7, [ConstantUImm8AsmOperandClass], -1> { 74709467b48Spatrick // Specify the names since the -1 offset causes invalid identifiers otherwise. 74809467b48Spatrick let Name = "UImm7_N1"; 74909467b48Spatrick let DiagnosticType = "UImm7_N1"; 75009467b48Spatrick} 75109467b48Spatrickdef ConstantUImm7AsmOperandClass 75209467b48Spatrick : ConstantUImmAsmOperandClass<7, [ConstantUImm7Sub1AsmOperandClass]>; 75309467b48Spatrickdef ConstantUImm6Lsl2AsmOperandClass : AsmOperandClass { 75409467b48Spatrick let Name = "UImm6Lsl2"; 75509467b48Spatrick let RenderMethod = "addImmOperands"; 75609467b48Spatrick let PredicateMethod = "isScaledUImm<6, 2>"; 75709467b48Spatrick let SuperClasses = [ConstantUImm7AsmOperandClass]; 75809467b48Spatrick let DiagnosticType = "UImm6_Lsl2"; 75909467b48Spatrick} 76009467b48Spatrickdef ConstantUImm6AsmOperandClass 76109467b48Spatrick : ConstantUImmAsmOperandClass<6, [ConstantUImm6Lsl2AsmOperandClass]>; 76209467b48Spatrickdef ConstantSImm6AsmOperandClass 76309467b48Spatrick : ConstantSImmAsmOperandClass<6, [ConstantUImm6AsmOperandClass]>; 76409467b48Spatrickdef ConstantUImm5Lsl2AsmOperandClass : AsmOperandClass { 76509467b48Spatrick let Name = "UImm5Lsl2"; 76609467b48Spatrick let RenderMethod = "addImmOperands"; 76709467b48Spatrick let PredicateMethod = "isScaledUImm<5, 2>"; 76809467b48Spatrick let SuperClasses = [ConstantSImm6AsmOperandClass]; 76909467b48Spatrick let DiagnosticType = "UImm5_Lsl2"; 77009467b48Spatrick} 77109467b48Spatrickdef ConstantUImm5_Range2_64AsmOperandClass 77209467b48Spatrick : ConstantUImmRangeAsmOperandClass<2, 64, [ConstantUImm5Lsl2AsmOperandClass]>; 77309467b48Spatrickdef ConstantUImm5Plus33AsmOperandClass 77409467b48Spatrick : ConstantUImmAsmOperandClass<5, [ConstantUImm5_Range2_64AsmOperandClass], 77509467b48Spatrick 33>; 77609467b48Spatrickdef ConstantUImm5ReportUImm6AsmOperandClass 77709467b48Spatrick : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus33AsmOperandClass]> { 77809467b48Spatrick let Name = "ConstantUImm5_0_Report_UImm6"; 77909467b48Spatrick let DiagnosticType = "UImm5_0_Report_UImm6"; 78009467b48Spatrick} 78109467b48Spatrickdef ConstantUImm5Plus32AsmOperandClass 78209467b48Spatrick : ConstantUImmAsmOperandClass< 78309467b48Spatrick 5, [ConstantUImm5ReportUImm6AsmOperandClass], 32>; 78409467b48Spatrickdef ConstantUImm5Plus32NormalizeAsmOperandClass 78509467b48Spatrick : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus32AsmOperandClass], 32> { 78609467b48Spatrick let Name = "ConstantUImm5_32_Norm"; 78709467b48Spatrick // We must also subtract 32 when we render the operand. 78809467b48Spatrick let RenderMethod = "addConstantUImmOperands<5, 32, -32>"; 78909467b48Spatrick} 79009467b48Spatrickdef ConstantUImm5Plus1ReportUImm6AsmOperandClass 79109467b48Spatrick : ConstantUImmAsmOperandClass< 79209467b48Spatrick 5, [ConstantUImm5Plus32NormalizeAsmOperandClass], 1>{ 79309467b48Spatrick let Name = "ConstantUImm5_Plus1_Report_UImm6"; 79409467b48Spatrick} 79509467b48Spatrickdef ConstantUImm5Plus1AsmOperandClass 79609467b48Spatrick : ConstantUImmAsmOperandClass< 79709467b48Spatrick 5, [ConstantUImm5Plus1ReportUImm6AsmOperandClass], 1>; 79809467b48Spatrickdef ConstantUImm5AsmOperandClass 79909467b48Spatrick : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus1AsmOperandClass]>; 80009467b48Spatrickdef ConstantSImm5AsmOperandClass 80109467b48Spatrick : ConstantSImmAsmOperandClass<5, [ConstantUImm5AsmOperandClass]>; 80209467b48Spatrickdef ConstantUImm4AsmOperandClass 80309467b48Spatrick : ConstantUImmAsmOperandClass<4, [ConstantSImm5AsmOperandClass]>; 80409467b48Spatrickdef ConstantSImm4AsmOperandClass 80509467b48Spatrick : ConstantSImmAsmOperandClass<4, [ConstantUImm4AsmOperandClass]>; 80609467b48Spatrickdef ConstantUImm3AsmOperandClass 80709467b48Spatrick : ConstantUImmAsmOperandClass<3, [ConstantSImm4AsmOperandClass]>; 80809467b48Spatrickdef ConstantUImm2Plus1AsmOperandClass 80909467b48Spatrick : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass], 1>; 81009467b48Spatrickdef ConstantUImm2AsmOperandClass 81109467b48Spatrick : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass]>; 81209467b48Spatrickdef ConstantUImm1AsmOperandClass 81309467b48Spatrick : ConstantUImmAsmOperandClass<1, [ConstantUImm2AsmOperandClass]>; 81409467b48Spatrickdef ConstantImmzAsmOperandClass : AsmOperandClass { 81509467b48Spatrick let Name = "ConstantImmz"; 81609467b48Spatrick let RenderMethod = "addConstantUImmOperands<1>"; 81709467b48Spatrick let PredicateMethod = "isConstantImmz"; 81809467b48Spatrick let SuperClasses = [ConstantUImm1AsmOperandClass]; 81909467b48Spatrick let DiagnosticType = "Immz"; 82009467b48Spatrick} 82109467b48Spatrick 82209467b48Spatrickdef Simm19Lsl2AsmOperand 82309467b48Spatrick : SimmLslAsmOperandClass<19, [], 2>; 82409467b48Spatrick 82509467b48Spatrickdef MipsJumpTargetAsmOperand : AsmOperandClass { 82609467b48Spatrick let Name = "JumpTarget"; 82709467b48Spatrick let ParserMethod = "parseJumpTarget"; 82809467b48Spatrick let PredicateMethod = "isImm"; 82909467b48Spatrick let RenderMethod = "addImmOperands"; 83009467b48Spatrick} 83109467b48Spatrick 83209467b48Spatrick// Instruction operand types 83309467b48Spatrickdef jmptarget : Operand<OtherVT> { 83409467b48Spatrick let EncoderMethod = "getJumpTargetOpValue"; 83509467b48Spatrick let ParserMatchClass = MipsJumpTargetAsmOperand; 836*a96b3639Srobert let PrintMethod = "printJumpOperand"; 83709467b48Spatrick} 83809467b48Spatrickdef brtarget : Operand<OtherVT> { 83909467b48Spatrick let EncoderMethod = "getBranchTargetOpValue"; 84009467b48Spatrick let OperandType = "OPERAND_PCREL"; 84109467b48Spatrick let DecoderMethod = "DecodeBranchTarget"; 84209467b48Spatrick let ParserMatchClass = MipsJumpTargetAsmOperand; 843*a96b3639Srobert let PrintMethod = "printBranchOperand"; 84409467b48Spatrick} 84509467b48Spatrickdef brtarget1SImm16 : Operand<OtherVT> { 84609467b48Spatrick let EncoderMethod = "getBranchTargetOpValue1SImm16"; 84709467b48Spatrick let OperandType = "OPERAND_PCREL"; 84809467b48Spatrick let DecoderMethod = "DecodeBranchTarget1SImm16"; 84909467b48Spatrick let ParserMatchClass = MipsJumpTargetAsmOperand; 850*a96b3639Srobert let PrintMethod = "printBranchOperand"; 85109467b48Spatrick} 85209467b48Spatrickdef calltarget : Operand<iPTR> { 85309467b48Spatrick let EncoderMethod = "getJumpTargetOpValue"; 85409467b48Spatrick let ParserMatchClass = MipsJumpTargetAsmOperand; 855*a96b3639Srobert let PrintMethod = "printJumpOperand"; 85609467b48Spatrick} 85709467b48Spatrick 85809467b48Spatrickdef imm64: Operand<i64>; 85909467b48Spatrick 86009467b48Spatrickdef simm19_lsl2 : Operand<i32> { 86109467b48Spatrick let EncoderMethod = "getSimm19Lsl2Encoding"; 86209467b48Spatrick let DecoderMethod = "DecodeSimm19Lsl2"; 86309467b48Spatrick let ParserMatchClass = Simm19Lsl2AsmOperand; 86409467b48Spatrick} 86509467b48Spatrick 86609467b48Spatrickdef simm18_lsl3 : Operand<i32> { 86709467b48Spatrick let EncoderMethod = "getSimm18Lsl3Encoding"; 86809467b48Spatrick let DecoderMethod = "DecodeSimm18Lsl3"; 86909467b48Spatrick let ParserMatchClass = MipsJumpTargetAsmOperand; 87009467b48Spatrick} 87109467b48Spatrick 87209467b48Spatrick// Zero 87309467b48Spatrickdef uimmz : Operand<i32> { 87409467b48Spatrick let PrintMethod = "printUImm<0>"; 87509467b48Spatrick let ParserMatchClass = ConstantImmzAsmOperandClass; 87609467b48Spatrick} 87709467b48Spatrick 87809467b48Spatrick// size operand of ins instruction 87909467b48Spatrickdef uimm_range_2_64 : Operand<i32> { 88009467b48Spatrick let PrintMethod = "printUImm<6, 2>"; 88109467b48Spatrick let EncoderMethod = "getSizeInsEncoding"; 88209467b48Spatrick let DecoderMethod = "DecodeInsSize"; 88309467b48Spatrick let ParserMatchClass = ConstantUImm5_Range2_64AsmOperandClass; 88409467b48Spatrick} 88509467b48Spatrick 88609467b48Spatrick// Unsigned Operands 88709467b48Spatrickforeach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20, 26} in 88809467b48Spatrick def uimm # I : Operand<i32> { 88909467b48Spatrick let PrintMethod = "printUImm<" # I # ">"; 89009467b48Spatrick let ParserMatchClass = 89109467b48Spatrick !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); 89209467b48Spatrick } 89309467b48Spatrick 89409467b48Spatrickdef uimm2_plus1 : Operand<i32> { 89509467b48Spatrick let PrintMethod = "printUImm<2, 1>"; 89609467b48Spatrick let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>"; 89709467b48Spatrick let DecoderMethod = "DecodeUImmWithOffset<2, 1>"; 89809467b48Spatrick let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass; 89909467b48Spatrick} 90009467b48Spatrick 90109467b48Spatrickdef uimm5_plus1 : Operand<i32> { 90209467b48Spatrick let PrintMethod = "printUImm<5, 1>"; 90309467b48Spatrick let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; 90409467b48Spatrick let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; 90509467b48Spatrick let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass; 90609467b48Spatrick} 90709467b48Spatrick 90809467b48Spatrickdef uimm5_plus1_report_uimm6 : Operand<i32> { 90909467b48Spatrick let PrintMethod = "printUImm<6, 1>"; 91009467b48Spatrick let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; 91109467b48Spatrick let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; 91209467b48Spatrick let ParserMatchClass = ConstantUImm5Plus1ReportUImm6AsmOperandClass; 91309467b48Spatrick} 91409467b48Spatrick 91509467b48Spatrickdef uimm5_plus32 : Operand<i32> { 91609467b48Spatrick let PrintMethod = "printUImm<5, 32>"; 91709467b48Spatrick let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass; 91809467b48Spatrick} 91909467b48Spatrick 92009467b48Spatrickdef uimm5_plus33 : Operand<i32> { 92109467b48Spatrick let PrintMethod = "printUImm<5, 33>"; 92209467b48Spatrick let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; 92309467b48Spatrick let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; 92409467b48Spatrick let ParserMatchClass = ConstantUImm5Plus33AsmOperandClass; 92509467b48Spatrick} 92609467b48Spatrick 92709467b48Spatrickdef uimm5_inssize_plus1 : Operand<i32> { 92809467b48Spatrick let PrintMethod = "printUImm<6>"; 92909467b48Spatrick let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass; 93009467b48Spatrick let EncoderMethod = "getSizeInsEncoding"; 93109467b48Spatrick let DecoderMethod = "DecodeInsSize"; 93209467b48Spatrick} 93309467b48Spatrick 93409467b48Spatrickdef uimm5_plus32_normalize : Operand<i32> { 93509467b48Spatrick let PrintMethod = "printUImm<5>"; 93609467b48Spatrick let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; 93709467b48Spatrick} 93809467b48Spatrick 93909467b48Spatrickdef uimm5_lsl2 : Operand<OtherVT> { 94009467b48Spatrick let EncoderMethod = "getUImm5Lsl2Encoding"; 94109467b48Spatrick let DecoderMethod = "DecodeUImmWithOffsetAndScale<5, 0, 4>"; 94209467b48Spatrick let ParserMatchClass = ConstantUImm5Lsl2AsmOperandClass; 94309467b48Spatrick} 94409467b48Spatrick 94509467b48Spatrickdef uimm5_plus32_normalize_64 : Operand<i64> { 94609467b48Spatrick let PrintMethod = "printUImm<5>"; 94709467b48Spatrick let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; 94809467b48Spatrick} 94909467b48Spatrick 95009467b48Spatrickdef uimm6_lsl2 : Operand<OtherVT> { 95109467b48Spatrick let EncoderMethod = "getUImm6Lsl2Encoding"; 95209467b48Spatrick let DecoderMethod = "DecodeUImmWithOffsetAndScale<6, 0, 4>"; 95309467b48Spatrick let ParserMatchClass = ConstantUImm6Lsl2AsmOperandClass; 95409467b48Spatrick} 95509467b48Spatrick 95609467b48Spatrickforeach I = {16} in 95709467b48Spatrick def uimm # I : Operand<i32> { 95809467b48Spatrick let PrintMethod = "printUImm<" # I # ">"; 95909467b48Spatrick let ParserMatchClass = 96009467b48Spatrick !cast<AsmOperandClass>("UImm" # I # "AsmOperandClass"); 96109467b48Spatrick } 96209467b48Spatrick 96309467b48Spatrick// Like uimm16_64 but coerces simm16 to uimm16. 96409467b48Spatrickdef uimm16_relaxed : Operand<i32> { 96509467b48Spatrick let PrintMethod = "printUImm<16>"; 96609467b48Spatrick let ParserMatchClass = UImm16RelaxedAsmOperandClass; 96709467b48Spatrick} 96809467b48Spatrick 96909467b48Spatrickforeach I = {5} in 97009467b48Spatrick def uimm # I # _64 : Operand<i64> { 97109467b48Spatrick let PrintMethod = "printUImm<" # I # ">"; 97209467b48Spatrick let ParserMatchClass = 97309467b48Spatrick !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); 97409467b48Spatrick } 97509467b48Spatrick 97609467b48Spatrickforeach I = {16} in 97709467b48Spatrick def uimm # I # _64 : Operand<i64> { 97809467b48Spatrick let PrintMethod = "printUImm<" # I # ">"; 97909467b48Spatrick let ParserMatchClass = 98009467b48Spatrick !cast<AsmOperandClass>("UImm" # I # "AsmOperandClass"); 98109467b48Spatrick } 98209467b48Spatrick 98309467b48Spatrick// Like uimm16_64 but coerces simm16 to uimm16. 98409467b48Spatrickdef uimm16_64_relaxed : Operand<i64> { 98509467b48Spatrick let PrintMethod = "printUImm<16>"; 98609467b48Spatrick let ParserMatchClass = UImm16RelaxedAsmOperandClass; 98709467b48Spatrick} 98809467b48Spatrick 98909467b48Spatrickdef uimm16_altrelaxed : Operand<i32> { 99009467b48Spatrick let PrintMethod = "printUImm<16>"; 99109467b48Spatrick let ParserMatchClass = UImm16AltRelaxedAsmOperandClass; 99209467b48Spatrick} 99309467b48Spatrick// Like uimm5 but reports a less confusing error for 32-63 when 99409467b48Spatrick// an instruction alias permits that. 99509467b48Spatrickdef uimm5_report_uimm6 : Operand<i32> { 99609467b48Spatrick let PrintMethod = "printUImm<6>"; 99709467b48Spatrick let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; 99809467b48Spatrick} 99909467b48Spatrick 100009467b48Spatrick// Like uimm5_64 but reports a less confusing error for 32-63 when 100109467b48Spatrick// an instruction alias permits that. 100209467b48Spatrickdef uimm5_64_report_uimm6 : Operand<i64> { 100309467b48Spatrick let PrintMethod = "printUImm<5>"; 100409467b48Spatrick let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; 100509467b48Spatrick} 100609467b48Spatrick 100709467b48Spatrickforeach I = {1, 2, 3, 4} in 100809467b48Spatrick def uimm # I # _ptr : Operand<iPTR> { 100909467b48Spatrick let PrintMethod = "printUImm<" # I # ">"; 101009467b48Spatrick let ParserMatchClass = 101109467b48Spatrick !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); 101209467b48Spatrick } 101309467b48Spatrick 101409467b48Spatrickforeach I = {1, 2, 3, 4, 5, 6, 8} in 101509467b48Spatrick def vsplat_uimm # I : Operand<vAny> { 101609467b48Spatrick let PrintMethod = "printUImm<" # I # ">"; 101709467b48Spatrick let ParserMatchClass = 101809467b48Spatrick !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); 101909467b48Spatrick } 102009467b48Spatrick 102109467b48Spatrick// Signed operands 102209467b48Spatrickforeach I = {4, 5, 6, 9, 10, 11} in 102309467b48Spatrick def simm # I : Operand<i32> { 102409467b48Spatrick let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">"; 102509467b48Spatrick let ParserMatchClass = 102609467b48Spatrick !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass"); 102709467b48Spatrick } 102809467b48Spatrick 102909467b48Spatrickforeach I = {1, 2, 3} in 103009467b48Spatrick def simm10_lsl # I : Operand<i32> { 103109467b48Spatrick let DecoderMethod = "DecodeSImmWithOffsetAndScale<10, " # I # ">"; 103209467b48Spatrick let ParserMatchClass = 103309467b48Spatrick !cast<AsmOperandClass>("ConstantSImm10Lsl" # I # "AsmOperandClass"); 103409467b48Spatrick } 103509467b48Spatrick 103609467b48Spatrickforeach I = {10} in 103709467b48Spatrick def simm # I # _64 : Operand<i64> { 103809467b48Spatrick let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">"; 103909467b48Spatrick let ParserMatchClass = 104009467b48Spatrick !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass"); 104109467b48Spatrick } 104209467b48Spatrick 104309467b48Spatrickforeach I = {5, 10} in 104409467b48Spatrick def vsplat_simm # I : Operand<vAny> { 104509467b48Spatrick let ParserMatchClass = 104609467b48Spatrick !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass"); 104709467b48Spatrick } 104809467b48Spatrick 104909467b48Spatrickdef simm7_lsl2 : Operand<OtherVT> { 105009467b48Spatrick let EncoderMethod = "getSImm7Lsl2Encoding"; 105109467b48Spatrick let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ", 0, 4>"; 105209467b48Spatrick let ParserMatchClass = ConstantSImm7Lsl2AsmOperandClass; 105309467b48Spatrick} 105409467b48Spatrick 105509467b48Spatrickforeach I = {16, 32} in 105609467b48Spatrick def simm # I : Operand<i32> { 105709467b48Spatrick let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">"; 105809467b48Spatrick let ParserMatchClass = !cast<AsmOperandClass>("SImm" # I # "AsmOperandClass"); 105909467b48Spatrick } 106009467b48Spatrick 106109467b48Spatrick// Like simm16 but coerces uimm16 to simm16. 106209467b48Spatrickdef simm16_relaxed : Operand<i32> { 106309467b48Spatrick let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>"; 106409467b48Spatrick let ParserMatchClass = SImm16RelaxedAsmOperandClass; 106509467b48Spatrick} 106609467b48Spatrick 106709467b48Spatrickdef simm16_64 : Operand<i64> { 106809467b48Spatrick let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>"; 106909467b48Spatrick let ParserMatchClass = SImm16AsmOperandClass; 107009467b48Spatrick} 107109467b48Spatrick 107209467b48Spatrick// like simm32 but coerces simm32 to uimm32. 107309467b48Spatrickdef uimm32_coerced : Operand<i32> { 107409467b48Spatrick let ParserMatchClass = UImm32CoercedAsmOperandClass; 107509467b48Spatrick} 107609467b48Spatrick// Like simm32 but coerces uimm32 to simm32. 107709467b48Spatrickdef simm32_relaxed : Operand<i32> { 107809467b48Spatrick let DecoderMethod = "DecodeSImmWithOffsetAndScale<32>"; 107909467b48Spatrick let ParserMatchClass = SImm32RelaxedAsmOperandClass; 108009467b48Spatrick} 108109467b48Spatrick 108209467b48Spatrick// This is almost the same as a uimm7 but 0x7f is interpreted as -1. 108309467b48Spatrickdef li16_imm : Operand<i32> { 108409467b48Spatrick let DecoderMethod = "DecodeLi16Imm"; 108509467b48Spatrick let ParserMatchClass = ConstantUImm7Sub1AsmOperandClass; 108609467b48Spatrick} 108709467b48Spatrick 108809467b48Spatrickdef MipsMemAsmOperand : AsmOperandClass { 108909467b48Spatrick let Name = "Mem"; 109009467b48Spatrick let ParserMethod = "parseMemOperand"; 109109467b48Spatrick} 109209467b48Spatrick 109309467b48Spatrickclass MipsMemSimmAsmOperand<int Width, int Shift = 0> : AsmOperandClass { 109409467b48Spatrick let Name = "MemOffsetSimm" # Width # "_" # Shift; 109509467b48Spatrick let SuperClasses = [MipsMemAsmOperand]; 109609467b48Spatrick let RenderMethod = "addMemOperands"; 109709467b48Spatrick let ParserMethod = "parseMemOperand"; 109809467b48Spatrick let PredicateMethod = "isMemWithSimmOffset<" # Width # ", " # Shift # ">"; 109909467b48Spatrick let DiagnosticType = !if(!eq(Shift, 0), "MemSImm" # Width, 110009467b48Spatrick "MemSImm" # Width # "Lsl" # Shift); 110109467b48Spatrick} 110209467b48Spatrick 110309467b48Spatrickdef MipsMemSimmPtrAsmOperand : AsmOperandClass { 110409467b48Spatrick let Name = "MemOffsetSimmPtr"; 110509467b48Spatrick let SuperClasses = [MipsMemAsmOperand]; 110609467b48Spatrick let RenderMethod = "addMemOperands"; 110709467b48Spatrick let ParserMethod = "parseMemOperand"; 110809467b48Spatrick let PredicateMethod = "isMemWithPtrSizeOffset"; 110909467b48Spatrick let DiagnosticType = "MemSImmPtr"; 111009467b48Spatrick} 111109467b48Spatrick 111209467b48Spatrickdef MipsInvertedImmoperand : AsmOperandClass { 111309467b48Spatrick let Name = "InvNum"; 111409467b48Spatrick let RenderMethod = "addImmOperands"; 111509467b48Spatrick let ParserMethod = "parseInvNum"; 111609467b48Spatrick} 111709467b48Spatrick 111809467b48Spatrickdef InvertedImOperand : Operand<i32> { 111909467b48Spatrick let ParserMatchClass = MipsInvertedImmoperand; 112009467b48Spatrick} 112109467b48Spatrick 112209467b48Spatrickdef InvertedImOperand64 : Operand<i64> { 112309467b48Spatrick let ParserMatchClass = MipsInvertedImmoperand; 112409467b48Spatrick} 112509467b48Spatrick 112609467b48Spatrickclass mem_generic : Operand<iPTR> { 112709467b48Spatrick let PrintMethod = "printMemOperand"; 112809467b48Spatrick let MIOperandInfo = (ops ptr_rc, simm16); 112909467b48Spatrick let EncoderMethod = "getMemEncoding"; 113009467b48Spatrick let ParserMatchClass = MipsMemAsmOperand; 113109467b48Spatrick let OperandType = "OPERAND_MEMORY"; 113209467b48Spatrick} 113309467b48Spatrick 113409467b48Spatrick// Address operand 113509467b48Spatrickdef mem : mem_generic; 113609467b48Spatrick 113709467b48Spatrick// MSA specific address operand 113809467b48Spatrickdef mem_msa : mem_generic { 113909467b48Spatrick let MIOperandInfo = (ops ptr_rc, simm10); 114009467b48Spatrick let EncoderMethod = "getMSAMemEncoding"; 114109467b48Spatrick} 114209467b48Spatrick 114309467b48Spatrickdef simm12 : Operand<i32> { 114409467b48Spatrick let DecoderMethod = "DecodeSimm12"; 114509467b48Spatrick} 114609467b48Spatrick 114709467b48Spatrickdef mem_simm9_exp : mem_generic { 114809467b48Spatrick let MIOperandInfo = (ops ptr_rc, simm9); 114909467b48Spatrick let ParserMatchClass = MipsMemSimmPtrAsmOperand; 115009467b48Spatrick let OperandNamespace = "MipsII"; 115109467b48Spatrick let OperandType = "OPERAND_MEM_SIMM9"; 115209467b48Spatrick} 115309467b48Spatrick 115409467b48Spatrickforeach I = {9, 10, 11, 12, 16} in 115509467b48Spatrick def mem_simm # I : mem_generic { 115609467b48Spatrick let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm" # I)); 115709467b48Spatrick let ParserMatchClass = MipsMemSimmAsmOperand<I>; 115809467b48Spatrick } 115909467b48Spatrick 116009467b48Spatrickforeach I = {1, 2, 3} in 116109467b48Spatrick def mem_simm10_lsl # I : mem_generic { 116209467b48Spatrick let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm10_lsl" # I)); 116309467b48Spatrick let EncoderMethod = "getMemEncoding<" # I # ">"; 116409467b48Spatrick let ParserMatchClass = MipsMemSimmAsmOperand<10, I>; 116509467b48Spatrick } 116609467b48Spatrick 116709467b48Spatrickdef mem_simmptr : mem_generic { 116809467b48Spatrick let ParserMatchClass = MipsMemSimmPtrAsmOperand; 116909467b48Spatrick} 117009467b48Spatrick 117109467b48Spatrickdef mem_ea : Operand<iPTR> { 117209467b48Spatrick let PrintMethod = "printMemOperandEA"; 117309467b48Spatrick let MIOperandInfo = (ops ptr_rc, simm16); 117409467b48Spatrick let EncoderMethod = "getMemEncoding"; 117509467b48Spatrick let OperandType = "OPERAND_MEMORY"; 117609467b48Spatrick} 117709467b48Spatrick 117809467b48Spatrickdef PtrRC : Operand<iPTR> { 117909467b48Spatrick let MIOperandInfo = (ops ptr_rc); 118009467b48Spatrick let DecoderMethod = "DecodePtrRegisterClass"; 118109467b48Spatrick let ParserMatchClass = GPR32AsmOperand; 118209467b48Spatrick} 118309467b48Spatrick 118409467b48Spatrick// size operand of ins instruction 118509467b48Spatrickdef size_ins : Operand<i32> { 118609467b48Spatrick let EncoderMethod = "getSizeInsEncoding"; 118709467b48Spatrick let DecoderMethod = "DecodeInsSize"; 118809467b48Spatrick} 118909467b48Spatrick 119009467b48Spatrick// Transformation Function - get the lower 16 bits. 119109467b48Spatrickdef LO16 : SDNodeXForm<imm, [{ 119209467b48Spatrick return getImm(N, N->getZExtValue() & 0xFFFF); 119309467b48Spatrick}]>; 119409467b48Spatrick 119509467b48Spatrick// Transformation Function - get the higher 16 bits. 119609467b48Spatrickdef HI16 : SDNodeXForm<imm, [{ 119709467b48Spatrick return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 119809467b48Spatrick}]>; 119909467b48Spatrick 120009467b48Spatrick// Plus 1. 120109467b48Spatrickdef Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 120209467b48Spatrick 120309467b48Spatrick// Node immediate is zero (e.g. insve.d) 120409467b48Spatrickdef immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>; 120509467b48Spatrick 120609467b48Spatrick// Node immediate fits as 16-bit sign extended on target immediate. 120709467b48Spatrick// e.g. addi, andi 120809467b48Spatrickdef immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 120909467b48Spatrick 121009467b48Spatrick// Node immediate fits as 16-bit sign extended on target immediate. 121109467b48Spatrick// e.g. addi, andi 121209467b48Spatrickdef immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 121309467b48Spatrickdef imm32SExt16 : IntImmLeaf<i32, [{ return isInt<16>(Imm.getSExtValue()); }]>; 121409467b48Spatrick 121509467b48Spatrick// Node immediate fits as 7-bit zero extended on target immediate. 121609467b48Spatrickdef immZExt7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>; 121709467b48Spatrickdef timmZExt7 : PatLeaf<(timm), [{ return isUInt<7>(N->getZExtValue()); }]>; 121809467b48Spatrick 121909467b48Spatrick// Node immediate fits as 16-bit zero extended on target immediate. 122009467b48Spatrick// The LO16 param means that only the lower 16 bits of the node 122109467b48Spatrick// immediate are caught. 122209467b48Spatrick// e.g. addiu, sltiu 122309467b48Spatrickdef immZExt16 : PatLeaf<(imm), [{ 122409467b48Spatrick if (N->getValueType(0) == MVT::i32) 122509467b48Spatrick return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 122609467b48Spatrick else 122709467b48Spatrick return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 122809467b48Spatrick}], LO16>; 122909467b48Spatrickdef imm32ZExt16 : IntImmLeaf<i32, [{ 123009467b48Spatrick return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue(); 123109467b48Spatrick}]>; 123209467b48Spatrick 123309467b48Spatrick// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 123409467b48Spatrickdef immSExt32Low16Zero : PatLeaf<(imm), [{ 123509467b48Spatrick int64_t Val = N->getSExtValue(); 123609467b48Spatrick return isInt<32>(Val) && !(Val & 0xffff); 123709467b48Spatrick}]>; 123809467b48Spatrick 123909467b48Spatrick// Zero-extended 32-bit unsigned int with lower 16-bit cleared. 124009467b48Spatrickdef immZExt32Low16Zero : PatLeaf<(imm), [{ 124109467b48Spatrick uint64_t Val = N->getZExtValue(); 124209467b48Spatrick return isUInt<32>(Val) && !(Val & 0xffff); 124309467b48Spatrick}]>; 124409467b48Spatrick 124509467b48Spatrick// Note immediate fits as a 32 bit signed extended on target immediate. 124609467b48Spatrickdef immSExt32 : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>; 124709467b48Spatrick 124809467b48Spatrick// Note immediate fits as a 32 bit zero extended on target immediate. 124909467b48Spatrickdef immZExt32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; 125009467b48Spatrick 125109467b48Spatrick// shamt field must fit in 5 bits. 125209467b48Spatrickdef immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 125309467b48Spatrickdef timmZExt5 : TImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 125409467b48Spatrick 125509467b48Spatrickdef immZExt5Plus1 : PatLeaf<(imm), [{ 125609467b48Spatrick return isUInt<5>(N->getZExtValue() - 1); 125709467b48Spatrick}]>; 125809467b48Spatrickdef immZExt5Plus32 : PatLeaf<(imm), [{ 125909467b48Spatrick return isUInt<5>(N->getZExtValue() - 32); 126009467b48Spatrick}]>; 126109467b48Spatrickdef immZExt5Plus33 : PatLeaf<(imm), [{ 126209467b48Spatrick return isUInt<5>(N->getZExtValue() - 33); 126309467b48Spatrick}]>; 126409467b48Spatrick 126509467b48Spatrickdef immZExt5To31 : SDNodeXForm<imm, [{ 126609467b48Spatrick return getImm(N, 31 - N->getZExtValue()); 126709467b48Spatrick}]>; 126809467b48Spatrick 126909467b48Spatrick// True if (N + 1) fits in 16-bit field. 127009467b48Spatrickdef immSExt16Plus1 : PatLeaf<(imm), [{ 127109467b48Spatrick return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 127209467b48Spatrick}]>; 127309467b48Spatrick 127409467b48Spatrickdef immZExtRange2To64 : PatLeaf<(imm), [{ 127509467b48Spatrick return isUInt<7>(N->getZExtValue()) && (N->getZExtValue() >= 2) && 127609467b48Spatrick (N->getZExtValue() <= 64); 127709467b48Spatrick}]>; 127809467b48Spatrick 127909467b48Spatrickdef ORiPred : PatLeaf<(imm), [{ 128009467b48Spatrick return isUInt<16>(N->getZExtValue()) && !isInt<16>(N->getSExtValue()); 128109467b48Spatrick}], LO16>; 128209467b48Spatrick 128309467b48Spatrickdef LUiPred : PatLeaf<(imm), [{ 128409467b48Spatrick int64_t Val = N->getSExtValue(); 128509467b48Spatrick return !isInt<16>(Val) && isInt<32>(Val) && !(Val & 0xffff); 128609467b48Spatrick}]>; 128709467b48Spatrick 128809467b48Spatrickdef LUiORiPred : PatLeaf<(imm), [{ 128909467b48Spatrick int64_t SVal = N->getSExtValue(); 129009467b48Spatrick return isInt<32>(SVal) && (SVal & 0xffff); 129109467b48Spatrick}]>; 129209467b48Spatrick 1293097a140dSpatrick// Mips Address Mode! SDNode frameindex could possibly be a match 129409467b48Spatrick// since load and store instructions from stack used it. 129509467b48Spatrickdef addr : 129609467b48Spatrick ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 129709467b48Spatrick 129809467b48Spatrickdef addrRegImm : 129909467b48Spatrick ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 130009467b48Spatrick 130109467b48Spatrickdef addrDefault : 130209467b48Spatrick ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 130309467b48Spatrick 130409467b48Spatrickdef addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10", [frameindex]>; 130509467b48Spatrickdef addrimm10lsl1 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl1", 130609467b48Spatrick [frameindex]>; 130709467b48Spatrickdef addrimm10lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl2", 130809467b48Spatrick [frameindex]>; 130909467b48Spatrickdef addrimm10lsl3 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl3", 131009467b48Spatrick [frameindex]>; 131109467b48Spatrick 131209467b48Spatrick//===----------------------------------------------------------------------===// 131309467b48Spatrick// Instructions specific format 131409467b48Spatrick//===----------------------------------------------------------------------===// 131509467b48Spatrick 131609467b48Spatrick// Arithmetic and logical instructions with 3 register operands. 131709467b48Spatrickclass ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 131809467b48Spatrick InstrItinClass Itin = NoItinerary, 131909467b48Spatrick SDPatternOperator OpNode = null_frag>: 132009467b48Spatrick InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 132109467b48Spatrick !strconcat(opstr, "\t$rd, $rs, $rt"), 132209467b48Spatrick [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 132309467b48Spatrick let isCommutable = isComm; 132409467b48Spatrick let isReMaterializable = 1; 132509467b48Spatrick let TwoOperandAliasConstraint = "$rd = $rs"; 132609467b48Spatrick} 132709467b48Spatrick 132809467b48Spatrick// Arithmetic and logical instructions with 2 register operands. 132909467b48Spatrickclass ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 133009467b48Spatrick InstrItinClass Itin = NoItinerary, 133109467b48Spatrick SDPatternOperator imm_type = null_frag, 133209467b48Spatrick SDPatternOperator OpNode = null_frag> : 133309467b48Spatrick InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 133409467b48Spatrick !strconcat(opstr, "\t$rt, $rs, $imm16"), 133509467b48Spatrick [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 133609467b48Spatrick Itin, FrmI, opstr> { 133709467b48Spatrick let isReMaterializable = 1; 133809467b48Spatrick let TwoOperandAliasConstraint = "$rs = $rt"; 133909467b48Spatrick} 134009467b48Spatrick 134109467b48Spatrick// Arithmetic Multiply ADD/SUB 134209467b48Spatrickclass MArithR<string opstr, InstrItinClass itin, bit isComm = 0> : 134309467b48Spatrick InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 134409467b48Spatrick !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> { 134509467b48Spatrick let Defs = [HI0, LO0]; 134609467b48Spatrick let Uses = [HI0, LO0]; 134709467b48Spatrick let isCommutable = isComm; 134809467b48Spatrick} 134909467b48Spatrick 135009467b48Spatrick// Logical 135109467b48Spatrickclass LogicNOR<string opstr, RegisterOperand RO>: 135209467b48Spatrick InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 135309467b48Spatrick !strconcat(opstr, "\t$rd, $rs, $rt"), 135409467b48Spatrick [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> { 135509467b48Spatrick let isCommutable = 1; 135609467b48Spatrick} 135709467b48Spatrick 135809467b48Spatrick// Shifts 135909467b48Spatrickclass shift_rotate_imm<string opstr, Operand ImmOpnd, 136009467b48Spatrick RegisterOperand RO, InstrItinClass itin, 136109467b48Spatrick SDPatternOperator OpNode = null_frag, 136209467b48Spatrick SDPatternOperator PF = null_frag> : 136309467b48Spatrick InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 136409467b48Spatrick !strconcat(opstr, "\t$rd, $rt, $shamt"), 136509467b48Spatrick [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> { 136609467b48Spatrick let TwoOperandAliasConstraint = "$rt = $rd"; 136709467b48Spatrick} 136809467b48Spatrick 136909467b48Spatrickclass shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin, 137009467b48Spatrick SDPatternOperator OpNode = null_frag>: 137109467b48Spatrick InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 137209467b48Spatrick !strconcat(opstr, "\t$rd, $rt, $rs"), 137309467b48Spatrick [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR, 137409467b48Spatrick opstr>; 137509467b48Spatrick 137609467b48Spatrick// Load Upper Immediate 137709467b48Spatrickclass LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 137809467b48Spatrick InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 137909467b48Spatrick [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove { 138009467b48Spatrick let hasSideEffects = 0; 138109467b48Spatrick let isReMaterializable = 1; 138209467b48Spatrick} 138309467b48Spatrick 138409467b48Spatrick// Memory Load/Store 138509467b48Spatrickclass LoadMemory<string opstr, DAGOperand RO, DAGOperand MO, 138609467b48Spatrick SDPatternOperator OpNode = null_frag, 138709467b48Spatrick InstrItinClass Itin = NoItinerary, 138809467b48Spatrick ComplexPattern Addr = addr> : 138909467b48Spatrick InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 139009467b48Spatrick [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 139109467b48Spatrick let DecoderMethod = "DecodeMem"; 139209467b48Spatrick let canFoldAsLoad = 1; 139309467b48Spatrick string BaseOpcode = opstr; 139409467b48Spatrick let mayLoad = 1; 139509467b48Spatrick} 139609467b48Spatrick 139709467b48Spatrickclass Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 139809467b48Spatrick InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 139909467b48Spatrick LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>; 140009467b48Spatrick 140109467b48Spatrickclass StoreMemory<string opstr, DAGOperand RO, DAGOperand MO, 140209467b48Spatrick SDPatternOperator OpNode = null_frag, 140309467b48Spatrick InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 140409467b48Spatrick InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 140509467b48Spatrick [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 140609467b48Spatrick let DecoderMethod = "DecodeMem"; 140709467b48Spatrick string BaseOpcode = opstr; 140809467b48Spatrick let mayStore = 1; 140909467b48Spatrick} 141009467b48Spatrick 141109467b48Spatrickclass Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 141209467b48Spatrick InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr, 141309467b48Spatrick DAGOperand MO = mem> : 141409467b48Spatrick StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>; 141509467b48Spatrick 141609467b48Spatrick// Load/Store Left/Right 141709467b48Spatricklet canFoldAsLoad = 1 in 141809467b48Spatrickclass LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 141909467b48Spatrick InstrItinClass Itin> : 142009467b48Spatrick InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 142109467b48Spatrick !strconcat(opstr, "\t$rt, $addr"), 142209467b48Spatrick [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 142309467b48Spatrick let DecoderMethod = "DecodeMem"; 142409467b48Spatrick string Constraints = "$src = $rt"; 142509467b48Spatrick let BaseOpcode = opstr; 142609467b48Spatrick} 142709467b48Spatrick 142809467b48Spatrickclass StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 142909467b48Spatrick InstrItinClass Itin> : 143009467b48Spatrick InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 143109467b48Spatrick [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 143209467b48Spatrick let DecoderMethod = "DecodeMem"; 143309467b48Spatrick let BaseOpcode = opstr; 143409467b48Spatrick} 143509467b48Spatrick 143609467b48Spatrick// COP2 Load/Store 143709467b48Spatrickclass LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, 143809467b48Spatrick SDPatternOperator OpNode= null_frag> : 143909467b48Spatrick InstSE<(outs RC:$rt), (ins mem_simm16:$addr), 144009467b48Spatrick !strconcat(opstr, "\t$rt, $addr"), 144109467b48Spatrick [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 144209467b48Spatrick let DecoderMethod = "DecodeFMem2"; 144309467b48Spatrick let mayLoad = 1; 144409467b48Spatrick} 144509467b48Spatrick 144609467b48Spatrickclass SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, 144709467b48Spatrick SDPatternOperator OpNode= null_frag> : 144809467b48Spatrick InstSE<(outs), (ins RC:$rt, mem_simm16:$addr), 144909467b48Spatrick !strconcat(opstr, "\t$rt, $addr"), 145009467b48Spatrick [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 145109467b48Spatrick let DecoderMethod = "DecodeFMem2"; 145209467b48Spatrick let mayStore = 1; 145309467b48Spatrick} 145409467b48Spatrick 145509467b48Spatrick// COP3 Load/Store 145609467b48Spatrickclass LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, 145709467b48Spatrick SDPatternOperator OpNode= null_frag> : 145809467b48Spatrick InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 145909467b48Spatrick [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 146009467b48Spatrick let DecoderMethod = "DecodeFMem3"; 146109467b48Spatrick let mayLoad = 1; 146209467b48Spatrick} 146309467b48Spatrick 146409467b48Spatrickclass SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, 146509467b48Spatrick SDPatternOperator OpNode= null_frag> : 146609467b48Spatrick InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 146709467b48Spatrick [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 146809467b48Spatrick let DecoderMethod = "DecodeFMem3"; 146909467b48Spatrick let mayStore = 1; 147009467b48Spatrick} 147109467b48Spatrick 147209467b48Spatrick// Conditional Branch 147309467b48Spatrickclass CBranch<string opstr, DAGOperand opnd, PatFrag cond_op, 147409467b48Spatrick RegisterOperand RO> : 147509467b48Spatrick InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 147609467b48Spatrick !strconcat(opstr, "\t$rs, $rt, $offset"), 147709467b48Spatrick [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC, 147809467b48Spatrick FrmI, opstr> { 147909467b48Spatrick let isBranch = 1; 148009467b48Spatrick let isTerminator = 1; 148109467b48Spatrick let hasDelaySlot = 1; 148209467b48Spatrick let Defs = [AT]; 148309467b48Spatrick bit isCTI = 1; 148409467b48Spatrick} 148509467b48Spatrick 148609467b48Spatrickclass CBranchLikely<string opstr, DAGOperand opnd, RegisterOperand RO> : 148709467b48Spatrick InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 148809467b48Spatrick !strconcat(opstr, "\t$rs, $rt, $offset"), [], II_BCC, FrmI, opstr> { 148909467b48Spatrick let isBranch = 1; 149009467b48Spatrick let isTerminator = 1; 149109467b48Spatrick let hasDelaySlot = 1; 149209467b48Spatrick let Defs = [AT]; 149309467b48Spatrick bit isCTI = 1; 149409467b48Spatrick} 149509467b48Spatrick 149609467b48Spatrickclass CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op, 149709467b48Spatrick RegisterOperand RO> : 149809467b48Spatrick InstSE<(outs), (ins RO:$rs, opnd:$offset), 149909467b48Spatrick !strconcat(opstr, "\t$rs, $offset"), 150009467b48Spatrick [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ, 150109467b48Spatrick FrmI, opstr> { 150209467b48Spatrick let isBranch = 1; 150309467b48Spatrick let isTerminator = 1; 150409467b48Spatrick let hasDelaySlot = 1; 150509467b48Spatrick let Defs = [AT]; 150609467b48Spatrick bit isCTI = 1; 150709467b48Spatrick} 150809467b48Spatrick 150909467b48Spatrickclass CBranchZeroLikely<string opstr, DAGOperand opnd, RegisterOperand RO> : 151009467b48Spatrick InstSE<(outs), (ins RO:$rs, opnd:$offset), 151109467b48Spatrick !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI, opstr> { 151209467b48Spatrick let isBranch = 1; 151309467b48Spatrick let isTerminator = 1; 151409467b48Spatrick let hasDelaySlot = 1; 151509467b48Spatrick let Defs = [AT]; 151609467b48Spatrick bit isCTI = 1; 151709467b48Spatrick} 151809467b48Spatrick 151909467b48Spatrick// SetCC 152009467b48Spatrickclass SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 152109467b48Spatrick InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 152209467b48Spatrick !strconcat(opstr, "\t$rd, $rs, $rt"), 152309467b48Spatrick [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 152409467b48Spatrick II_SLT_SLTU, FrmR, opstr>; 152509467b48Spatrick 152609467b48Spatrickclass SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 152709467b48Spatrick RegisterOperand RO>: 152809467b48Spatrick InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 152909467b48Spatrick !strconcat(opstr, "\t$rt, $rs, $imm16"), 153009467b48Spatrick [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 153109467b48Spatrick II_SLTI_SLTIU, FrmI, opstr>; 153209467b48Spatrick 153309467b48Spatrick// Jump 153409467b48Spatrickclass JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 153509467b48Spatrick SDPatternOperator targetoperator, string bopstr> : 153609467b48Spatrick InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 153709467b48Spatrick [(operator targetoperator:$target)], II_J, FrmJ, bopstr> { 153809467b48Spatrick let isTerminator=1; 153909467b48Spatrick let isBarrier=1; 154009467b48Spatrick let hasDelaySlot = 1; 154109467b48Spatrick let DecoderMethod = "DecodeJumpTarget"; 154209467b48Spatrick let Defs = [AT]; 154309467b48Spatrick bit isCTI = 1; 154409467b48Spatrick} 154509467b48Spatrick 154609467b48Spatrick// Unconditional branch 154709467b48Spatrickclass UncondBranch<Instruction BEQInst, DAGOperand opnd> : 154809467b48Spatrick PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>, 154909467b48Spatrick PseudoInstExpansion<(BEQInst ZERO, ZERO, opnd:$offset)> { 155009467b48Spatrick let isBranch = 1; 155109467b48Spatrick let isTerminator = 1; 155209467b48Spatrick let isBarrier = 1; 155309467b48Spatrick let hasDelaySlot = 1; 155409467b48Spatrick let AdditionalPredicates = [RelocPIC]; 155509467b48Spatrick let Defs = [AT]; 155609467b48Spatrick bit isCTI = 1; 155709467b48Spatrick} 155809467b48Spatrick 155909467b48Spatrick// Base class for indirect branch and return instruction classes. 156009467b48Spatricklet isTerminator=1, isBarrier=1, hasDelaySlot = 1, isCTI = 1 in 156109467b48Spatrickclass JumpFR<string opstr, RegisterOperand RO, 156209467b48Spatrick SDPatternOperator operator = null_frag>: 156309467b48Spatrick InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR, 156409467b48Spatrick FrmR, opstr>; 156509467b48Spatrick 156609467b48Spatrick// Indirect branch 156709467b48Spatrickclass IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> { 156809467b48Spatrick let isBranch = 1; 156909467b48Spatrick let isIndirectBranch = 1; 157009467b48Spatrick} 157109467b48Spatrick 157209467b48Spatrick// Jump and Link (Call) 157309467b48Spatricklet isCall=1, hasDelaySlot=1, isCTI=1, Defs = [RA] in { 157409467b48Spatrick class JumpLink<string opstr, DAGOperand opnd> : 157509467b48Spatrick InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 157609467b48Spatrick [(MipsJmpLink tglobaladdr:$target)], II_JAL, FrmJ, opstr> { 157709467b48Spatrick let DecoderMethod = "DecodeJumpTarget"; 157809467b48Spatrick } 157909467b48Spatrick 158009467b48Spatrick class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 158109467b48Spatrick Register RetReg, RegisterOperand ResRO = RO>: 158209467b48Spatrick PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>, 158309467b48Spatrick PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)> { 158409467b48Spatrick let hasPostISelHook = 1; 158509467b48Spatrick } 158609467b48Spatrick 158709467b48Spatrick class JumpLinkReg<string opstr, RegisterOperand RO>: 158809467b48Spatrick InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 158909467b48Spatrick [], II_JALR, FrmR, opstr> { 159009467b48Spatrick let hasPostISelHook = 1; 159109467b48Spatrick } 159209467b48Spatrick 159309467b48Spatrick class BGEZAL_FT<string opstr, DAGOperand opnd, 159409467b48Spatrick RegisterOperand RO> : 159509467b48Spatrick InstSE<(outs), (ins RO:$rs, opnd:$offset), 159609467b48Spatrick !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> { 159709467b48Spatrick let hasDelaySlot = 1; 159809467b48Spatrick } 159909467b48Spatrick 160009467b48Spatrick} 160109467b48Spatrick 160209467b48Spatricklet isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, 160309467b48Spatrick hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in { 160409467b48Spatrick class TailCall<Instruction JumpInst, DAGOperand Opnd> : 160509467b48Spatrick PseudoSE<(outs), (ins calltarget:$target), [], II_J>, 160609467b48Spatrick PseudoInstExpansion<(JumpInst Opnd:$target)>; 160709467b48Spatrick 160809467b48Spatrick class TailCallReg<Instruction JumpInst, RegisterOperand RO> : 160909467b48Spatrick PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>, 161009467b48Spatrick PseudoInstExpansion<(JumpInst RO:$rs)> { 161109467b48Spatrick let hasPostISelHook = 1; 161209467b48Spatrick } 161309467b48Spatrick} 161409467b48Spatrick 161509467b48Spatrickclass BAL_BR_Pseudo<Instruction RealInst, DAGOperand opnd> : 161609467b48Spatrick PseudoSE<(outs), (ins opnd:$offset), [], II_BCCZAL>, 161709467b48Spatrick PseudoInstExpansion<(RealInst ZERO, opnd:$offset)> { 161809467b48Spatrick let isBranch = 1; 161909467b48Spatrick let isTerminator = 1; 162009467b48Spatrick let isBarrier = 1; 162109467b48Spatrick let hasDelaySlot = 1; 162209467b48Spatrick let Defs = [RA]; 162309467b48Spatrick bit isCTI = 1; 162409467b48Spatrick} 162509467b48Spatrick 162609467b48Spatricklet isCTI = 1 in { 162709467b48Spatrick// Syscall 162809467b48Spatrickclass SYS_FT<string opstr, Operand ImmOp, InstrItinClass itin = NoItinerary> : 162909467b48Spatrick InstSE<(outs), (ins ImmOp:$code_), 163009467b48Spatrick !strconcat(opstr, "\t$code_"), [], itin, FrmI, opstr>; 163109467b48Spatrick// Break 163209467b48Spatrickclass BRK_FT<string opstr> : 163309467b48Spatrick InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 163409467b48Spatrick !strconcat(opstr, "\t$code_1, $code_2"), [], II_BREAK, 163509467b48Spatrick FrmOther, opstr>; 163609467b48Spatrick 163709467b48Spatrick// (D)Eret 163809467b48Spatrickclass ER_FT<string opstr, InstrItinClass itin = NoItinerary> : 163909467b48Spatrick InstSE<(outs), (ins), 164009467b48Spatrick opstr, [], itin, FrmOther, opstr>; 164109467b48Spatrick 164209467b48Spatrick// Wait 164309467b48Spatrickclass WAIT_FT<string opstr> : 164409467b48Spatrick InstSE<(outs), (ins), opstr, [], II_WAIT, FrmOther, opstr>; 164509467b48Spatrick} 164609467b48Spatrick 164709467b48Spatrick// Interrupts 164809467b48Spatrickclass DEI_FT<string opstr, RegisterOperand RO, 164909467b48Spatrick InstrItinClass itin = NoItinerary> : 165009467b48Spatrick InstSE<(outs RO:$rt), (ins), 165109467b48Spatrick !strconcat(opstr, "\t$rt"), [], itin, FrmOther, opstr>; 165209467b48Spatrick 165309467b48Spatrick// Sync 165409467b48Spatricklet hasSideEffects = 1 in 165509467b48Spatrickclass SYNC_FT<string opstr> : 165609467b48Spatrick InstSE<(outs), (ins uimm5:$stype), "sync $stype", 165709467b48Spatrick [(MipsSync immZExt5:$stype)], II_SYNC, FrmOther, opstr>; 165809467b48Spatrick 165909467b48Spatrickclass SYNCI_FT<string opstr, DAGOperand MO> : 166009467b48Spatrick InstSE<(outs), (ins MO:$addr), !strconcat(opstr, "\t$addr"), [], 166109467b48Spatrick II_SYNCI, FrmOther, opstr> { 166209467b48Spatrick let hasSideEffects = 1; 166309467b48Spatrick let DecoderMethod = "DecodeSyncI"; 166409467b48Spatrick} 166509467b48Spatrick 166609467b48Spatricklet hasSideEffects = 1, isCTI = 1 in { 166709467b48Spatrickclass TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp, 166809467b48Spatrick InstrItinClass itin = NoItinerary> : 166909467b48Spatrick InstSE<(outs), (ins RO:$rs, RO:$rt, ImmOp:$code_), 167009467b48Spatrick !strconcat(opstr, "\t$rs, $rt, $code_"), [], itin, FrmI, opstr>; 167109467b48Spatrick 167209467b48Spatrickclass TEQI_FT<string opstr, RegisterOperand RO, 167309467b48Spatrick InstrItinClass itin = NoItinerary> : 167409467b48Spatrick InstSE<(outs), (ins RO:$rs, simm16:$imm16), 167509467b48Spatrick !strconcat(opstr, "\t$rs, $imm16"), [], itin, FrmOther, opstr>; 167609467b48Spatrick} 167709467b48Spatrick 167809467b48Spatrick// Mul, Div 167909467b48Spatrickclass Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 168009467b48Spatrick list<Register> DefRegs> : 168109467b48Spatrick InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 168209467b48Spatrick itin, FrmR, opstr> { 168309467b48Spatrick let isCommutable = 1; 168409467b48Spatrick let Defs = DefRegs; 168509467b48Spatrick let hasSideEffects = 0; 168609467b48Spatrick} 168709467b48Spatrick 168809467b48Spatrick// Pseudo multiply/divide instruction with explicit accumulator register 168909467b48Spatrick// operands. 169009467b48Spatrickclass MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 169109467b48Spatrick SDPatternOperator OpNode, InstrItinClass Itin, 169209467b48Spatrick bit IsComm = 1, bit HasSideEffects = 0, 169309467b48Spatrick bit UsesCustomInserter = 0> : 169409467b48Spatrick PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 169509467b48Spatrick [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 169609467b48Spatrick PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 169709467b48Spatrick let isCommutable = IsComm; 169809467b48Spatrick let hasSideEffects = HasSideEffects; 169909467b48Spatrick let usesCustomInserter = UsesCustomInserter; 170009467b48Spatrick} 170109467b48Spatrick 170209467b48Spatrick// Pseudo multiply add/sub instruction with explicit accumulator register 170309467b48Spatrick// operands. 170409467b48Spatrickclass MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode, 170509467b48Spatrick InstrItinClass itin> 170609467b48Spatrick : PseudoSE<(outs ACC64:$ac), 170709467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 170809467b48Spatrick [(set ACC64:$ac, 170909467b48Spatrick (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 171009467b48Spatrick itin>, 171109467b48Spatrick PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 171209467b48Spatrick string Constraints = "$acin = $ac"; 171309467b48Spatrick} 171409467b48Spatrick 171509467b48Spatrickclass Div<string opstr, InstrItinClass itin, RegisterOperand RO, 171609467b48Spatrick list<Register> DefRegs> : 171709467b48Spatrick InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 171809467b48Spatrick [], itin, FrmR, opstr> { 171909467b48Spatrick let Defs = DefRegs; 172009467b48Spatrick} 172109467b48Spatrick 172209467b48Spatrick// Move from Hi/Lo 172309467b48Spatrickclass PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> 172409467b48Spatrick : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo), 172509467b48Spatrick [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>; 172609467b48Spatrick 172709467b48Spatrickclass MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>: 172809467b48Spatrick InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO, 172909467b48Spatrick FrmR, opstr> { 173009467b48Spatrick let Uses = [UseReg]; 173109467b48Spatrick let hasSideEffects = 0; 173209467b48Spatrick let isMoveReg = 1; 173309467b48Spatrick} 173409467b48Spatrick 173509467b48Spatrickclass PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC> 173609467b48Spatrick : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi), 173709467b48Spatrick [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], 173809467b48Spatrick II_MTHI_MTLO>; 173909467b48Spatrick 174009467b48Spatrickclass MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 174109467b48Spatrick InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO, 174209467b48Spatrick FrmR, opstr> { 174309467b48Spatrick let Defs = DefRegs; 174409467b48Spatrick let hasSideEffects = 0; 174509467b48Spatrick let isMoveReg = 1; 174609467b48Spatrick} 174709467b48Spatrick 174809467b48Spatrickclass EffectiveAddress<string opstr, RegisterOperand RO> : 174909467b48Spatrick InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 175009467b48Spatrick [(set RO:$rt, addr:$addr)], II_ADDIU, FrmI, 175109467b48Spatrick !strconcat(opstr, "_lea")> { 175209467b48Spatrick let isCodeGenOnly = 1; 175309467b48Spatrick let hasNoSchedulingInfo = 1; 175409467b48Spatrick let DecoderMethod = "DecodeMem"; 175509467b48Spatrick} 175609467b48Spatrick 175709467b48Spatrick// Count Leading Ones/Zeros in Word 175809467b48Spatrickclass CountLeading0<string opstr, RegisterOperand RO, 175909467b48Spatrick InstrItinClass itin = NoItinerary>: 176009467b48Spatrick InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 176109467b48Spatrick [(set RO:$rd, (ctlz RO:$rs))], itin, FrmR, opstr>; 176209467b48Spatrick 176309467b48Spatrickclass CountLeading1<string opstr, RegisterOperand RO, 176409467b48Spatrick InstrItinClass itin = NoItinerary>: 176509467b48Spatrick InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 176609467b48Spatrick [(set RO:$rd, (ctlz (not RO:$rs)))], itin, FrmR, opstr>; 176709467b48Spatrick 176809467b48Spatrick// Sign Extend in Register. 176909467b48Spatrickclass SignExtInReg<string opstr, ValueType vt, RegisterOperand RO, 177009467b48Spatrick InstrItinClass itin> : 177109467b48Spatrick InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 177209467b48Spatrick [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>; 177309467b48Spatrick 177409467b48Spatrick// Subword Swap 177509467b48Spatrickclass SubwordSwap<string opstr, RegisterOperand RO, 177609467b48Spatrick InstrItinClass itin = NoItinerary>: 177709467b48Spatrick InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin, 177809467b48Spatrick FrmR, opstr> { 177909467b48Spatrick let hasSideEffects = 0; 178009467b48Spatrick} 178109467b48Spatrick 178209467b48Spatrick// Read Hardware 178309467b48Spatrickclass ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 178409467b48Spatrick InstSE<(outs CPURegOperand:$rt), (ins RO:$rd, uimm8:$sel), 178509467b48Spatrick "rdhwr\t$rt, $rd, $sel", [], II_RDHWR, FrmR, "rdhwr">; 178609467b48Spatrick 178709467b48Spatrick// Ext and Ins 178809467b48Spatrickclass ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, 178909467b48Spatrick Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm, 179009467b48Spatrick SDPatternOperator Op = null_frag> : 179109467b48Spatrick InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size), 179209467b48Spatrick !strconcat(opstr, "\t$rt, $rs, $pos, $size"), 179309467b48Spatrick [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT, 179409467b48Spatrick FrmR, opstr>; 179509467b48Spatrick 179609467b48Spatrick// 'ins' and its' 64 bit variants are matched by C++ code. 179709467b48Spatrickclass InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, 179809467b48Spatrick Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm>: 179909467b48Spatrick InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src), 180009467b48Spatrick !strconcat(opstr, "\t$rt, $rs, $pos, $size"), 180109467b48Spatrick [(set RO:$rt, (null_frag RO:$rs, PosImm:$pos, SizeImm:$size, 180209467b48Spatrick RO:$src))], 180309467b48Spatrick II_INS, FrmR, opstr> { 180409467b48Spatrick let Constraints = "$src = $rt"; 180509467b48Spatrick} 180609467b48Spatrick 180709467b48Spatrick// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 180809467b48Spatrickclass Atomic2Ops<PatFrag Op, RegisterClass DRC> : 180909467b48Spatrick PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 181009467b48Spatrick [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]> { 181109467b48Spatrick let hasNoSchedulingInfo = 1; 181209467b48Spatrick} 181309467b48Spatrick 181409467b48Spatrickclass Atomic2OpsPostRA<RegisterClass RC> : 181509467b48Spatrick PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$incr), []> { 181609467b48Spatrick let mayLoad = 1; 181709467b48Spatrick let mayStore = 1; 181809467b48Spatrick} 181909467b48Spatrick 182009467b48Spatrickclass Atomic2OpsSubwordPostRA<RegisterClass RC> : 182109467b48Spatrick PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$incr, RC:$mask, RC:$mask2, 182209467b48Spatrick RC:$shiftamnt), []>; 182309467b48Spatrick 182409467b48Spatrick// Atomic Compare & Swap. 182509467b48Spatrick// Atomic compare and swap is lowered into two stages. The first stage happens 182609467b48Spatrick// during ISelLowering, which produces the PostRA version of this instruction. 182709467b48Spatrickclass AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 182809467b48Spatrick PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 182909467b48Spatrick [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]> { 183009467b48Spatrick let hasNoSchedulingInfo = 1; 183109467b48Spatrick} 183209467b48Spatrick 183309467b48Spatrickclass AtomicCmpSwapPostRA<RegisterClass RC> : 183409467b48Spatrick PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$cmp, RC:$swap), []> { 183509467b48Spatrick let mayLoad = 1; 183609467b48Spatrick let mayStore = 1; 183709467b48Spatrick} 183809467b48Spatrick 183909467b48Spatrickclass AtomicCmpSwapSubwordPostRA<RegisterClass RC> : 184009467b48Spatrick PseudoSE<(outs RC:$dst), (ins PtrRC:$ptr, RC:$mask, RC:$ShiftCmpVal, 184109467b48Spatrick RC:$mask2, RC:$ShiftNewVal, RC:$ShiftAmt), []> { 184209467b48Spatrick let mayLoad = 1; 184309467b48Spatrick let mayStore = 1; 184409467b48Spatrick} 184509467b48Spatrick 184609467b48Spatrickclass LLBase<string opstr, RegisterOperand RO, DAGOperand MO = mem> : 184709467b48Spatrick InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 184809467b48Spatrick [], II_LL, FrmI, opstr> { 184909467b48Spatrick let DecoderMethod = "DecodeMem"; 185009467b48Spatrick let mayLoad = 1; 185109467b48Spatrick} 185209467b48Spatrick 185309467b48Spatrickclass SCBase<string opstr, RegisterOperand RO> : 185409467b48Spatrick InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 185509467b48Spatrick !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> { 185609467b48Spatrick let DecoderMethod = "DecodeMem"; 185709467b48Spatrick let mayStore = 1; 185809467b48Spatrick let Constraints = "$rt = $dst"; 185909467b48Spatrick} 186009467b48Spatrick 186109467b48Spatrickclass MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD, 186209467b48Spatrick InstrItinClass itin> : 186309467b48Spatrick InstSE<(outs RO:$rt), (ins RD:$rd, uimm3:$sel), 186409467b48Spatrick !strconcat(asmstr, "\t$rt, $rd, $sel"), [], itin, FrmFR> { 186509467b48Spatrick let BaseOpcode = asmstr; 186609467b48Spatrick} 186709467b48Spatrick 186809467b48Spatrickclass MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD, 186909467b48Spatrick InstrItinClass itin> : 187009467b48Spatrick InstSE<(outs RO:$rd), (ins RD:$rt, uimm3:$sel), 187109467b48Spatrick !strconcat(asmstr, "\t$rt, $rd, $sel"), [], itin, FrmFR> { 187209467b48Spatrick let BaseOpcode = asmstr; 187309467b48Spatrick} 187409467b48Spatrick 187509467b48Spatrickclass TrapBase<Instruction RealInst> 187609467b48Spatrick : PseudoSE<(outs), (ins), [(trap)], II_TRAP>, 187709467b48Spatrick PseudoInstExpansion<(RealInst 0, 0)> { 1878097a140dSpatrick let mayStore = 0; 1879097a140dSpatrick let mayLoad = 0; 1880097a140dSpatrick let hasSideEffects = 1; 1881097a140dSpatrick let isTrap = 1; 188209467b48Spatrick let isCodeGenOnly = 1; 188309467b48Spatrick} 188409467b48Spatrick 188509467b48Spatrick//===----------------------------------------------------------------------===// 188609467b48Spatrick// Pseudo instructions 188709467b48Spatrick//===----------------------------------------------------------------------===// 188809467b48Spatrick 188909467b48Spatrick// Return RA. 189009467b48Spatricklet isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, isCTI=1 in { 189109467b48Spatrick let hasDelaySlot=1 in 189209467b48Spatrick def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 189309467b48Spatrick 189409467b48Spatrick let hasSideEffects=1 in 189509467b48Spatrick def ERet : PseudoSE<(outs), (ins), [(MipsERet)]>; 189609467b48Spatrick} 189709467b48Spatrick 189809467b48Spatricklet Defs = [SP], Uses = [SP], hasSideEffects = 1, hasNoSchedulingInfo = 1 in { 189909467b48Spatrickdef ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 190009467b48Spatrick [(callseq_start timm:$amt1, timm:$amt2)]>; 190109467b48Spatrickdef ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 190209467b48Spatrick [(callseq_end timm:$amt1, timm:$amt2)]>; 190309467b48Spatrick} 190409467b48Spatrick 190509467b48Spatricklet usesCustomInserter = 1 in { 190609467b48Spatrick def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 190709467b48Spatrick def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 190809467b48Spatrick def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 190909467b48Spatrick def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 191009467b48Spatrick def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 191109467b48Spatrick def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 191209467b48Spatrick def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 191309467b48Spatrick def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 191409467b48Spatrick def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 191509467b48Spatrick def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 191609467b48Spatrick def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 191709467b48Spatrick def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 191809467b48Spatrick def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 191909467b48Spatrick def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 192009467b48Spatrick def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 192109467b48Spatrick def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 192209467b48Spatrick def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 192309467b48Spatrick def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 192409467b48Spatrick 192509467b48Spatrick def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 192609467b48Spatrick def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 192709467b48Spatrick def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 192809467b48Spatrick 192909467b48Spatrick def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 193009467b48Spatrick def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 193109467b48Spatrick def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 193209467b48Spatrick 193309467b48Spatrick def ATOMIC_LOAD_MIN_I8 : Atomic2Ops<atomic_load_min_8, GPR32>; 193409467b48Spatrick def ATOMIC_LOAD_MIN_I16 : Atomic2Ops<atomic_load_min_16, GPR32>; 193509467b48Spatrick def ATOMIC_LOAD_MIN_I32 : Atomic2Ops<atomic_load_min_32, GPR32>; 193609467b48Spatrick def ATOMIC_LOAD_MAX_I8 : Atomic2Ops<atomic_load_max_8, GPR32>; 193709467b48Spatrick def ATOMIC_LOAD_MAX_I16 : Atomic2Ops<atomic_load_max_16, GPR32>; 193809467b48Spatrick def ATOMIC_LOAD_MAX_I32 : Atomic2Ops<atomic_load_max_32, GPR32>; 193909467b48Spatrick def ATOMIC_LOAD_UMIN_I8 : Atomic2Ops<atomic_load_umin_8, GPR32>; 194009467b48Spatrick def ATOMIC_LOAD_UMIN_I16 : Atomic2Ops<atomic_load_umin_16, GPR32>; 194109467b48Spatrick def ATOMIC_LOAD_UMIN_I32 : Atomic2Ops<atomic_load_umin_32, GPR32>; 194209467b48Spatrick def ATOMIC_LOAD_UMAX_I8 : Atomic2Ops<atomic_load_umax_8, GPR32>; 194309467b48Spatrick def ATOMIC_LOAD_UMAX_I16 : Atomic2Ops<atomic_load_umax_16, GPR32>; 194409467b48Spatrick def ATOMIC_LOAD_UMAX_I32 : Atomic2Ops<atomic_load_umax_32, GPR32>; 194509467b48Spatrick} 194609467b48Spatrick 194709467b48Spatrickdef ATOMIC_LOAD_ADD_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 194809467b48Spatrickdef ATOMIC_LOAD_ADD_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 194909467b48Spatrickdef ATOMIC_LOAD_ADD_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 195009467b48Spatrickdef ATOMIC_LOAD_SUB_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 195109467b48Spatrickdef ATOMIC_LOAD_SUB_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 195209467b48Spatrickdef ATOMIC_LOAD_SUB_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 195309467b48Spatrickdef ATOMIC_LOAD_AND_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 195409467b48Spatrickdef ATOMIC_LOAD_AND_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 195509467b48Spatrickdef ATOMIC_LOAD_AND_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 195609467b48Spatrickdef ATOMIC_LOAD_OR_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 195709467b48Spatrickdef ATOMIC_LOAD_OR_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 195809467b48Spatrickdef ATOMIC_LOAD_OR_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 195909467b48Spatrickdef ATOMIC_LOAD_XOR_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 196009467b48Spatrickdef ATOMIC_LOAD_XOR_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 196109467b48Spatrickdef ATOMIC_LOAD_XOR_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 196209467b48Spatrickdef ATOMIC_LOAD_NAND_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 196309467b48Spatrickdef ATOMIC_LOAD_NAND_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 196409467b48Spatrickdef ATOMIC_LOAD_NAND_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 196509467b48Spatrick 196609467b48Spatrickdef ATOMIC_SWAP_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 196709467b48Spatrickdef ATOMIC_SWAP_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 196809467b48Spatrickdef ATOMIC_SWAP_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 196909467b48Spatrick 197009467b48Spatrickdef ATOMIC_CMP_SWAP_I8_POSTRA : AtomicCmpSwapSubwordPostRA<GPR32>; 197109467b48Spatrickdef ATOMIC_CMP_SWAP_I16_POSTRA : AtomicCmpSwapSubwordPostRA<GPR32>; 197209467b48Spatrickdef ATOMIC_CMP_SWAP_I32_POSTRA : AtomicCmpSwapPostRA<GPR32>; 197309467b48Spatrick 197409467b48Spatrickdef ATOMIC_LOAD_MIN_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 197509467b48Spatrickdef ATOMIC_LOAD_MIN_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 197609467b48Spatrickdef ATOMIC_LOAD_MIN_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 197709467b48Spatrickdef ATOMIC_LOAD_MAX_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 197809467b48Spatrickdef ATOMIC_LOAD_MAX_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 197909467b48Spatrickdef ATOMIC_LOAD_MAX_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 198009467b48Spatrickdef ATOMIC_LOAD_UMIN_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 198109467b48Spatrickdef ATOMIC_LOAD_UMIN_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 198209467b48Spatrickdef ATOMIC_LOAD_UMIN_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 198309467b48Spatrickdef ATOMIC_LOAD_UMAX_I8_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 198409467b48Spatrickdef ATOMIC_LOAD_UMAX_I16_POSTRA : Atomic2OpsSubwordPostRA<GPR32>; 198509467b48Spatrickdef ATOMIC_LOAD_UMAX_I32_POSTRA : Atomic2OpsPostRA<GPR32>; 198609467b48Spatrick 198709467b48Spatrick/// Pseudo instructions for loading and storing accumulator registers. 198809467b48Spatricklet isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { 198909467b48Spatrick def LOAD_ACC64 : Load<"", ACC64>; 199009467b48Spatrick def STORE_ACC64 : Store<"", ACC64>; 199109467b48Spatrick} 199209467b48Spatrick 199309467b48Spatrick// We need these two pseudo instructions to avoid offset calculation for long 199409467b48Spatrick// branches. See the comment in file MipsLongBranch.cpp for detailed 199509467b48Spatrick// explanation. 199609467b48Spatrick 199709467b48Spatrick// Expands to: lui $dst, %highest/%higher/%hi/%lo($tgt - $baltgt) 199809467b48Spatrickdef LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst), 199909467b48Spatrick (ins brtarget:$tgt, brtarget:$baltgt), []> { 200009467b48Spatrick bit hasNoSchedulingInfo = 1; 200109467b48Spatrick} 200209467b48Spatrick// Expands to: lui $dst, highest/%higher/%hi/%lo($tgt) 200309467b48Spatrickdef LONG_BRANCH_LUi2Op : PseudoSE<(outs GPR32Opnd:$dst), 200409467b48Spatrick (ins brtarget:$tgt), []> { 200509467b48Spatrick bit hasNoSchedulingInfo = 1; 200609467b48Spatrick} 200709467b48Spatrick 200809467b48Spatrick// Expands to: addiu $dst, $src, %highest/%higher/%hi/%lo($tgt - $baltgt) 200909467b48Spatrickdef LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst), 201009467b48Spatrick (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []> { 201109467b48Spatrick bit hasNoSchedulingInfo = 1; 201209467b48Spatrick} 201309467b48Spatrick// Expands to: addiu $dst, $src, %highest/%higher/%hi/%lo($tgt) 201409467b48Spatrickdef LONG_BRANCH_ADDiu2Op : PseudoSE<(outs GPR32Opnd:$dst), 201509467b48Spatrick (ins GPR32Opnd:$src, brtarget:$tgt), []> { 201609467b48Spatrick bit hasNoSchedulingInfo = 1; 201709467b48Spatrick} 201809467b48Spatrick 2019adae0cfdSpatrick// Pseudo instructions used by retguard. In order to calculste the PC 2020adae0cfdSpatrick// for PIC code, we use a pair of pseudos to get the function address 2021adae0cfdSpatrick// into T9, which is normally used to hold this value but is trashed 2022adae0cfdSpatrick// by function epilogue. 2023adae0cfdSpatricklet isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { 2024adae0cfdSpatrick 2025adae0cfdSpatrick // Use BAL to get the PC into RA, then calculate the address of the 2026adae0cfdSpatrick // current function and save this value in $rd. $rs and $rt are used 2027adae0cfdSpatrick // as scratch registers and are trashed by this pseudo. $tgt is the 2028adae0cfdSpatrick // symbol to branch to when calling BAL. 2029adae0cfdSpatrick let Size = 32 in { 2030adae0cfdSpatrick def RETGUARD_GET_FUNCTION_ADDR: PseudoSE<(outs GPR64:$rd), 2031adae0cfdSpatrick (ins GPR64:$rs, GPR64:$rt, brtarget:$tgt), []>; 2032adae0cfdSpatrick } 2033adae0cfdSpatrick 2034adae0cfdSpatrick // Emit the symbol used for $tgt in RETGUARD_GET_FUNCTION_ADDR. We 2035adae0cfdSpatrick // emit this symbol immediately before the usual function return, with 2036adae0cfdSpatrick // the effect that the BAL branches to an immediate return and resumes 2037adae0cfdSpatrick // execution through the rest of the RETGUARD epilogue. We pair BAL 2038adae0cfdSpatrick // with RET to satisfy return branch predictors. 2039adae0cfdSpatrick let Size = 0 in { 2040adae0cfdSpatrick def RETGUARD_EMIT_SYMBOL: PseudoSE<(outs), (ins brtarget:$tgt), []>; 2041adae0cfdSpatrick } 2042adae0cfdSpatrick} 2043adae0cfdSpatrick 204409467b48Spatrick//===----------------------------------------------------------------------===// 204509467b48Spatrick// Instruction definition 204609467b48Spatrick//===----------------------------------------------------------------------===// 204709467b48Spatrick//===----------------------------------------------------------------------===// 204809467b48Spatrick// MipsI Instructions 204909467b48Spatrick//===----------------------------------------------------------------------===// 205009467b48Spatrick 205109467b48Spatrick/// Arithmetic Instructions (ALU Immediate) 205209467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 205309467b48Spatrick def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd, 205409467b48Spatrick II_ADDIU, imm32SExt16, add>, 205509467b48Spatrick ADDI_FM<0x9>, IsAsCheapAsAMove, ISA_MIPS1; 205609467b48Spatrick 205709467b48Spatrick def ANDi : MMRel, StdMMR6Rel, 205809467b48Spatrick ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, imm32ZExt16, and>, 205909467b48Spatrick ADDI_FM<0xc>, ISA_MIPS1; 206009467b48Spatrick def ORi : MMRel, StdMMR6Rel, 206109467b48Spatrick ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, imm32ZExt16, or>, 206209467b48Spatrick ADDI_FM<0xd>, ISA_MIPS1; 206309467b48Spatrick def XORi : MMRel, StdMMR6Rel, 206409467b48Spatrick ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, imm32ZExt16, xor>, 206509467b48Spatrick ADDI_FM<0xe>, ISA_MIPS1; 206609467b48Spatrick def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, 206709467b48Spatrick ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; 206809467b48Spatrick def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 206909467b48Spatrick SLTI_FM<0xa>, ISA_MIPS1; 207009467b48Spatrick def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 207109467b48Spatrick SLTI_FM<0xb>, ISA_MIPS1; 207209467b48Spatrick 207309467b48Spatrick def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM, 207409467b48Spatrick ISA_MIPS1; 207509467b48Spatrick 207609467b48Spatrick /// Arithmetic Instructions (3-Operand, R-Type) 207709467b48Spatrick def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, 207809467b48Spatrick ADD_FM<0, 0x21>, ISA_MIPS1; 207909467b48Spatrick def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, 208009467b48Spatrick ADD_FM<0, 0x23>, ISA_MIPS1; 208109467b48Spatrick 208209467b48Spatrick let Defs = [HI0, LO0] in 208309467b48Spatrick def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, 208409467b48Spatrick ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; 208509467b48Spatrick 208609467b48Spatrick def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, 208709467b48Spatrick ADD_FM<0, 0x20>, ISA_MIPS1; 208809467b48Spatrick def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, 208909467b48Spatrick ADD_FM<0, 0x22>, ISA_MIPS1; 209009467b48Spatrick 209109467b48Spatrick def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>, 209209467b48Spatrick ISA_MIPS1; 209309467b48Spatrick def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>, 209409467b48Spatrick ISA_MIPS1; 209509467b48Spatrick def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, 209609467b48Spatrick ADD_FM<0, 0x24>, ISA_MIPS1; 209709467b48Spatrick def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, 209809467b48Spatrick ADD_FM<0, 0x25>, ISA_MIPS1; 209909467b48Spatrick def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, 210009467b48Spatrick ADD_FM<0, 0x26>, ISA_MIPS1; 210109467b48Spatrick def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>, 210209467b48Spatrick ISA_MIPS1; 210309467b48Spatrick} 210409467b48Spatrick 210509467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 210609467b48Spatrick /// Shift Instructions 210709467b48Spatrick def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, 210809467b48Spatrick immZExt5>, SRA_FM<0, 0>, ISA_MIPS1; 210909467b48Spatrick def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, 211009467b48Spatrick immZExt5>, SRA_FM<2, 0>, ISA_MIPS1; 211109467b48Spatrick def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, 211209467b48Spatrick immZExt5>, SRA_FM<3, 0>, ISA_MIPS1; 211309467b48Spatrick def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, 211409467b48Spatrick SRLV_FM<4, 0>, ISA_MIPS1; 211509467b48Spatrick def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, 211609467b48Spatrick SRLV_FM<6, 0>, ISA_MIPS1; 211709467b48Spatrick def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, 211809467b48Spatrick SRLV_FM<7, 0>, ISA_MIPS1; 211909467b48Spatrick 212009467b48Spatrick // Rotate Instructions 212109467b48Spatrick def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, 212209467b48Spatrick immZExt5>, 212309467b48Spatrick SRA_FM<2, 1>, ISA_MIPS32R2; 212409467b48Spatrick def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, 212509467b48Spatrick SRLV_FM<6, 1>, ISA_MIPS32R2; 212609467b48Spatrick} 212709467b48Spatrick 212809467b48Spatrick/// Load and Store Instructions 212909467b48Spatrick/// aligned 213009467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 213109467b48Spatrick def LB : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel, 213209467b48Spatrick LW_FM<0x20>, ISA_MIPS1; 213309467b48Spatrick def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU, 213409467b48Spatrick addrDefault>, MMRel, LW_FM<0x24>, ISA_MIPS1; 213509467b48Spatrick def LH : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH, 213609467b48Spatrick addrDefault>, MMRel, LW_FM<0x21>, ISA_MIPS1; 213709467b48Spatrick def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>, 213809467b48Spatrick MMRel, LW_FM<0x25>, ISA_MIPS1; 213909467b48Spatrick def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, 214009467b48Spatrick LW_FM<0x23>, ISA_MIPS1; 214109467b48Spatrick def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, 214209467b48Spatrick LW_FM<0x28>, ISA_MIPS1; 214309467b48Spatrick def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>, 214409467b48Spatrick ISA_MIPS1; 214509467b48Spatrick def SW : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>, 214609467b48Spatrick MMRel, LW_FM<0x2b>, ISA_MIPS1; 214709467b48Spatrick} 214809467b48Spatrick 214909467b48Spatrick/// load/store left/right 215009467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 215109467b48Spatrickdef LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>, 215209467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 215309467b48Spatrickdef LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>, 215409467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 215509467b48Spatrickdef SWL : MMRel, StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>, 215609467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 215709467b48Spatrickdef SWR : MMRel, StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>, 215809467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 215909467b48Spatrick 216009467b48Spatrick// COP2 Memory Instructions 216109467b48Spatrickdef LWC2 : StdMMR6Rel, LW_FT2<"lwc2", COP2Opnd, II_LWC2, load>, LW_FM<0x32>, 216209467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 216309467b48Spatrickdef SWC2 : StdMMR6Rel, SW_FT2<"swc2", COP2Opnd, II_SWC2, store>, 216409467b48Spatrick LW_FM<0x3a>, ISA_MIPS1_NOT_32R6_64R6; 216509467b48Spatrickdef LDC2 : StdMMR6Rel, LW_FT2<"ldc2", COP2Opnd, II_LDC2, load>, LW_FM<0x36>, 216609467b48Spatrick ISA_MIPS2_NOT_32R6_64R6; 216709467b48Spatrickdef SDC2 : StdMMR6Rel, SW_FT2<"sdc2", COP2Opnd, II_SDC2, store>, 216809467b48Spatrick LW_FM<0x3e>, ISA_MIPS2_NOT_32R6_64R6; 216909467b48Spatrick 217009467b48Spatrick// COP3 Memory Instructions 217109467b48Spatricklet DecoderNamespace = "COP3_" in { 217209467b48Spatrick def LWC3 : LW_FT3<"lwc3", COP3Opnd, II_LWC3, load>, LW_FM<0x33>, 217309467b48Spatrick ISA_MIPS1_NOT_32R6_64R6, NOT_ASE_CNMIPS; 217409467b48Spatrick def SWC3 : SW_FT3<"swc3", COP3Opnd, II_SWC3, store>, LW_FM<0x3b>, 217509467b48Spatrick ISA_MIPS1_NOT_32R6_64R6, NOT_ASE_CNMIPS; 217609467b48Spatrick def LDC3 : LW_FT3<"ldc3", COP3Opnd, II_LDC3, load>, LW_FM<0x37>, 217709467b48Spatrick ISA_MIPS2, NOT_ASE_CNMIPS; 217809467b48Spatrick def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>, 217909467b48Spatrick ISA_MIPS2, NOT_ASE_CNMIPS; 218009467b48Spatrick} 218109467b48Spatrick 218209467b48Spatrick def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2; 218309467b48Spatrick def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci", mem_simm16>, SYNCI_FM, 218409467b48Spatrick ISA_MIPS32R2; 218509467b48Spatrick} 218609467b48Spatrick 218709467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 218809467b48Spatrick def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, 218909467b48Spatrick ISA_MIPS2; 219009467b48Spatrick def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>, 219109467b48Spatrick ISA_MIPS2; 219209467b48Spatrick def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>, 219309467b48Spatrick ISA_MIPS2; 219409467b48Spatrick def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10, II_TLT>, TEQ_FM<0x32>, 219509467b48Spatrick ISA_MIPS2; 219609467b48Spatrick def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>, 219709467b48Spatrick ISA_MIPS2; 219809467b48Spatrick def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm10, II_TNE>, TEQ_FM<0x36>, 219909467b48Spatrick ISA_MIPS2; 220009467b48Spatrick 220109467b48Spatrick def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM<0xc>, 220209467b48Spatrick ISA_MIPS2_NOT_32R6_64R6; 220309467b48Spatrick def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM<0x8>, 220409467b48Spatrick ISA_MIPS2_NOT_32R6_64R6; 220509467b48Spatrick def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>, TEQI_FM<0x9>, 220609467b48Spatrick ISA_MIPS2_NOT_32R6_64R6; 220709467b48Spatrick def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM<0xa>, 220809467b48Spatrick ISA_MIPS2_NOT_32R6_64R6; 220909467b48Spatrick def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>, TEQI_FM<0xb>, 221009467b48Spatrick ISA_MIPS2_NOT_32R6_64R6; 221109467b48Spatrick def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM<0xe>, 221209467b48Spatrick ISA_MIPS2_NOT_32R6_64R6; 221309467b48Spatrick} 221409467b48Spatrick 221509467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 221609467b48Spatrick def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>, ISA_MIPS1; 221709467b48Spatrick def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>, 221809467b48Spatrick ISA_MIPS1; 221909467b48Spatrick def TRAP : TrapBase<BREAK>, ISA_MIPS1; 222009467b48Spatrick def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM, 222109467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 222209467b48Spatrick 222309467b48Spatrick def ERET : MMRel, ER_FT<"eret", II_ERET>, ER_FM<0x18, 0x0>, INSN_MIPS3_32; 222409467b48Spatrick def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>, 222509467b48Spatrick ISA_MIPS32R5; 222609467b48Spatrick def DERET : MMRel, ER_FT<"deret", II_DERET>, ER_FM<0x1f, 0x0>, ISA_MIPS32; 222709467b48Spatrick 222809467b48Spatrick def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>, 222909467b48Spatrick ISA_MIPS32R2; 223009467b48Spatrick def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>, 223109467b48Spatrick ISA_MIPS32R2; 223209467b48Spatrick 223309467b48Spatrick def WAIT : MMRel, StdMMR6Rel, WAIT_FT<"wait">, WAIT_FM, INSN_MIPS3_32; 223409467b48Spatrick} 223509467b48Spatrick 223609467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 223709467b48Spatrick/// Load-linked, Store-conditional 223809467b48Spatrickdef LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_32, ISA_MIPS2_NOT_32R6_64R6; 223909467b48Spatrickdef SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6; 224009467b48Spatrick} 224109467b48Spatrick/// Jump and Branch Instructions 224209467b48Spatricklet AdditionalPredicates = [NotInMicroMips, RelocNotPIC] in 224309467b48Spatrickdef J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>, 224409467b48Spatrick IsBranch, ISA_MIPS1; 224509467b48Spatrick 224609467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 224709467b48Spatrickdef JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, 224809467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 224909467b48Spatrickdef BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>, 225009467b48Spatrick ISA_MIPS1; 225109467b48Spatrickdef BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>, 225209467b48Spatrick BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6; 225309467b48Spatrickdef BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>, 225409467b48Spatrick ISA_MIPS1; 225509467b48Spatrickdef BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>, 225609467b48Spatrick BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6; 225709467b48Spatrickdef BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>, 225809467b48Spatrick BGEZ_FM<1, 1>, ISA_MIPS1; 225909467b48Spatrickdef BGEZL : MMRel, CBranchZeroLikely<"bgezl", brtarget, GPR32Opnd>, 226009467b48Spatrick BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6; 226109467b48Spatrickdef BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, 226209467b48Spatrick BGEZ_FM<7, 0>, ISA_MIPS1; 226309467b48Spatrickdef BGTZL : MMRel, CBranchZeroLikely<"bgtzl", brtarget, GPR32Opnd>, 226409467b48Spatrick BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6; 226509467b48Spatrickdef BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>, 226609467b48Spatrick BGEZ_FM<6, 0>, ISA_MIPS1; 226709467b48Spatrickdef BLEZL : MMRel, CBranchZeroLikely<"blezl", brtarget, GPR32Opnd>, 226809467b48Spatrick BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6; 226909467b48Spatrickdef BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, 227009467b48Spatrick BGEZ_FM<1, 0>, ISA_MIPS1; 227109467b48Spatrickdef BLTZL : MMRel, CBranchZeroLikely<"bltzl", brtarget, GPR32Opnd>, 227209467b48Spatrick BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6; 227309467b48Spatrickdef B : UncondBranch<BEQ, brtarget>, ISA_MIPS1; 227409467b48Spatrick 227509467b48Spatrickdef JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>, ISA_MIPS1; 227609467b48Spatrick 227709467b48Spatrick} 227809467b48Spatrick 227909467b48Spatricklet AdditionalPredicates = [NotInMicroMips, NoIndirectJumpGuards] in { 228009467b48Spatrick def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM, ISA_MIPS1; 228109467b48Spatrick def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>, ISA_MIPS1; 228209467b48Spatrick} 228309467b48Spatrick 228409467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 228509467b48Spatrick def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>, 228609467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 228709467b48Spatrick def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>, 228809467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 228909467b48Spatrick def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>, 229009467b48Spatrick BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6; 229109467b48Spatrick def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>, 229209467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 229309467b48Spatrick def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>, 229409467b48Spatrick BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6; 229509467b48Spatrick def BAL_BR : BAL_BR_Pseudo<BGEZAL, brtarget>, ISA_MIPS1; 229609467b48Spatrick} 229709467b48Spatricklet AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in { 229809467b48Spatrick def TAILCALL : TailCall<J, jmptarget>, ISA_MIPS1; 229909467b48Spatrick} 230009467b48Spatricklet AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 230109467b48Spatrick NoIndirectJumpGuards] in 230209467b48Spatrick def TAILCALLREG : TailCallReg<JR, GPR32Opnd>, ISA_MIPS1_NOT_32R6_64R6; 230309467b48Spatrick 230409467b48Spatrick// Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64 230509467b48Spatrick// then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA. 230609467b48Spatrickclass PseudoIndirectBranchBase<Instruction JumpInst, RegisterOperand RO> : 230709467b48Spatrick MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], 230809467b48Spatrick II_IndirectBranchPseudo>, 230909467b48Spatrick PseudoInstExpansion<(JumpInst RO:$rs)> { 231009467b48Spatrick let isTerminator=1; 231109467b48Spatrick let isBarrier=1; 231209467b48Spatrick let hasDelaySlot = 1; 231309467b48Spatrick let isBranch = 1; 231409467b48Spatrick let isIndirectBranch = 1; 231509467b48Spatrick bit isCTI = 1; 231609467b48Spatrick} 231709467b48Spatrick 231809467b48Spatricklet AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 231909467b48Spatrick NoIndirectJumpGuards] in 232009467b48Spatrick def PseudoIndirectBranch : PseudoIndirectBranchBase<JR, GPR32Opnd>, 232109467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 232209467b48Spatrick 232309467b48Spatrick// Return instructions are matched as a RetRA instruction, then are expanded 232409467b48Spatrick// into PseudoReturn/PseudoReturn64 after register allocation. Finally, 232509467b48Spatrick// MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the 232609467b48Spatrick// ISA. 232709467b48Spatrickclass PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs), 232809467b48Spatrick [], II_ReturnPseudo> { 232909467b48Spatrick let isTerminator = 1; 233009467b48Spatrick let isBarrier = 1; 233109467b48Spatrick let hasDelaySlot = 1; 233209467b48Spatrick let isReturn = 1; 233309467b48Spatrick let isCodeGenOnly = 1; 233409467b48Spatrick let hasCtrlDep = 1; 233509467b48Spatrick let hasExtraSrcRegAllocReq = 1; 233609467b48Spatrick bit isCTI = 1; 233709467b48Spatrick} 233809467b48Spatrick 233909467b48Spatrickdef PseudoReturn : PseudoReturnBase<GPR32Opnd>; 234009467b48Spatrick 234109467b48Spatrick// Exception handling related node and instructions. 234209467b48Spatrick// The conversion sequence is: 234309467b48Spatrick// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 234409467b48Spatrick// MIPSeh_return -> (stack change + indirect branch) 234509467b48Spatrick// 234609467b48Spatrick// MIPSeh_return takes the place of regular return instruction 234709467b48Spatrick// but takes two arguments (V1, V0) which are used for storing 234809467b48Spatrick// the offset and return address respectively. 234909467b48Spatrickdef SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 235009467b48Spatrick 235109467b48Spatrickdef MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 235209467b48Spatrick [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 235309467b48Spatrick 235409467b48Spatricklet Uses = [V0, V1], isTerminator = 1, isReturn = 1, 235509467b48Spatrick isBarrier = 1, isCTI = 1, hasNoSchedulingInfo = 1 in { 235609467b48Spatrick def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 235709467b48Spatrick [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 235809467b48Spatrick def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, GPR64:$dst), 235909467b48Spatrick [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 236009467b48Spatrick} 236109467b48Spatrick 236209467b48Spatrick/// Multiply and Divide Instructions. 236309467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 236409467b48Spatrick def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, 236509467b48Spatrick MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6; 236609467b48Spatrick def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, 236709467b48Spatrick MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6; 236809467b48Spatrick def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>, 236909467b48Spatrick MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6; 237009467b48Spatrick def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>, 237109467b48Spatrick MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6; 237209467b48Spatrick def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>, 237309467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 237409467b48Spatrick def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, 237509467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 237609467b48Spatrick def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, 237709467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 237809467b48Spatrick def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, 237909467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 238009467b48Spatrick 238109467b48Spatrick /// Sign Ext In Register Instructions. 238209467b48Spatrick def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, 238309467b48Spatrick SEB_FM<0x10, 0x20>, ISA_MIPS32R2; 238409467b48Spatrick def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, 238509467b48Spatrick SEB_FM<0x18, 0x20>, ISA_MIPS32R2; 238609467b48Spatrick 238709467b48Spatrick /// Count Leading 238809467b48Spatrick def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>, 238909467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 239009467b48Spatrick def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>, 239109467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 239209467b48Spatrick 239309467b48Spatrick /// Word Swap Bytes Within Halfwords 239409467b48Spatrick def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>, 239509467b48Spatrick ISA_MIPS32R2; 239609467b48Spatrick 239709467b48Spatrick /// No operation. 239809467b48Spatrick def NOP : PseudoSE<(outs), (ins), []>, 239909467b48Spatrick PseudoInstExpansion<(SLL ZERO, ZERO, 0)>, ISA_MIPS1; 240009467b48Spatrick 240109467b48Spatrick // FrameIndexes are legalized when they are operands from load/store 240209467b48Spatrick // instructions. The same not happens for stack address copies, so an 240309467b48Spatrick // add op with mem ComplexPattern is used and the stack address copy 240409467b48Spatrick // can be matched. It's similar to Sparc LEA_ADDRi 240509467b48Spatrick let AdditionalPredicates = [NotInMicroMips] in 240609467b48Spatrick def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, 240709467b48Spatrick ISA_MIPS1; 240809467b48Spatrick 240909467b48Spatrick // MADD*/MSUB* 241009467b48Spatrick def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, 241109467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 241209467b48Spatrick def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, 241309467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 241409467b48Spatrick def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, 241509467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 241609467b48Spatrick def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, 241709467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 241809467b48Spatrick} 241909467b48Spatrick 242009467b48Spatricklet AdditionalPredicates = [NotDSP] in { 242109467b48Spatrickdef PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>, 242209467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 242309467b48Spatrickdef PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>, 242409467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 242509467b48Spatrickdef PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6; 242609467b48Spatrickdef PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6; 242709467b48Spatrickdef PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6; 242809467b48Spatrickdef PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>, 242909467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 243009467b48Spatrickdef PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>, 243109467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 243209467b48Spatrickdef PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>, 243309467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 243409467b48Spatrickdef PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>, 243509467b48Spatrick ISA_MIPS32_NOT_32R6_64R6; 243609467b48Spatrick} 243709467b48Spatrick 243809467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 243909467b48Spatrick def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV, 244009467b48Spatrick 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; 244109467b48Spatrick def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU, 244209467b48Spatrick 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; 244309467b48Spatrick def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM, ISA_MIPS1; 244409467b48Spatrick // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction 244509467b48Spatrick def EXT : MMRel, StdMMR6Rel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, 244609467b48Spatrick immZExt5, immZExt5Plus1, MipsExt>, 244709467b48Spatrick EXT_FM<0>, ISA_MIPS32R2; 244809467b48Spatrick def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5, 244909467b48Spatrick uimm5_inssize_plus1, immZExt5, 245009467b48Spatrick immZExt5Plus1>, 245109467b48Spatrick EXT_FM<4>, ISA_MIPS32R2; 245209467b48Spatrick} 245309467b48Spatrick/// Move Control Registers From/To CPU Registers 245409467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 245509467b48Spatrick def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>, 245609467b48Spatrick MFC3OP_FM<0x10, 4, 0>, ISA_MIPS1; 245709467b48Spatrick def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd, II_MFC0>, 245809467b48Spatrick MFC3OP_FM<0x10, 0, 0>, ISA_MIPS1; 245909467b48Spatrick def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd, II_MFC2>, 246009467b48Spatrick MFC3OP_FM<0x12, 0, 0>, ISA_MIPS1; 246109467b48Spatrick def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd, II_MTC2>, 246209467b48Spatrick MFC3OP_FM<0x12, 4, 0>, ISA_MIPS1; 246309467b48Spatrick} 246409467b48Spatrick 246509467b48Spatrickclass Barrier<string asmstr, InstrItinClass itin = NoItinerary> : 246609467b48Spatrick InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>; 246709467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 246809467b48Spatrick def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM<1>, 246909467b48Spatrick ISA_MIPS1; 247009467b48Spatrick def EHB : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM<3>, ISA_MIPS1; 247109467b48Spatrick 247209467b48Spatrick let isCTI = 1 in 247309467b48Spatrick def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause", II_PAUSE>, BARRIER_FM<5>, 247409467b48Spatrick ISA_MIPS32R2; 247509467b48Spatrick} 247609467b48Spatrick 247709467b48Spatrick// JR_HB and JALR_HB are defined here using the new style naming 247809467b48Spatrick// scheme because some of this code is shared with Mips32r6InstrInfo.td 247909467b48Spatrick// and because of that it doesn't follow the naming convention of the 248009467b48Spatrick// rest of the file. To avoid a mixture of old vs new style, the new 248109467b48Spatrick// style was chosen. 248209467b48Spatrickclass JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 248309467b48Spatrick dag OutOperandList = (outs); 248409467b48Spatrick dag InOperandList = (ins GPROpnd:$rs); 248509467b48Spatrick string AsmString = !strconcat(instr_asm, "\t$rs"); 248609467b48Spatrick list<dag> Pattern = []; 248709467b48Spatrick} 248809467b48Spatrick 248909467b48Spatrickclass JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 249009467b48Spatrick dag OutOperandList = (outs GPROpnd:$rd); 249109467b48Spatrick dag InOperandList = (ins GPROpnd:$rs); 249209467b48Spatrick string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 249309467b48Spatrick list<dag> Pattern = []; 249409467b48Spatrick} 249509467b48Spatrick 249609467b48Spatrickclass JR_HB_DESC<RegisterOperand RO> : 249709467b48Spatrick InstSE<(outs), (ins), "", [], II_JR_HB, FrmJ>, JR_HB_DESC_BASE<"jr.hb", RO> { 249809467b48Spatrick let isBranch=1; 249909467b48Spatrick let isIndirectBranch=1; 250009467b48Spatrick let hasDelaySlot=1; 250109467b48Spatrick let isTerminator=1; 250209467b48Spatrick let isBarrier=1; 250309467b48Spatrick bit isCTI = 1; 250409467b48Spatrick} 250509467b48Spatrick 250609467b48Spatrickclass JALR_HB_DESC<RegisterOperand RO> : 250709467b48Spatrick InstSE<(outs), (ins), "", [], II_JALR_HB, FrmJ>, JALR_HB_DESC_BASE<"jalr.hb", 250809467b48Spatrick RO> { 250909467b48Spatrick let isIndirectBranch=1; 251009467b48Spatrick let hasDelaySlot=1; 251109467b48Spatrick bit isCTI = 1; 251209467b48Spatrick} 251309467b48Spatrick 251409467b48Spatrickclass JR_HB_ENC : JR_HB_FM<8>; 251509467b48Spatrickclass JALR_HB_ENC : JALR_HB_FM<9>; 251609467b48Spatrick 251709467b48Spatrickdef JR_HB : JR_HB_DESC<GPR32Opnd>, JR_HB_ENC, ISA_MIPS32R2_NOT_32R6_64R6; 251809467b48Spatrickdef JALR_HB : JALR_HB_DESC<GPR32Opnd>, JALR_HB_ENC, ISA_MIPS32; 251909467b48Spatrick 252009467b48Spatricklet AdditionalPredicates = [NotInMicroMips, UseIndirectJumpsHazard] in 252109467b48Spatrick def JALRHBPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR_HB, RA>; 252209467b48Spatrick 252309467b48Spatrick 252409467b48Spatricklet AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, 252509467b48Spatrick UseIndirectJumpsHazard] in { 252609467b48Spatrick def TAILCALLREGHB : TailCallReg<JR_HB, GPR32Opnd>, ISA_MIPS32_NOT_32R6_64R6; 252709467b48Spatrick def PseudoIndirectHazardBranch : PseudoIndirectBranchBase<JR_HB, GPR32Opnd>, 252809467b48Spatrick ISA_MIPS32R2_NOT_32R6_64R6; 252909467b48Spatrick} 253009467b48Spatrick 253109467b48Spatrickclass TLB<string asmstr, InstrItinClass itin = NoItinerary> : 253209467b48Spatrick InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>; 253309467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 253409467b48Spatrick def TLBP : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM<0x08>, ISA_MIPS1; 253509467b48Spatrick def TLBR : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM<0x01>, ISA_MIPS1; 253609467b48Spatrick def TLBWI : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM<0x02>, ISA_MIPS1; 253709467b48Spatrick def TLBWR : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM<0x06>, ISA_MIPS1; 253809467b48Spatrick} 253909467b48Spatrickclass CacheOp<string instr_asm, Operand MemOpnd, 254009467b48Spatrick InstrItinClass itin = NoItinerary> : 254109467b48Spatrick InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), 254209467b48Spatrick !strconcat(instr_asm, "\t$hint, $addr"), [], itin, FrmOther, 254309467b48Spatrick instr_asm> { 254409467b48Spatrick let DecoderMethod = "DecodeCacheOp"; 254509467b48Spatrick} 254609467b48Spatrick 254709467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 254809467b48Spatrick def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>, 254909467b48Spatrick INSN_MIPS3_32_NOT_32R6_64R6; 255009467b48Spatrick def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>, 255109467b48Spatrick INSN_MIPS3_32_NOT_32R6_64R6; 255209467b48Spatrick} 255309467b48Spatrick// FIXME: We are missing the prefx instruction. 255409467b48Spatrickdef ROL : MipsAsmPseudoInst<(outs), 255509467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 255609467b48Spatrick "rol\t$rs, $rt, $rd">; 255709467b48Spatrickdef ROLImm : MipsAsmPseudoInst<(outs), 255809467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 255909467b48Spatrick "rol\t$rs, $rt, $imm">; 256009467b48Spatrickdef : MipsInstAlias<"rol $rd, $rs", 256109467b48Spatrick (ROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 256209467b48Spatrickdef : MipsInstAlias<"rol $rd, $imm", 256309467b48Spatrick (ROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>; 256409467b48Spatrick 256509467b48Spatrickdef ROR : MipsAsmPseudoInst<(outs), 256609467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 256709467b48Spatrick "ror\t$rs, $rt, $rd">; 256809467b48Spatrickdef RORImm : MipsAsmPseudoInst<(outs), 256909467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 257009467b48Spatrick "ror\t$rs, $rt, $imm">; 257109467b48Spatrickdef : MipsInstAlias<"ror $rd, $rs", 257209467b48Spatrick (ROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 257309467b48Spatrickdef : MipsInstAlias<"ror $rd, $imm", 257409467b48Spatrick (RORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>; 257509467b48Spatrick 257609467b48Spatrickdef DROL : MipsAsmPseudoInst<(outs), 257709467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 257809467b48Spatrick "drol\t$rs, $rt, $rd">, ISA_MIPS64; 257909467b48Spatrickdef DROLImm : MipsAsmPseudoInst<(outs), 258009467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 258109467b48Spatrick "drol\t$rs, $rt, $imm">, ISA_MIPS64; 258209467b48Spatrickdef : MipsInstAlias<"drol $rd, $rs", 258309467b48Spatrick (DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, 258409467b48Spatrick ISA_MIPS64; 258509467b48Spatrickdef : MipsInstAlias<"drol $rd, $imm", 258609467b48Spatrick (DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, 258709467b48Spatrick ISA_MIPS64; 258809467b48Spatrick 258909467b48Spatrickdef DROR : MipsAsmPseudoInst<(outs), 259009467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 259109467b48Spatrick "dror\t$rs, $rt, $rd">, ISA_MIPS64; 259209467b48Spatrickdef DRORImm : MipsAsmPseudoInst<(outs), 259309467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 259409467b48Spatrick "dror\t$rs, $rt, $imm">, ISA_MIPS64; 259509467b48Spatrickdef : MipsInstAlias<"dror $rd, $rs", 259609467b48Spatrick (DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, 259709467b48Spatrick ISA_MIPS64; 259809467b48Spatrickdef : MipsInstAlias<"dror $rd, $imm", 259909467b48Spatrick (DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, 260009467b48Spatrick ISA_MIPS64; 260109467b48Spatrick 260209467b48Spatrickdef ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), 260309467b48Spatrick "abs\t$rd, $rs">; 260409467b48Spatrick 260509467b48Spatrickdef SEQMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 260609467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 260709467b48Spatrick "seq $rd, $rs, $rt">, NOT_ASE_CNMIPS; 260809467b48Spatrick 260909467b48Spatrickdef : MipsInstAlias<"seq $rd, $rs", 261009467b48Spatrick (SEQMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, 261109467b48Spatrick NOT_ASE_CNMIPS; 261209467b48Spatrick 261309467b48Spatrickdef SEQIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 261409467b48Spatrick (ins GPR32Opnd:$rs, simm32_relaxed:$imm), 261509467b48Spatrick "seq $rd, $rs, $imm">, NOT_ASE_CNMIPS; 261609467b48Spatrick 261709467b48Spatrickdef : MipsInstAlias<"seq $rd, $imm", 261809467b48Spatrick (SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>, 261909467b48Spatrick NOT_ASE_CNMIPS; 262009467b48Spatrick 2621097a140dSpatrickdef SNEMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2622097a140dSpatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2623097a140dSpatrick "sne $rd, $rs, $rt">, NOT_ASE_CNMIPS; 2624097a140dSpatrick 2625097a140dSpatrickdef : MipsInstAlias<"sne $rd, $rs", 2626097a140dSpatrick (SNEMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, 2627097a140dSpatrick NOT_ASE_CNMIPS; 2628097a140dSpatrick 2629097a140dSpatrickdef SNEIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2630097a140dSpatrick (ins GPR32Opnd:$rs, simm32_relaxed:$imm), 2631097a140dSpatrick "sne $rd, $rs, $imm">, NOT_ASE_CNMIPS; 2632097a140dSpatrick 2633097a140dSpatrickdef : MipsInstAlias<"sne $rd, $imm", 2634097a140dSpatrick (SNEIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>, 2635097a140dSpatrick NOT_ASE_CNMIPS; 2636097a140dSpatrick 263709467b48Spatrickdef MULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, 263809467b48Spatrick simm32_relaxed:$imm), 263909467b48Spatrick "mul\t$rd, $rs, $imm">, 264009467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 264109467b48Spatrickdef MULOMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, 264209467b48Spatrick GPR32Opnd:$rt), 264309467b48Spatrick "mulo\t$rd, $rs, $rt">, 264409467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 264509467b48Spatrickdef MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, 264609467b48Spatrick GPR32Opnd:$rt), 264709467b48Spatrick "mulou\t$rd, $rs, $rt">, 264809467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 264909467b48Spatrick 265009467b48Spatrick// Virtualization ASE 265109467b48Spatrickclass HYPCALL_FT<string opstr> : 265209467b48Spatrick InstSE<(outs), (ins uimm10:$code_), 265309467b48Spatrick !strconcat(opstr, "\t$code_"), [], II_HYPCALL, FrmOther, opstr> { 265409467b48Spatrick let BaseOpcode = opstr; 265509467b48Spatrick} 265609467b48Spatrick 265709467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 265809467b48Spatrick def MFGC0 : MMRel, MFC3OP<"mfgc0", GPR32Opnd, COP0Opnd, II_MFGC0>, 265909467b48Spatrick MFC3OP_FM<0x10, 3, 0>, ISA_MIPS32R5, ASE_VIRT; 266009467b48Spatrick def MTGC0 : MMRel, MTC3OP<"mtgc0", COP0Opnd, GPR32Opnd, II_MTGC0>, 266109467b48Spatrick MFC3OP_FM<0x10, 3, 2>, ISA_MIPS32R5, ASE_VIRT; 266209467b48Spatrick def MFHGC0 : MMRel, MFC3OP<"mfhgc0", GPR32Opnd, COP0Opnd, II_MFHGC0>, 266309467b48Spatrick MFC3OP_FM<0x10, 3, 4>, ISA_MIPS32R5, ASE_VIRT; 266409467b48Spatrick def MTHGC0 : MMRel, MTC3OP<"mthgc0", COP0Opnd, GPR32Opnd, II_MTHGC0>, 266509467b48Spatrick MFC3OP_FM<0x10, 3, 6>, ISA_MIPS32R5, ASE_VIRT; 266609467b48Spatrick def TLBGINV : MMRel, TLB<"tlbginv", II_TLBGINV>, COP0_TLB_FM<0b001011>, 266709467b48Spatrick ISA_MIPS32R5, ASE_VIRT; 266809467b48Spatrick def TLBGINVF : MMRel, TLB<"tlbginvf", II_TLBGINVF>, COP0_TLB_FM<0b001100>, 266909467b48Spatrick ISA_MIPS32R5, ASE_VIRT; 267009467b48Spatrick def TLBGP : MMRel, TLB<"tlbgp", II_TLBGP>, COP0_TLB_FM<0b010000>, 267109467b48Spatrick ISA_MIPS32R5, ASE_VIRT; 267209467b48Spatrick def TLBGR : MMRel, TLB<"tlbgr", II_TLBGR>, COP0_TLB_FM<0b001001>, 267309467b48Spatrick ISA_MIPS32R5, ASE_VIRT; 267409467b48Spatrick def TLBGWI : MMRel, TLB<"tlbgwi", II_TLBGWI>, COP0_TLB_FM<0b001010>, 267509467b48Spatrick ISA_MIPS32R5, ASE_VIRT; 267609467b48Spatrick def TLBGWR : MMRel, TLB<"tlbgwr", II_TLBGWR>, COP0_TLB_FM<0b001110>, 267709467b48Spatrick ISA_MIPS32R5, ASE_VIRT; 267809467b48Spatrick def HYPCALL : MMRel, HYPCALL_FT<"hypcall">, 267909467b48Spatrick HYPCALL_FM<0b101000>, ISA_MIPS32R5, ASE_VIRT; 268009467b48Spatrick} 268109467b48Spatrick 268209467b48Spatrick//===----------------------------------------------------------------------===// 268309467b48Spatrick// Instruction aliases 268409467b48Spatrick//===----------------------------------------------------------------------===// 268509467b48Spatrick 268609467b48Spatrickmulticlass OneOrTwoOperandMacroImmediateAlias<string Memnomic, 268709467b48Spatrick Instruction Opcode, 268809467b48Spatrick RegisterOperand RO = GPR32Opnd, 268909467b48Spatrick Operand Imm = simm32_relaxed> { 269009467b48Spatrick def : MipsInstAlias<!strconcat(Memnomic, " $rs, $rt, $imm"), 269109467b48Spatrick (Opcode RO:$rs, 269209467b48Spatrick RO:$rt, 269309467b48Spatrick Imm:$imm), 0>; 269409467b48Spatrick def : MipsInstAlias<!strconcat(Memnomic, " $rs, $imm"), 269509467b48Spatrick (Opcode RO:$rs, 269609467b48Spatrick RO:$rs, 269709467b48Spatrick Imm:$imm), 0>; 269809467b48Spatrick} 269909467b48Spatrick 270009467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 270109467b48Spatrick def : MipsInstAlias<"move $dst, $src", 270209467b48Spatrick (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>, 270309467b48Spatrick GPR_32, ISA_MIPS1; 270409467b48Spatrick def : MipsInstAlias<"move $dst, $src", 270509467b48Spatrick (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>, 270609467b48Spatrick GPR_32, ISA_MIPS1; 270709467b48Spatrick 270809467b48Spatrick def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 1>, 270909467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 271009467b48Spatrick 271109467b48Spatrick def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>, ISA_MIPS1; 271209467b48Spatrick 271309467b48Spatrick def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 271409467b48Spatrick 271509467b48Spatrick def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, 271609467b48Spatrick ISA_MIPS32; 271709467b48Spatrick 271809467b48Spatrick def : MipsInstAlias<"neg $rt, $rs", 271909467b48Spatrick (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS1; 272009467b48Spatrick def : MipsInstAlias<"neg $rt", 272109467b48Spatrick (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1; 272209467b48Spatrick def : MipsInstAlias<"negu $rt, $rs", 272309467b48Spatrick (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS1; 272409467b48Spatrick def : MipsInstAlias<"negu $rt", 272509467b48Spatrick (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1; 272609467b48Spatrick 272709467b48Spatrick def SGE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 272809467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 272909467b48Spatrick "sge\t$rd, $rs, $rt">, ISA_MIPS1; 273009467b48Spatrick def : MipsInstAlias<"sge $rs, $rt", 273109467b48Spatrick (SGE GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 273209467b48Spatrick ISA_MIPS1; 273309467b48Spatrick def SGEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 273409467b48Spatrick (ins GPR32Opnd:$rs, simm32:$imm), 273509467b48Spatrick "sge\t$rd, $rs, $imm">, GPR_32; 273609467b48Spatrick def : MipsInstAlias<"sge $rs, $imm", (SGEImm GPR32Opnd:$rs, 273709467b48Spatrick GPR32Opnd:$rs, 273809467b48Spatrick simm32:$imm), 0>, 273909467b48Spatrick GPR_32; 274009467b48Spatrick 274109467b48Spatrick def SGEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 274209467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 274309467b48Spatrick "sgeu\t$rd, $rs, $rt">, ISA_MIPS1; 274409467b48Spatrick def : MipsInstAlias<"sgeu $rs, $rt", 274509467b48Spatrick (SGEU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 274609467b48Spatrick ISA_MIPS1; 274709467b48Spatrick def SGEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 274809467b48Spatrick (ins GPR32Opnd:$rs, uimm32_coerced:$imm), 274909467b48Spatrick "sgeu\t$rd, $rs, $imm">, GPR_32; 275009467b48Spatrick def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm GPR32Opnd:$rs, 275109467b48Spatrick GPR32Opnd:$rs, 275209467b48Spatrick uimm32_coerced:$imm), 0>, 275309467b48Spatrick GPR_32; 275409467b48Spatrick 275509467b48Spatrick def : MipsInstAlias< 275609467b48Spatrick "sgt $rd, $rs, $rt", 275709467b48Spatrick (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1; 275809467b48Spatrick def : MipsInstAlias< 275909467b48Spatrick "sgt $rs, $rt", 276009467b48Spatrick (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1; 276109467b48Spatrick 276209467b48Spatrick def SGTImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 276309467b48Spatrick (ins GPR32Opnd:$rs, simm32:$imm), 276409467b48Spatrick "sgt\t$rd, $rs, $imm">, GPR_32; 276509467b48Spatrick def : MipsInstAlias<"sgt $rs, $imm", (SGTImm GPR32Opnd:$rs, 276609467b48Spatrick GPR32Opnd:$rs, 276709467b48Spatrick simm32:$imm), 0>, 276809467b48Spatrick GPR_32; 276909467b48Spatrick def : MipsInstAlias< 277009467b48Spatrick "sgtu $rd, $rs, $rt", 277109467b48Spatrick (SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1; 277209467b48Spatrick def : MipsInstAlias< 277309467b48Spatrick "sgtu $$rs, $rt", 277409467b48Spatrick (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1; 277509467b48Spatrick 277609467b48Spatrick def SGTUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 277709467b48Spatrick (ins GPR32Opnd:$rs, uimm32_coerced:$imm), 277809467b48Spatrick "sgtu\t$rd, $rs, $imm">, GPR_32; 277909467b48Spatrick def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm GPR32Opnd:$rs, 278009467b48Spatrick GPR32Opnd:$rs, 278109467b48Spatrick uimm32_coerced:$imm), 0>, 278209467b48Spatrick GPR_32; 278309467b48Spatrick 2784097a140dSpatrick def SLE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2785097a140dSpatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2786097a140dSpatrick "sle\t$rd, $rs, $rt">, ISA_MIPS1; 2787097a140dSpatrick def : MipsInstAlias<"sle $rs, $rt", 2788097a140dSpatrick (SLE GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 2789097a140dSpatrick ISA_MIPS1; 2790097a140dSpatrick def SLEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2791097a140dSpatrick (ins GPR32Opnd:$rs, simm32:$imm), 2792097a140dSpatrick "sle\t$rd, $rs, $imm">, GPR_32; 2793097a140dSpatrick def : MipsInstAlias<"sle $rs, $imm", (SLEImm GPR32Opnd:$rs, 2794097a140dSpatrick GPR32Opnd:$rs, 2795097a140dSpatrick simm32:$imm), 0>, 2796097a140dSpatrick GPR_32; 2797097a140dSpatrick 2798097a140dSpatrick def SLEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2799097a140dSpatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2800097a140dSpatrick "sleu\t$rd, $rs, $rt">, ISA_MIPS1; 2801097a140dSpatrick def : MipsInstAlias<"sleu $rs, $rt", 2802097a140dSpatrick (SLEU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 2803097a140dSpatrick ISA_MIPS1; 2804097a140dSpatrick def SLEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 2805097a140dSpatrick (ins GPR32Opnd:$rs, uimm32_coerced:$imm), 2806097a140dSpatrick "sleu\t$rd, $rs, $imm">, GPR_32; 2807097a140dSpatrick def : MipsInstAlias<"sleu $rs, $imm", (SLEUImm GPR32Opnd:$rs, 2808097a140dSpatrick GPR32Opnd:$rs, 2809097a140dSpatrick uimm32_coerced:$imm), 0>, 2810097a140dSpatrick GPR_32; 2811097a140dSpatrick 281209467b48Spatrick def : MipsInstAlias< 281309467b48Spatrick "not $rt, $rs", 281409467b48Spatrick (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MIPS1; 281509467b48Spatrick def : MipsInstAlias< 281609467b48Spatrick "not $rt", 281709467b48Spatrick (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>, ISA_MIPS1; 281809467b48Spatrick 281909467b48Spatrick def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MIPS1; 282009467b48Spatrick 282109467b48Spatrick defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, 282209467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 282309467b48Spatrick 282409467b48Spatrick defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>, ISA_MIPS1; 282509467b48Spatrick 282609467b48Spatrick defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi>, ISA_MIPS1, GPR_32; 282709467b48Spatrick 282809467b48Spatrick defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi>, ISA_MIPS1, GPR_32; 282909467b48Spatrick 283009467b48Spatrick defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>, ISA_MIPS1, GPR_32; 283109467b48Spatrick 283209467b48Spatrick defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>, ISA_MIPS1, GPR_32; 283309467b48Spatrick 283409467b48Spatrick defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>, ISA_MIPS1, GPR_32; 283509467b48Spatrick 283609467b48Spatrick def : MipsInstAlias<"mfgc0 $rt, $rd", 283709467b48Spatrick (MFGC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>, 283809467b48Spatrick ISA_MIPS32R5, ASE_VIRT; 283909467b48Spatrick def : MipsInstAlias<"mtgc0 $rt, $rd", 284009467b48Spatrick (MTGC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>, 284109467b48Spatrick ISA_MIPS32R5, ASE_VIRT; 284209467b48Spatrick def : MipsInstAlias<"mfhgc0 $rt, $rd", 284309467b48Spatrick (MFHGC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>, 284409467b48Spatrick ISA_MIPS32R5, ASE_VIRT; 284509467b48Spatrick def : MipsInstAlias<"mthgc0 $rt, $rd", 284609467b48Spatrick (MTHGC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>, 284709467b48Spatrick ISA_MIPS32R5, ASE_VIRT; 284809467b48Spatrick def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>, 284909467b48Spatrick ISA_MIPS1; 285009467b48Spatrick def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>, 285109467b48Spatrick ISA_MIPS1; 285209467b48Spatrick def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>, 285309467b48Spatrick ISA_MIPS1; 285409467b48Spatrick def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>, 285509467b48Spatrick ISA_MIPS1; 285609467b48Spatrick 285709467b48Spatrick def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>, 285809467b48Spatrick ISA_MIPS1; 285909467b48Spatrick 286009467b48Spatrick def : MipsInstAlias<"bnez $rs,$offset", 286109467b48Spatrick (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>, 286209467b48Spatrick ISA_MIPS1; 286309467b48Spatrick def : MipsInstAlias<"bnezl $rs, $offset", 286409467b48Spatrick (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 1>, 286509467b48Spatrick ISA_MIPS2; 286609467b48Spatrick def : MipsInstAlias<"beqz $rs,$offset", 286709467b48Spatrick (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>, 286809467b48Spatrick ISA_MIPS1; 286909467b48Spatrick def : MipsInstAlias<"beqzl $rs, $offset", 287009467b48Spatrick (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 1>, 287109467b48Spatrick ISA_MIPS2; 287209467b48Spatrick 287309467b48Spatrick def : MipsInstAlias<"syscall", (SYSCALL 0), 1>, ISA_MIPS1; 287409467b48Spatrick 287509467b48Spatrick def : MipsInstAlias<"break", (BREAK 0, 0), 1>, ISA_MIPS1; 287609467b48Spatrick def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>, ISA_MIPS1; 287709467b48Spatrick def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; 287809467b48Spatrick def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; 287909467b48Spatrick 288009467b48Spatrick def : MipsInstAlias<"teq $rs, $rt", 288109467b48Spatrick (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 288209467b48Spatrick def : MipsInstAlias<"tge $rs, $rt", 288309467b48Spatrick (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 288409467b48Spatrick def : MipsInstAlias<"tgeu $rs, $rt", 288509467b48Spatrick (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 288609467b48Spatrick def : MipsInstAlias<"tlt $rs, $rt", 288709467b48Spatrick (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 288809467b48Spatrick def : MipsInstAlias<"tltu $rs, $rt", 288909467b48Spatrick (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 289009467b48Spatrick def : MipsInstAlias<"tne $rs, $rt", 289109467b48Spatrick (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 289209467b48Spatrick def : MipsInstAlias<"rdhwr $rt, $rs", 289309467b48Spatrick (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, ISA_MIPS1; 289409467b48Spatrick 289509467b48Spatrick} 289609467b48Spatrickdef : MipsInstAlias<"sub, $rd, $rs, $imm", 289709467b48Spatrick (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, 289809467b48Spatrick InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6; 289909467b48Spatrickdef : MipsInstAlias<"sub $rs, $imm", 290009467b48Spatrick (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm), 290109467b48Spatrick 0>, ISA_MIPS1_NOT_32R6_64R6; 290209467b48Spatrickdef : MipsInstAlias<"subu, $rd, $rs, $imm", 290309467b48Spatrick (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, 290409467b48Spatrick InvertedImOperand:$imm), 0>; 290509467b48Spatrickdef : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, 290609467b48Spatrick InvertedImOperand:$imm), 0>; 290709467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 290809467b48Spatrick def : MipsInstAlias<"sll $rd, $rt, $rs", 290909467b48Spatrick (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 291009467b48Spatrick def : MipsInstAlias<"sra $rd, $rt, $rs", 291109467b48Spatrick (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 291209467b48Spatrick def : MipsInstAlias<"srl $rd, $rt, $rs", 291309467b48Spatrick (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 291409467b48Spatrick def : MipsInstAlias<"sll $rd, $rt", 291509467b48Spatrick (SLLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; 291609467b48Spatrick def : MipsInstAlias<"sra $rd, $rt", 291709467b48Spatrick (SRAV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; 291809467b48Spatrick def : MipsInstAlias<"srl $rd, $rt", 291909467b48Spatrick (SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; 292009467b48Spatrick def : MipsInstAlias<"seh $rd", (SEH GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, 292109467b48Spatrick ISA_MIPS32R2; 292209467b48Spatrick def : MipsInstAlias<"seb $rd", (SEB GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, 292309467b48Spatrick ISA_MIPS32R2; 292409467b48Spatrick} 292509467b48Spatrickdef : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; 292609467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in 292709467b48Spatrick def : MipsInstAlias<"sync", (SYNC 0), 1>, ISA_MIPS2; 292809467b48Spatrick 292909467b48Spatrickdef : MipsInstAlias<"mulo $rs, $rt", 293009467b48Spatrick (MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 293109467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 293209467b48Spatrickdef : MipsInstAlias<"mulou $rs, $rt", 293309467b48Spatrick (MULOUMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 293409467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 293509467b48Spatrick 293609467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in 293709467b48Spatrick def : MipsInstAlias<"hypcall", (HYPCALL 0), 1>, ISA_MIPS32R5, ASE_VIRT; 293809467b48Spatrick 293909467b48Spatrick//===----------------------------------------------------------------------===// 294009467b48Spatrick// Assembler Pseudo Instructions 294109467b48Spatrick//===----------------------------------------------------------------------===// 294209467b48Spatrick 294309467b48Spatrick// We use uimm32_coerced to accept a 33 bit signed number that is rendered into 294409467b48Spatrick// a 32 bit number. 294509467b48Spatrickclass LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> : 294609467b48Spatrick MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 294709467b48Spatrick !strconcat(instr_asm, "\t$rt, $imm32")> ; 294809467b48Spatrickdef LoadImm32 : LoadImmediate32<"li", uimm32_coerced, GPR32Opnd>; 294909467b48Spatrick 295009467b48Spatrickclass LoadAddressFromReg32<string instr_asm, Operand MemOpnd, 295109467b48Spatrick RegisterOperand RO> : 295209467b48Spatrick MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 295309467b48Spatrick !strconcat(instr_asm, "\t$rt, $addr")> ; 295409467b48Spatrickdef LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>; 295509467b48Spatrick 295609467b48Spatrickclass LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> : 295709467b48Spatrick MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 295809467b48Spatrick !strconcat(instr_asm, "\t$rt, $imm32")> ; 295909467b48Spatrickdef LoadAddrImm32 : LoadAddressFromImm32<"la", i32imm, GPR32Opnd>; 296009467b48Spatrick 296109467b48Spatrickdef JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), 296209467b48Spatrick "jal\t$rd, $rs"> ; 296309467b48Spatrickdef JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs), 296409467b48Spatrick "jal\t$rs"> ; 296509467b48Spatrick 296609467b48Spatrickclass NORIMM_DESC_BASE<RegisterOperand RO, DAGOperand Imm> : 296709467b48Spatrick MipsAsmPseudoInst<(outs RO:$rs), (ins RO:$rt, Imm:$imm), 296809467b48Spatrick "nor\t$rs, $rt, $imm">; 296909467b48Spatrickdef NORImm : NORIMM_DESC_BASE<GPR32Opnd, simm32_relaxed>, GPR_32; 297009467b48Spatrickdef : MipsInstAlias<"nor\t$rs, $imm", (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, 297109467b48Spatrick simm32_relaxed:$imm)>, GPR_32; 297209467b48Spatrick 297309467b48Spatricklet hasDelaySlot = 1, isCTI = 1 in { 297409467b48Spatrickdef BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), 297509467b48Spatrick (ins imm64:$imm64, brtarget:$offset), 297609467b48Spatrick "bne\t$rt, $imm64, $offset">; 297709467b48Spatrickdef BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), 297809467b48Spatrick (ins imm64:$imm64, brtarget:$offset), 297909467b48Spatrick "beq\t$rt, $imm64, $offset">; 298009467b48Spatrick 298109467b48Spatrickclass CondBranchPseudo<string instr_asm> : 298209467b48Spatrick MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, 298309467b48Spatrick brtarget:$offset), 298409467b48Spatrick !strconcat(instr_asm, "\t$rs, $rt, $offset")>; 298509467b48Spatrick} 298609467b48Spatrick 298709467b48Spatrickdef BLT : CondBranchPseudo<"blt">; 298809467b48Spatrickdef BLE : CondBranchPseudo<"ble">; 298909467b48Spatrickdef BGE : CondBranchPseudo<"bge">; 299009467b48Spatrickdef BGT : CondBranchPseudo<"bgt">; 299109467b48Spatrickdef BLTU : CondBranchPseudo<"bltu">; 299209467b48Spatrickdef BLEU : CondBranchPseudo<"bleu">; 299309467b48Spatrickdef BGEU : CondBranchPseudo<"bgeu">; 299409467b48Spatrickdef BGTU : CondBranchPseudo<"bgtu">; 299509467b48Spatrickdef BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6; 299609467b48Spatrickdef BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6; 299709467b48Spatrickdef BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6; 299809467b48Spatrickdef BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6; 299909467b48Spatrickdef BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6; 300009467b48Spatrickdef BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6; 300109467b48Spatrickdef BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6; 300209467b48Spatrickdef BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6; 300309467b48Spatrick 300409467b48Spatricklet isCTI = 1 in 300509467b48Spatrickclass CondBranchImmPseudo<string instr_asm> : 300609467b48Spatrick MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset), 300709467b48Spatrick !strconcat(instr_asm, "\t$rs, $imm, $offset")>; 300809467b48Spatrick 300909467b48Spatrickdef BEQLImmMacro : CondBranchImmPseudo<"beql">, ISA_MIPS2_NOT_32R6_64R6; 301009467b48Spatrickdef BNELImmMacro : CondBranchImmPseudo<"bnel">, ISA_MIPS2_NOT_32R6_64R6; 301109467b48Spatrick 301209467b48Spatrickdef BLTImmMacro : CondBranchImmPseudo<"blt">; 301309467b48Spatrickdef BLEImmMacro : CondBranchImmPseudo<"ble">; 301409467b48Spatrickdef BGEImmMacro : CondBranchImmPseudo<"bge">; 301509467b48Spatrickdef BGTImmMacro : CondBranchImmPseudo<"bgt">; 301609467b48Spatrickdef BLTUImmMacro : CondBranchImmPseudo<"bltu">; 301709467b48Spatrickdef BLEUImmMacro : CondBranchImmPseudo<"bleu">; 301809467b48Spatrickdef BGEUImmMacro : CondBranchImmPseudo<"bgeu">; 301909467b48Spatrickdef BGTUImmMacro : CondBranchImmPseudo<"bgtu">; 302009467b48Spatrickdef BLTLImmMacro : CondBranchImmPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6; 302109467b48Spatrickdef BLELImmMacro : CondBranchImmPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6; 302209467b48Spatrickdef BGELImmMacro : CondBranchImmPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6; 302309467b48Spatrickdef BGTLImmMacro : CondBranchImmPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6; 302409467b48Spatrickdef BLTULImmMacro : CondBranchImmPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6; 302509467b48Spatrickdef BLEULImmMacro : CondBranchImmPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6; 302609467b48Spatrickdef BGEULImmMacro : CondBranchImmPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6; 302709467b48Spatrickdef BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6; 302809467b48Spatrick 302909467b48Spatrick// FIXME: Predicates are removed because instructions are matched regardless of 303009467b48Spatrick// predicates, because PredicateControl was not in the hierarchy. This was 303109467b48Spatrick// done to emit more precise error message from expansion function. 303209467b48Spatrick// Once the tablegen-erated errors are made better, this needs to be fixed and 303309467b48Spatrick// predicates needs to be restored. 303409467b48Spatrick 303509467b48Spatrickdef SDivMacro : MipsAsmPseudoInst<(outs GPR32NonZeroOpnd:$rd), 303609467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 303709467b48Spatrick "div\t$rd, $rs, $rt">, 303809467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 303909467b48Spatrickdef SDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 304009467b48Spatrick (ins GPR32Opnd:$rs, simm32:$imm), 304109467b48Spatrick "div\t$rd, $rs, $imm">, 304209467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 304309467b48Spatrickdef UDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 304409467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 304509467b48Spatrick "divu\t$rd, $rs, $rt">, 304609467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 304709467b48Spatrickdef UDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 304809467b48Spatrick (ins GPR32Opnd:$rs, simm32:$imm), 304909467b48Spatrick "divu\t$rd, $rs, $imm">, 305009467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 305109467b48Spatrick 305209467b48Spatrick 305309467b48Spatrickdef : MipsInstAlias<"div $rs, $rt", (SDIV GPR32ZeroOpnd:$rs, 305409467b48Spatrick GPR32Opnd:$rt), 0>, 305509467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 305609467b48Spatrickdef : MipsInstAlias<"div $rs, $rt", (SDivMacro GPR32NonZeroOpnd:$rs, 305709467b48Spatrick GPR32NonZeroOpnd:$rs, 305809467b48Spatrick GPR32Opnd:$rt), 0>, 305909467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 306009467b48Spatrickdef : MipsInstAlias<"div $rd, $imm", (SDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, 306109467b48Spatrick simm32:$imm), 0>, 306209467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 306309467b48Spatrick 306409467b48Spatrickdef : MipsInstAlias<"divu $rt, $rs", (UDIV GPR32ZeroOpnd:$rt, 306509467b48Spatrick GPR32Opnd:$rs), 0>, 306609467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 306709467b48Spatrickdef : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32NonZeroOpnd:$rt, 306809467b48Spatrick GPR32NonZeroOpnd:$rt, 306909467b48Spatrick GPR32Opnd:$rs), 0>, 307009467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 307109467b48Spatrick 307209467b48Spatrickdef : MipsInstAlias<"divu $rd, $imm", (UDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, 307309467b48Spatrick simm32:$imm), 0>, 307409467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 307509467b48Spatrick 307609467b48Spatrickdef SRemMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 307709467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 307809467b48Spatrick "rem\t$rd, $rs, $rt">, 307909467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 308009467b48Spatrickdef SRemIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 308109467b48Spatrick (ins GPR32Opnd:$rs, simm32_relaxed:$imm), 308209467b48Spatrick "rem\t$rd, $rs, $imm">, 308309467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 308409467b48Spatrickdef URemMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 308509467b48Spatrick (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 308609467b48Spatrick "remu\t$rd, $rs, $rt">, 308709467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 308809467b48Spatrickdef URemIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 308909467b48Spatrick (ins GPR32Opnd:$rs, simm32_relaxed:$imm), 309009467b48Spatrick "remu\t$rd, $rs, $imm">, 309109467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 309209467b48Spatrick 309309467b48Spatrickdef : MipsInstAlias<"rem $rt, $rs", (SRemMacro GPR32Opnd:$rt, GPR32Opnd:$rt, 309409467b48Spatrick GPR32Opnd:$rs), 0>, 309509467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 309609467b48Spatrickdef : MipsInstAlias<"rem $rd, $imm", (SRemIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, 309709467b48Spatrick simm32_relaxed:$imm), 0>, 309809467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 309909467b48Spatrickdef : MipsInstAlias<"remu $rt, $rs", (URemMacro GPR32Opnd:$rt, GPR32Opnd:$rt, 310009467b48Spatrick GPR32Opnd:$rs), 0>, 310109467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 310209467b48Spatrickdef : MipsInstAlias<"remu $rd, $imm", (URemIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, 310309467b48Spatrick simm32_relaxed:$imm), 0>, 310409467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 310509467b48Spatrick 310609467b48Spatrickdef Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 310709467b48Spatrick "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 310809467b48Spatrick 310909467b48Spatrickdef Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 311009467b48Spatrick "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 311109467b48Spatrick 311209467b48Spatrickdef Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 311309467b48Spatrick "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 311409467b48Spatrick 311509467b48Spatrickdef Ush : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 311609467b48Spatrick "ush\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 311709467b48Spatrick 311809467b48Spatrickdef Usw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 311909467b48Spatrick "usw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 312009467b48Spatrick 312109467b48Spatrickdef LDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), 312209467b48Spatrick (ins mem_simm16:$addr), "ld $rt, $addr">, 312309467b48Spatrick ISA_MIPS1_NOT_MIPS3; 312409467b48Spatrickdef SDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), 312509467b48Spatrick (ins mem_simm16:$addr), "sd $rt, $addr">, 312609467b48Spatrick ISA_MIPS1_NOT_MIPS3; 312709467b48Spatrick//===----------------------------------------------------------------------===// 312809467b48Spatrick// Arbitrary patterns that map to one or more instructions 312909467b48Spatrick//===----------------------------------------------------------------------===// 313009467b48Spatrick 313109467b48Spatrick// Load/store pattern templates. 313209467b48Spatrickclass LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 313309467b48Spatrick MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 313409467b48Spatrick 313509467b48Spatrickclass StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 313609467b48Spatrick MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 313709467b48Spatrick 313809467b48Spatrick// Materialize constants. 313909467b48Spatrickmulticlass MaterializeImms<ValueType VT, Register ZEROReg, 314009467b48Spatrick Instruction ADDiuOp, Instruction LUiOp, 314109467b48Spatrick Instruction ORiOp> { 314209467b48Spatrick 314309467b48Spatrick// Constant synthesis previously relied on the ordering of the patterns below. 314409467b48Spatrick// By making the predicates they use non-overlapping, the patterns were 314509467b48Spatrick// reordered so that the effect of the newly introduced predicates can be 314609467b48Spatrick// observed. 314709467b48Spatrick 314809467b48Spatrick// Arbitrary immediates 314909467b48Spatrickdef : MipsPat<(VT LUiORiPred:$imm), 315009467b48Spatrick (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>; 315109467b48Spatrick 315209467b48Spatrick// Bits 32-16 set, sign/zero extended. 315309467b48Spatrickdef : MipsPat<(VT LUiPred:$imm), (LUiOp (HI16 imm:$imm))>; 315409467b48Spatrick 315509467b48Spatrick// Small immediates 315609467b48Spatrickdef : MipsPat<(VT ORiPred:$imm), (ORiOp ZEROReg, imm:$imm)>; 315709467b48Spatrickdef : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>; 315809467b48Spatrick} 315909467b48Spatrick 316009467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in 316109467b48Spatrick defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>, ISA_MIPS1; 316209467b48Spatrick 316309467b48Spatrick// Carry MipsPatterns 316409467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 316509467b48Spatrick def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 316609467b48Spatrick (SUBu GPR32:$lhs, GPR32:$rhs)>, ISA_MIPS1; 316709467b48Spatrick} 316809467b48Spatrickdef : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 316909467b48Spatrick (ADDu GPR32:$lhs, GPR32:$rhs)>, ISA_MIPS1, ASE_NOT_DSP; 317009467b48Spatrickdef : MipsPat<(addc GPR32:$src, immSExt16:$imm), 317109467b48Spatrick (ADDiu GPR32:$src, imm:$imm)>, ISA_MIPS1, ASE_NOT_DSP; 317209467b48Spatrick 317309467b48Spatrick// Support multiplication for pre-Mips32 targets that don't have 317409467b48Spatrick// the MUL instruction. 317509467b48Spatrickdef : MipsPat<(mul GPR32:$lhs, GPR32:$rhs), 317609467b48Spatrick (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>, 317709467b48Spatrick ISA_MIPS1_NOT_32R6_64R6; 317809467b48Spatrick 317909467b48Spatrick// SYNC 318009467b48Spatrickdef : MipsPat<(MipsSync (i32 immz)), 318109467b48Spatrick (SYNC 0)>, ISA_MIPS2; 318209467b48Spatrick 318309467b48Spatrick// Call 318409467b48Spatrickdef : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 318509467b48Spatrick (JAL texternalsym:$dst)>, ISA_MIPS1; 318609467b48Spatrick//def : MipsPat<(MipsJmpLink GPR32:$dst), 318709467b48Spatrick// (JALR GPR32:$dst)>; 318809467b48Spatrick 318909467b48Spatrick// Tail call 319009467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 319109467b48Spatrick def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 319209467b48Spatrick (TAILCALL tglobaladdr:$dst)>, ISA_MIPS1; 319309467b48Spatrick def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 319409467b48Spatrick (TAILCALL texternalsym:$dst)>, ISA_MIPS1; 319509467b48Spatrick} 319609467b48Spatrick// hi/lo relocs 319709467b48Spatrickmulticlass MipsHiLoRelocs<Instruction Lui, Instruction Addiu, 319809467b48Spatrick Register ZeroReg, RegisterOperand GPROpnd> { 319909467b48Spatrick def : MipsPat<(MipsHi tglobaladdr:$in), (Lui tglobaladdr:$in)>; 320009467b48Spatrick def : MipsPat<(MipsHi tblockaddress:$in), (Lui tblockaddress:$in)>; 320109467b48Spatrick def : MipsPat<(MipsHi tjumptable:$in), (Lui tjumptable:$in)>; 320209467b48Spatrick def : MipsPat<(MipsHi tconstpool:$in), (Lui tconstpool:$in)>; 320309467b48Spatrick def : MipsPat<(MipsHi texternalsym:$in), (Lui texternalsym:$in)>; 320409467b48Spatrick 320509467b48Spatrick def : MipsPat<(MipsLo tglobaladdr:$in), 320609467b48Spatrick (Addiu ZeroReg, tglobaladdr:$in)>; 320709467b48Spatrick def : MipsPat<(MipsLo tblockaddress:$in), 320809467b48Spatrick (Addiu ZeroReg, tblockaddress:$in)>; 320909467b48Spatrick def : MipsPat<(MipsLo tjumptable:$in), 321009467b48Spatrick (Addiu ZeroReg, tjumptable:$in)>; 321109467b48Spatrick def : MipsPat<(MipsLo tconstpool:$in), 321209467b48Spatrick (Addiu ZeroReg, tconstpool:$in)>; 321309467b48Spatrick def : MipsPat<(MipsLo tglobaltlsaddr:$in), 321409467b48Spatrick (Addiu ZeroReg, tglobaltlsaddr:$in)>; 321509467b48Spatrick def : MipsPat<(MipsLo texternalsym:$in), 321609467b48Spatrick (Addiu ZeroReg, texternalsym:$in)>; 321709467b48Spatrick 321809467b48Spatrick def : MipsPat<(add GPROpnd:$hi, (MipsLo tglobaladdr:$lo)), 321909467b48Spatrick (Addiu GPROpnd:$hi, tglobaladdr:$lo)>; 322009467b48Spatrick def : MipsPat<(add GPROpnd:$hi, (MipsLo tblockaddress:$lo)), 322109467b48Spatrick (Addiu GPROpnd:$hi, tblockaddress:$lo)>; 322209467b48Spatrick def : MipsPat<(add GPROpnd:$hi, (MipsLo tjumptable:$lo)), 322309467b48Spatrick (Addiu GPROpnd:$hi, tjumptable:$lo)>; 322409467b48Spatrick def : MipsPat<(add GPROpnd:$hi, (MipsLo tconstpool:$lo)), 322509467b48Spatrick (Addiu GPROpnd:$hi, tconstpool:$lo)>; 322609467b48Spatrick def : MipsPat<(add GPROpnd:$hi, (MipsLo tglobaltlsaddr:$lo)), 322709467b48Spatrick (Addiu GPROpnd:$hi, tglobaltlsaddr:$lo)>; 322809467b48Spatrick def : MipsPat<(add GPROpnd:$hi, (MipsLo texternalsym:$lo)), 322909467b48Spatrick (Addiu GPROpnd:$hi, texternalsym:$lo)>; 323009467b48Spatrick} 323109467b48Spatrick 323209467b48Spatrick// wrapper_pic 323309467b48Spatrickclass WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 323409467b48Spatrick MipsPat<(MipsWrapper RC:$gp, node:$in), (ADDiuOp RC:$gp, node:$in)>; 323509467b48Spatrick 323609467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 323709467b48Spatrick defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>, ISA_MIPS1; 323809467b48Spatrick 323909467b48Spatrick def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi tglobaladdr:$in)>, ISA_MIPS1; 324009467b48Spatrick def : MipsPat<(MipsGotHi texternalsym:$in), (LUi texternalsym:$in)>, 324109467b48Spatrick ISA_MIPS1; 324209467b48Spatrick 324309467b48Spatrick def : MipsPat<(MipsTlsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>, 324409467b48Spatrick ISA_MIPS1; 324509467b48Spatrick 324609467b48Spatrick // gp_rel relocs 324709467b48Spatrick def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 324809467b48Spatrick (ADDiu GPR32:$gp, tglobaladdr:$in)>, ISA_MIPS1, ABI_NOT_N64; 324909467b48Spatrick def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 325009467b48Spatrick (ADDiu GPR32:$gp, tconstpool:$in)>, ISA_MIPS1, ABI_NOT_N64; 325109467b48Spatrick 325209467b48Spatrick def : WrapperPat<tglobaladdr, ADDiu, GPR32>, ISA_MIPS1; 325309467b48Spatrick def : WrapperPat<tconstpool, ADDiu, GPR32>, ISA_MIPS1; 325409467b48Spatrick def : WrapperPat<texternalsym, ADDiu, GPR32>, ISA_MIPS1; 325509467b48Spatrick def : WrapperPat<tblockaddress, ADDiu, GPR32>, ISA_MIPS1; 325609467b48Spatrick def : WrapperPat<tjumptable, ADDiu, GPR32>, ISA_MIPS1; 325709467b48Spatrick def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>, ISA_MIPS1; 325809467b48Spatrick 325909467b48Spatrick // Mips does not have "not", so we expand our way 326009467b48Spatrick def : MipsPat<(not GPR32:$in), 326109467b48Spatrick (NOR GPR32Opnd:$in, ZERO)>, ISA_MIPS1; 326209467b48Spatrick} 326309467b48Spatrick 326409467b48Spatrick// extended loads 326509467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 326609467b48Spatrick def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>, ISA_MIPS1; 326709467b48Spatrick def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>, ISA_MIPS1; 326809467b48Spatrick def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>, ISA_MIPS1; 326909467b48Spatrick 327009467b48Spatrick // peepholes 327109467b48Spatrick def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, ISA_MIPS1; 327209467b48Spatrick} 327309467b48Spatrick 327409467b48Spatrick// brcond patterns 327509467b48Spatrickmulticlass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1, 327609467b48Spatrick Instruction BNEOp, Instruction SLTOp, Instruction SLTuOp, 327709467b48Spatrick Instruction SLTiOp, Instruction SLTiuOp, 327809467b48Spatrick Register ZEROReg> { 327909467b48Spatrickdef : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 328009467b48Spatrick (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 328109467b48Spatrickdef : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 328209467b48Spatrick (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 328309467b48Spatrick 328409467b48Spatrickdef : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 328509467b48Spatrick (BEQOp1 (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 328609467b48Spatrickdef : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 328709467b48Spatrick (BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 328809467b48Spatrickdef : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 328909467b48Spatrick (BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 329009467b48Spatrickdef : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 329109467b48Spatrick (BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 329209467b48Spatrickdef : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 329309467b48Spatrick (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 329409467b48Spatrickdef : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 329509467b48Spatrick (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 329609467b48Spatrick 329709467b48Spatrickdef : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 329809467b48Spatrick (BEQOp1 (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 329909467b48Spatrickdef : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 330009467b48Spatrick (BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 330109467b48Spatrick 330209467b48Spatrickdef : MipsPat<(brcond RC:$cond, bb:$dst), 330309467b48Spatrick (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 330409467b48Spatrick} 330509467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 330609467b48Spatrick defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>, 330709467b48Spatrick ISA_MIPS1; 330809467b48Spatrick def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 330909467b48Spatrick (BLEZ i32:$lhs, bb:$dst)>, ISA_MIPS1; 331009467b48Spatrick def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 331109467b48Spatrick (BGEZ i32:$lhs, bb:$dst)>, ISA_MIPS1; 331209467b48Spatrick} 331309467b48Spatrick 331409467b48Spatrick// setcc patterns 331509467b48Spatrickmulticlass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 331609467b48Spatrick Instruction SLTuOp, Register ZEROReg> { 331709467b48Spatrick def : MipsPat<(seteq RC:$lhs, 0), 331809467b48Spatrick (SLTiuOp RC:$lhs, 1)>; 331909467b48Spatrick def : MipsPat<(setne RC:$lhs, 0), 332009467b48Spatrick (SLTuOp ZEROReg, RC:$lhs)>; 332109467b48Spatrick def : MipsPat<(seteq RC:$lhs, RC:$rhs), 332209467b48Spatrick (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 332309467b48Spatrick def : MipsPat<(setne RC:$lhs, RC:$rhs), 332409467b48Spatrick (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 332509467b48Spatrick} 332609467b48Spatrick 332709467b48Spatrickmulticlass SetlePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp, 332809467b48Spatrick Instruction SLTuOp> { 332909467b48Spatrick def : MipsPat<(setle RC:$lhs, RC:$rhs), 333009467b48Spatrick (XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>; 333109467b48Spatrick def : MipsPat<(setule RC:$lhs, RC:$rhs), 333209467b48Spatrick (XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>; 333309467b48Spatrick} 333409467b48Spatrick 333509467b48Spatrickmulticlass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 333609467b48Spatrick def : MipsPat<(setgt RC:$lhs, RC:$rhs), 333709467b48Spatrick (SLTOp RC:$rhs, RC:$lhs)>; 333809467b48Spatrick def : MipsPat<(setugt RC:$lhs, RC:$rhs), 333909467b48Spatrick (SLTuOp RC:$rhs, RC:$lhs)>; 334009467b48Spatrick} 334109467b48Spatrick 334209467b48Spatrickmulticlass SetgePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp, 334309467b48Spatrick Instruction SLTuOp> { 334409467b48Spatrick def : MipsPat<(setge RC:$lhs, RC:$rhs), 334509467b48Spatrick (XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>; 334609467b48Spatrick def : MipsPat<(setuge RC:$lhs, RC:$rhs), 334709467b48Spatrick (XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>; 334809467b48Spatrick} 334909467b48Spatrick 335009467b48Spatrickmulticlass SetgeImmPats<RegisterClass RC, Instruction XORiOp, 335109467b48Spatrick Instruction SLTiOp, Instruction SLTiuOp> { 335209467b48Spatrick def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 335309467b48Spatrick (XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 335409467b48Spatrick def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 335509467b48Spatrick (XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 335609467b48Spatrick} 335709467b48Spatrick 335809467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 335909467b48Spatrick defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>, ISA_MIPS1; 336009467b48Spatrick defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1; 336109467b48Spatrick defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1; 336209467b48Spatrick defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1; 336309467b48Spatrick defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>, ISA_MIPS1; 336409467b48Spatrick 336509467b48Spatrick // bswap pattern 336609467b48Spatrick def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>, ISA_MIPS32R2; 336709467b48Spatrick} 336809467b48Spatrick 336909467b48Spatrick// Load halfword/word patterns. 337009467b48Spatricklet AdditionalPredicates = [NotInMicroMips] in { 337109467b48Spatrick let AddedComplexity = 40 in { 337209467b48Spatrick def : LoadRegImmPat<LBu, i32, zextloadi8>, ISA_MIPS1; 337309467b48Spatrick def : LoadRegImmPat<LHu, i32, zextloadi16>, ISA_MIPS1; 337409467b48Spatrick def : LoadRegImmPat<LB, i32, sextloadi8>, ISA_MIPS1; 337509467b48Spatrick def : LoadRegImmPat<LH, i32, sextloadi16>, ISA_MIPS1; 337609467b48Spatrick def : LoadRegImmPat<LW, i32, load>, ISA_MIPS1; 337709467b48Spatrick } 337809467b48Spatrick 337909467b48Spatrick // Atomic load patterns. 338009467b48Spatrick def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>, ISA_MIPS1; 338109467b48Spatrick def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>, ISA_MIPS1; 338209467b48Spatrick def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>, ISA_MIPS1; 338309467b48Spatrick 338409467b48Spatrick // Atomic store patterns. 338509467b48Spatrick def : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>, 338609467b48Spatrick ISA_MIPS1; 338709467b48Spatrick def : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>, 338809467b48Spatrick ISA_MIPS1; 338909467b48Spatrick def : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>, 339009467b48Spatrick ISA_MIPS1; 339109467b48Spatrick} 339209467b48Spatrick 339309467b48Spatrick//===----------------------------------------------------------------------===// 339409467b48Spatrick// Floating Point Support 339509467b48Spatrick//===----------------------------------------------------------------------===// 339609467b48Spatrick 339709467b48Spatrickinclude "MipsInstrFPU.td" 339809467b48Spatrickinclude "Mips64InstrInfo.td" 339909467b48Spatrickinclude "MipsCondMov.td" 340009467b48Spatrick 340109467b48Spatrickinclude "Mips32r6InstrInfo.td" 340209467b48Spatrickinclude "Mips64r6InstrInfo.td" 340309467b48Spatrick 340409467b48Spatrick// 340509467b48Spatrick// Mips16 340609467b48Spatrick 340709467b48Spatrickinclude "Mips16InstrFormats.td" 340809467b48Spatrickinclude "Mips16InstrInfo.td" 340909467b48Spatrick 341009467b48Spatrick// DSP 341109467b48Spatrickinclude "MipsDSPInstrFormats.td" 341209467b48Spatrickinclude "MipsDSPInstrInfo.td" 341309467b48Spatrick 341409467b48Spatrick// MSA 341509467b48Spatrickinclude "MipsMSAInstrFormats.td" 341609467b48Spatrickinclude "MipsMSAInstrInfo.td" 341709467b48Spatrick 341809467b48Spatrick// EVA 341909467b48Spatrickinclude "MipsEVAInstrFormats.td" 342009467b48Spatrickinclude "MipsEVAInstrInfo.td" 342109467b48Spatrick 342209467b48Spatrick// MT 342309467b48Spatrickinclude "MipsMTInstrFormats.td" 342409467b48Spatrickinclude "MipsMTInstrInfo.td" 342509467b48Spatrick 342609467b48Spatrick// Micromips 342709467b48Spatrickinclude "MicroMipsInstrFormats.td" 342809467b48Spatrickinclude "MicroMipsInstrInfo.td" 342909467b48Spatrickinclude "MicroMipsInstrFPU.td" 343009467b48Spatrick 343109467b48Spatrick// Micromips r6 343209467b48Spatrickinclude "MicroMips32r6InstrFormats.td" 343309467b48Spatrickinclude "MicroMips32r6InstrInfo.td" 343409467b48Spatrick 343509467b48Spatrick// Micromips DSP 343609467b48Spatrickinclude "MicroMipsDSPInstrFormats.td" 343709467b48Spatrickinclude "MicroMipsDSPInstrInfo.td" 3438