1*d415bd75Srobert //===- MipsMulMulBugPass.cpp - Mips VR4300 mulmul bugfix pass -------------===//
2*d415bd75Srobert //
3*d415bd75Srobert // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*d415bd75Srobert // See https://llvm.org/LICENSE.txt for license information.
5*d415bd75Srobert // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*d415bd75Srobert //
7*d415bd75Srobert //===----------------------------------------------------------------------===//
8*d415bd75Srobert //
9*d415bd75Srobert // Early revisions of the VR4300 have a hardware bug where two consecutive
10*d415bd75Srobert // multiplications can produce an incorrect result in the second multiply.
11*d415bd75Srobert //
12*d415bd75Srobert // This pass scans for mul instructions in each basic block and inserts
13*d415bd75Srobert // a nop whenever the following conditions are met:
14*d415bd75Srobert //
15*d415bd75Srobert // - The current instruction is a single or double-precision floating-point
16*d415bd75Srobert // mul instruction.
17*d415bd75Srobert // - The next instruction is either a mul instruction (any kind)
18*d415bd75Srobert // or a branch instruction.
19*d415bd75Srobert //===----------------------------------------------------------------------===//
20*d415bd75Srobert
21*d415bd75Srobert #include "Mips.h"
22*d415bd75Srobert #include "MipsInstrInfo.h"
23*d415bd75Srobert #include "MipsSubtarget.h"
24*d415bd75Srobert #include "llvm/CodeGen/MachineBasicBlock.h"
25*d415bd75Srobert #include "llvm/CodeGen/MachineFunction.h"
26*d415bd75Srobert #include "llvm/CodeGen/MachineFunctionPass.h"
27*d415bd75Srobert #include "llvm/Support/CommandLine.h"
28*d415bd75Srobert #include "llvm/Support/Debug.h"
29*d415bd75Srobert #include "llvm/Target/TargetMachine.h"
30*d415bd75Srobert
31*d415bd75Srobert #define DEBUG_TYPE "mips-vr4300-mulmul-fix"
32*d415bd75Srobert
33*d415bd75Srobert using namespace llvm;
34*d415bd75Srobert
35*d415bd75Srobert namespace {
36*d415bd75Srobert
37*d415bd75Srobert class MipsMulMulBugFix : public MachineFunctionPass {
38*d415bd75Srobert public:
MipsMulMulBugFix()39*d415bd75Srobert MipsMulMulBugFix() : MachineFunctionPass(ID) {
40*d415bd75Srobert initializeMipsMulMulBugFixPass(*PassRegistry::getPassRegistry());
41*d415bd75Srobert }
42*d415bd75Srobert
getPassName() const43*d415bd75Srobert StringRef getPassName() const override { return "Mips VR4300 mulmul bugfix"; }
44*d415bd75Srobert
getRequiredProperties() const45*d415bd75Srobert MachineFunctionProperties getRequiredProperties() const override {
46*d415bd75Srobert return MachineFunctionProperties().set(
47*d415bd75Srobert MachineFunctionProperties::Property::NoVRegs);
48*d415bd75Srobert }
49*d415bd75Srobert
50*d415bd75Srobert bool runOnMachineFunction(MachineFunction &MF) override;
51*d415bd75Srobert
52*d415bd75Srobert static char ID;
53*d415bd75Srobert
54*d415bd75Srobert private:
55*d415bd75Srobert bool fixMulMulBB(MachineBasicBlock &MBB, const MipsInstrInfo &MipsII);
56*d415bd75Srobert };
57*d415bd75Srobert
58*d415bd75Srobert } // namespace
59*d415bd75Srobert
60*d415bd75Srobert INITIALIZE_PASS(MipsMulMulBugFix, "mips-vr4300-mulmul-fix",
61*d415bd75Srobert "Mips VR4300 mulmul bugfix", false, false)
62*d415bd75Srobert
63*d415bd75Srobert char MipsMulMulBugFix::ID = 0;
64*d415bd75Srobert
runOnMachineFunction(MachineFunction & MF)65*d415bd75Srobert bool MipsMulMulBugFix::runOnMachineFunction(MachineFunction &MF) {
66*d415bd75Srobert const MipsInstrInfo &MipsII =
67*d415bd75Srobert *static_cast<const MipsInstrInfo *>(MF.getSubtarget().getInstrInfo());
68*d415bd75Srobert
69*d415bd75Srobert bool Modified = false;
70*d415bd75Srobert
71*d415bd75Srobert for (auto &MBB : MF)
72*d415bd75Srobert Modified |= fixMulMulBB(MBB, MipsII);
73*d415bd75Srobert
74*d415bd75Srobert return Modified;
75*d415bd75Srobert }
76*d415bd75Srobert
isFirstMul(const MachineInstr & MI)77*d415bd75Srobert static bool isFirstMul(const MachineInstr &MI) {
78*d415bd75Srobert switch (MI.getOpcode()) {
79*d415bd75Srobert case Mips::FMUL_S:
80*d415bd75Srobert case Mips::FMUL_D:
81*d415bd75Srobert case Mips::FMUL_D32:
82*d415bd75Srobert case Mips::FMUL_D64:
83*d415bd75Srobert return true;
84*d415bd75Srobert default:
85*d415bd75Srobert return false;
86*d415bd75Srobert }
87*d415bd75Srobert }
88*d415bd75Srobert
isSecondMulOrBranch(const MachineInstr & MI)89*d415bd75Srobert static bool isSecondMulOrBranch(const MachineInstr &MI) {
90*d415bd75Srobert if (MI.isBranch() || MI.isIndirectBranch() || MI.isCall())
91*d415bd75Srobert return true;
92*d415bd75Srobert
93*d415bd75Srobert switch (MI.getOpcode()) {
94*d415bd75Srobert case Mips::MUL:
95*d415bd75Srobert case Mips::FMUL_S:
96*d415bd75Srobert case Mips::FMUL_D:
97*d415bd75Srobert case Mips::FMUL_D32:
98*d415bd75Srobert case Mips::FMUL_D64:
99*d415bd75Srobert case Mips::MULT:
100*d415bd75Srobert case Mips::MULTu:
101*d415bd75Srobert case Mips::DMULT:
102*d415bd75Srobert case Mips::DMULTu:
103*d415bd75Srobert return true;
104*d415bd75Srobert default:
105*d415bd75Srobert return false;
106*d415bd75Srobert }
107*d415bd75Srobert }
108*d415bd75Srobert
fixMulMulBB(MachineBasicBlock & MBB,const MipsInstrInfo & MipsII)109*d415bd75Srobert bool MipsMulMulBugFix::fixMulMulBB(MachineBasicBlock &MBB,
110*d415bd75Srobert const MipsInstrInfo &MipsII) {
111*d415bd75Srobert bool Modified = false;
112*d415bd75Srobert
113*d415bd75Srobert MachineBasicBlock::instr_iterator NextMII;
114*d415bd75Srobert
115*d415bd75Srobert // Iterate through the instructions in the basic block
116*d415bd75Srobert for (MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
117*d415bd75Srobert E = MBB.instr_end();
118*d415bd75Srobert MII != E; MII = NextMII) {
119*d415bd75Srobert
120*d415bd75Srobert NextMII = next_nodbg(MII, E);
121*d415bd75Srobert
122*d415bd75Srobert // Trigger when the current instruction is a mul and the next instruction
123*d415bd75Srobert // is either a mul or a branch in case the branch target start with a mul
124*d415bd75Srobert if (NextMII != E && isFirstMul(*MII) && isSecondMulOrBranch(*NextMII)) {
125*d415bd75Srobert LLVM_DEBUG(dbgs() << "Found mulmul!\n");
126*d415bd75Srobert
127*d415bd75Srobert const MCInstrDesc &NewMCID = MipsII.get(Mips::NOP);
128*d415bd75Srobert BuildMI(MBB, NextMII, DebugLoc(), NewMCID);
129*d415bd75Srobert Modified = true;
130*d415bd75Srobert }
131*d415bd75Srobert }
132*d415bd75Srobert
133*d415bd75Srobert return Modified;
134*d415bd75Srobert }
135*d415bd75Srobert
createMipsMulMulBugPass()136*d415bd75Srobert FunctionPass *llvm::createMipsMulMulBugPass() { return new MipsMulMulBugFix(); }
137