109467b48Spatrick//===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===// 209467b48Spatrick// 309467b48Spatrick// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 409467b48Spatrick// See https://llvm.org/LICENSE.txt for license information. 509467b48Spatrick// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 609467b48Spatrick// 709467b48Spatrick//===----------------------------------------------------------------------===// 809467b48Spatrick 909467b48Spatrick//===----------------------------------------------------------------------===// 1009467b48Spatrick// Declarations that describe the VE register file 1109467b48Spatrick//===----------------------------------------------------------------------===// 1209467b48Spatrick 13097a140dSpatrickclass VEReg<bits<7> enc, string n, list<Register> subregs = [], 14097a140dSpatrick list<string> altNames = [], list<Register> aliases = []> 15097a140dSpatrick : Register<n, altNames> { 1609467b48Spatrick let HWEncoding{15-7} = 0; 17097a140dSpatrick let HWEncoding{6-0} = enc; 1809467b48Spatrick let Namespace = "VE"; 1909467b48Spatrick let SubRegs = subregs; 2009467b48Spatrick let Aliases = aliases; 2109467b48Spatrick} 2209467b48Spatrick 23097a140dSpatrickclass VEMiscReg<bits<6> enc, string n>: Register<n> { 24097a140dSpatrick let HWEncoding{15-6} = 0; 25097a140dSpatrick let HWEncoding{5-0} = enc; 26097a140dSpatrick let Namespace = "VE"; 27097a140dSpatrick} 28097a140dSpatrick 2973471bf0Spatrickclass VEVecReg<bits<8> enc, string n, list<Register> subregs = [], 3073471bf0Spatrick list<string> altNames = [], list<Register> aliases = []> 3173471bf0Spatrick : Register<n, altNames> { 3273471bf0Spatrick let HWEncoding{15-8} = 0; 3373471bf0Spatrick let HWEncoding{7-0} = enc; 3473471bf0Spatrick let Namespace = "VE"; 3573471bf0Spatrick let SubRegs = subregs; 3673471bf0Spatrick let Aliases = aliases; 3773471bf0Spatrick} 3873471bf0Spatrick 3973471bf0Spatrickclass VEMaskReg<bits<4> enc, string n, list<Register> subregs = [], 4073471bf0Spatrick list<string> altNames = [], list<Register> aliases = []> 4173471bf0Spatrick : Register<n, altNames> { 4273471bf0Spatrick let HWEncoding{15-4} = 0; 4373471bf0Spatrick let HWEncoding{3-0} = enc; 4473471bf0Spatrick let Namespace = "VE"; 4573471bf0Spatrick let SubRegs = subregs; 4673471bf0Spatrick let Aliases = aliases; 4773471bf0Spatrick} 4873471bf0Spatrick 49097a140dSpatricklet Namespace = "VE" in { 50097a140dSpatrick def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63) 51097a140dSpatrick def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31) 52097a140dSpatrick def sub_even : SubRegIndex<64>; // High 64 bit (0..63) 53097a140dSpatrick def sub_odd : SubRegIndex<64, 64>; // Low 64 bit (64..127) 5473471bf0Spatrick def sub_vm_even : SubRegIndex<256>; // High 256 bit (0..255) 5573471bf0Spatrick def sub_vm_odd : SubRegIndex<256, 256>; // Low 256 bit (256..511) 56097a140dSpatrick def AsmName : RegAltNameIndex; 57097a140dSpatrick} 58097a140dSpatrick 59097a140dSpatrick//----------------------------------------------------------------------------- 60097a140dSpatrick// Miscellaneous Registers 61097a140dSpatrick//----------------------------------------------------------------------------- 62097a140dSpatrick 63097a140dSpatrickdef USRCC : VEMiscReg<0, "usrcc">; // User clock counter 64097a140dSpatrickdef PSW : VEMiscReg<1, "psw">; // Program status word 65097a140dSpatrickdef SAR : VEMiscReg<2, "sar">; // Store address register 66097a140dSpatrickdef PMMR : VEMiscReg<7, "pmmr">; // Performance monitor mode register 67097a140dSpatrick 68097a140dSpatrick// Performance monitor configuration registers 69097a140dSpatrickforeach I = 0-3 in 70097a140dSpatrick def PMCR#I : VEMiscReg<!add(8,I), "pmcr"#I>; 71097a140dSpatrick 72097a140dSpatrick// Performance monitor counter 73097a140dSpatrickforeach I = 0-14 in 74097a140dSpatrick def PMC#I : VEMiscReg<!add(16,I), "pmc"#I>; 75097a140dSpatrick 76097a140dSpatrick// Register classes. 77097a140dSpatrickdef MISC : RegisterClass<"VE", [i64], 64, 78097a140dSpatrick (add USRCC, PSW, SAR, PMMR, 79097a140dSpatrick (sequence "PMCR%u", 0, 3), 80097a140dSpatrick (sequence "PMC%u", 0, 14))>; 81097a140dSpatrick 82097a140dSpatrick//----------------------------------------------------------------------------- 83097a140dSpatrick// Instruction Counter Register 84097a140dSpatrick//----------------------------------------------------------------------------- 85097a140dSpatrick 86097a140dSpatrickdef IC : VEMiscReg<62, "ic">; 87097a140dSpatrick 88097a140dSpatrick//----------------------------------------------------------------------------- 8973471bf0Spatrick// Vector Length Register 9073471bf0Spatrick//----------------------------------------------------------------------------- 9173471bf0Spatrick 9273471bf0Spatrickdef VL : VEMiscReg<63, "vl">; 9373471bf0Spatrick 9473471bf0Spatrick// Register classes. 9573471bf0Spatrickdef VLS : RegisterClass<"VE", [i32], 64, (add VL)>; 9673471bf0Spatrick 9773471bf0Spatrick//----------------------------------------------------------------------------- 9873471bf0Spatrick// Generic Registers 99097a140dSpatrick//----------------------------------------------------------------------------- 100097a140dSpatrick 101097a140dSpatricklet RegAltNameIndices = [AsmName] in { 102097a140dSpatrick 103097a140dSpatrick// Generic integer registers - 32 bits wide 104097a140dSpatrickforeach I = 0-63 in 10573471bf0Spatrick def SW#I : VEReg<I, "sw"#I, [], ["s"#I]>, DwarfRegNum<[I]>; 106097a140dSpatrick 107097a140dSpatrick// Generic floating point registers - 32 bits wide 108097a140dSpatrick// NOTE: Mark SF#I as alias of SW#I temporary to avoid register allocation 109097a140dSpatrick// problem. 110097a140dSpatrickforeach I = 0-63 in 111097a140dSpatrick def SF#I : VEReg<I, "sf"#I, [], ["s"#I], [!cast<VEReg>("SW"#I)]>, 112097a140dSpatrick DwarfRegNum<[I]>; 113097a140dSpatrick 114097a140dSpatrick// Generic integer registers - 64 bits wide 11573471bf0Spatricklet SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in { 11673471bf0Spatrick // Several registers have specific names, so add them to one of aliases. 11773471bf0Spatrick def SX8 : VEReg<8, "s8", [SW8, SF8], ["s8", "sl"]>, DwarfRegNum<[8]>; 11873471bf0Spatrick def SX9 : VEReg<9, "s9", [SW9, SF9], ["s9", "fp"]>, DwarfRegNum<[9]>; 11973471bf0Spatrick def SX10 : VEReg<10, "s10", [SW10, SF10], ["s10", "lr"]>, DwarfRegNum<[10]>; 12073471bf0Spatrick def SX11 : VEReg<11, "s11", [SW11, SF11], ["s11", "sp"]>, DwarfRegNum<[11]>; 12173471bf0Spatrick def SX14 : VEReg<14, "s14", [SW14, SF14], ["s14", "tp"]>, DwarfRegNum<[14]>; 12273471bf0Spatrick def SX15 : VEReg<15, "s15", [SW15, SF15], ["s15", "got"]>, DwarfRegNum<[15]>; 12373471bf0Spatrick def SX16 : VEReg<16, "s16", [SW16, SF16], ["s16", "plt"]>, DwarfRegNum<[16]>; 12473471bf0Spatrick 12573471bf0Spatrick // Other generic registers. 12673471bf0Spatrick foreach I = { 0-7, 12-13, 17-63 } in 127097a140dSpatrick def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)], 128097a140dSpatrick ["s"#I]>, DwarfRegNum<[I]>; 12973471bf0Spatrick} 130097a140dSpatrick 131097a140dSpatrick// Aliases of the S* registers used to hold 128-bit for values (long doubles). 132097a140dSpatrick// Following foreach represents something like: 133097a140dSpatrick// def Q0 : VEReg<0, "q0", [SX0, SX1], ["s0"]>; 134097a140dSpatrick// def Q1 : VEReg<2, "q2", [SX2, SX3], ["s2"]>; 135097a140dSpatrick// ... 136097a140dSpatricklet SubRegIndices = [sub_even, sub_odd], CoveredBySubRegs = 1 in 137097a140dSpatrickforeach I = 0-31 in 138097a140dSpatrick def Q#I : VEReg<!shl(I,1), "q"#I, 139097a140dSpatrick [!cast<VEReg>("SX"#!shl(I,1)), 140097a140dSpatrick !cast<VEReg>("SX"#!add(!shl(I,1),1))], 141097a140dSpatrick ["s"#!shl(I,1)]>; 142097a140dSpatrick 14373471bf0Spatrick// Vector registers - 64 bits wide 256 elements 14473471bf0Spatrickforeach I = 0-63 in 14573471bf0Spatrick def V#I : VEVecReg<I, "v"#I, [], ["v"#I]>, DwarfRegNum<[!add(64,I)]>; 14673471bf0Spatrick 14773471bf0Spatrick// Vector Index Register 14873471bf0Spatrickdef VIX : VEVecReg<255, "vix", [], ["vix"]>; 14973471bf0Spatrick 15073471bf0Spatrick// Vector mask registers - 256 bits wide 151*d415bd75Srobertlet isConstant = true in 152*d415bd75Srobertdef VM0 : VEMaskReg<0, "vm0", [], ["vm0"]>, DwarfRegNum<[128]>; 153*d415bd75Srobertforeach I = 1-15 in 15473471bf0Spatrick def VM#I : VEMaskReg<I, "vm"#I, [], ["vm"#I]>, DwarfRegNum<[!add(128,I)]>; 15573471bf0Spatrick 15673471bf0Spatrick// Aliases of VMs to use as a pair of two VM for packed instructions 157*d415bd75Srobertlet isConstant = true in 158*d415bd75Srobertdef VMP0 : VEMaskReg<0, "vm0", [], ["vm0"]>; 159*d415bd75Srobert 16073471bf0Spatricklet SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in 161*d415bd75Srobertforeach I = 1-7 in 16273471bf0Spatrick def VMP#I : VEMaskReg<!shl(I,1), "vmp"#I, 16373471bf0Spatrick [!cast<VEMaskReg>("VM"#!shl(I,1)), 16473471bf0Spatrick !cast<VEMaskReg>("VM"#!add(!shl(I,1),1))], 16573471bf0Spatrick ["vm"#!shl(I,1)]>; 16673471bf0Spatrick 167097a140dSpatrick} // RegAltNameIndices = [AsmName] 168097a140dSpatrick 16909467b48Spatrick// Register classes. 17009467b48Spatrick// 17109467b48Spatrick// The register order is defined in terms of the preferred 17209467b48Spatrick// allocation order. 173097a140dSpatrickdef I32 : RegisterClass<"VE", [i32], 32, 174097a140dSpatrick (add (sequence "SW%u", 0, 7), 175097a140dSpatrick (sequence "SW%u", 34, 63), 176097a140dSpatrick (sequence "SW%u", 8, 33))>; 177097a140dSpatrickdef I64 : RegisterClass<"VE", [i64, f64], 64, 178097a140dSpatrick (add (sequence "SX%u", 0, 7), 179097a140dSpatrick (sequence "SX%u", 34, 63), 180097a140dSpatrick (sequence "SX%u", 8, 33))>; 181097a140dSpatrickdef F32 : RegisterClass<"VE", [f32], 32, 182097a140dSpatrick (add (sequence "SF%u", 0, 7), 183097a140dSpatrick (sequence "SF%u", 34, 63), 184097a140dSpatrick (sequence "SF%u", 8, 33))>; 185097a140dSpatrickdef F128 : RegisterClass<"VE", [f128], 128, 186097a140dSpatrick (add (sequence "Q%u", 0, 3), 187097a140dSpatrick (sequence "Q%u", 17, 31), 188097a140dSpatrick (sequence "Q%u", 4, 16))>; 18973471bf0Spatrick 19073471bf0Spatrickdef V64 : RegisterClass<"VE", 19173471bf0Spatrick [v256f64, // default type for vector registers 19273471bf0Spatrick v512i32, v512f32, 19373471bf0Spatrick v256i64, v256i32, v256f32, /* v256f64, */], 64, 19473471bf0Spatrick (add (sequence "V%u", 0, 63), 19573471bf0Spatrick VIX)>; 19673471bf0Spatrick 19773471bf0Spatrick// vm0 is reserved for always true 19873471bf0Spatrickdef VM : RegisterClass<"VE", [v256i1], 64, (sequence "VM%u", 0, 15)>; 19973471bf0Spatrickdef VM512 : RegisterClass<"VE", [v512i1], 64, (sequence "VMP%u", 0, 7)>; 200