109467b48Spatrick//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=// 209467b48Spatrick// 309467b48Spatrick// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 409467b48Spatrick// See https://llvm.org/LICENSE.txt for license information. 509467b48Spatrick// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 609467b48Spatrick// 709467b48Spatrick//===----------------------------------------------------------------------===// 809467b48Spatrick// 909467b48Spatrick// This file defines the machine model for Intel Silvermont to support 1009467b48Spatrick// instruction scheduling and other instruction cost heuristics. 1109467b48Spatrick// 1209467b48Spatrick//===----------------------------------------------------------------------===// 1309467b48Spatrick 1409467b48Spatrickdef SLMModel : SchedMachineModel { 1509467b48Spatrick // All x86 instructions are modeled as a single micro-op, and SLM can decode 2 1609467b48Spatrick // instructions per cycle. 1709467b48Spatrick let IssueWidth = 2; 1809467b48Spatrick let MicroOpBufferSize = 32; // Based on the reorder buffer. 1909467b48Spatrick let LoadLatency = 3; 2009467b48Spatrick let MispredictPenalty = 10; 2109467b48Spatrick let PostRAScheduler = 1; 2209467b48Spatrick 2309467b48Spatrick // For small loops, expand by a small factor to hide the backedge cost. 2409467b48Spatrick let LoopMicroOpBufferSize = 10; 2509467b48Spatrick 2609467b48Spatrick // FIXME: SSE4 is unimplemented. This flag is set to allow 2709467b48Spatrick // the scheduler to assign a default model to unrecognized opcodes. 2809467b48Spatrick let CompleteModel = 0; 2909467b48Spatrick} 3009467b48Spatrick 3109467b48Spatricklet SchedModel = SLMModel in { 3209467b48Spatrick 3309467b48Spatrick// Silvermont has 5 reservation stations for micro-ops 3409467b48Spatrickdef SLM_IEC_RSV0 : ProcResource<1>; 3509467b48Spatrickdef SLM_IEC_RSV1 : ProcResource<1>; 3609467b48Spatrickdef SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; } 3709467b48Spatrickdef SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; } 3809467b48Spatrickdef SLM_MEC_RSV : ProcResource<1>; 3909467b48Spatrick 4009467b48Spatrick// Many micro-ops are capable of issuing on multiple ports. 4109467b48Spatrickdef SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>; 4209467b48Spatrickdef SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>; 4309467b48Spatrick 4409467b48Spatrickdef SLMDivider : ProcResource<1>; 4509467b48Spatrickdef SLMFPMultiplier : ProcResource<1>; 4609467b48Spatrickdef SLMFPDivider : ProcResource<1>; 4709467b48Spatrick 4809467b48Spatrick// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 4909467b48Spatrick// cycles after the memory operand. 5009467b48Spatrickdef : ReadAdvance<ReadAfterLd, 3>; 5109467b48Spatrickdef : ReadAdvance<ReadAfterVecLd, 3>; 5209467b48Spatrickdef : ReadAdvance<ReadAfterVecXLd, 3>; 5309467b48Spatrickdef : ReadAdvance<ReadAfterVecYLd, 3>; 5409467b48Spatrick 5509467b48Spatrickdef : ReadAdvance<ReadInt2Fpu, 0>; 5609467b48Spatrick 5709467b48Spatrick// Many SchedWrites are defined in pairs with and without a folded load. 5809467b48Spatrick// Instructions with folded loads are usually micro-fused, so they only appear 5909467b48Spatrick// as two micro-ops when queued in the reservation station. 6009467b48Spatrick// This multiclass defines the resource usage for variants with and without 6109467b48Spatrick// folded loads. 6209467b48Spatrickmulticlass SLMWriteResPair<X86FoldableSchedWrite SchedRW, 6309467b48Spatrick list<ProcResourceKind> ExePorts, 6409467b48Spatrick int Lat, list<int> Res = [1], int UOps = 1, 65*d415bd75Srobert int LoadUOps = 0, int LoadLat = 3> { 6609467b48Spatrick // Register variant is using a single cycle on ExePort. 6709467b48Spatrick def : WriteRes<SchedRW, ExePorts> { 6809467b48Spatrick let Latency = Lat; 6909467b48Spatrick let ResourceCycles = Res; 7009467b48Spatrick let NumMicroOps = UOps; 7109467b48Spatrick } 7209467b48Spatrick 7309467b48Spatrick // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to 7409467b48Spatrick // the latency (default = 3). 7509467b48Spatrick def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> { 7609467b48Spatrick let Latency = !add(Lat, LoadLat); 7709467b48Spatrick let ResourceCycles = !listconcat([1], Res); 78*d415bd75Srobert let NumMicroOps = !add(UOps, LoadUOps); 7909467b48Spatrick } 8009467b48Spatrick} 8109467b48Spatrick 82*d415bd75Srobert// A folded store needs a cycle on MEC_RSV for the store data (using the same uop), 83*d415bd75Srobert// but it does not need an extra port cycle to recompute the address. 84*d415bd75Srobertdef : WriteRes<WriteRMW, [SLM_MEC_RSV]> { let NumMicroOps = 0; } 8509467b48Spatrick 8609467b48Spatrickdef : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 8709467b48Spatrickdef : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 8809467b48Spatrickdef : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; } 8909467b48Spatrickdef : WriteRes<WriteMove, [SLM_IEC_RSV01]>; 9009467b48Spatrickdef : WriteRes<WriteZero, []>; 9173471bf0Spatrickdefm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>; 9209467b48Spatrick 9309467b48Spatrick// Load/store MXCSR. 94*d415bd75Srobertdefm : X86WriteRes<WriteSTMXCSR, [SLM_MEC_RSV], 12,[11], 4>; 95*d415bd75Srobertdefm : X86WriteRes<WriteLDMXCSR, [SLM_MEC_RSV], 10, [8], 5>; 9609467b48Spatrick 9709467b48Spatrick// Treat misc copies as a move. 9809467b48Spatrickdef : InstRW<[WriteMove], (instrs COPY)>; 9909467b48Spatrick 10009467b48Spatrickdefm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>; 10109467b48Spatrickdefm : SLMWriteResPair<WriteADC, [SLM_IEC_RSV01], 1>; 10209467b48Spatrick 103*d415bd75Srobertdefm : SLMWriteResPair<WriteIMul8, [SLM_IEC_RSV1], 5, [5], 3>; 104*d415bd75Srobertdefm : SLMWriteResPair<WriteIMul16, [SLM_IEC_RSV1], 5, [5], 4, 1>; 105*d415bd75Srobertdefm : SLMWriteResPair<WriteIMul16Imm, [SLM_IEC_RSV1], 4, [4], 2, 1>; 106*d415bd75Srobertdefm : SLMWriteResPair<WriteIMul16Reg, [SLM_IEC_RSV1], 4, [4], 2, 1>; 107*d415bd75Srobertdefm : SLMWriteResPair<WriteIMul32, [SLM_IEC_RSV1], 5, [5], 3, 1>; 10809467b48Spatrickdefm : SLMWriteResPair<WriteIMul32Imm, [SLM_IEC_RSV1], 3>; 10909467b48Spatrickdefm : SLMWriteResPair<WriteIMul32Reg, [SLM_IEC_RSV1], 3>; 110*d415bd75Srobertdefm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1], 7, [7], 3>; 111*d415bd75Srobertdefm : SLMWriteResPair<WriteIMul64Imm, [SLM_IEC_RSV1], 5, [2]>; 112*d415bd75Srobertdefm : SLMWriteResPair<WriteIMul64Reg, [SLM_IEC_RSV1], 5, [2]>; 113*d415bd75Srobertdefm : X86WriteResUnsupported<WriteIMulH>; 114*d415bd75Srobertdefm : X86WriteResUnsupported<WriteIMulHLd>; 115*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteMULX32>; 116*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteMULX64>; 11709467b48Spatrick 11809467b48Spatrickdefm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>; 11909467b48Spatrickdefm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>; 120*d415bd75Srobertdefm : X86WriteRes<WriteCMPXCHG, [SLM_IEC_RSV01], 6, [6], 5>; 121*d415bd75Srobertdefm : X86WriteRes<WriteCMPXCHGRMW, [SLM_IEC_RSV01, SLM_MEC_RSV], 10, [6, 2], 8>; 122*d415bd75Srobertdefm : X86WriteRes<WriteXCHG, [SLM_IEC_RSV01], 3, [3], 3>; 12309467b48Spatrick 12409467b48Spatrickdefm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>; 12509467b48Spatrickdefm : SLMWriteResPair<WriteShiftCL, [SLM_IEC_RSV0], 1>; 12609467b48Spatrickdefm : SLMWriteResPair<WriteRotate, [SLM_IEC_RSV0], 1>; 12709467b48Spatrickdefm : SLMWriteResPair<WriteRotateCL, [SLM_IEC_RSV0], 1>; 12809467b48Spatrick 12909467b48Spatrickdefm : X86WriteRes<WriteSHDrri, [SLM_IEC_RSV0], 1, [1], 1>; 13009467b48Spatrickdefm : X86WriteRes<WriteSHDrrcl,[SLM_IEC_RSV0], 1, [1], 1>; 13109467b48Spatrickdefm : X86WriteRes<WriteSHDmri, [SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>; 13209467b48Spatrickdefm : X86WriteRes<WriteSHDmrcl,[SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>; 13309467b48Spatrick 13409467b48Spatrickdefm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>; 13509467b48Spatrickdefm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1], 3>; 13609467b48Spatrick 13709467b48Spatrickdefm : SLMWriteResPair<WriteCMOV, [SLM_IEC_RSV01], 2, [2]>; 13809467b48Spatrickdefm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional move. 13909467b48Spatrickdef : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>; 14009467b48Spatrickdef : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> { 14109467b48Spatrick // FIXME Latency and NumMicrOps? 14209467b48Spatrick let ResourceCycles = [2,1]; 14309467b48Spatrick} 14409467b48Spatrickdefm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>; 145*d415bd75Srobertdefm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>; 146*d415bd75Srobertdefm : X86WriteRes<WriteBitTestImmLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 4, [1,1,1], 1>; 147*d415bd75Srobertdefm : X86WriteRes<WriteBitTestRegLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 4, [1,1,1], 7>; 148*d415bd75Srobertdefm : X86WriteRes<WriteBitTestSet, [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>; 149*d415bd75Srobertdefm : X86WriteRes<WriteBitTestSetImmLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 3, [1,1,1], 1>; 150*d415bd75Srobertdefm : X86WriteRes<WriteBitTestSetRegLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 3, [1,1,1], 8>; 15109467b48Spatrick 15209467b48Spatrick// This is for simple LEAs with one or two input operands. 15309467b48Spatrick// The complex ones can only execute on port 1, and they require two cycles on 15409467b48Spatrick// the port to read all inputs. We don't model that. 15509467b48Spatrickdef : WriteRes<WriteLEA, [SLM_IEC_RSV1]>; 15609467b48Spatrick 15709467b48Spatrick// Bit counts. 158*d415bd75Srobertdefm : SLMWriteResPair<WriteBSF, [SLM_IEC_RSV0, SLM_IEC_RSV1], 10, [10,10], 10>; 159*d415bd75Srobertdefm : SLMWriteResPair<WriteBSR, [SLM_IEC_RSV0, SLM_IEC_RSV1], 10, [10,10], 10>; 16009467b48Spatrickdefm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>; 16109467b48Spatrickdefm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>; 16209467b48Spatrickdefm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>; 16309467b48Spatrick 16409467b48Spatrick// BMI1 BEXTR/BLS, BMI2 BZHI 16509467b48Spatrickdefm : X86WriteResPairUnsupported<WriteBEXTR>; 16609467b48Spatrickdefm : X86WriteResPairUnsupported<WriteBLS>; 16709467b48Spatrickdefm : X86WriteResPairUnsupported<WriteBZHI>; 16809467b48Spatrick 169*d415bd75Srobertdefm : SLMWriteResPair<WriteDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 170*d415bd75Srobertdefm : SLMWriteResPair<WriteDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 171*d415bd75Srobertdefm : SLMWriteResPair<WriteDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 172*d415bd75Srobertdefm : SLMWriteResPair<WriteDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 173*d415bd75Srobertdefm : SLMWriteResPair<WriteIDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 174*d415bd75Srobertdefm : SLMWriteResPair<WriteIDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 175*d415bd75Srobertdefm : SLMWriteResPair<WriteIDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 176*d415bd75Srobertdefm : SLMWriteResPair<WriteIDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 17709467b48Spatrick 17809467b48Spatrick// Scalar and vector floating point. 17909467b48Spatrickdefm : X86WriteRes<WriteFLD0, [SLM_FPC_RSV01], 1, [1], 1>; 18009467b48Spatrickdefm : X86WriteRes<WriteFLD1, [SLM_FPC_RSV01], 1, [1], 1>; 18109467b48Spatrickdefm : X86WriteRes<WriteFLDC, [SLM_FPC_RSV01], 1, [2], 2>; 18209467b48Spatrickdef : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; } 18309467b48Spatrickdef : WriteRes<WriteFLoadX, [SLM_MEC_RSV]> { let Latency = 3; } 184*d415bd75Srobertdefm : X86WriteResUnsupported<WriteFLoadY>; 18509467b48Spatrickdef : WriteRes<WriteFMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; } 186*d415bd75Srobertdefm : X86WriteResUnsupported<WriteFMaskedLoadY>; 18709467b48Spatrickdef : WriteRes<WriteFStore, [SLM_MEC_RSV]>; 18809467b48Spatrickdef : WriteRes<WriteFStoreX, [SLM_MEC_RSV]>; 189*d415bd75Srobertdefm : X86WriteResUnsupported<WriteFStoreY>; 19009467b48Spatrickdef : WriteRes<WriteFStoreNT, [SLM_MEC_RSV]>; 19109467b48Spatrickdef : WriteRes<WriteFStoreNTX, [SLM_MEC_RSV]>; 192*d415bd75Srobertdefm : X86WriteResUnsupported<WriteFStoreNTY>; 19309467b48Spatrick 19409467b48Spatrickdef : WriteRes<WriteFMaskedStore32, [SLM_MEC_RSV]>; 195*d415bd75Srobertdefm : X86WriteResUnsupported<WriteFMaskedStore32Y>; 19609467b48Spatrickdef : WriteRes<WriteFMaskedStore64, [SLM_MEC_RSV]>; 197*d415bd75Srobertdefm : X86WriteResUnsupported<WriteFMaskedStore64Y>; 19809467b48Spatrick 19909467b48Spatrickdef : WriteRes<WriteFMove, [SLM_FPC_RSV01]>; 20009467b48Spatrickdef : WriteRes<WriteFMoveX, [SLM_FPC_RSV01]>; 201*d415bd75Srobertdefm : X86WriteResUnsupported<WriteFMoveY>; 202*d415bd75Srobertdefm : X86WriteResUnsupported<WriteFMoveZ>; 20309467b48Spatrickdefm : X86WriteRes<WriteEMMS, [SLM_FPC_RSV01], 10, [10], 9>; 20409467b48Spatrick 20509467b48Spatrickdefm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>; 20609467b48Spatrickdefm : SLMWriteResPair<WriteFAddX, [SLM_FPC_RSV1], 3>; 207*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFAddY>; 20809467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFAddZ>; 20909467b48Spatrickdefm : SLMWriteResPair<WriteFAdd64, [SLM_FPC_RSV1], 3>; 21009467b48Spatrickdefm : SLMWriteResPair<WriteFAdd64X, [SLM_FPC_RSV1], 4, [2]>; 211*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFAdd64Y>; 21209467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFAdd64Z>; 21309467b48Spatrickdefm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>; 21409467b48Spatrickdefm : SLMWriteResPair<WriteFCmpX, [SLM_FPC_RSV1], 3>; 215*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFCmpY>; 21609467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFCmpZ>; 21709467b48Spatrickdefm : SLMWriteResPair<WriteFCmp64, [SLM_FPC_RSV1], 3>; 21809467b48Spatrickdefm : SLMWriteResPair<WriteFCmp64X, [SLM_FPC_RSV1], 3>; 219*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFCmp64Y>; 22009467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFCmp64Z>; 22109467b48Spatrickdefm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>; 222097a140dSpatrickdefm : SLMWriteResPair<WriteFComX, [SLM_FPC_RSV1], 3>; 22309467b48Spatrickdefm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 22409467b48Spatrickdefm : SLMWriteResPair<WriteFMulX, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 225*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFMulY>; 22609467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFMulZ>; 22709467b48Spatrickdefm : SLMWriteResPair<WriteFMul64, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 22809467b48Spatrickdefm : SLMWriteResPair<WriteFMul64X, [SLM_FPC_RSV0, SLMFPMultiplier], 7, [1,4]>; 229*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFMul64Y>; 23009467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFMul64Z>; 23173471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteFMA>; 23273471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteFMAX>; 23373471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteFMAY>; 23473471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteFMAZ>; 23509467b48Spatrickdefm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 19, [1,17]>; 236*d415bd75Srobertdefm : SLMWriteResPair<WriteFDivX, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39], 6, 1>; 237*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFDivY>; 23809467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFDivZ>; 23909467b48Spatrickdefm : SLMWriteResPair<WriteFDiv64, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,32]>; 240*d415bd75Srobertdefm : SLMWriteResPair<WriteFDiv64X, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69], 6, 1>; 241*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFDiv64Y>; 24209467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFDiv64Z>; 243*d415bd75Srobertdefm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 4>; 244*d415bd75Srobertdefm : SLMWriteResPair<WriteFRcpX, [SLM_FPC_RSV0], 9, [8], 5, 1>; 245*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFRcpY>; 24609467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFRcpZ>; 247*d415bd75Srobertdefm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 4>; 248*d415bd75Srobertdefm : SLMWriteResPair<WriteFRsqrtX, [SLM_FPC_RSV0], 9, [8], 5, 1>; 249*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFRsqrtY>; 25009467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 251*d415bd75Srobertdefm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0, SLMFPDivider], 20, [1,20]>; 252*d415bd75Srobertdefm : SLMWriteResPair<WriteFSqrtX, [SLM_FPC_RSV0, SLMFPDivider], 41, [1,40], 5, 1>; 253*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFSqrtY>; 25409467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFSqrtZ>; 255*d415bd75Srobertdefm : SLMWriteResPair<WriteFSqrt64, [SLM_FPC_RSV0, SLMFPDivider], 35, [1,35]>; 256*d415bd75Srobertdefm : SLMWriteResPair<WriteFSqrt64X, [SLM_FPC_RSV0, SLMFPDivider], 71, [1,70], 5, 1>; 257*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFSqrt64Y>; 25809467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 25909467b48Spatrickdefm : SLMWriteResPair<WriteFSqrt80, [SLM_FPC_RSV0,SLMFPDivider], 40, [1,40]>; 260*d415bd75Srobertdefm : SLMWriteResPair<WriteDPPD, [SLM_FPC_RSV1], 12, [8], 5, 1>; 261*d415bd75Srobertdefm : SLMWriteResPair<WriteDPPS, [SLM_FPC_RSV1], 15, [12], 9, 1>; 262*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteDPPSY>; 26309467b48Spatrickdefm : SLMWriteResPair<WriteFSign, [SLM_FPC_RSV01], 1>; 26409467b48Spatrickdefm : SLMWriteResPair<WriteFRnd, [SLM_FPC_RSV1], 3>; 265*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFRndY>; 26609467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFRndZ>; 26709467b48Spatrickdefm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>; 268*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFLogicY>; 26909467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFLogicZ>; 27009467b48Spatrickdefm : SLMWriteResPair<WriteFTest, [SLM_FPC_RSV01], 1>; 271*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFTestY>; 27209467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFTestZ>; 27309467b48Spatrickdefm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>; 274*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFShuffleY>; 27509467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFShuffleZ>; 27609467b48Spatrickdefm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>; 277*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFVarShuffleY>; 27809467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 27909467b48Spatrickdefm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>; 28073471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteFBlendY>; 28173471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteFBlendZ>; 282*d415bd75Srobertdefm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 4, [4], 2, 1>; 28373471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteFVarBlendY>; 28473471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 28573471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteFShuffle256>; 28673471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 28709467b48Spatrick 28809467b48Spatrick// Conversion between integer and float. 28973471bf0Spatrickdefm : SLMWriteResPair<WriteCvtSS2I, [SLM_FPC_RSV0], 5>; 29073471bf0Spatrickdefm : SLMWriteResPair<WriteCvtPS2I, [SLM_FPC_RSV0], 5, [2]>; 291*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteCvtPS2IY>; 29209467b48Spatrickdefm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 29373471bf0Spatrickdefm : SLMWriteResPair<WriteCvtSD2I, [SLM_FPC_RSV0], 5>; 29473471bf0Spatrickdefm : SLMWriteResPair<WriteCvtPD2I, [SLM_FPC_RSV0], 5, [2]>; 295*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteCvtPD2IY>; 29609467b48Spatrickdefm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 29709467b48Spatrick 29873471bf0Spatrickdefm : SLMWriteResPair<WriteCvtI2SS, [SLM_FPC_RSV0], 5, [2]>; 29973471bf0Spatrickdefm : SLMWriteResPair<WriteCvtI2PS, [SLM_FPC_RSV0], 5, [2]>; 300*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteCvtI2PSY>; 30109467b48Spatrickdefm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 30273471bf0Spatrickdefm : SLMWriteResPair<WriteCvtI2SD, [SLM_FPC_RSV0], 5, [2]>; 30373471bf0Spatrickdefm : SLMWriteResPair<WriteCvtI2PD, [SLM_FPC_RSV0], 5, [2]>; 304*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteCvtI2PDY>; 30509467b48Spatrickdefm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 30609467b48Spatrick 30773471bf0Spatrickdefm : SLMWriteResPair<WriteCvtSS2SD, [SLM_FPC_RSV0], 4, [2]>; 30873471bf0Spatrickdefm : SLMWriteResPair<WriteCvtPS2PD, [SLM_FPC_RSV0], 5, [2]>; 309*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteCvtPS2PDY>; 31009467b48Spatrickdefm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 31173471bf0Spatrickdefm : SLMWriteResPair<WriteCvtSD2SS, [SLM_FPC_RSV0], 4, [2]>; 31273471bf0Spatrickdefm : SLMWriteResPair<WriteCvtPD2PS, [SLM_FPC_RSV0], 5, [2]>; 313*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteCvtPD2PSY>; 31409467b48Spatrickdefm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 31509467b48Spatrick 31673471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 31773471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 31873471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 31973471bf0Spatrick 32073471bf0Spatrickdefm : X86WriteResUnsupported<WriteCvtPS2PH>; 32173471bf0Spatrickdefm : X86WriteResUnsupported<WriteCvtPS2PHY>; 32273471bf0Spatrickdefm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 32373471bf0Spatrickdefm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 32473471bf0Spatrickdefm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 32573471bf0Spatrickdefm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 32673471bf0Spatrick 32709467b48Spatrick// Vector integer operations. 32809467b48Spatrickdef : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; } 32909467b48Spatrickdef : WriteRes<WriteVecLoadX, [SLM_MEC_RSV]> { let Latency = 3; } 330*d415bd75Srobertdefm : X86WriteResUnsupported<WriteVecLoadY>; 33109467b48Spatrickdef : WriteRes<WriteVecLoadNT, [SLM_MEC_RSV]> { let Latency = 3; } 332*d415bd75Srobertdefm : X86WriteResUnsupported<WriteVecLoadNTY>; 33309467b48Spatrickdef : WriteRes<WriteVecMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; } 334*d415bd75Srobertdefm : X86WriteResUnsupported<WriteVecMaskedLoadY>; 33509467b48Spatrickdef : WriteRes<WriteVecStore, [SLM_MEC_RSV]>; 33609467b48Spatrickdef : WriteRes<WriteVecStoreX, [SLM_MEC_RSV]>; 337*d415bd75Srobertdefm : X86WriteResUnsupported<WriteVecStoreY>; 33809467b48Spatrickdef : WriteRes<WriteVecStoreNT, [SLM_MEC_RSV]>; 339*d415bd75Srobertdefm : X86WriteResUnsupported<WriteVecStoreNTY>; 340097a140dSpatrickdef : WriteRes<WriteVecMaskedStore32, [SLM_MEC_RSV]>; 341*d415bd75Srobertdefm : X86WriteResUnsupported<WriteVecMaskedStore32Y>; 342097a140dSpatrickdef : WriteRes<WriteVecMaskedStore64, [SLM_MEC_RSV]>; 343*d415bd75Srobertdefm : X86WriteResUnsupported<WriteVecMaskedStore64Y>; 34409467b48Spatrickdef : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>; 34509467b48Spatrickdef : WriteRes<WriteVecMoveX, [SLM_FPC_RSV01]>; 346*d415bd75Srobertdefm : X86WriteResUnsupported<WriteVecMoveY>; 347*d415bd75Srobertdefm : X86WriteResUnsupported<WriteVecMoveZ>; 34809467b48Spatrickdef : WriteRes<WriteVecMoveToGpr, [SLM_IEC_RSV01]>; 34909467b48Spatrickdef : WriteRes<WriteVecMoveFromGpr, [SLM_IEC_RSV01]>; 35009467b48Spatrick 351*d415bd75Srobertdefm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 2, [2]>; 352*d415bd75Srobertdefm : SLMWriteResPair<WriteVecShiftX, [SLM_FPC_RSV0], 2, [2]>; 353*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteVecShiftY>; 35409467b48Spatrickdefm : X86WriteResPairUnsupported<WriteVecShiftZ>; 35509467b48Spatrickdefm : SLMWriteResPair<WriteVecShiftImm, [SLM_FPC_RSV0], 1>; 35609467b48Spatrickdefm : SLMWriteResPair<WriteVecShiftImmX,[SLM_FPC_RSV0], 1>; 357*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteVecShiftImmY>; 35809467b48Spatrickdefm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 359*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteVarVecShift>; 36073471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 36173471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 36273471bf0Spatrick 36309467b48Spatrickdefm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>; 36409467b48Spatrickdefm : SLMWriteResPair<WriteVecLogicX,[SLM_FPC_RSV01], 1>; 365*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteVecLogicY>; 36609467b48Spatrickdefm : X86WriteResPairUnsupported<WriteVecLogicZ>; 36709467b48Spatrickdefm : SLMWriteResPair<WriteVecTest, [SLM_FPC_RSV01], 1>; 368*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteVecTestY>; 36909467b48Spatrickdefm : X86WriteResPairUnsupported<WriteVecTestZ>; 37009467b48Spatrickdefm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>; 37109467b48Spatrickdefm : SLMWriteResPair<WriteVecALUX, [SLM_FPC_RSV01], 1>; 372*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteVecALUY>; 37309467b48Spatrickdefm : X86WriteResPairUnsupported<WriteVecALUZ>; 37409467b48Spatrickdefm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>; 375*d415bd75Srobertdefm : SLMWriteResPair<WriteVecIMulX, [SLM_FPC_RSV0], 5, [2]>; 376*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteVecIMulY>; 37709467b48Spatrickdefm : X86WriteResPairUnsupported<WriteVecIMulZ>; 378*d415bd75Srobertdefm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>; 379*d415bd75Srobertdefm : X86WriteResPairUnsupported<WritePMULLDY>; 38009467b48Spatrickdefm : X86WriteResPairUnsupported<WritePMULLDZ>; 38109467b48Spatrickdefm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>; 382*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteShuffleY>; 38309467b48Spatrickdefm : X86WriteResPairUnsupported<WriteShuffleZ>; 38409467b48Spatrickdefm : SLMWriteResPair<WriteShuffleX, [SLM_FPC_RSV0], 1>; 38509467b48Spatrickdefm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>; 386*d415bd75Srobertdefm : SLMWriteResPair<WriteVarShuffleX, [SLM_FPC_RSV0], 5, [5], 4, 1>; 387*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteVarShuffleY>; 38809467b48Spatrickdefm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 38909467b48Spatrickdefm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>; 390*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteBlendY>; 39109467b48Spatrickdefm : X86WriteResPairUnsupported<WriteBlendZ>; 392*d415bd75Srobertdefm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 4, [4], 2, 1>; 39373471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteVarBlendY>; 39473471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteVarBlendZ>; 395*d415bd75Srobertdefm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7, [5], 3, 1>; 396*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteMPSADY>; 39709467b48Spatrickdefm : X86WriteResPairUnsupported<WriteMPSADZ>; 39809467b48Spatrickdefm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>; 399*d415bd75Srobertdefm : SLMWriteResPair<WritePSADBWX, [SLM_FPC_RSV0], 5, [2]>; 400*d415bd75Srobertdefm : X86WriteResPairUnsupported<WritePSADBWY>; 40109467b48Spatrickdefm : X86WriteResPairUnsupported<WritePSADBWZ>; 40209467b48Spatrickdefm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>; 40373471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteShuffle256>; 40473471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteVarShuffle256>; 40573471bf0Spatrickdefm : X86WriteResPairUnsupported<WriteVPMOV256>; 40609467b48Spatrick 40709467b48Spatrick// Vector insert/extract operations. 40809467b48Spatrickdefm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0], 1>; 40909467b48Spatrick 410*d415bd75Srobertdef : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]> { 411*d415bd75Srobert let NumMicroOps = 2; 412*d415bd75Srobert} 41309467b48Spatrickdef : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 41409467b48Spatrick let Latency = 4; 415*d415bd75Srobert let NumMicroOps = 5; 41609467b48Spatrick let ResourceCycles = [1, 2]; 41709467b48Spatrick} 41809467b48Spatrick 41909467b48Spatrick//////////////////////////////////////////////////////////////////////////////// 42009467b48Spatrick// Horizontal add/sub instructions. 42109467b48Spatrick//////////////////////////////////////////////////////////////////////////////// 42209467b48Spatrick 423*d415bd75Srobertdefm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV1], 6, [6], 4, 1>; 424*d415bd75Srobertdefm : X86WriteResPairUnsupported<WriteFHAddY>; 42509467b48Spatrickdefm : X86WriteResPairUnsupported<WriteFHAddZ>; 426*d415bd75Srobertdefm : SLMWriteResPair<WritePHAdd, [SLM_FPC_RSV01], 6, [6], 3, 1>; 427*d415bd75Srobertdefm : SLMWriteResPair<WritePHAddX, [SLM_FPC_RSV01], 6, [6], 3, 1>; 428*d415bd75Srobertdefm : X86WriteResPairUnsupported<WritePHAddY>; 42909467b48Spatrickdefm : X86WriteResPairUnsupported<WritePHAddZ>; 43009467b48Spatrick 43109467b48Spatrick// String instructions. 43209467b48Spatrick// Packed Compare Implicit Length Strings, Return Mask 433*d415bd75Srobertdefm : SLMWriteResPair<WritePCmpIStrM, [SLM_FPC_RSV0], 13, [13], 5, 1>; 43409467b48Spatrick 43509467b48Spatrick// Packed Compare Explicit Length Strings, Return Mask 436*d415bd75Srobertdefm : SLMWriteResPair<WritePCmpEStrM, [SLM_FPC_RSV0], 17, [17], 8, 1>; 43773471bf0Spatrick 43809467b48Spatrick// Packed Compare Implicit Length Strings, Return Index 439*d415bd75Srobertdefm : SLMWriteResPair<WritePCmpIStrI, [SLM_FPC_RSV0], 17, [17], 6, 1>; 44009467b48Spatrick 44109467b48Spatrick// Packed Compare Explicit Length Strings, Return Index 442*d415bd75Srobertdefm : SLMWriteResPair<WritePCmpEStrI, [SLM_FPC_RSV0], 21, [21], 9, 1>; 44309467b48Spatrick 44409467b48Spatrick// MOVMSK Instructions. 44509467b48Spatrickdef : WriteRes<WriteFMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 44609467b48Spatrickdef : WriteRes<WriteVecMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 44709467b48Spatrickdef : WriteRes<WriteMMXMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 448*d415bd75Srobertdefm : X86WriteResUnsupported<WriteVecMOVMSKY>; 44909467b48Spatrick 45009467b48Spatrick// AES Instructions. 451*d415bd75Srobertdefm : SLMWriteResPair<WriteAESDecEnc, [SLM_FPC_RSV0], 8, [5], 4, 1>; 452*d415bd75Srobertdefm : SLMWriteResPair<WriteAESIMC, [SLM_FPC_RSV0], 8, [4], 3, 1>; 453*d415bd75Srobertdefm : SLMWriteResPair<WriteAESKeyGen, [SLM_FPC_RSV0], 8, [4], 3, 1>; 45409467b48Spatrick 45509467b48Spatrick// Carry-less multiplication instructions. 456*d415bd75Srobertdefm : SLMWriteResPair<WriteCLMul, [SLM_FPC_RSV0], 10, [10], 8, 1>; 45709467b48Spatrick 45809467b48Spatrickdef : WriteRes<WriteSystem, [SLM_FPC_RSV0]> { let Latency = 100; } 45909467b48Spatrickdef : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; } 46009467b48Spatrickdef : WriteRes<WriteFence, [SLM_MEC_RSV]>; 46109467b48Spatrickdef : WriteRes<WriteNop, []>; 46209467b48Spatrick 46309467b48Spatrick// Remaining SLM instrs. 46409467b48Spatrick 46509467b48Spatrickdef SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> { 46609467b48Spatrick let Latency = 4; 46709467b48Spatrick let NumMicroOps = 2; 468*d415bd75Srobert let ResourceCycles = [8]; 46909467b48Spatrick} 470*d415bd75Srobertdef: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr, 471*d415bd75Srobert MMX_PSUBQrr, PSUBQrr, 472*d415bd75Srobert PCMPEQQrr)>; 473*d415bd75Srobert 474*d415bd75Srobertdef SLMWriteResGroup2rr : SchedWriteRes<[SLM_FPC_RSV0]> { 475*d415bd75Srobert let Latency = 5; 476*d415bd75Srobert let NumMicroOps = 1; 477*d415bd75Srobert let ResourceCycles = [2]; 478*d415bd75Srobert} 479*d415bd75Srobertdef: InstRW<[SLMWriteResGroup2rr], (instrs PCMPGTQrr)>; 48009467b48Spatrick 48109467b48Spatrickdef SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> { 48209467b48Spatrick let Latency = 7; 48309467b48Spatrick let NumMicroOps = 3; 484*d415bd75Srobert let ResourceCycles = [1,8]; 48509467b48Spatrick} 486*d415bd75Srobert 487*d415bd75Srobertdef: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm, 488*d415bd75Srobert MMX_PSUBQrm, PSUBQrm, 489*d415bd75Srobert PCMPEQQrm)>; 490*d415bd75Srobert 491*d415bd75Srobertdef SLMWriteResGroup2rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0]> { 492*d415bd75Srobert let Latency = 8; 493*d415bd75Srobert let NumMicroOps = 2; 494*d415bd75Srobert let ResourceCycles = [1,2]; 495*d415bd75Srobert} 496*d415bd75Srobertdef: InstRW<[SLMWriteResGroup2rm], (instrs PCMPGTQrm)>; 497*d415bd75Srobert 498*d415bd75Srobert/////////////////////////////////////////////////////////////////////////////// 499*d415bd75Srobert// Dependency breaking instructions. 500*d415bd75Srobert/////////////////////////////////////////////////////////////////////////////// 501*d415bd75Srobert 502*d415bd75Srobertdef : IsZeroIdiomFunction<[ 503*d415bd75Srobert // GPR Zero-idioms. 504*d415bd75Srobert DepBreakingClass<[ XOR32rr ], ZeroIdiomPredicate>, 505*d415bd75Srobert 506*d415bd75Srobert // SSE Zero-idioms. 507*d415bd75Srobert DepBreakingClass<[ 508*d415bd75Srobert // fp variants. 509*d415bd75Srobert XORPSrr, XORPDrr, 510*d415bd75Srobert 511*d415bd75Srobert // int variants. 512*d415bd75Srobert PXORrr, 513*d415bd75Srobert ], ZeroIdiomPredicate>, 514*d415bd75Srobert]>; 51509467b48Spatrick 51609467b48Spatrick} // SchedModel 517