1*d415bd75Srobert//===- XtensaOperands.td - Xtensa instruction operands -------*- tblgen-*--===// 2*d415bd75Srobert// 3*d415bd75Srobert// The LLVM Compiler Infrastructure 4*d415bd75Srobert// 5*d415bd75Srobert// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6*d415bd75Srobert// See https://llvm.org/LICENSE.txt for license information. 7*d415bd75Srobert// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8*d415bd75Srobert// 9*d415bd75Srobert//===----------------------------------------------------------------------===// 10*d415bd75Srobert 11*d415bd75Srobert// Immediate operands with a shared generic render method. 12*d415bd75Srobertclass ImmAsmOperand<string name> : AsmOperandClass { 13*d415bd75Srobert let Name = name; 14*d415bd75Srobert let RenderMethod = "addImmOperands"; 15*d415bd75Srobert let DiagnosticType = !strconcat("Invalid", name); 16*d415bd75Srobert} 17*d415bd75Srobert 18*d415bd75Srobertclass Immediate<ValueType vt, code pred, string asmop> 19*d415bd75Srobert : Operand<vt>, ImmLeaf<vt, pred> { 20*d415bd75Srobert let PrintMethod = "print"#asmop; 21*d415bd75Srobert let ParserMatchClass = !cast<AsmOperandClass>(asmop); 22*d415bd75Srobert} 23*d415bd75Srobert 24*d415bd75Srobert// imm8 predicate - Immediate in the range [-128,127] 25*d415bd75Srobertdef Imm8_AsmOperand : ImmAsmOperand<"Imm8">; 26*d415bd75Srobertdef imm8 : Immediate<i32, [{ return Imm >= -128 && Imm <= 127; }], "Imm8_AsmOperand"> { 27*d415bd75Srobert let EncoderMethod = "getImm8OpValue"; 28*d415bd75Srobert let DecoderMethod = "decodeImm8Operand"; 29*d415bd75Srobert} 30*d415bd75Srobert 31*d415bd75Srobert// imm8_sh8 predicate - Immediate in the range [-32768,32512] with (bits[7-0] == 0) 32*d415bd75Srobert// imm8 value left shifted by 8 bits 33*d415bd75Srobertdef Imm8_sh8_AsmOperand : ImmAsmOperand<"Imm8_sh8">; 34*d415bd75Srobertdef imm8_sh8 : Immediate<i32, [{ return Imm >= -32768 && Imm <= 32512 && ((Imm & 0xFF) == 0); }], 35*d415bd75Srobert "Imm8_sh8_AsmOperand"> { 36*d415bd75Srobert let EncoderMethod = "getImm8_sh8OpValue"; 37*d415bd75Srobert let DecoderMethod = "decodeImm8_sh8Operand"; 38*d415bd75Srobert} 39*d415bd75Srobert 40*d415bd75Srobert// imm12 predicate - Immediate in the range [-2048,2047] 41*d415bd75Srobertdef Imm12_AsmOperand : ImmAsmOperand<"Imm12">; 42*d415bd75Srobertdef imm12 : Immediate<i32, [{ return Imm >= -2048 && Imm <= 2047; }], "Imm12_AsmOperand"> { 43*d415bd75Srobert let EncoderMethod = "getImm12OpValue"; 44*d415bd75Srobert let DecoderMethod = "decodeImm12Operand"; 45*d415bd75Srobert} 46*d415bd75Srobert 47*d415bd75Srobert// imm12m predicate - Immediate for MOV operation 48*d415bd75Srobertdef Imm12m_AsmOperand : ImmAsmOperand<"Imm12m">; 49*d415bd75Srobertdef imm12m : Immediate<i32, [{ return Imm >= -2048 && Imm <= 2047; }], "Imm12m_AsmOperand"> { 50*d415bd75Srobert let EncoderMethod = "getImm12OpValue"; 51*d415bd75Srobert let DecoderMethod = "decodeImm12Operand"; 52*d415bd75Srobert} 53*d415bd75Srobert 54*d415bd75Srobert// uimm4 predicate - Immediate in the range [0,15] 55*d415bd75Srobertdef Uimm4_AsmOperand : ImmAsmOperand<"Uimm4">; 56*d415bd75Srobertdef uimm4 : Immediate<i32, [{ return Imm >= 0 && Imm <= 15; }], "Uimm4_AsmOperand"> { 57*d415bd75Srobert let EncoderMethod = "getUimm4OpValue"; 58*d415bd75Srobert let DecoderMethod = "decodeUimm4Operand"; 59*d415bd75Srobert} 60*d415bd75Srobert 61*d415bd75Srobert// uimm5 predicate - Immediate in the range [0,31] 62*d415bd75Srobertdef Uimm5_AsmOperand : ImmAsmOperand<"Uimm5">; 63*d415bd75Srobertdef uimm5 : Immediate<i32, [{ return Imm >= 0 && Imm <= 31; }], "Uimm5_AsmOperand"> { 64*d415bd75Srobert let EncoderMethod = "getUimm5OpValue"; 65*d415bd75Srobert let DecoderMethod = "decodeUimm5Operand"; 66*d415bd75Srobert} 67*d415bd75Srobert 68*d415bd75Srobert// imm1_16 predicate - Immediate in the range [1,16] 69*d415bd75Srobertdef Imm1_16_AsmOperand : ImmAsmOperand<"Imm1_16">; 70*d415bd75Srobertdef imm1_16 : Immediate<i32, [{ return Imm >= 1 && Imm <= 16; }], "Imm1_16_AsmOperand"> { 71*d415bd75Srobert let EncoderMethod = "getImm1_16OpValue"; 72*d415bd75Srobert let DecoderMethod = "decodeImm1_16Operand"; 73*d415bd75Srobert} 74*d415bd75Srobert 75*d415bd75Srobert// shimm1_31 predicate - Immediate in the range [1,31] 76*d415bd75Srobertdef Shimm1_31_AsmOperand : ImmAsmOperand<"Shimm1_31">; 77*d415bd75Srobertdef shimm1_31 : Immediate<i32, [{ return Imm >= 1 && Imm <= 31; }], "Shimm1_31_AsmOperand"> { 78*d415bd75Srobert let EncoderMethod = "getShimm1_31OpValue"; 79*d415bd75Srobert let DecoderMethod = "decodeShimm1_31Operand"; 80*d415bd75Srobert} 81*d415bd75Srobert 82*d415bd75Srobert// Memory offset 0..255 for 8-bit memory accesses 83*d415bd75Srobertdef Offset8m8_AsmOperand : ImmAsmOperand<"Offset8m8">; 84*d415bd75Srobertdef offset8m8 : Immediate<i32, 85*d415bd75Srobert [{ return Imm >= 0 && Imm <= 255; }], 86*d415bd75Srobert "Offset8m8_AsmOperand">; 87*d415bd75Srobert 88*d415bd75Srobert// Memory offset 0..510 for 16-bit memory accesses 89*d415bd75Srobertdef Offset8m16_AsmOperand : ImmAsmOperand<"Offset8m16">; 90*d415bd75Srobertdef offset8m16 : Immediate<i32, 91*d415bd75Srobert [{ return Imm >= 0 && Imm <= 510 && (Imm & 0x1 == 0); }], 92*d415bd75Srobert "Offset8m16_AsmOperand">; 93*d415bd75Srobert 94*d415bd75Srobert// Memory offset 0..1020 for 32-bit memory accesses 95*d415bd75Srobertdef Offset8m32_AsmOperand : ImmAsmOperand<"Offset8m32">; 96*d415bd75Srobertdef offset8m32 : Immediate<i32, 97*d415bd75Srobert [{ return Imm >= 0 && Imm <= 1020 && (Imm & 0x3 == 0); }], 98*d415bd75Srobert "Offset8m32_AsmOperand">; 99*d415bd75Srobert 100*d415bd75Srobert// Memory offset 0..60 for 32-bit memory accesses 101*d415bd75Srobertdef Offset4m32_AsmOperand : ImmAsmOperand<"Offset4m32">; 102*d415bd75Srobertdef offset4m32 : Immediate<i32, 103*d415bd75Srobert [{ return Imm >= 0 && Imm <= 60 && (Imm & 0x3 == 0); }], 104*d415bd75Srobert "Offset4m32_AsmOperand">; 105*d415bd75Srobert 106*d415bd75Srobert// b4const predicate - Branch Immediate 4-bit signed operand 107*d415bd75Srobertdef B4const_AsmOperand: ImmAsmOperand<"B4const">; 108*d415bd75Srobertdef b4const: Immediate<i32, 109*d415bd75Srobert [{ switch (Imm) { 110*d415bd75Srobert case -1: case 1: case 2: case 3: case 4: 111*d415bd75Srobert case 5: case 6: case 7: case 8: case 10: case 12: 112*d415bd75Srobert case 16: case 32: case 64: case 128: case 256: return 1; 113*d415bd75Srobert default: return 0; 114*d415bd75Srobert } 115*d415bd75Srobert }], 116*d415bd75Srobert "B4const_AsmOperand"> { 117*d415bd75Srobert let EncoderMethod = "getB4constOpValue"; 118*d415bd75Srobert let DecoderMethod = "decodeB4constOperand"; 119*d415bd75Srobert} 120*d415bd75Srobert 121*d415bd75Srobert// b4constu predicate - Branch Immediate 4-bit unsigned operand 122*d415bd75Srobertdef B4constu_AsmOperand: ImmAsmOperand<"B4constu">; 123*d415bd75Srobertdef b4constu: Immediate<i32, 124*d415bd75Srobert [{ switch (Imm) { 125*d415bd75Srobert case 32768: case 65536: case 2: case 3: case 4: 126*d415bd75Srobert case 5: case 6: case 7: case 8: case 10: case 12: 127*d415bd75Srobert case 16: case 32: case 64: case 128: case 256: return 1; 128*d415bd75Srobert default: return 0; 129*d415bd75Srobert } 130*d415bd75Srobert }], 131*d415bd75Srobert "B4constu_AsmOperand"> { 132*d415bd75Srobert let EncoderMethod = "getB4constuOpValue"; 133*d415bd75Srobert let DecoderMethod = "decodeB4constuOperand"; 134*d415bd75Srobert} 135*d415bd75Srobert//===----------------------------------------------------------------------===// 136*d415bd75Srobert// Memory address operands 137*d415bd75Srobert//===----------------------------------------------------------------------===// 138*d415bd75Srobert 139*d415bd75Srobertclass mem<Operand offset> : Operand<i32> { 140*d415bd75Srobert let MIOperandInfo = (ops AR, offset); 141*d415bd75Srobert let EncoderMethod = "getMemRegEncoding"; 142*d415bd75Srobert let OperandType = "OPERAND_MEMORY"; 143*d415bd75Srobert let PrintMethod = "printMemOperand"; 144*d415bd75Srobert} 145*d415bd75Srobert 146*d415bd75Srobertdef mem8 : mem<offset8m8> { 147*d415bd75Srobert let DecoderMethod = "decodeMem8Operand"; 148*d415bd75Srobert} 149*d415bd75Srobert 150*d415bd75Srobertdef mem16 : mem<offset8m16> { 151*d415bd75Srobert let DecoderMethod = "decodeMem16Operand"; 152*d415bd75Srobert} 153*d415bd75Srobert 154*d415bd75Srobertdef mem32 : mem<offset8m32> { 155*d415bd75Srobert let DecoderMethod = "decodeMem32Operand"; 156*d415bd75Srobert} 157*d415bd75Srobert 158*d415bd75Srobertdef mem32n : mem<offset4m32> { 159*d415bd75Srobert let DecoderMethod = "decodeMem32nOperand"; 160*d415bd75Srobert} 161*d415bd75Srobert 162*d415bd75Srobert//Add patterns for future use in stack addressing mode 163*d415bd75Srobertdef addr_ish1 : ComplexPattern<iPTR, 2, "selectMemRegAddrISH1", [frameindex]>; 164*d415bd75Srobertdef addr_ish2 : ComplexPattern<iPTR, 2, "selectMemRegAddrISH2", [frameindex]>; 165*d415bd75Srobertdef addr_ish4 : ComplexPattern<iPTR, 2, "selectMemRegAddrISH4", [frameindex]>; 166*d415bd75Srobert 167*d415bd75Srobert//===----------------------------------------------------------------------===// 168*d415bd75Srobert// Symbolic address operands 169*d415bd75Srobert//===----------------------------------------------------------------------===// 170*d415bd75Srobertdef XtensaPCRelTargetAsmOperand : AsmOperandClass { 171*d415bd75Srobert let Name = "PCRelTarget"; 172*d415bd75Srobert let ParserMethod = "parsePCRelTarget"; 173*d415bd75Srobert let PredicateMethod = "isImm"; 174*d415bd75Srobert let RenderMethod = "addImmOperands"; 175*d415bd75Srobert} 176*d415bd75Srobert 177*d415bd75Srobertdef pcrel32call : Operand<iPTR> { 178*d415bd75Srobert let PrintMethod = "printCallOperand"; 179*d415bd75Srobert let EncoderMethod = "getCallEncoding"; 180*d415bd75Srobert let DecoderMethod = "decodeCallOperand"; 181*d415bd75Srobert let ParserMatchClass = XtensaPCRelTargetAsmOperand; 182*d415bd75Srobert} 183*d415bd75Srobert 184*d415bd75Srobertdef brtarget : Operand<OtherVT> { 185*d415bd75Srobert let PrintMethod = "printBranchTarget"; 186*d415bd75Srobert let EncoderMethod = "getBranchTargetEncoding"; 187*d415bd75Srobert let DecoderMethod = "decodeBranchOperand"; 188*d415bd75Srobert let ParserMatchClass = XtensaPCRelTargetAsmOperand; 189*d415bd75Srobert} 190*d415bd75Srobert 191*d415bd75Srobertdef jumptarget : Operand<OtherVT> { 192*d415bd75Srobert let PrintMethod = "printJumpTarget"; 193*d415bd75Srobert let EncoderMethod = "getJumpTargetEncoding"; 194*d415bd75Srobert let DecoderMethod = "decodeJumpOperand"; 195*d415bd75Srobert let ParserMatchClass = XtensaPCRelTargetAsmOperand; 196*d415bd75Srobert} 197*d415bd75Srobert 198*d415bd75Srobertdef L32Rtarget : Operand<OtherVT> { 199*d415bd75Srobert let PrintMethod = "printL32RTarget"; 200*d415bd75Srobert let EncoderMethod = "getL32RTargetEncoding"; 201*d415bd75Srobert let DecoderMethod = "decodeL32ROperand"; 202*d415bd75Srobert let ParserMatchClass = XtensaPCRelTargetAsmOperand; 203*d415bd75Srobert} 204