1; IQ2000/IQ10 Common CPU description. -*- Scheme -*- 2; Copyright (C) 2000, 2001, 2002 Red Hat, Inc. 3; This file is part of CGEN. 4; See file COPYING.CGEN for details. 5 6(include "simplify.inc") 7 8(define-arch 9 (name iq2000) 10 (comment "IQ2000 architecture") 11 (insn-lsb0? #t) 12 (machs iq2000 iq10) 13 (isas iq2000) 14) 15 16(define-isa 17 (name iq2000) 18 (comment "Basic IQ2000 instruction set") 19 (default-insn-word-bitsize 32) 20 (default-insn-bitsize 32) 21 (base-insn-bitsize 32) 22 (decode-assist (31 30 29 28 27 26)) 23) 24 25(define-cpu 26 (name iq2000bf) 27 (comment "IQ2000 family") 28 (endian big) 29 (word-bitsize 32) 30 (file-transform "") 31) 32 33(define-cpu 34 (name iq10bf) 35 (comment "IQ10 coprocessor family") 36 (endian big) 37 (word-bitsize 32) 38 (file-transform "") 39 40) 41 42(define-mach 43 (name iq2000) 44 (comment "IQ2000 packet processing engine") 45 (cpu iq2000bf) 46 (isas iq2000) 47) 48 49(define-mach 50 (name iq10) 51 (comment "IQ10 coprocessor") 52 (cpu iq10bf) 53 (isas iq2000) 54) 55 56(define-model 57 (name iq2000) 58 (comment "IQ2000 microprocessor") 59 (mach iq2000) 60 (unit u-exec "Execution Unit" () 61 1 1 ; issue done 62 () () () ()) 63) 64 65(define-model 66 (name iq10) 67 (comment "IQ10 coprocessor") 68 (mach iq10) 69 (unit u-exec "Execution Unit" () 70 1 1 ; issue done 71 () () () ()) 72) 73 74; Macros to simplify MACH attribute specification. 75 76(define-pmacro MACH2000 (MACH iq2000)) 77(define-pmacro MACH10 (MACH iq10)) 78 79 80; Hardware elements. 81 82(define-hardware 83 (name h-pc) 84 (comment "program counter") 85 (attrs PC PROFILE (ISA iq2000)) 86 (type pc) 87 (get () (c-call USI "get_h_pc")) 88 (set (newval) (c-call VOID "set_h_pc" newval)) 89) 90; FIXME: it would be nice if the hardwired zero in R0 could be 91; specified as a virtual hardware element, with one less register in 92; the register file proper. 93 94(define-keyword 95 (name gr-names) 96 (print-name h-gr) 97 (values (r0 0) (%0 0) (r1 1) (%1 1) (r2 2) (%2 2) (r3 3) (%3 3) 98 (r4 4) (%4 4) (r5 5) (%5 5) (r6 6) (%6 6) (r7 7) (%7 7) 99 (r8 8) (%8 8) (r9 9) (%9 9) (r10 10) (%10 10) (r11 11) (%11 11) 100 (r12 12) (%12 12) (r13 13) (%13 13) (r14 14) (%14 14) (r15 15) (%15 15) 101 (r16 16) (%16 16) (r17 17) (%17 17) (r18 18) (%18 18) (r19 19) (%19 19) 102 (r20 20) (%20 20) (r21 21) (%21 21) (r22 22) (%22 22) (r23 23) (%23 23) 103 (r24 24) (%24 24) (r25 25) (%25 25) (r26 26) (%26 26) (r27 27) (%27 27) 104 (r28 28) (%28 28) (r29 29) (%29 29) (r30 30) (%30 30) (r31 31) (%31 31)) 105) 106 107(define-hardware 108 (name h-gr) 109 (comment "General purpose registers") 110; (attrs (ISA iq2000) CACHE-ADDR) 111 (type register SI (32)) 112 (indices extern-keyword gr-names) 113 (get (idx) 114 (cond SI 115 ((eq idx 0) (const 0)) 116 (else (raw-reg h-gr idx)))) 117 (set (idx newval) 118 (cond VOID 119 ((eq idx 0) (nop)) 120 (else (set (raw-reg h-gr idx) newval)))) 121) 122 123 124; Instruction fields. 125 126(dnf f-opcode "opcode field" () 31 6) 127(dnf f-rs "register field Rs" () 25 5) 128(dnf f-rt "register field Rt" () 20 5) 129(dnf f-rd "register field Rd" () 15 5) 130(dnf f-shamt "shift amount field" () 10 5) 131(dnf f-cp-op "coprocessor op field" () 10 3) 132(dnf f-cp-op-10 "coprocessor op field for CAM" () 10 5) 133(dnf f-cp-grp "coprocessor group field" () 7 2) 134(dnf f-func "function field" () 5 6) 135(dnf f-imm "immediate field" () 15 16) 136 137(define-multi-ifield 138 (name f-rd-rs) 139 (comment "register Rd implied from Rs") 140 (attrs) 141 (mode UINT) 142 (subfields f-rd f-rs) 143 (insert (sequence () 144 (set (ifield f-rd) (ifield f-rd-rs)) 145 (set (ifield f-rs) (ifield f-rd-rs)) 146 )) 147 (extract (sequence () 148 (set (ifield f-rd-rs) (ifield f-rs)) 149 )) 150) 151 152(define-multi-ifield 153 (name f-rd-rt) 154 (comment "register Rd implied from Rt") 155 (attrs) 156 (mode UINT) 157 (subfields f-rd f-rt) 158 (insert (sequence () 159 (set (ifield f-rd) (ifield f-rd-rt)) 160 (set (ifield f-rt) (ifield f-rd-rt)) 161 )) 162 (extract (sequence () 163 (set (ifield f-rd-rt) (ifield f-rt)) 164 )) 165) 166 167(define-multi-ifield 168 (name f-rt-rs) 169 (comment "register Rt implied from Rs") 170 (attrs) 171 (mode UINT) 172 (subfields f-rt f-rs) 173 (insert (sequence () 174 (set (ifield f-rt) (ifield f-rt-rs)) 175 (set (ifield f-rs) (ifield f-rt-rs)) 176 )) 177 (extract (sequence () 178 (set (ifield f-rd-rs) (ifield f-rs)) 179 )) 180) 181 182(df f-jtarg "jump target field" (ABS-ADDR) 15 16 UINT 183 ((value pc) (srl USI (and USI value #x03FFFF) 2)) 184 ((value pc) (or USI (and USI pc #xF0000000) (sll USI value 2)))) 185 186(df f-jtargq10 "iq10 jump target field" (ABS-ADDR) 20 21 UINT 187 ((value pc) (srl SI (and SI value #x7FFFFF) 2)) 188 ((value pc) (or SI (and SI pc #xF0000000) (sll SI value 2)))) 189 190(df f-offset "pc offset field" (PCREL-ADDR) 15 16 INT 191 ; Actually, this is relative to the address of the delay slot. 192 ((value pc) (sra SI (sub SI value pc) 2)) 193 ((value pc) (add SI (sll SI value 2) (add pc 4)))) 194 195; Instruction fields that scarcely appear in instructions. 196 197(dnf f-count "count field" () 15 7) 198(dnf f-bytecount "byte count field" () 7 8) 199(dnf f-index "index field" () 8 9) 200(dnf f-mask "mask field" () 9 4) 201(dnf f-maskq10 "iq10 mask field" () 10 5) 202(dnf f-maskl "mask left field" () 4 5) 203(dnf f-excode "execcode field" () 25 20) 204(dnf f-rsrvd "reserved field" () 25 10) 205(dnf f-10-11 "bits 10:0" () 10 11) 206(dnf f-24-19 "bits 24:6" () 24 19) 207(dnf f-5 "bit 5" () 5 1) 208(dnf f-10 "bit 10" () 10 1) 209(dnf f-25 "bit 25" () 25 1) 210(dnf f-cam-z "cam global mask z" () 5 3) 211(dnf f-cam-y "cam operation y" () 2 3) 212(dnf f-cm-3func "CM 3 bit fn field" () 5 3) 213(dnf f-cm-4func "CM 4 bit fn field" () 5 4) 214(dnf f-cm-3z "CM 3Z field" () 1 2) 215(dnf f-cm-4z "CM 4Z field" () 2 3) 216 217 218; Enumerations. 219 220(define-normal-insn-enum 221 opcodes "primary opcodes" () OP_ f-opcode 222 (("SPECIAL" 0) ("REGIMM" 1) ("J" 2) ("JAL" 3) ("BEQ" 4) ("BNE" 5) ("BLEZ" 6) ("BGTZ" 7) 223 ("ADDI" 8) ("ADDIU" 9) ("SLTI" 10) ("SLTIU" 11) ("ANDI" 12) ("ORI" 13) ("XORI" 14) ("LUI" 15) 224 ("COP0" 16) ("COP1" 17) ("COP2" 18) ("COP3" 19) ("BEQL" 20) ("BNEL" 21) ("BLEZL" 22) ("BGTZL" 23) 225 ("BMB0" 24) ("BMB1" 25) ("BMB2" 26) ("BMB3" 27) ("BBI" 28) ("BBV" 29) ("BBIN" 30) ("BBVN" 31) 226 ("LB" 32) ("LH" 33) ("LW" 35) ("LBU" 36) ("LHU" 37) ("RAM" 39) 227 ("SB" 40) ("SH" 41) ("SW" 43) ("ANDOI" 44) ("BMB" 45) ("ORUI" 47) 228 ("LDW" 48) 229 ("SDW" 56) ("ANDOUI" 63)) 230) 231 232(define-normal-insn-enum 233 q10_opcodes "iq10-only primary opcodes" () OP10_ f-opcode 234 (("BMB" 6) ("ORUI" 15) ("BMBL" 22) ("ANDOUI" 47) ("BBIL" 60) ("BBVL" 61) ("BBINL" 62) ("BBVNL" 63)) 235) 236 237(define-normal-insn-enum 238 regimm-functions "branch sub-opcodes" () FUNC_ f-rt 239 (("BLTZ" 0) ("BGEZ" 1) ("BLTZL" 2) ("BGEZL" 3) ("BLEZ" 4) ("BGTZ" 5) ("BLEZL" 6) ("BGTZL" 7) 240 ("BRI" 8) ("BRV" 9) ("BCTX" 12) 241 ("BLTZAL" 16) ("BGEZAL" 17) ("BLTZALL" 18) ("BGEZALL" 19) ("BLEZAL" 20) ("BGTZAL" 21) ("BLEZALL" 22) ("BGTZALL" 23)) 242) 243 244(define-normal-insn-enum 245 functions "function sub-opcodes" () FUNC_ f-func 246 (("SLL" 0) ("SLMV" 1) ("SRL" 2) ("SRA" 3) ("SLLV" 4) ("SRMV" 5) ("SRLV" 6) ("SRAV" 7) 247 ("JR" 8) ("JALR" 9) ("JCR" 10) ("SYSCALL" 12) ("BREAK" 13) ("SLEEP" 14) 248 ("ADD" 32) ("ADDU" 33) ("SUB" 34) ("SUBU" 35) ("AND" 36) ("OR" 37) ("XOR" 38) ("NOR" 39) 249 ("ADO16" 41) ("SLT" 42) ("SLTU" 43) ("MRGB" 45)) 250) 251 252; iq10 special function sub-opcodes 253(define-normal-insn-enum 254 q10s_functions "iq10-only special function sub-opcodes" () FUNC10_ f-func 255 (("YIELD" 14) ("CNT1S" 46)) 256) 257 258; coprocessor opcodes in concert with f-cp-grp 259(define-normal-insn-enum 260 cop_functions "iq10 function sub-opcodes" () FUNC10_ f-func 261 (("CFC" 0) ("LOCK" 1) ("CTC" 2) ("UNLK" 3) ("SWRD" 4) ("SWRDL" 5) ("SWWR" 6) ("SWWRU" 7) 262 ("RBA" 8) ("RBAL" 9) ("RBAR" 10) ("DWRD" 12) ("DWRDL" 13) 263 ("WBA" 16) ("WBAU" 17) ("WBAC" 18) ("CRC32" 20) ("CRC32B" 21) 264 ("MCID" 32) ("DBD" 33) ("DBA" 34) ("DPWT" 35) ("AVAIL" 36) ("FREE" 37) ("CHKHDR" 38) ("TSTOD" 39) 265 ("PKRLA" 40) ("PKRLAU" 41) ("PKRLAH" 42) ("PKRLAC" 43) ("CMPHDR" 44) 266 267 ("CM64RS" 0) ("CM64RD" 1) ("CM64RI" 4) ("CM64CLR" 5) 268 ("CM64SS" 8) ("CM64SD" 9) ("CM64SI" 12) 269 ("CM64RA" 16) ("CM64RIA2" 20) ("CM128RIA2" 21) 270 ("CM64SA" 24) ("CM64SIA2" 28) ("CM128SIA2" 29) 271 ("CM32RS" 32) ("CM32RD" 33) ("CM32XOR" 34) ("CM32ANDN" 35) ("CM32RI" 36) ("CM128VSA" 38) 272 ("CM32SS" 40) ("CM32SD" 41) ("CM32OR" 42) ("CM32AND" 43) ("CM32SI" 44) 273 ("CM32RA" 48) 274 ("CM32SA" 56) ) 275) 276 277; coprocessor opcodes in concert with f-cp-grp 278(define-normal-insn-enum 279 cop_cm128_4functions "iq10 function sub-opcodes" () FUNC10_ f-cm-4func 280 (("CM128RIA3" 4) ("CM128SIA3" 6)) 281) 282 283(define-normal-insn-enum 284 cop_cm128_3functions "iq10 function sub-opcodes" () FUNC10_ f-cm-3func 285 (("CM128RIA4" 6) ("CM128SIA4" 7)) 286) 287 288(define-normal-insn-enum 289 cop2_functions "iq10 coprocessor sub-opcodes" () FUNC10_ f-cp-op 290 (("PKRLI" 0) ("PKRLIU" 1) ("PKRLIH" 2) ("PKRLIC" 3) ("RBIR" 1) ("RBI" 2) ("RBIL" 3) ("WBIC" 5) ("WBI" 6) ("WBIU" 7)) 291) 292 293(define-normal-insn-enum 294 cop3_cam_functions "iq10 coprocessor cam sub-opcodes" () FUNC10_ f-cp-op-10 295 (("CAM36" 16) ("CAM72" 17) ("CAM144" 18) ("CAM288" 19)) 296) 297 298 299; Attributes. 300 301(define-attr 302 (for insn) 303 (type boolean) 304 (name YIELD-INSN) 305 (comment "insn generates a context yield") 306) 307 308(define-attr 309 (for insn) 310 (type boolean) 311 (name LOAD-DELAY) 312 (comment "insn has a load delay") 313) 314 315(define-attr 316 (for insn) 317 (type boolean) 318 (name EVEN-REG-NUM) 319 (comment "insn requires an even numbered register in rt(2000) or rd(10)") 320) 321 322(define-attr 323 (for insn) 324 (type boolean) 325 (name UNSUPPORTED) 326 (comment "insn is unsupported") 327) 328 329(define-pmacro (define-reg-use-attr regfield) 330 (define-attr 331 (for insn) 332 (type boolean) 333 (name (.sym USES- (.upcase regfield))) 334 (comment ("insn accesses register operand " regfield)))) 335 336(define-reg-use-attr "rd") 337(define-reg-use-attr "rs") 338(define-reg-use-attr "rt") 339(define-reg-use-attr "r31") 340 341 342; Operands. 343 344(dnop rs "register Rs" () h-gr f-rs) 345(dnop rt "register Rt" () h-gr f-rt) 346(dnop rd "register Rd" () h-gr f-rd) 347(dnop rd-rs "register Rd from Rs" () h-gr f-rd-rs) 348(dnop rd-rt "register Rd from Rt" () h-gr f-rd-rt) 349(dnop rt-rs "register Rt from Rs" () h-gr f-rt-rs) 350(dnop shamt "shift amount" () h-uint f-shamt) 351(define-operand (name imm) (comment "immediate") (attrs) 352 (type h-uint) (index f-imm) (handlers (parse "imm"))) 353(dnop offset "pc-relative offset" () h-iaddr f-offset) 354(dnop baseoff "base register offset" () h-iaddr f-imm) 355(dnop jmptarg "jump target" () h-iaddr f-jtarg) 356(dnop mask "mask" () h-uint f-mask) 357(dnop maskq10 "iq10 mask" () h-uint f-maskq10) 358(dnop maskl "mask left" () h-uint f-maskl) 359(dnop count "count" () h-uint f-count) 360(dnop _index "index" () h-uint f-index) 361(dnop execode "execcode" () h-uint f-excode) 362(dnop bytecount "byte count" () h-uint f-bytecount) 363(dnop cam-y "cam global opn y" () h-uint f-cam-y) 364(dnop cam-z "cam global mask z" () h-uint f-cam-z) 365(dnop cm-3func "CM 3 bit fn field" () h-uint f-cm-3func) 366(dnop cm-4func "CM 4 bit fn field" () h-uint f-cm-4func) 367(dnop cm-3z "CM 3 bit Z field" () h-uint f-cm-3z) 368(dnop cm-4z "CM 4 bit Z field" () h-uint f-cm-4z) 369 370; Aliases for the rs and rt operands. This just makes the load/store 371; insns easier to compare with the instruction set documentation. 372 373(dnop base "base register" () h-gr f-rs) 374(dnop maskr "mask right" () h-uint f-rs) 375(dnop bitnum "bit number" () h-uint f-rt) 376 377; For high(foo). 378(define-operand 379 (name hi16) 380 (comment "high 16 bit immediate") 381 (attrs) 382 (type h-uint) 383 (index f-imm) 384 (handlers (parse "hi16")) 385) 386 387; For low(foo). 388(define-operand 389 (name lo16) 390 (comment "16 bit signed immediate, for low") 391 (attrs) 392 (type h-uint) 393 (index f-imm) 394 (handlers (parse "lo16")) 395) 396 397; For negated imm. 398(define-operand 399 (name mlo16) 400 (comment "negated 16 bit signed immediate") 401 (attrs) 402 (type h-uint) 403 (index f-imm) 404 (handlers (parse "mlo16")) 405) 406 407; For iq10 jmps 408; In the future, we'll want the j & jal to use the 21 bit target, with 409; the upper five bits shifted up. For now, don't use this. 410(define-operand 411 (name jmptargq10) 412 (comment "iq10 21-bit jump offset") 413 (attrs) 414 (type h-iaddr) 415 (index f-jtargq10) 416 (handlers (parse "jtargq10")) 417) 418 419 420; Instructions. 421 422; A pmacro for use in semantic bodies of unimplemented insns. 423(define-pmacro (unimp mnemonic) (nop)) 424 425(define-pmacro (bitset? value bit-num) 426 (and value (sll 1 bit-num))) 427 428(define-pmacro (bitclear? value bit-num) 429 (not (bitset? value bit-num))) 430 431; Arithmetic/logic instructions. 432 433(dni add2 "add registers" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 434 "add ${rd-rs},$rt" 435 (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_ADD) 436 (set rd-rs (add rt rd-rs)) 437 ()) 438 439(dni add "add registers" (USES-RD USES-RS USES-RT) 440 "add $rd,$rs,$rt" 441 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADD) 442 (set rd (add rs rt)) 443 ()) 444 445 446(dni addi2 "add immediate" (ALIAS NO-DIS USES-RS USES-RT) 447 "addi ${rt-rs},$lo16" 448 (+ OP_ADDI rt-rs lo16) 449 (set rt-rs (add rt-rs (ext SI (trunc HI lo16)))) 450 ()) 451 452(dni addi "add immediate" (USES-RS USES-RT) 453 "addi $rt,$rs,$lo16" 454 (+ OP_ADDI rs rt lo16) 455 (set rt (add rs (ext SI (trunc HI lo16)))) 456 ()) 457 458(dni addiu2 "add immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT) 459 "addiu ${rt-rs},$lo16" 460 (+ OP_ADDIU rt-rs lo16) 461 (set rt-rs (add rt-rs (ext SI (trunc HI lo16)))) 462 ()) 463 464(dni addiu "add immediate unsigned" (USES-RS USES-RT) 465 "addiu $rt,$rs,$lo16" 466 (+ OP_ADDIU rs rt lo16) 467 (set rt (add rs (ext SI (trunc HI lo16)))) 468 ()) 469 470(dni addu2 "add unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 471 "addu ${rd-rs},$rt" 472 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADDU) 473 (set rd-rs (add rd-rs rt)) 474 ()) 475 476(dni addu "add unsigned" (USES-RD USES-RS USES-RT) 477 "addu $rd,$rs,$rt" 478 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADDU) 479 (set rd (add rs rt)) 480 ()) 481 482(dni ado162 "add 16, ones complement" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 483 "ado16 ${rd-rs},$rt" 484 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADO16) 485 (sequence ((HI high) (HI low)) 486 (set low (add HI (and HI rd-rs #xFFFF) (and HI rt #xFFFF))) 487 (set high (add HI (srl rd-rs 16) (srl rt 16))) 488 (set rd-rs (or SI (sll SI high 16) low))) 489 ()) 490 491(dni ado16 "add 16, ones complement" (USES-RD USES-RS USES-RT) 492 "ado16 $rd,$rs,$rt" 493 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADO16) 494 (sequence ((HI high) (HI low)) 495 (set low (add HI (and HI rs #xFFFF) (and HI rt #xFFFF))) 496 (set high (add HI (srl rs 16) (srl rt 16))) 497 (set rd (or SI (sll SI high 16) low))) 498 ()) 499 500(dni and2 "and register" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 501 "and ${rd-rs},$rt" 502 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_AND) 503 (set rd-rs (and rd-rs rt)) 504 ()) 505 506(dni and "and register" (USES-RD USES-RS USES-RT) 507 "and $rd,$rs,$rt" 508 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_AND) 509 (set rd (and rs rt)) 510 ()) 511 512(dni andi2 "and immediate" (ALIAS NO-DIS USES-RS USES-RT) 513 "andi ${rt-rs},$lo16" 514 (+ OP_ANDI rt-rs lo16) 515 (set rt-rs (and rt-rs (zext SI lo16))) 516 ()) 517 518(dni andi "and immediate" (USES-RS USES-RT) 519 "andi $rt,$rs,$lo16" 520 (+ OP_ANDI rs rt lo16) 521 (set rt (and rs (zext SI lo16))) 522 ()) 523 524(dni andoi2 "and ones immediate" (ALIAS NO-DIS USES-RS USES-RT) 525 "andoi ${rt-rs},$lo16" 526 (+ OP_ANDOI rt-rs lo16) 527 (set rt-rs (and rt-rs (or #xFFFF0000 (ext SI (trunc HI lo16))))) 528 ()) 529 530(dni andoi "and ones immediate" (USES-RS USES-RT) 531 "andoi $rt,$rs,$lo16" 532 (+ OP_ANDOI rs rt lo16) 533 (set rt (and rs (or #xFFFF0000 (ext SI (trunc HI lo16))))) 534 ()) 535 536(dni nor2 "nor" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 537 "nor ${rd-rs},$rt" 538 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_NOR) 539 (set rd-rs (inv (or rd-rs rt))) 540 ()) 541 542(dni nor "nor" (USES-RD USES-RS USES-RT) 543 "nor $rd,$rs,$rt" 544 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_NOR) 545 (set rd (inv (or rs rt))) 546 ()) 547 548(dni or2 "or" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 549 "or ${rd-rs},$rt" 550 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_OR) 551 (set rd-rs (or rd-rs rt)) 552 ()) 553 554(dni or "or" (USES-RD USES-RS USES-RT) 555 "or $rd,$rs,$rt" 556 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_OR) 557 (set rd (or rs rt)) 558 ()) 559 560(dni ori2 "or immediate" (ALIAS NO-DIS USES-RS USES-RT) 561 "ori ${rt-rs},$lo16" 562 (+ OP_ORI rt-rs lo16) 563 (set rt-rs (or rt-rs (zext SI lo16))) 564 ()) 565 566(dni ori "or immediate" (USES-RS USES-RT) 567 "ori $rt,$rs,$lo16" 568 (+ OP_ORI rs rt lo16) 569 (set rt (or rs (zext SI lo16))) 570 ()) 571 572(dni ram "rotate and mask" (USES-RD USES-RT) 573 "ram $rd,$rt,$shamt,$maskl,$maskr" 574 (+ OP_RAM maskr rt rd shamt (f-5 0) maskl) 575 (sequence () 576 (set rd (ror rt shamt)) 577 (set rd (and rd (srl #xFFFFFFFF maskl))) 578 (set rd (and rd (sll #xFFFFFFFF maskr)))) 579 ()) 580 581(dni sll "shift left logical" (USES-RD USES-RT) 582 "sll $rd,$rt,$shamt" 583 (+ OP_SPECIAL (f-rs 0) rt rd shamt (f-func 0)) 584 (set rd (sll rt shamt)) 585 ()) 586 587(dni sllv2 "shift left logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 588 "sllv ${rd-rt},$rs" 589 (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SLLV) 590 (set rd-rt (sll rd-rt (and rs #x1F))) 591 ()) 592 593(dni sllv "shift left logical variable" (USES-RD USES-RS USES-RT) 594 "sllv $rd,$rt,$rs" 595 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLLV) 596 (set rd (sll rt (and rs #x1F))) 597 ()) 598 599(dni slmv2 "shift left and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 600 "slmv ${rd-rt},$rs,$shamt" 601 (+ OP_SPECIAL rs rd-rt shamt FUNC_SLMV) 602 (set rd-rt (and (sll rd-rt shamt) (srl #xFFFFFFFF rs))) 603 ()) 604 605(dni slmv "shift left and mask variable" (USES-RD USES-RS USES-RT) 606 "slmv $rd,$rt,$rs,$shamt" 607 (+ OP_SPECIAL rs rt rd shamt FUNC_SLMV) 608 (set rd (and (sll rt shamt) (srl #xFFFFFFFF rs))) 609 ()) 610 611(dni slt2 "set if less than" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 612 "slt ${rd-rs},$rt" 613 (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SLT) 614 (if (lt rd-rs rt) 615 (set rd-rs 1) 616 (set rd-rs 0)) 617 ()) 618 619(dni slt "set if less than" (USES-RD USES-RS USES-RT) 620 "slt $rd,$rs,$rt" 621 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLT) 622 (if (lt rs rt) 623 (set rd 1) 624 (set rd 0)) 625 ()) 626 627(dni slti2 "set if less than immediate" (ALIAS NO-DIS USES-RS USES-RT) 628 "slti ${rt-rs},$imm" 629 (+ OP_SLTI rt-rs imm) 630 (if (lt rt-rs (ext SI (trunc HI imm))) 631 (set rt-rs 1) 632 (set rt-rs 0)) 633 ()) 634 635(dni slti "set if less than immediate" (USES-RS USES-RT) 636 "slti $rt,$rs,$imm" 637 (+ OP_SLTI rs rt imm) 638 (if (lt rs (ext SI (trunc HI imm))) 639 (set rt 1) 640 (set rt 0)) 641 ()) 642 643(dni sltiu2 "set if less than immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT) 644 "sltiu ${rt-rs},$imm" 645 (+ OP_SLTIU rt-rs imm) 646 (if (ltu rt-rs (ext SI (trunc HI imm))) 647 (set rt-rs 1) 648 (set rt-rs 0)) 649 ()) 650 651(dni sltiu "set if less than immediate unsigned" (USES-RS USES-RT) 652 "sltiu $rt,$rs,$imm" 653 (+ OP_SLTIU rs rt imm) 654 (if (ltu rs (ext SI (trunc HI imm))) 655 (set rt 1) 656 (set rt 0)) 657 ()) 658 659(dni sltu2 "set if less than unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 660 "sltu ${rd-rs},$rt" 661 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_SLTU) 662 (if (ltu rd-rs rt) 663 (set rd-rs 1) 664 (set rd-rs 0)) 665 ()) 666 667(dni sltu "set if less than unsigned" (USES-RD USES-RS USES-RT) 668 "sltu $rd,$rs,$rt" 669 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLTU) 670 (if (ltu rs rt) 671 (set rd 1) 672 (set rd 0)) 673 ()) 674 675(dni sra2 "shift right arithmetic" (ALIAS NO-DIS USES-RD USES-RT) 676 "sra ${rd-rt},$shamt" 677 (+ OP_SPECIAL (f-rs 0) rd-rt shamt FUNC_SRA) 678 (set rd-rt (sra rd-rt shamt)) 679 ()) 680 681(dni sra "shift right arithmetic" (USES-RD USES-RT) 682 "sra $rd,$rt,$shamt" 683 (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRA) 684 (set rd (sra rt shamt)) 685 ()) 686 687(dni srav2 "shift right arithmetic variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 688 "srav ${rd-rt},$rs" 689 (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRAV) 690 (set rd-rt (sra rd-rt (and rs #x1F))) 691 ()) 692 693(dni srav "shift right arithmetic variable" (USES-RD USES-RS USES-RT) 694 "srav $rd,$rt,$rs" 695 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRAV) 696 (set rd (sra rt (and rs #x1F))) 697 ()) 698 699(dni srl "shift right logical" (USES-RD USES-RT) 700 "srl $rd,$rt,$shamt" 701 (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRL) 702 (set rd (srl rt shamt)) 703 ()) 704 705(dni srlv2 "shift right logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 706 "srlv ${rd-rt},$rs" 707 (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRLV) 708 (set rd-rt (srl rd-rt (and rs #x1F))) 709 ()) 710 711(dni srlv "shift right logical variable" (USES-RD USES-RS USES-RT) 712 "srlv $rd,$rt,$rs" 713 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRLV) 714 (set rd (srl rt (and rs #x1F))) 715 ()) 716 717(dni srmv2 "shift right and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 718 "srmv ${rd-rt},$rs,$shamt" 719 (+ OP_SPECIAL rs rd-rt shamt FUNC_SRMV) 720 (set rd-rt (and (srl rd-rt shamt) (sll #xFFFFFFFF rs))) 721 ()) 722 723(dni srmv "shift right and mask variable" (USES-RD USES-RS USES-RT) 724 "srmv $rd,$rt,$rs,$shamt" 725 (+ OP_SPECIAL rs rt rd shamt FUNC_SRMV) 726 (set rd (and (srl rt shamt) (sll #xFFFFFFFF rs))) 727 ()) 728 729(dni sub2 "subtract" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 730 "sub ${rd-rs},$rt" 731 (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUB) 732 (set rd-rs (sub rd-rs rt)) 733 ()) 734 735(dni sub "subtract" (USES-RD USES-RS USES-RT) 736 "sub $rd,$rs,$rt" 737 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUB) 738 (set rd (sub rs rt)) 739 ()) 740 741(dni subu2 "subtract unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 742 "subu ${rd-rs},$rt" 743 (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUBU) 744 (set rd-rs (sub rd-rs rt)) 745 ()) 746 747(dni subu "subtract unsigned" (USES-RD USES-RS USES-RT) 748 "subu $rd,$rs,$rt" 749 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUBU) 750 (set rd (sub rs rt)) 751 ()) 752 753(dni xor2 "exclusive or" (ALIAS NO-DIS USES-RD USES-RS USES-RT) 754 "xor ${rd-rs},$rt" 755 (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_XOR) 756 (set rd-rs (xor rd-rs rt)) 757 ()) 758 759(dni xor "exclusive or" (USES-RD USES-RS USES-RT) 760 "xor $rd,$rs,$rt" 761 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_XOR) 762 (set rd (xor rs rt)) 763 ()) 764 765(dni xori2 "exclusive or immediate" (ALIAS NO-DIS USES-RS USES-RT) 766 "xori ${rt-rs},$lo16" 767 (+ OP_XORI rt-rs lo16) 768 (set rt-rs (xor rt-rs (zext SI lo16))) 769 ()) 770 771(dni xori "exclusive or immediate" (USES-RS USES-RT) 772 "xori $rt,$rs,$lo16" 773 (+ OP_XORI rs rt lo16) 774 (set rt (xor rs (zext SI lo16))) 775 ()) 776 777 778; Branch instructions. 779 780(dni bbi "branch bit immediate" (USES-RS) 781 "bbi $rs($bitnum),$offset" 782 (+ OP_BBI rs bitnum offset) 783 (if (bitset? rs bitnum) 784 (delay 1 (set pc offset))) 785 ()) 786 787(dni bbin "branch bit immediate negated" (USES-RS) 788 "bbin $rs($bitnum),$offset" 789 (+ OP_BBIN rs bitnum offset) 790 (if (bitclear? rs bitnum) 791 (delay 1 (set pc offset))) 792 ()) 793 794(dni bbv "branch bit variable" (USES-RS USES-RT) 795 "bbv $rs,$rt,$offset" 796 (+ OP_BBV rs rt offset) 797 (if (bitset? rs (and rt #x1F)) 798 (delay 1 (set pc offset))) 799 ()) 800 801(dni bbvn "branch bit variable negated" (USES-RS USES-RT) 802 "bbvn $rs,$rt,$offset" 803 (+ OP_BBVN rs rt offset) 804 (if (bitclear? rs (and rt #x1F)) 805 (delay 1 (set pc offset))) 806 ()) 807 808(dni beq "branch if equal" (USES-RS USES-RT) 809 "beq $rs,$rt,$offset" 810 (+ OP_BEQ rs rt offset) 811 (if (eq rs rt) 812 (delay 1 (set pc offset))) 813 ()) 814 815(dni beql "branch if equal likely" (USES-RS USES-RT) 816 "beql $rs,$rt,$offset" 817 (+ OP_BEQL rs rt offset) 818 (if (eq rs rt) 819 (delay 1 (set pc offset)) 820 (skip 1)) 821 ()) 822 823(dni bgez "branch if greater than or equal to zero" (USES-RS) 824 "bgez $rs,$offset" 825 (+ OP_REGIMM rs FUNC_BGEZ offset) 826 (if (ge rs 0) 827 (delay 1 (set pc offset))) 828 ()) 829 830(dni bgezal "branch if greater than or equal to zero and link" (USES-RS USES-R31) 831 "bgezal $rs,$offset" 832 (+ OP_REGIMM rs FUNC_BGEZAL offset) 833 (if (ge rs 0) 834 (sequence () 835 (set (reg h-gr 31) (add pc 8)) 836 (delay 1 (set pc offset)))) 837 ()) 838 839(dni bgezall 840 "branch if greater than equal to zero and link likely" (USES-RS USES-R31) 841 "bgezall $rs,$offset" 842 (+ OP_REGIMM rs FUNC_BGEZALL offset) 843 (if (ge rs 0) 844 (sequence () 845 (set (reg h-gr 31) (add pc 8)) 846 (delay 1 (set pc offset))) 847 (skip 1)) 848 ()) 849 850(dni bgezl "branch if greater or equal to zero likely" (USES-RS) 851 "bgezl $rs,$offset" 852 (+ OP_REGIMM rs FUNC_BGEZL offset) 853 (if (ge rs 0) 854 (delay 1 (set pc offset)) 855 (skip 1)) 856 ()) 857 858(dni bltz "branch if less than zero" (USES-RS) 859 "bltz $rs,$offset" 860 (+ OP_REGIMM rs FUNC_BLTZ offset) 861 (if (lt rs 0) 862 (delay 1 (set pc offset))) 863 ()) 864 865(dni bltzl "branch if less than zero likely" (USES-RS) 866 "bltzl $rs,$offset" 867 (+ OP_REGIMM rs FUNC_BLTZL offset) 868 (if (lt rs 0) 869 (delay 1 (set pc offset)) 870 (skip 1)) 871 ()) 872 873(dni bltzal "branch if less than zero and link" (USES-RS USES-R31) 874 "bltzal $rs,$offset" 875 (+ OP_REGIMM rs FUNC_BLTZAL offset) 876 (if (lt rs 0) 877 (sequence () 878 (set (reg h-gr 31) (add pc 8)) 879 (delay 1 (set pc offset)))) 880 ()) 881 882(dni bltzall "branch if less than zero and link likely" (USES-RS USES-R31) 883 "bltzall $rs,$offset" 884 (+ OP_REGIMM rs FUNC_BLTZALL offset) 885 (if (lt rs 0) 886 (sequence () 887 (set (reg h-gr 31) (add pc 8)) 888 (delay 1 (set pc offset))) 889 (skip 1)) 890 ()) 891 892(dni bmb0 "branch if matching byte-lane 0" (USES-RS USES-RT) 893 "bmb0 $rs,$rt,$offset" 894 (+ OP_BMB0 rs rt offset) 895 (if (eq (and rs #xFF) (and rt #xFF)) 896 (delay 1 (set pc offset))) 897 ()) 898 899(dni bmb1 "branch if matching byte-lane 1" (USES-RS USES-RT) 900 "bmb1 $rs,$rt,$offset" 901 (+ OP_BMB1 rs rt offset) 902 (if (eq (and rs #xFF00) (and rt #xFF00)) 903 (delay 1 (set pc offset))) 904 ()) 905 906(dni bmb2 "branch if matching byte-lane 2" (USES-RS USES-RT) 907 "bmb2 $rs,$rt,$offset" 908 (+ OP_BMB2 rs rt offset) 909 (if (eq (and rs #xFF0000) (and rt #xFF0000)) 910 (delay 1 (set pc offset))) 911 ()) 912 913(dni bmb3 "branch if matching byte-lane 3" (USES-RS USES-RT) 914 "bmb3 $rs,$rt,$offset" 915 (+ OP_BMB3 rs rt offset) 916 (if (eq (and rs #xFF000000) (and rt #xFF000000)) 917 (delay 1 (set pc offset))) 918 ()) 919 920(dni bne "branch if not equal" (USES-RS USES-RT) 921 "bne $rs,$rt,$offset" 922 (+ OP_BNE rs rt offset) 923 (if (ne rs rt) 924 (delay 1 (set pc offset))) 925 ()) 926 927(dni bnel "branch if not equal likely" (USES-RS USES-RT) 928 "bnel $rs,$rt,$offset" 929 (+ OP_BNEL rs rt offset) 930 (if (ne rs rt) 931 (delay 1 (set pc offset)) 932 (skip 1)) 933 ()) 934 935 936 937 938; Jump instructions. 939; Might as well jump! 940 941(dni jalr "jump and link register" (USES-RD USES-RS) 942 "jalr $rd,$rs" 943 (+ OP_SPECIAL rs (f-rt 0) rd (f-shamt 0) FUNC_JALR) 944 (delay 1 945 (sequence () 946 (set rd (add pc 8)) 947 (set pc rs))) 948 ()) 949 950(dni jr "jump register" (USES-RS) 951 "jr $rs" 952 (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JR) 953 (delay 1 (set pc rs)) 954 ()) 955 956 957; Load instructions. 958 959(dni lb "load byte" (LOAD-DELAY USES-RS USES-RT) 960 "lb $rt,$lo16($base)" 961 (+ OP_LB base rt lo16) 962 (set rt (ext WI (mem QI (add base (ext SI (trunc HI lo16)))))) 963; (sequence ((SI addr) (SI word)) 964; (set addr (add base lo16)) 965; (set word (mem SI (and addr (inv 3)))) 966; (set word (srl word (sll (and addr 2) 3))) 967; (set rt (ext SI word))) 968 ()) 969 970(dni lbu "load byte unsigned" (LOAD-DELAY USES-RS USES-RT) 971 "lbu $rt,$lo16($base)" 972 (+ OP_LBU base rt lo16) 973 (set rt (zext WI (mem QI (add base (ext SI (trunc HI lo16)))))) 974; (sequence ((SI addr) (SI word)) 975; (set addr (add base lo16)) 976; (set word (mem SI (and addr (inv 3)))) 977; (set rt (srl word (sll (and addr 2) 3)))) 978 ()) 979 980(dni lh "load half word" (LOAD-DELAY USES-RS USES-RT) 981 "lh $rt,$lo16($base)" 982 (+ OP_LH base rt lo16) 983 (set rt (ext WI (mem HI (add base (ext SI (trunc HI lo16)))))) 984; (sequence ((SI addr) (HI word)) 985; (set addr (add base lo16)) 986; (set word (mem SI (and addr (inv 3)))) 987; (set word (srl word (sll (and addr 1) 4))) 988; (set rt (ext SI word))) 989 ()) 990 991(dni lhu "load half word unsigned" (LOAD-DELAY USES-RS USES-RT) 992 "lhu $rt,$lo16($base)" 993 (+ OP_LHU base rt lo16) 994 (set rt (zext WI (mem HI (add base (ext SI (trunc HI lo16)))))) 995; (sequence ((SI addr) (SI word)) 996; (set addr (add base lo16)) 997; (set word (mem SI (and addr (inv 3)))) 998; (set rt (srl word (sll (and addr 1) 4)))) 999 ()) 1000 1001(dni lui "load upper immediate" (USES-RT) 1002 "lui $rt,$hi16" 1003 (+ OP_LUI (f-rs 0) rt hi16) 1004 (set rt (sll hi16 16)) 1005 ()) 1006 1007(dni lw "load word" (LOAD-DELAY USES-RS USES-RT) 1008 "lw $rt,$lo16($base)" 1009 (+ OP_LW base rt lo16) 1010 (set rt (mem SI (add base (ext SI (trunc HI lo16))))) 1011 ()) 1012 1013 1014; Store instructions. 1015 1016(dni sb "store byte" (USES-RS USES-RT) 1017 "sb $rt,$lo16($base)" 1018 (+ OP_SB base rt lo16) 1019 (set (mem QI (add base (ext SI (trunc HI lo16)))) (and QI rt #xFF)) 1020 ()) 1021 1022(dni sh "store half word" (USES-RS USES-RT) 1023 "sh $rt,$lo16($base)" 1024 (+ OP_SH base rt lo16) 1025 (set (mem HI (add base (ext SI (trunc HI lo16)))) (and HI rt #xFFFF)) 1026 ()) 1027 1028(dni sw "store word" (USES-RS USES-RT) 1029 "sw $rt,$lo16($base)" 1030 (+ OP_SW base rt lo16) 1031 (set (mem SI (add base (ext SI (trunc HI lo16)))) rt) 1032 ()) 1033 1034 1035; Special instructions for simulation/debugging 1036(dni break "breakpoint" () 1037 "break" 1038 (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_BREAK) 1039 (c-call VOID "do_break" pc) 1040 ()) 1041 1042(dni syscall "system call" (YIELD-INSN) 1043 "syscall" 1044 (+ OP_SPECIAL execode (f-func 12)) 1045 (c-call VOID "do_syscall") 1046 ()) 1047 1048; Macro instructions, common to iq10 & iq2000 1049 1050(dnmi nop "nop" () 1051 "nop" 1052 (emit sll (rd 0) (rt 0) (shamt 0)) 1053) 1054 1055(dnmi li "load immediate" (USES-RS NO-DIS) 1056 "li $rs,$imm" 1057 (emit ori (rt 0) rs imm) 1058) 1059 1060(dnmi move "move" (USES-RD USES-RT NO-DIS) 1061 "move $rd,$rt" 1062 (emit or rd (rs 0) rt) 1063) 1064 1065(dnmi lb-base-0 "load byte - implied base 0" (USES-RT NO-DIS) 1066 "lb $rt,$lo16" 1067 (emit lb rt lo16 (base 0)) 1068) 1069 1070(dnmi lbu-base-0 "load byte unsigned - implied base 0" (USES-RT NO-DIS) 1071 "lbu $rt,$lo16" 1072 (emit lbu rt lo16 (base 0)) 1073) 1074 1075(dnmi lh-base-0 "load half - implied base 0" (USES-RT NO-DIS) 1076 "lh $rt,$lo16" 1077 (emit lh rt lo16 (base 0)) 1078) 1079 1080(dnmi lw-base-0 "load word - implied base 0" (USES-RT NO-DIS) 1081 "lw $rt,$lo16" 1082 (emit lw rt lo16 (base 0)) 1083) 1084 1085(dnmi m-add "add immediate" (USES-RS USES-RT NO-DIS) 1086 "add $rt,$rs,$lo16" 1087 (emit addi rt rs lo16)) 1088 1089(dnmi m-addu "add immediate unsigned" (USES-RS USES-RT NO-DIS) 1090 "addu $rt,$rs,$lo16" 1091 (emit addiu rt rs lo16) 1092) 1093 1094(dnmi m-and "and immediate" (USES-RS USES-RT NO-DIS) 1095 "and $rt,$rs,$lo16" 1096 (emit andi rt rs lo16) 1097) 1098 1099(dnmi m-j "jump register" (USES-RS NO-DIS) 1100 "j $rs" 1101 (emit jr rs) 1102) 1103 1104(dnmi m-or "or immediate" (USES-RS USES-RT NO-DIS) 1105 "or $rt,$rs,$lo16" 1106 (emit ori rt rs lo16) 1107) 1108 1109(dnmi m-sll "shift left logical" (USES-RD USES-RT USES-RS NO-DIS) 1110 "sll $rd,$rt,$rs" 1111 (emit sllv rd rt rs) 1112) 1113 1114(dnmi m-slt "slt immediate" (USES-RS USES-RT NO-DIS) 1115 "slt $rt,$rs,$imm" 1116 (emit slti rt rs imm) 1117) 1118 1119(dnmi m-sltu "sltu immediate" (USES-RS USES-RT NO-DIS) 1120 "sltu $rt,$rs,$imm" 1121 (emit sltiu rt rs imm) 1122) 1123 1124(dnmi m-sra "shift right arithmetic" (USES-RD USES-RT USES-RS NO-DIS) 1125 "sra $rd,$rt,$rs" 1126 (emit srav rd rt rs) 1127) 1128 1129(dnmi m-srl "shift right logical" (USES-RD USES-RT USES-RS NO-DIS) 1130 "srl $rd,$rt,$rs" 1131 (emit srlv rd rt rs) 1132) 1133 1134(dnmi not "not" (USES-RD USES-RT NO-DIS) 1135 "not $rd,$rt" 1136 (emit nor rd (rs 0) rt) 1137) 1138 1139(dnmi subi "sub immediate" (USES-RS USES-RT NO-DIS) 1140 "subi $rt,$rs,$mlo16" 1141 (emit addiu rt rs mlo16) 1142) 1143 1144(dnmi m-sub "subtract immediate" (USES-RS USES-RT NO-DIS) 1145 "sub $rt,$rs,$mlo16" 1146 (emit addiu rt rs mlo16) 1147) 1148 1149(dnmi m-subu "subtract unsigned" (USES-RS USES-RT NO-DIS) 1150 "subu $rt,$rs,$mlo16" 1151 (emit addiu rt rs mlo16) 1152) 1153 1154(dnmi sb-base-0 "store byte - implied base 0" (USES-RT NO-DIS) 1155 "sb $rt,$lo16" 1156 (emit sb rt lo16 (base 0)) 1157) 1158 1159(dnmi sh-base-0 "store half - implied base 0" (USES-RT NO-DIS) 1160 "sh $rt,$lo16" 1161 (emit sh rt lo16 (base 0)) 1162) 1163 1164(dnmi sw-base-0 "store word - implied base 0" (USES-RT NO-DIS) 1165 "sw $rt,$lo16" 1166 (emit sw rt lo16 (base 0)) 1167) 1168 1169(dnmi m-xor "xor immediate" (USES-RS USES-RT NO-DIS) 1170 "xor $rt,$rs,$lo16" 1171 (emit xori rt rs lo16) 1172) 1173 1174 1175(if (keep-mach? (iq2000)) 1176(include "../../cpu/iq2000m.cpu")) 1177 1178(if (keep-mach? (iq10)) 1179(include "../../cpu/iq10.cpu")) 1180 1181 1182 1183