1 /* tc-i386.h -- Header file for tc-i386.c 2 Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 21 02110-1301, USA. */ 22 23 #ifndef TC_I386 24 #define TC_I386 1 25 26 struct fix; 27 28 #define TARGET_BYTES_BIG_ENDIAN 0 29 30 #define TARGET_ARCH bfd_arch_i386 31 #define TARGET_MACH (i386_mach ()) 32 extern unsigned long i386_mach (void); 33 34 #ifdef TE_FreeBSD 35 #define AOUT_TARGET_FORMAT "a.out-i386-freebsd" 36 #endif 37 #if defined(TE_NetBSD) || defined(TE_OpenBSD) 38 #define AOUT_TARGET_FORMAT "a.out-i386-netbsd" 39 #endif 40 #ifdef TE_386BSD 41 #define AOUT_TARGET_FORMAT "a.out-i386-bsd" 42 #endif 43 #ifdef TE_LINUX 44 #define AOUT_TARGET_FORMAT "a.out-i386-linux" 45 #endif 46 #ifdef TE_Mach 47 #define AOUT_TARGET_FORMAT "a.out-mach3" 48 #endif 49 #ifdef TE_DYNIX 50 #define AOUT_TARGET_FORMAT "a.out-i386-dynix" 51 #endif 52 #ifndef AOUT_TARGET_FORMAT 53 #define AOUT_TARGET_FORMAT "a.out-i386" 54 #endif 55 56 #ifdef TE_FreeBSD 57 #define ELF_TARGET_FORMAT "elf32-i386-freebsd" 58 #elif defined (TE_VXWORKS) 59 #define ELF_TARGET_FORMAT "elf32-i386-vxworks" 60 #endif 61 62 #ifndef ELF_TARGET_FORMAT 63 #define ELF_TARGET_FORMAT "elf32-i386" 64 #endif 65 66 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 67 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 68 extern const char *i386_target_format PARAMS ((void)); 69 #define TARGET_FORMAT i386_target_format () 70 #else 71 #ifdef OBJ_ELF 72 #define TARGET_FORMAT ELF_TARGET_FORMAT 73 #endif 74 #ifdef OBJ_AOUT 75 #define TARGET_FORMAT AOUT_TARGET_FORMAT 76 #endif 77 #endif 78 79 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)) 80 #define md_end i386_elf_emit_arch_note 81 extern void i386_elf_emit_arch_note PARAMS ((void)); 82 #endif 83 84 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 85 86 #define LOCAL_LABELS_FB 1 87 88 extern const char extra_symbol_chars[]; 89 #define tc_symbol_chars extra_symbol_chars 90 91 extern const char *i386_comment_chars; 92 #define tc_comment_chars i386_comment_chars 93 94 #define MAX_OPERANDS 3 /* max operands per insn */ 95 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ 96 #define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ 97 98 /* Prefixes will be emitted in the order defined below. 99 WAIT_PREFIX must be the first prefix since FWAIT is really is an 100 instruction, and so must come before any prefixes. */ 101 #define WAIT_PREFIX 0 102 #define LOCKREP_PREFIX 1 103 #define ADDR_PREFIX 2 104 #define DATA_PREFIX 3 105 #define SEG_PREFIX 4 106 #define REX_PREFIX 5 /* must come last. */ 107 #define MAX_PREFIXES 6 /* max prefixes per opcode */ 108 109 /* we define the syntax here (modulo base,index,scale syntax) */ 110 #define REGISTER_PREFIX '%' 111 #define IMMEDIATE_PREFIX '$' 112 #define ABSOLUTE_PREFIX '*' 113 114 #define TWO_BYTE_OPCODE_ESCAPE 0x0f 115 #define NOP_OPCODE (char) 0x90 116 117 /* register numbers */ 118 #define EBP_REG_NUM 5 119 #define ESP_REG_NUM 4 120 121 /* modrm_byte.regmem for twobyte escape */ 122 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM 123 /* index_base_byte.index for no index register addressing */ 124 #define NO_INDEX_REGISTER ESP_REG_NUM 125 /* index_base_byte.base for no base register addressing */ 126 #define NO_BASE_REGISTER EBP_REG_NUM 127 #define NO_BASE_REGISTER_16 6 128 129 /* these are the instruction mnemonic suffixes. */ 130 #define WORD_MNEM_SUFFIX 'w' 131 #define BYTE_MNEM_SUFFIX 'b' 132 #define SHORT_MNEM_SUFFIX 's' 133 #define LONG_MNEM_SUFFIX 'l' 134 #define QWORD_MNEM_SUFFIX 'q' 135 /* Intel Syntax */ 136 #define LONG_DOUBLE_MNEM_SUFFIX 'x' 137 138 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ 139 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ 140 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) 141 142 #define END_OF_INSN '\0' 143 144 typedef struct 145 { 146 /* instruction name sans width suffix ("mov" for movl insns) */ 147 char *name; 148 149 /* how many operands */ 150 unsigned int operands; 151 152 /* base_opcode is the fundamental opcode byte without optional 153 prefix(es). */ 154 unsigned int base_opcode; 155 156 /* extension_opcode is the 3 bit extension for group <n> insns. 157 This field is also used to store the 8-bit opcode suffix for the 158 AMD 3DNow! instructions. 159 If this template has no extension opcode (the usual case) use None */ 160 unsigned int extension_opcode; 161 #define None 0xffff /* If no extension_opcode is possible. */ 162 163 /* cpu feature flags */ 164 unsigned int cpu_flags; 165 #define Cpu086 0x1 /* Any old cpu will do, 0 does the same */ 166 #define Cpu186 0x2 /* i186 or better required */ 167 #define Cpu286 0x4 /* i286 or better required */ 168 #define Cpu386 0x8 /* i386 or better required */ 169 #define Cpu486 0x10 /* i486 or better required */ 170 #define Cpu586 0x20 /* i585 or better required */ 171 #define Cpu686 0x40 /* i686 or better required */ 172 #define CpuP4 0x80 /* Pentium4 or better required */ 173 #define CpuK6 0x100 /* AMD K6 or better required*/ 174 #define CpuAthlon 0x200 /* AMD Athlon or better required*/ 175 #define CpuSledgehammer 0x400 /* Sledgehammer or better required */ 176 #define CpuMMX 0x800 /* MMX support required */ 177 #define CpuMMX2 0x1000 /* extended MMX support (with SSE or 3DNow!Ext) required */ 178 #define CpuSSE 0x2000 /* Streaming SIMD extensions required */ 179 #define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */ 180 #define Cpu3dnow 0x8000 /* 3dnow! support required */ 181 #define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */ 182 #define CpuSSE3 0x20000 /* Streaming SIMD extensions 3 required */ 183 #define CpuPNI CpuSSE3 /* Prescott New Instructions required */ 184 #define CpuPadLock 0x40000 /* VIA PadLock required */ 185 #define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */ 186 #define CpuVMX 0x100000 /* VMX Instructions required */ 187 #define CpuMNI 0x200000 /* Merom New Instructions required */ 188 #define CpuXSAVE 0x400000 /* XSAVE Instructions required */ 189 #define CpuAES 0x800000 /* Intel AES extensions required */ 190 #define CpuPCLMUL 0x1000000 /* Intel Carry-less Multiplication extensions */ 191 #define CpuNEW 0x2000000 /* Generic "new" ops w/o encoding hacks */ 192 #define CpuSMAP 0x4000000 /* Intel Supervisor Mode Access Prevention */ 193 194 /* These flags are set by gas depending on the flag_code. */ 195 #define Cpu64 0x8000000 /* 64bit support required */ 196 #define CpuNo64 0x10000000 /* Not supported in the 64bit mode */ 197 198 /* The default value for unknown CPUs - enable all features to avoid problems. */ 199 #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ 200 |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \ 201 |Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME|CpuMNI \ 202 |CpuXSAVE|CpuAES|CpuPCLMUL|CpuNEW|CpuSMAP) 203 204 /* the bits in opcode_modifier are used to generate the final opcode from 205 the base_opcode. These bits also are used to detect alternate forms of 206 the same instruction */ 207 unsigned int opcode_modifier; 208 209 /* opcode_modifier bits: */ 210 #define W 0x1 /* set if operands can be words or dwords 211 encoded the canonical way */ 212 #define D 0x2 /* D = 0 if Reg --> Regmem; 213 D = 1 if Regmem --> Reg: MUST BE 0x2 */ 214 #define Modrm 0x4 215 #define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ 216 #define ShortForm 0x10 /* register is in low 3 bits of opcode */ 217 #define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ 218 #define Jump 0x40 /* special case for jump insns. */ 219 #define JumpDword 0x80 /* call and jump */ 220 #define JumpByte 0x100 /* loop and jecxz */ 221 #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ 222 #define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ 223 #define Seg2ShortForm 0x800 /* encoding of load segment reg insns */ 224 #define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ 225 #define Size16 0x2000 /* needs size prefix if in 32-bit mode */ 226 #define Size32 0x4000 /* needs size prefix if in 16-bit mode */ 227 #define Size64 0x8000 /* needs size prefix if in 16-bit mode */ 228 #define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ 229 #define DefaultSize 0x20000 /* default insn size depends on mode */ 230 #define No_bSuf 0x40000 /* b suffix on instruction illegal */ 231 #define No_wSuf 0x80000 /* w suffix on instruction illegal */ 232 #define No_lSuf 0x100000 /* l suffix on instruction illegal */ 233 #define No_sSuf 0x200000 /* s suffix on instruction illegal */ 234 #define No_qSuf 0x400000 /* q suffix on instruction illegal */ 235 #define No_xSuf 0x800000 /* x suffix on instruction illegal */ 236 #define FWait 0x1000000 /* instruction needs FWAIT */ 237 #define IsString 0x2000000 /* quick test for string instructions */ 238 #define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ 239 #define IsPrefix 0x8000000 /* opcode is a prefix */ 240 #define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ 241 #define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ 242 #define Rex64 0x40000000 /* instruction require Rex64 prefix. */ 243 #define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ 244 245 /* operand_types[i] describes the type of operand i. This is made 246 by OR'ing together all of the possible type masks. (e.g. 247 'operand_types[i] = Reg|Imm' specifies that operand i can be 248 either a register or an immediate operand. */ 249 unsigned int operand_types[3]; 250 251 /* operand_types[i] bits */ 252 /* register */ 253 #define Reg8 0x1 /* 8 bit reg */ 254 #define Reg16 0x2 /* 16 bit reg */ 255 #define Reg32 0x4 /* 32 bit reg */ 256 #define Reg64 0x8 /* 64 bit reg */ 257 /* immediate */ 258 #define Imm8 0x10 /* 8 bit immediate */ 259 #define Imm8S 0x20 /* 8 bit immediate sign extended */ 260 #define Imm16 0x40 /* 16 bit immediate */ 261 #define Imm32 0x80 /* 32 bit immediate */ 262 #define Imm32S 0x100 /* 32 bit immediate sign extended */ 263 #define Imm64 0x200 /* 64 bit immediate */ 264 #define Imm1 0x400 /* 1 bit immediate */ 265 /* memory */ 266 #define BaseIndex 0x800 267 /* Disp8,16,32 are used in different ways, depending on the 268 instruction. For jumps, they specify the size of the PC relative 269 displacement, for baseindex type instructions, they specify the 270 size of the offset relative to the base register, and for memory 271 offset instructions such as `mov 1234,%al' they specify the size of 272 the offset relative to the segment base. */ 273 #define Disp8 0x1000 /* 8 bit displacement */ 274 #define Disp16 0x2000 /* 16 bit displacement */ 275 #define Disp32 0x4000 /* 32 bit displacement */ 276 #define Disp32S 0x8000 /* 32 bit signed displacement */ 277 #define Disp64 0x10000 /* 64 bit displacement */ 278 /* specials */ 279 #define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ 280 #define ShiftCount 0x40000 /* register to hold shift cound = cl */ 281 #define Control 0x80000 /* Control register */ 282 #define Debug 0x100000 /* Debug register */ 283 #define Test 0x200000 /* Test register */ 284 #define FloatReg 0x400000 /* Float register */ 285 #define FloatAcc 0x800000 /* Float stack top %st(0) */ 286 #define SReg2 0x1000000 /* 2 bit segment register */ 287 #define SReg3 0x2000000 /* 3 bit segment register */ 288 #define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ 289 #define JumpAbsolute 0x8000000 290 #define RegMMX 0x10000000 /* MMX register */ 291 #define RegXMM 0x20000000 /* XMM registers in PIII */ 292 #define EsSeg 0x40000000 /* String insn operand with fixed es segment */ 293 294 /* InvMem is for instructions with a modrm byte that only allow a 295 general register encoding in the i.tm.mode and i.tm.regmem fields, 296 eg. control reg moves. They really ought to support a memory form, 297 but don't, so we add an InvMem flag to the register operand to 298 indicate that it should be encoded in the i.tm.regmem field. */ 299 #define InvMem 0x80000000 300 301 #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ 302 #define WordReg (Reg16|Reg32|Reg64) 303 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) 304 #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ 305 #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ 306 #define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ 307 #define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ 308 /* The following aliases are defined because the opcode table 309 carefully specifies the allowed memory types for each instruction. 310 At the moment we can only tell a memory reference size by the 311 instruction suffix, so there's not much point in defining Mem8, 312 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use 313 the suffix directly to check memory operands. */ 314 #define LLongMem AnyMem /* 64 bits (or more) */ 315 #define LongMem AnyMem /* 32 bit memory ref */ 316 #define ShortMem AnyMem /* 16 bit memory ref */ 317 #define WordMem AnyMem /* 16 or 32 bit memory ref */ 318 #define ByteMem AnyMem /* 8 bit memory ref */ 319 } 320 template; 321 322 /* 323 'templates' is for grouping together 'template' structures for opcodes 324 of the same name. This is only used for storing the insns in the grand 325 ole hash table of insns. 326 The templates themselves start at START and range up to (but not including) 327 END. 328 */ 329 typedef struct 330 { 331 const template *start; 332 const template *end; 333 } 334 templates; 335 336 /* these are for register name --> number & type hash lookup */ 337 typedef struct 338 { 339 char *reg_name; 340 unsigned int reg_type; 341 unsigned int reg_flags; 342 #define RegRex 0x1 /* Extended register. */ 343 #define RegRex64 0x2 /* Extended 8 bit register. */ 344 unsigned int reg_num; 345 } 346 reg_entry; 347 348 typedef struct 349 { 350 char *seg_name; 351 unsigned int seg_prefix; 352 } 353 seg_entry; 354 355 /* 386 operand encoding bytes: see 386 book for details of this. */ 356 typedef struct 357 { 358 unsigned int regmem; /* codes register or memory operand */ 359 unsigned int reg; /* codes register operand (or extended opcode) */ 360 unsigned int mode; /* how to interpret regmem & reg */ 361 } 362 modrm_byte; 363 364 /* x86-64 extension prefix. */ 365 typedef int rex_byte; 366 #define REX_OPCODE 0x40 367 368 /* Indicates 64 bit operand size. */ 369 #define REX_MODE64 8 370 /* High extension to reg field of modrm byte. */ 371 #define REX_EXTX 4 372 /* High extension to SIB index field. */ 373 #define REX_EXTY 2 374 /* High extension to base field of modrm or SIB, or reg field of opcode. */ 375 #define REX_EXTZ 1 376 377 /* 386 opcode byte to code indirect addressing. */ 378 typedef struct 379 { 380 unsigned base; 381 unsigned index; 382 unsigned scale; 383 } 384 sib_byte; 385 386 /* x86 arch names and features */ 387 typedef struct 388 { 389 const char *name; /* arch name */ 390 unsigned int flags; /* cpu feature flags */ 391 } 392 arch_entry; 393 394 /* The name of the global offset table generated by the compiler. Allow 395 this to be overridden if need be. */ 396 #ifndef GLOBAL_OFFSET_TABLE_NAME 397 #ifdef OBJ_ELF 398 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" 399 #else 400 #define GLOBAL_OFFSET_TABLE_NAME "__GLOBAL_OFFSET_TABLE_" 401 #endif 402 #endif 403 404 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT) 405 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES) 406 extern void x86_cons PARAMS ((expressionS *, int)); 407 #endif 408 409 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP) 410 extern void x86_cons_fix_new 411 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *)); 412 413 #define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ 414 415 #define NO_RELOC BFD_RELOC_NONE 416 417 void i386_validate_fix PARAMS ((struct fix *)); 418 #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX) 419 420 #define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) 421 extern int tc_i386_fix_adjustable PARAMS ((struct fix *)); 422 423 /* Values passed to md_apply_fix don't include the symbol value. */ 424 #define MD_APPLY_SYM_VALUE(FIX) 0 425 426 /* ELF wants external syms kept, as does PE COFF. */ 427 #if defined (TE_PE) && defined (STRICT_PE_FORMAT) 428 #define EXTERN_FORCE_RELOC \ 429 (OUTPUT_FLAVOR == bfd_target_elf_flavour \ 430 || OUTPUT_FLAVOR == bfd_target_coff_flavour) 431 #else 432 #define EXTERN_FORCE_RELOC \ 433 (OUTPUT_FLAVOR == bfd_target_elf_flavour) 434 #endif 435 436 /* This expression evaluates to true if the relocation is for a local 437 object for which we still want to do the relocation at runtime. 438 False if we are willing to perform this relocation while building 439 the .o file. GOTOFF does not need to be checked here because it is 440 not pcrel. I am not sure if some of the others are ever used with 441 pcrel, but it is easier to be safe than sorry. */ 442 443 #define TC_FORCE_RELOCATION_LOCAL(FIX) \ 444 (!(FIX)->fx_pcrel \ 445 || (FIX)->fx_plt \ 446 || (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \ 447 || (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \ 448 || (FIX)->fx_r_type == BFD_RELOC_386_GOT32X \ 449 || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \ 450 || (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCREL \ 451 || TC_FORCE_RELOCATION (FIX)) 452 453 extern int i386_parse_name (char *, expressionS *, char *); 454 #define md_parse_name(s, e, m, c) i386_parse_name (s, e, c) 455 456 extern const struct relax_type md_relax_table[]; 457 #define TC_GENERIC_RELAX_TABLE md_relax_table 458 459 extern int optimize_align_code; 460 461 #define md_do_align(n, fill, len, max, around) \ 462 if ((n) \ 463 && !need_pass_2 \ 464 && optimize_align_code \ 465 && (!(fill) \ 466 || ((char)*(fill) == (char)0x90 && (len) == 1)) \ 467 && subseg_text_p (now_seg)) \ 468 { \ 469 frag_align_code ((n), (max)); \ 470 goto around; \ 471 } 472 473 #define MAX_MEM_FOR_RS_ALIGN_CODE 15 474 475 extern void i386_align_code PARAMS ((fragS *, int)); 476 477 #define HANDLE_ALIGN(fragP) \ 478 if (fragP->fr_type == rs_align_code) \ 479 i386_align_code (fragP, (fragP->fr_next->fr_address \ 480 - fragP->fr_address \ 481 - fragP->fr_fix)); 482 483 void i386_print_statistics PARAMS ((FILE *)); 484 #define tc_print_statistics i386_print_statistics 485 486 #define md_number_to_chars number_to_chars_littleendian 487 488 #ifdef SCO_ELF 489 #define tc_init_after_args() sco_id () 490 extern void sco_id PARAMS ((void)); 491 #endif 492 493 /* We want .cfi_* pseudo-ops for generating unwind info. */ 494 #define TARGET_USE_CFIPOP 1 495 496 extern unsigned int x86_dwarf2_return_column; 497 #define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column 498 499 extern int x86_cie_data_alignment; 500 #define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment 501 502 #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum 503 extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname)); 504 505 #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions 506 extern void tc_x86_frame_initial_instructions PARAMS ((void)); 507 508 #define md_elf_section_type(str,len) i386_elf_section_type (str, len) 509 extern int i386_elf_section_type PARAMS ((const char *, size_t len)); 510 511 /* Support for SHF_X86_64_LARGE */ 512 extern int x86_64_section_word PARAMS ((char *, size_t)); 513 extern int x86_64_section_letter PARAMS ((int letter, char **ptr_msg)); 514 #define md_elf_section_letter(LETTER, PTR_MSG) x86_64_section_letter (LETTER, PTR_MSG) 515 #define md_elf_section_word(STR, LEN) x86_64_section_word (STR, LEN) 516 517 #ifdef TE_PE 518 519 #define O_secrel O_md1 520 521 #define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset 522 void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int); 523 524 #endif /* TE_PE */ 525 526 #endif /* TC_I386 */ 527