1 /* tc-sparc.c -- Assemble for the SPARC 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004, 2005 4 Free Software Foundation, Inc. 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public 18 License along with GAS; see the file COPYING. If not, write 19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 #include <stdio.h> 23 24 #include "as.h" 25 #include "safe-ctype.h" 26 #include "subsegs.h" 27 28 #include "opcode/sparc.h" 29 #include "dw2gencfi.h" 30 31 #ifdef OBJ_ELF 32 #include "elf/sparc.h" 33 #include "dwarf2dbg.h" 34 #endif 35 36 /* Some ancient Sun C compilers would not take such hex constants as 37 unsigned, and would end up sign-extending them to form an offsetT, 38 so use these constants instead. */ 39 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) 40 #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) 41 42 static struct sparc_arch *lookup_arch PARAMS ((char *)); 43 static void init_default_arch PARAMS ((void)); 44 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **)); 45 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 46 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 47 static int sparc_ffs PARAMS ((unsigned int)); 48 static void synthetize_setuw PARAMS ((const struct sparc_opcode *)); 49 static void synthetize_setsw PARAMS ((const struct sparc_opcode *)); 50 static void synthetize_setx PARAMS ((const struct sparc_opcode *)); 51 static bfd_vma BSR PARAMS ((bfd_vma, int)); 52 static int cmp_reg_entry PARAMS ((const PTR, const PTR)); 53 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *)); 54 static int parse_const_expr_arg PARAMS ((char **, int *)); 55 static int get_expression PARAMS ((char *str)); 56 57 /* Default architecture. */ 58 /* ??? The default value should be V8, but sparclite support was added 59 by making it the default. GCC now passes -Asparclite, so maybe sometime in 60 the future we can set this to V8. */ 61 #ifndef DEFAULT_ARCH 62 #define DEFAULT_ARCH "sparclite" 63 #endif 64 static char *default_arch = DEFAULT_ARCH; 65 66 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 67 have been set. */ 68 static int default_init_p; 69 70 /* Current architecture. We don't bump up unless necessary. */ 71 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 72 73 /* The maximum architecture level we can bump up to. 74 In a 32 bit environment, don't allow bumping up to v9 by default. 75 The native assembler works this way. The user is required to pass 76 an explicit argument before we'll create v9 object files. However, if 77 we don't see any v9 insns, a v8plus object file is not created. */ 78 static enum sparc_opcode_arch_val max_architecture; 79 80 /* Either 32 or 64, selects file format. */ 81 static int sparc_arch_size; 82 /* Initial (default) value, recorded separately in case a user option 83 changes the value before md_show_usage is called. */ 84 static int default_arch_size; 85 86 #ifdef OBJ_ELF 87 /* The currently selected v9 memory model. Currently only used for 88 ELF. */ 89 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 90 #endif 91 92 static int architecture_requested; 93 static int warn_on_bump; 94 95 /* If warn_on_bump and the needed architecture is higher than this 96 architecture, issue a warning. */ 97 static enum sparc_opcode_arch_val warn_after_architecture; 98 99 /* Non-zero if as should generate error if an undeclared g[23] register 100 has been used in -64. */ 101 static int no_undeclared_regs; 102 103 /* Non-zero if we should try to relax jumps and calls. */ 104 static int sparc_relax; 105 106 /* Non-zero if we are generating PIC code. */ 107 int sparc_pic_code; 108 109 /* Non-zero if we should give an error when misaligned data is seen. */ 110 static int enforce_aligned_data; 111 112 extern int target_big_endian; 113 114 static int target_little_endian_data; 115 116 /* Symbols for global registers on v9. */ 117 static symbolS *globals[8]; 118 119 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 120 int sparc_cie_data_alignment; 121 122 /* V9 and 86x have big and little endian data, but instructions are always big 123 endian. The sparclet has bi-endian support but both data and insns have 124 the same endianness. Global `target_big_endian' is used for data. 125 The following macro is used for instructions. */ 126 #ifndef INSN_BIG_ENDIAN 127 #define INSN_BIG_ENDIAN (target_big_endian \ 128 || default_arch_type == sparc86x \ 129 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 130 #endif 131 132 /* Handle of the OPCODE hash table. */ 133 static struct hash_control *op_hash; 134 135 static int mylog2 PARAMS ((int)); 136 static void s_data1 PARAMS ((void)); 137 static void s_seg PARAMS ((int)); 138 static void s_proc PARAMS ((int)); 139 static void s_reserve PARAMS ((int)); 140 static void s_common PARAMS ((int)); 141 static void s_empty PARAMS ((int)); 142 static void s_uacons PARAMS ((int)); 143 static void s_ncons PARAMS ((int)); 144 #ifdef OBJ_ELF 145 static void s_register PARAMS ((int)); 146 #endif 147 148 const pseudo_typeS md_pseudo_table[] = 149 { 150 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 151 {"common", s_common, 0}, 152 {"empty", s_empty, 0}, 153 {"global", s_globl, 0}, 154 {"half", cons, 2}, 155 {"nword", s_ncons, 0}, 156 {"optim", s_ignore, 0}, 157 {"proc", s_proc, 0}, 158 {"reserve", s_reserve, 0}, 159 {"seg", s_seg, 0}, 160 {"skip", s_space, 0}, 161 {"word", cons, 4}, 162 {"xword", cons, 8}, 163 {"uahalf", s_uacons, 2}, 164 {"uaword", s_uacons, 4}, 165 {"uaxword", s_uacons, 8}, 166 #ifdef OBJ_ELF 167 /* These are specific to sparc/svr4. */ 168 {"2byte", s_uacons, 2}, 169 {"4byte", s_uacons, 4}, 170 {"8byte", s_uacons, 8}, 171 {"register", s_register, 0}, 172 #endif 173 {NULL, 0, 0}, 174 }; 175 176 /* This array holds the chars that always start a comment. If the 177 pre-processor is disabled, these aren't very useful. */ 178 const char comment_chars[] = "!"; /* JF removed '|' from 179 comment_chars. */ 180 181 /* This array holds the chars that only start a comment at the beginning of 182 a line. If the line seems to have the form '# 123 filename' 183 .line and .file directives will appear in the pre-processed output. */ 184 /* Note that input_file.c hand checks for '#' at the beginning of the 185 first line of the input file. This is because the compiler outputs 186 #NO_APP at the beginning of its output. */ 187 /* Also note that comments started like this one will always 188 work if '/' isn't otherwise defined. */ 189 const char line_comment_chars[] = "#"; 190 191 const char line_separator_chars[] = ";"; 192 193 /* Chars that can be used to separate mant from exp in floating point 194 nums. */ 195 const char EXP_CHARS[] = "eE"; 196 197 /* Chars that mean this number is a floating point constant. 198 As in 0f12.456 199 or 0d1.2345e12 */ 200 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 201 202 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 203 changed in read.c. Ideally it shouldn't have to know about it at all, 204 but nothing is ideal around here. */ 205 206 #define isoctal(c) ((unsigned) ((c) - '0') < 8) 207 208 struct sparc_it 209 { 210 char *error; 211 unsigned long opcode; 212 struct nlist *nlistp; 213 expressionS exp; 214 expressionS exp2; 215 int pcrel; 216 bfd_reloc_code_real_type reloc; 217 }; 218 219 struct sparc_it the_insn, set_insn; 220 221 static void output_insn 222 PARAMS ((const struct sparc_opcode *, struct sparc_it *)); 223 224 /* Table of arguments to -A. 225 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 226 for this use. That table is for opcodes only. This table is for opcodes 227 and file formats. */ 228 229 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, 230 v8plusa, v9, v9a, v9b, v9_64}; 231 232 static struct sparc_arch { 233 char *name; 234 char *opcode_arch; 235 enum sparc_arch_types arch_type; 236 /* Default word size, as specified during configuration. 237 A value of zero means can't be used to specify default architecture. */ 238 int default_arch_size; 239 /* Allowable arg to -A? */ 240 int user_option_p; 241 } sparc_arch_table[] = { 242 { "v6", "v6", v6, 0, 1 }, 243 { "v7", "v7", v7, 0, 1 }, 244 { "v8", "v8", v8, 32, 1 }, 245 { "sparclet", "sparclet", sparclet, 32, 1 }, 246 { "sparclite", "sparclite", sparclite, 32, 1 }, 247 { "sparc86x", "sparclite", sparc86x, 32, 1 }, 248 { "v8plus", "v9", v9, 0, 1 }, 249 { "v8plusa", "v9a", v9, 0, 1 }, 250 { "v8plusb", "v9b", v9, 0, 1 }, 251 { "v9", "v9", v9, 0, 1 }, 252 { "v9a", "v9a", v9, 0, 1 }, 253 { "v9b", "v9b", v9, 0, 1 }, 254 /* This exists to allow configure.in/Makefile.in to pass one 255 value to specify both the default machine and default word size. */ 256 { "v9-64", "v9", v9, 64, 0 }, 257 { NULL, NULL, v8, 0, 0 } 258 }; 259 260 /* Variant of default_arch */ 261 static enum sparc_arch_types default_arch_type; 262 263 static struct sparc_arch * 264 lookup_arch (name) 265 char *name; 266 { 267 struct sparc_arch *sa; 268 269 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 270 if (strcmp (sa->name, name) == 0) 271 break; 272 if (sa->name == NULL) 273 return NULL; 274 return sa; 275 } 276 277 /* Initialize the default opcode arch and word size from the default 278 architecture name. */ 279 280 static void 281 init_default_arch () 282 { 283 struct sparc_arch *sa = lookup_arch (default_arch); 284 285 if (sa == NULL 286 || sa->default_arch_size == 0) 287 as_fatal (_("Invalid default architecture, broken assembler.")); 288 289 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 290 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 291 as_fatal (_("Bad opcode table, broken assembler.")); 292 default_arch_size = sparc_arch_size = sa->default_arch_size; 293 default_init_p = 1; 294 default_arch_type = sa->arch_type; 295 } 296 297 /* Called by TARGET_FORMAT. */ 298 299 const char * 300 sparc_target_format () 301 { 302 /* We don't get a chance to initialize anything before we're called, 303 so handle that now. */ 304 if (! default_init_p) 305 init_default_arch (); 306 307 #ifdef OBJ_AOUT 308 #if defined(TE_NetBSD) || defined(TE_OpenBSD) 309 return "a.out-sparc-netbsd"; 310 #else 311 #ifdef TE_SPARCAOUT 312 if (target_big_endian) 313 return "a.out-sunos-big"; 314 else if (default_arch_type == sparc86x && target_little_endian_data) 315 return "a.out-sunos-big"; 316 else 317 return "a.out-sparc-little"; 318 #else 319 return "a.out-sunos-big"; 320 #endif 321 #endif 322 #endif 323 324 #ifdef OBJ_BOUT 325 return "b.out.big"; 326 #endif 327 328 #ifdef OBJ_COFF 329 #ifdef TE_LYNX 330 return "coff-sparc-lynx"; 331 #else 332 return "coff-sparc"; 333 #endif 334 #endif 335 336 #ifdef TE_VXWORKS 337 return "elf32-sparc-vxworks"; 338 #endif 339 340 #ifdef OBJ_ELF 341 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc"; 342 #endif 343 344 abort (); 345 } 346 347 /* md_parse_option 348 * Invocation line includes a switch not recognized by the base assembler. 349 * See if it's a processor-specific option. These are: 350 * 351 * -bump 352 * Warn on architecture bumps. See also -A. 353 * 354 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet 355 * Standard 32 bit architectures. 356 * -Av9, -Av9a, -Av9b 357 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 358 * This used to only mean 64 bits, but properly specifying it 359 * complicated gcc's ASM_SPECs, so now opcode selection is 360 * specified orthogonally to word size (except when specifying 361 * the default, but that is an internal implementation detail). 362 * -Av8plus, -Av8plusa, -Av8plusb 363 * Same as -Av9{,a,b}. 364 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 365 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 366 * assembler. 367 * -xarch=v9, -xarch=v9a, -xarch=v9b 368 * Same as -Av9{,a,b} -64, for compatibility with Sun's 369 * assembler. 370 * 371 * Select the architecture and possibly the file format. 372 * Instructions or features not supported by the selected 373 * architecture cause fatal errors. 374 * 375 * The default is to start at v6, and bump the architecture up 376 * whenever an instruction is seen at a higher level. In 32 bit 377 * environments, v9 is not bumped up to, the user must pass 378 * -Av8plus{,a,b}. 379 * 380 * If -bump is specified, a warning is printing when bumping to 381 * higher levels. 382 * 383 * If an architecture is specified, all instructions must match 384 * that architecture. Any higher level instructions are flagged 385 * as errors. Note that in the 32 bit environment specifying 386 * -Av8plus does not automatically create a v8plus object file, a 387 * v9 insn must be seen. 388 * 389 * If both an architecture and -bump are specified, the 390 * architecture starts at the specified level, but bumps are 391 * warnings. Note that we can't set `current_architecture' to 392 * the requested level in this case: in the 32 bit environment, 393 * we still must avoid creating v8plus object files unless v9 394 * insns are seen. 395 * 396 * Note: 397 * Bumping between incompatible architectures is always an 398 * error. For example, from sparclite to v9. 399 */ 400 401 #ifdef OBJ_ELF 402 const char *md_shortopts = "A:K:VQ:sq"; 403 #else 404 #ifdef OBJ_AOUT 405 const char *md_shortopts = "A:k"; 406 #else 407 const char *md_shortopts = "A:"; 408 #endif 409 #endif 410 struct option md_longopts[] = { 411 #define OPTION_BUMP (OPTION_MD_BASE) 412 {"bump", no_argument, NULL, OPTION_BUMP}, 413 #define OPTION_SPARC (OPTION_MD_BASE + 1) 414 {"sparc", no_argument, NULL, OPTION_SPARC}, 415 #define OPTION_XARCH (OPTION_MD_BASE + 2) 416 {"xarch", required_argument, NULL, OPTION_XARCH}, 417 #ifdef OBJ_ELF 418 #define OPTION_32 (OPTION_MD_BASE + 3) 419 {"32", no_argument, NULL, OPTION_32}, 420 #define OPTION_64 (OPTION_MD_BASE + 4) 421 {"64", no_argument, NULL, OPTION_64}, 422 #define OPTION_TSO (OPTION_MD_BASE + 5) 423 {"TSO", no_argument, NULL, OPTION_TSO}, 424 #define OPTION_PSO (OPTION_MD_BASE + 6) 425 {"PSO", no_argument, NULL, OPTION_PSO}, 426 #define OPTION_RMO (OPTION_MD_BASE + 7) 427 {"RMO", no_argument, NULL, OPTION_RMO}, 428 #endif 429 #ifdef SPARC_BIENDIAN 430 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 431 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 432 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 433 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 434 #endif 435 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 436 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 437 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 438 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 439 #ifdef OBJ_ELF 440 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 441 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 442 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 443 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 444 #endif 445 #define OPTION_RELAX (OPTION_MD_BASE + 14) 446 {"relax", no_argument, NULL, OPTION_RELAX}, 447 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 448 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 449 {NULL, no_argument, NULL, 0} 450 }; 451 452 size_t md_longopts_size = sizeof (md_longopts); 453 454 int 455 md_parse_option (c, arg) 456 int c; 457 char *arg; 458 { 459 /* We don't get a chance to initialize anything before we're called, 460 so handle that now. */ 461 if (! default_init_p) 462 init_default_arch (); 463 464 switch (c) 465 { 466 case OPTION_BUMP: 467 warn_on_bump = 1; 468 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 469 break; 470 471 case OPTION_XARCH: 472 #ifdef OBJ_ELF 473 if (strncmp (arg, "v9", 2) != 0) 474 md_parse_option (OPTION_32, NULL); 475 else 476 md_parse_option (OPTION_64, NULL); 477 #endif 478 /* Fall through. */ 479 480 case 'A': 481 { 482 struct sparc_arch *sa; 483 enum sparc_opcode_arch_val opcode_arch; 484 485 sa = lookup_arch (arg); 486 if (sa == NULL 487 || ! sa->user_option_p) 488 { 489 if (c == OPTION_XARCH) 490 as_bad (_("invalid architecture -xarch=%s"), arg); 491 else 492 as_bad (_("invalid architecture -A%s"), arg); 493 return 0; 494 } 495 496 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 497 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 498 as_fatal (_("Bad opcode table, broken assembler.")); 499 500 max_architecture = opcode_arch; 501 architecture_requested = 1; 502 } 503 break; 504 505 case OPTION_SPARC: 506 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 507 break; 508 509 case OPTION_ENFORCE_ALIGNED_DATA: 510 enforce_aligned_data = 1; 511 break; 512 513 #ifdef SPARC_BIENDIAN 514 case OPTION_LITTLE_ENDIAN: 515 target_big_endian = 0; 516 if (default_arch_type != sparclet) 517 as_fatal ("This target does not support -EL"); 518 break; 519 case OPTION_LITTLE_ENDIAN_DATA: 520 target_little_endian_data = 1; 521 target_big_endian = 0; 522 if (default_arch_type != sparc86x 523 && default_arch_type != v9) 524 as_fatal ("This target does not support --little-endian-data"); 525 break; 526 case OPTION_BIG_ENDIAN: 527 target_big_endian = 1; 528 break; 529 #endif 530 531 #ifdef OBJ_AOUT 532 case 'k': 533 sparc_pic_code = 1; 534 break; 535 #endif 536 537 #ifdef OBJ_ELF 538 case OPTION_32: 539 case OPTION_64: 540 { 541 const char **list, **l; 542 543 sparc_arch_size = c == OPTION_32 ? 32 : 64; 544 list = bfd_target_list (); 545 for (l = list; *l != NULL; l++) 546 { 547 if (sparc_arch_size == 32) 548 { 549 if (strcmp (*l, "elf32-sparc") == 0) 550 break; 551 } 552 else 553 { 554 if (strcmp (*l, "elf64-sparc") == 0) 555 break; 556 } 557 } 558 if (*l == NULL) 559 as_fatal (_("No compiled in support for %d bit object file format"), 560 sparc_arch_size); 561 free (list); 562 } 563 break; 564 565 case OPTION_TSO: 566 sparc_memory_model = MM_TSO; 567 break; 568 569 case OPTION_PSO: 570 sparc_memory_model = MM_PSO; 571 break; 572 573 case OPTION_RMO: 574 sparc_memory_model = MM_RMO; 575 break; 576 577 case 'V': 578 print_version_id (); 579 break; 580 581 case 'Q': 582 /* Qy - do emit .comment 583 Qn - do not emit .comment. */ 584 break; 585 586 case 's': 587 /* Use .stab instead of .stab.excl. */ 588 break; 589 590 case 'q': 591 /* quick -- Native assembler does fewer checks. */ 592 break; 593 594 case 'K': 595 if (strcmp (arg, "PIC") != 0) 596 as_warn (_("Unrecognized option following -K")); 597 else 598 sparc_pic_code = 1; 599 break; 600 601 case OPTION_NO_UNDECLARED_REGS: 602 no_undeclared_regs = 1; 603 break; 604 605 case OPTION_UNDECLARED_REGS: 606 no_undeclared_regs = 0; 607 break; 608 #endif 609 610 case OPTION_RELAX: 611 sparc_relax = 1; 612 break; 613 614 case OPTION_NO_RELAX: 615 sparc_relax = 0; 616 break; 617 618 default: 619 return 0; 620 } 621 622 return 1; 623 } 624 625 void 626 md_show_usage (stream) 627 FILE *stream; 628 { 629 const struct sparc_arch *arch; 630 int column; 631 632 /* We don't get a chance to initialize anything before we're called, 633 so handle that now. */ 634 if (! default_init_p) 635 init_default_arch (); 636 637 fprintf (stream, _("SPARC options:\n")); 638 column = 0; 639 for (arch = &sparc_arch_table[0]; arch->name; arch++) 640 { 641 if (!arch->user_option_p) 642 continue; 643 if (arch != &sparc_arch_table[0]) 644 fprintf (stream, " | "); 645 if (column + strlen (arch->name) > 70) 646 { 647 column = 0; 648 fputc ('\n', stream); 649 } 650 column += 5 + 2 + strlen (arch->name); 651 fprintf (stream, "-A%s", arch->name); 652 } 653 for (arch = &sparc_arch_table[0]; arch->name; arch++) 654 { 655 if (!arch->user_option_p) 656 continue; 657 fprintf (stream, " | "); 658 if (column + strlen (arch->name) > 65) 659 { 660 column = 0; 661 fputc ('\n', stream); 662 } 663 column += 5 + 7 + strlen (arch->name); 664 fprintf (stream, "-xarch=%s", arch->name); 665 } 666 fprintf (stream, _("\n\ 667 specify variant of SPARC architecture\n\ 668 -bump warn when assembler switches architectures\n\ 669 -sparc ignored\n\ 670 --enforce-aligned-data force .long, etc., to be aligned correctly\n\ 671 -relax relax jumps and branches (default)\n\ 672 -no-relax avoid changing any jumps and branches\n")); 673 #ifdef OBJ_AOUT 674 fprintf (stream, _("\ 675 -k generate PIC\n")); 676 #endif 677 #ifdef OBJ_ELF 678 fprintf (stream, _("\ 679 -32 create 32 bit object file\n\ 680 -64 create 64 bit object file\n")); 681 fprintf (stream, _("\ 682 [default is %d]\n"), default_arch_size); 683 fprintf (stream, _("\ 684 -TSO use Total Store Ordering\n\ 685 -PSO use Partial Store Ordering\n\ 686 -RMO use Relaxed Memory Ordering\n")); 687 fprintf (stream, _("\ 688 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 689 fprintf (stream, _("\ 690 -KPIC generate PIC\n\ 691 -V print assembler version number\n\ 692 -undeclared-regs ignore application global register usage without\n\ 693 appropriate .register directive (default)\n\ 694 -no-undeclared-regs force error on application global register usage\n\ 695 without appropriate .register directive\n\ 696 -q ignored\n\ 697 -Qy, -Qn ignored\n\ 698 -s ignored\n")); 699 #endif 700 #ifdef SPARC_BIENDIAN 701 fprintf (stream, _("\ 702 -EL generate code for a little endian machine\n\ 703 -EB generate code for a big endian machine\n\ 704 --little-endian-data generate code for a machine having big endian\n\ 705 instructions and little endian data.\n")); 706 #endif 707 } 708 709 /* Native operand size opcode translation. */ 710 struct 711 { 712 char *name; 713 char *name32; 714 char *name64; 715 } native_op_table[] = 716 { 717 {"ldn", "ld", "ldx"}, 718 {"ldna", "lda", "ldxa"}, 719 {"stn", "st", "stx"}, 720 {"stna", "sta", "stxa"}, 721 {"slln", "sll", "sllx"}, 722 {"srln", "srl", "srlx"}, 723 {"sran", "sra", "srax"}, 724 {"casn", "cas", "casx"}, 725 {"casna", "casa", "casxa"}, 726 {"clrn", "clr", "clrx"}, 727 {NULL, NULL, NULL}, 728 }; 729 730 /* sparc64 privileged and hyperprivileged registers. */ 731 732 struct priv_reg_entry 733 { 734 char *name; 735 int regnum; 736 }; 737 738 struct priv_reg_entry priv_reg_table[] = 739 { 740 {"tpc", 0}, 741 {"tnpc", 1}, 742 {"tstate", 2}, 743 {"tt", 3}, 744 {"tick", 4}, 745 {"tba", 5}, 746 {"pstate", 6}, 747 {"tl", 7}, 748 {"pil", 8}, 749 {"cwp", 9}, 750 {"cansave", 10}, 751 {"canrestore", 11}, 752 {"cleanwin", 12}, 753 {"otherwin", 13}, 754 {"wstate", 14}, 755 {"fq", 15}, 756 {"gl", 16}, 757 {"ver", 31}, 758 {"", -1}, /* End marker. */ 759 }; 760 761 struct priv_reg_entry hpriv_reg_table[] = 762 { 763 {"hpstate", 0}, 764 {"htstate", 1}, 765 {"hintp", 3}, 766 {"htba", 5}, 767 {"hver", 6}, 768 {"hstick_cmpr", 31}, 769 {"", -1}, /* End marker. */ 770 }; 771 772 /* v9a specific asrs. */ 773 774 struct priv_reg_entry v9a_asr_table[] = 775 { 776 {"tick_cmpr", 23}, 777 {"sys_tick_cmpr", 25}, 778 {"sys_tick", 24}, 779 {"softint", 22}, 780 {"set_softint", 20}, 781 {"pic", 17}, 782 {"pcr", 16}, 783 {"gsr", 19}, 784 {"dcr", 18}, 785 {"clear_softint", 21}, 786 {"", -1}, /* End marker. */ 787 }; 788 789 static int 790 cmp_reg_entry (parg, qarg) 791 const PTR parg; 792 const PTR qarg; 793 { 794 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 795 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 796 797 return strcmp (q->name, p->name); 798 } 799 800 /* This function is called once, at assembler startup time. It should 801 set up all the tables, etc. that the MD part of the assembler will 802 need. */ 803 804 void 805 md_begin () 806 { 807 register const char *retval = NULL; 808 int lose = 0; 809 register unsigned int i = 0; 810 811 /* We don't get a chance to initialize anything before md_parse_option 812 is called, and it may not be called, so handle default initialization 813 now if not already done. */ 814 if (! default_init_p) 815 init_default_arch (); 816 817 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; 818 op_hash = hash_new (); 819 820 while (i < (unsigned int) sparc_num_opcodes) 821 { 822 const char *name = sparc_opcodes[i].name; 823 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]); 824 if (retval != NULL) 825 { 826 as_bad (_("Internal error: can't hash `%s': %s\n"), 827 sparc_opcodes[i].name, retval); 828 lose = 1; 829 } 830 do 831 { 832 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 833 { 834 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 835 sparc_opcodes[i].name, sparc_opcodes[i].args); 836 lose = 1; 837 } 838 ++i; 839 } 840 while (i < (unsigned int) sparc_num_opcodes 841 && !strcmp (sparc_opcodes[i].name, name)); 842 } 843 844 for (i = 0; native_op_table[i].name; i++) 845 { 846 const struct sparc_opcode *insn; 847 char *name = ((sparc_arch_size == 32) 848 ? native_op_table[i].name32 849 : native_op_table[i].name64); 850 insn = (struct sparc_opcode *) hash_find (op_hash, name); 851 if (insn == NULL) 852 { 853 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 854 name, native_op_table[i].name); 855 lose = 1; 856 } 857 else 858 { 859 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn); 860 if (retval != NULL) 861 { 862 as_bad (_("Internal error: can't hash `%s': %s\n"), 863 sparc_opcodes[i].name, retval); 864 lose = 1; 865 } 866 } 867 } 868 869 if (lose) 870 as_fatal (_("Broken assembler. No assembly attempted.")); 871 872 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 873 sizeof (priv_reg_table[0]), cmp_reg_entry); 874 875 /* If -bump, record the architecture level at which we start issuing 876 warnings. The behaviour is different depending upon whether an 877 architecture was explicitly specified. If it wasn't, we issue warnings 878 for all upwards bumps. If it was, we don't start issuing warnings until 879 we need to bump beyond the requested architecture or when we bump between 880 conflicting architectures. */ 881 882 if (warn_on_bump 883 && architecture_requested) 884 { 885 /* `max_architecture' records the requested architecture. 886 Issue warnings if we go above it. */ 887 warn_after_architecture = max_architecture; 888 889 /* Find the highest architecture level that doesn't conflict with 890 the requested one. */ 891 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 892 max_architecture > warn_after_architecture; 893 --max_architecture) 894 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 895 warn_after_architecture)) 896 break; 897 } 898 } 899 900 /* Called after all assembly has been done. */ 901 902 void 903 sparc_md_end () 904 { 905 unsigned long mach = bfd_mach_sparc; 906 907 if (sparc_arch_size == 64) 908 switch (current_architecture) 909 { 910 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 911 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 912 default: mach = bfd_mach_sparc_v9; break; 913 } 914 else 915 switch (current_architecture) 916 { 917 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 918 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 919 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 920 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 921 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 922 be but for now it is (since that's the way it's always been 923 treated). */ 924 default: break; 925 } 926 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 927 } 928 929 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 930 931 static INLINE int 932 in_signed_range (val, max) 933 bfd_signed_vma val, max; 934 { 935 if (max <= 0) 936 abort (); 937 /* Sign-extend the value from the architecture word size, so that 938 0xffffffff is always considered -1 on sparc32. */ 939 if (sparc_arch_size == 32) 940 { 941 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 942 val = ((val & U0xffffffff) ^ sign) - sign; 943 } 944 if (val > max) 945 return 0; 946 if (val < ~max) 947 return 0; 948 return 1; 949 } 950 951 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 952 (e.g. -15 to +31). */ 953 954 static INLINE int 955 in_bitfield_range (val, max) 956 bfd_signed_vma val, max; 957 { 958 if (max <= 0) 959 abort (); 960 if (val > max) 961 return 0; 962 if (val < ~(max >> 1)) 963 return 0; 964 return 1; 965 } 966 967 static int 968 sparc_ffs (mask) 969 unsigned int mask; 970 { 971 int i; 972 973 if (mask == 0) 974 return -1; 975 976 for (i = 0; (mask & 1) == 0; ++i) 977 mask >>= 1; 978 return i; 979 } 980 981 /* Implement big shift right. */ 982 static bfd_vma 983 BSR (val, amount) 984 bfd_vma val; 985 int amount; 986 { 987 if (sizeof (bfd_vma) <= 4 && amount >= 32) 988 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 989 return val >> amount; 990 } 991 992 /* For communication between sparc_ip and get_expression. */ 993 static char *expr_end; 994 995 /* Values for `special_case'. 996 Instructions that require wierd handling because they're longer than 997 4 bytes. */ 998 #define SPECIAL_CASE_NONE 0 999 #define SPECIAL_CASE_SET 1 1000 #define SPECIAL_CASE_SETSW 2 1001 #define SPECIAL_CASE_SETX 3 1002 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 1003 #define SPECIAL_CASE_FDIV 4 1004 1005 /* Bit masks of various insns. */ 1006 #define NOP_INSN 0x01000000 1007 #define OR_INSN 0x80100000 1008 #define XOR_INSN 0x80180000 1009 #define FMOVS_INSN 0x81A00020 1010 #define SETHI_INSN 0x01000000 1011 #define SLLX_INSN 0x81281000 1012 #define SRA_INSN 0x81380000 1013 1014 /* The last instruction to be assembled. */ 1015 static const struct sparc_opcode *last_insn; 1016 /* The assembled opcode of `last_insn'. */ 1017 static unsigned long last_opcode; 1018 1019 /* Handle the set and setuw synthetic instructions. */ 1020 1021 static void 1022 synthetize_setuw (insn) 1023 const struct sparc_opcode *insn; 1024 { 1025 int need_hi22_p = 0; 1026 int rd = (the_insn.opcode & RD (~0)) >> 25; 1027 1028 if (the_insn.exp.X_op == O_constant) 1029 { 1030 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1031 { 1032 if (sizeof (offsetT) > 4 1033 && (the_insn.exp.X_add_number < 0 1034 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1035 as_warn (_("set: number not in 0..4294967295 range")); 1036 } 1037 else 1038 { 1039 if (sizeof (offsetT) > 4 1040 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1041 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1042 as_warn (_("set: number not in -2147483648..4294967295 range")); 1043 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1044 } 1045 } 1046 1047 /* See if operand is absolute and small; skip sethi if so. */ 1048 if (the_insn.exp.X_op != O_constant 1049 || the_insn.exp.X_add_number >= (1 << 12) 1050 || the_insn.exp.X_add_number < -(1 << 12)) 1051 { 1052 the_insn.opcode = (SETHI_INSN | RD (rd) 1053 | ((the_insn.exp.X_add_number >> 10) 1054 & (the_insn.exp.X_op == O_constant 1055 ? 0x3fffff : 0))); 1056 the_insn.reloc = (the_insn.exp.X_op != O_constant 1057 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1058 output_insn (insn, &the_insn); 1059 need_hi22_p = 1; 1060 } 1061 1062 /* See if operand has no low-order bits; skip OR if so. */ 1063 if (the_insn.exp.X_op != O_constant 1064 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1065 || ! need_hi22_p) 1066 { 1067 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1068 | RD (rd) | IMMED 1069 | (the_insn.exp.X_add_number 1070 & (the_insn.exp.X_op != O_constant 1071 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1072 the_insn.reloc = (the_insn.exp.X_op != O_constant 1073 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1074 output_insn (insn, &the_insn); 1075 } 1076 } 1077 1078 /* Handle the setsw synthetic instruction. */ 1079 1080 static void 1081 synthetize_setsw (insn) 1082 const struct sparc_opcode *insn; 1083 { 1084 int low32, rd, opc; 1085 1086 rd = (the_insn.opcode & RD (~0)) >> 25; 1087 1088 if (the_insn.exp.X_op != O_constant) 1089 { 1090 synthetize_setuw (insn); 1091 1092 /* Need to sign extend it. */ 1093 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1094 the_insn.reloc = BFD_RELOC_NONE; 1095 output_insn (insn, &the_insn); 1096 return; 1097 } 1098 1099 if (sizeof (offsetT) > 4 1100 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1101 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1102 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1103 1104 low32 = the_insn.exp.X_add_number; 1105 1106 if (low32 >= 0) 1107 { 1108 synthetize_setuw (insn); 1109 return; 1110 } 1111 1112 opc = OR_INSN; 1113 1114 the_insn.reloc = BFD_RELOC_NONE; 1115 /* See if operand is absolute and small; skip sethi if so. */ 1116 if (low32 < -(1 << 12)) 1117 { 1118 the_insn.opcode = (SETHI_INSN | RD (rd) 1119 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1120 output_insn (insn, &the_insn); 1121 low32 = 0x1c00 | (low32 & 0x3ff); 1122 opc = RS1 (rd) | XOR_INSN; 1123 } 1124 1125 the_insn.opcode = (opc | RD (rd) | IMMED 1126 | (low32 & 0x1fff)); 1127 output_insn (insn, &the_insn); 1128 } 1129 1130 /* Handle the setsw synthetic instruction. */ 1131 1132 static void 1133 synthetize_setx (insn) 1134 const struct sparc_opcode *insn; 1135 { 1136 int upper32, lower32; 1137 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1138 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1139 int upper_dstreg; 1140 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1141 int need_xor10_p = 0; 1142 1143 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) 1144 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1145 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1146 #undef SIGNEXT32 1147 1148 upper_dstreg = tmpreg; 1149 /* The tmp reg should not be the dst reg. */ 1150 if (tmpreg == dstreg) 1151 as_warn (_("setx: temporary register same as destination register")); 1152 1153 /* ??? Obviously there are other optimizations we can do 1154 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1155 doing some of these. Later. If you do change things, try to 1156 change all of this to be table driven as well. */ 1157 /* What to output depends on the number if it's constant. 1158 Compute that first, then output what we've decided upon. */ 1159 if (the_insn.exp.X_op != O_constant) 1160 { 1161 if (sparc_arch_size == 32) 1162 { 1163 /* When arch size is 32, we want setx to be equivalent 1164 to setuw for anything but constants. */ 1165 the_insn.exp.X_add_number &= 0xffffffff; 1166 synthetize_setuw (insn); 1167 return; 1168 } 1169 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1170 lower32 = 0; 1171 upper32 = 0; 1172 } 1173 else 1174 { 1175 /* Reset X_add_number, we've extracted it as upper32/lower32. 1176 Otherwise fixup_segment will complain about not being able to 1177 write an 8 byte number in a 4 byte field. */ 1178 the_insn.exp.X_add_number = 0; 1179 1180 /* Only need hh22 if `or' insn can't handle constant. */ 1181 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1182 need_hh22_p = 1; 1183 1184 /* Does bottom part (after sethi) have bits? */ 1185 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1186 /* No hh22, but does upper32 still have bits we can't set 1187 from lower32? */ 1188 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1189 need_hm10_p = 1; 1190 1191 /* If the lower half is all zero, we build the upper half directly 1192 into the dst reg. */ 1193 if (lower32 != 0 1194 /* Need lower half if number is zero or 0xffffffff00000000. */ 1195 || (! need_hh22_p && ! need_hm10_p)) 1196 { 1197 /* No need for sethi if `or' insn can handle constant. */ 1198 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1199 /* Note that we can't use a negative constant in the `or' 1200 insn unless the upper 32 bits are all ones. */ 1201 || (lower32 < 0 && upper32 != -1) 1202 || (lower32 >= 0 && upper32 == -1)) 1203 need_hi22_p = 1; 1204 1205 if (need_hi22_p && upper32 == -1) 1206 need_xor10_p = 1; 1207 1208 /* Does bottom part (after sethi) have bits? */ 1209 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1210 /* No sethi. */ 1211 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1212 /* Need `or' if we didn't set anything else. */ 1213 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1214 need_lo10_p = 1; 1215 } 1216 else 1217 /* Output directly to dst reg if lower 32 bits are all zero. */ 1218 upper_dstreg = dstreg; 1219 } 1220 1221 if (!upper_dstreg && dstreg) 1222 as_warn (_("setx: illegal temporary register g0")); 1223 1224 if (need_hh22_p) 1225 { 1226 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1227 | ((upper32 >> 10) & 0x3fffff)); 1228 the_insn.reloc = (the_insn.exp.X_op != O_constant 1229 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1230 output_insn (insn, &the_insn); 1231 } 1232 1233 if (need_hi22_p) 1234 { 1235 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1236 | (((need_xor10_p ? ~lower32 : lower32) 1237 >> 10) & 0x3fffff)); 1238 the_insn.reloc = (the_insn.exp.X_op != O_constant 1239 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1240 output_insn (insn, &the_insn); 1241 } 1242 1243 if (need_hm10_p) 1244 { 1245 the_insn.opcode = (OR_INSN 1246 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1247 | RD (upper_dstreg) 1248 | IMMED 1249 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1250 the_insn.reloc = (the_insn.exp.X_op != O_constant 1251 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1252 output_insn (insn, &the_insn); 1253 } 1254 1255 if (need_lo10_p) 1256 { 1257 /* FIXME: One nice optimization to do here is to OR the low part 1258 with the highpart if hi22 isn't needed and the low part is 1259 positive. */ 1260 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1261 | RD (dstreg) 1262 | IMMED 1263 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1264 the_insn.reloc = (the_insn.exp.X_op != O_constant 1265 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1266 output_insn (insn, &the_insn); 1267 } 1268 1269 /* If we needed to build the upper part, shift it into place. */ 1270 if (need_hh22_p || need_hm10_p) 1271 { 1272 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1273 | IMMED | 32); 1274 the_insn.reloc = BFD_RELOC_NONE; 1275 output_insn (insn, &the_insn); 1276 } 1277 1278 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1279 if (need_xor10_p) 1280 { 1281 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1282 | 0x1c00 | (lower32 & 0x3ff)); 1283 the_insn.reloc = BFD_RELOC_NONE; 1284 output_insn (insn, &the_insn); 1285 } 1286 1287 /* If we needed to build both upper and lower parts, OR them together. */ 1288 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1289 { 1290 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1291 | RD (dstreg)); 1292 the_insn.reloc = BFD_RELOC_NONE; 1293 output_insn (insn, &the_insn); 1294 } 1295 } 1296 1297 /* Main entry point to assemble one instruction. */ 1298 1299 void 1300 md_assemble (str) 1301 char *str; 1302 { 1303 const struct sparc_opcode *insn; 1304 int special_case; 1305 1306 know (str); 1307 special_case = sparc_ip (str, &insn); 1308 if (insn == NULL) 1309 return; 1310 1311 /* We warn about attempts to put a floating point branch in a delay slot, 1312 unless the delay slot has been annulled. */ 1313 if (last_insn != NULL 1314 && (insn->flags & F_FBR) != 0 1315 && (last_insn->flags & F_DELAYED) != 0 1316 /* ??? This test isn't completely accurate. We assume anything with 1317 F_{UNBR,CONDBR,FBR} set is annullable. */ 1318 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1319 || (last_opcode & ANNUL) == 0)) 1320 as_warn (_("FP branch in delay slot")); 1321 1322 /* SPARC before v9 requires a nop instruction between a floating 1323 point instruction and a floating point branch. We insert one 1324 automatically, with a warning. */ 1325 if (max_architecture < SPARC_OPCODE_ARCH_V9 1326 && last_insn != NULL 1327 && (insn->flags & F_FBR) != 0 1328 && (last_insn->flags & F_FLOAT) != 0) 1329 { 1330 struct sparc_it nop_insn; 1331 1332 nop_insn.opcode = NOP_INSN; 1333 nop_insn.reloc = BFD_RELOC_NONE; 1334 output_insn (insn, &nop_insn); 1335 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1336 } 1337 1338 switch (special_case) 1339 { 1340 case SPECIAL_CASE_NONE: 1341 /* Normal insn. */ 1342 output_insn (insn, &the_insn); 1343 break; 1344 1345 case SPECIAL_CASE_SETSW: 1346 synthetize_setsw (insn); 1347 break; 1348 1349 case SPECIAL_CASE_SET: 1350 synthetize_setuw (insn); 1351 break; 1352 1353 case SPECIAL_CASE_SETX: 1354 synthetize_setx (insn); 1355 break; 1356 1357 case SPECIAL_CASE_FDIV: 1358 { 1359 int rd = (the_insn.opcode >> 25) & 0x1f; 1360 1361 output_insn (insn, &the_insn); 1362 1363 /* According to information leaked from Sun, the "fdiv" instructions 1364 on early SPARC machines would produce incorrect results sometimes. 1365 The workaround is to add an fmovs of the destination register to 1366 itself just after the instruction. This was true on machines 1367 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1368 assert (the_insn.reloc == BFD_RELOC_NONE); 1369 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1370 output_insn (insn, &the_insn); 1371 return; 1372 } 1373 1374 default: 1375 as_fatal (_("failed special case insn sanity check")); 1376 } 1377 } 1378 1379 /* Subroutine of md_assemble to do the actual parsing. */ 1380 1381 static int 1382 sparc_ip (str, pinsn) 1383 char *str; 1384 const struct sparc_opcode **pinsn; 1385 { 1386 char *error_message = ""; 1387 char *s; 1388 const char *args; 1389 char c; 1390 const struct sparc_opcode *insn; 1391 char *argsStart; 1392 unsigned long opcode; 1393 unsigned int mask = 0; 1394 int match = 0; 1395 int comma = 0; 1396 int v9_arg_p; 1397 int special_case = SPECIAL_CASE_NONE; 1398 1399 s = str; 1400 if (ISLOWER (*s)) 1401 { 1402 do 1403 ++s; 1404 while (ISLOWER (*s) || ISDIGIT (*s)); 1405 } 1406 1407 switch (*s) 1408 { 1409 case '\0': 1410 break; 1411 1412 case ',': 1413 comma = 1; 1414 /* Fall through. */ 1415 1416 case ' ': 1417 *s++ = '\0'; 1418 break; 1419 1420 default: 1421 as_bad (_("Unknown opcode: `%s'"), str); 1422 *pinsn = NULL; 1423 return special_case; 1424 } 1425 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1426 *pinsn = insn; 1427 if (insn == NULL) 1428 { 1429 as_bad (_("Unknown opcode: `%s'"), str); 1430 return special_case; 1431 } 1432 if (comma) 1433 { 1434 *--s = ','; 1435 } 1436 1437 argsStart = s; 1438 for (;;) 1439 { 1440 opcode = insn->match; 1441 memset (&the_insn, '\0', sizeof (the_insn)); 1442 the_insn.reloc = BFD_RELOC_NONE; 1443 v9_arg_p = 0; 1444 1445 /* Build the opcode, checking as we go to make sure that the 1446 operands match. */ 1447 for (args = insn->args;; ++args) 1448 { 1449 switch (*args) 1450 { 1451 case 'K': 1452 { 1453 int kmask = 0; 1454 1455 /* Parse a series of masks. */ 1456 if (*s == '#') 1457 { 1458 while (*s == '#') 1459 { 1460 int mask; 1461 1462 if (! parse_keyword_arg (sparc_encode_membar, &s, 1463 &mask)) 1464 { 1465 error_message = _(": invalid membar mask name"); 1466 goto error; 1467 } 1468 kmask |= mask; 1469 while (*s == ' ') 1470 ++s; 1471 if (*s == '|' || *s == '+') 1472 ++s; 1473 while (*s == ' ') 1474 ++s; 1475 } 1476 } 1477 else 1478 { 1479 if (! parse_const_expr_arg (&s, &kmask)) 1480 { 1481 error_message = _(": invalid membar mask expression"); 1482 goto error; 1483 } 1484 if (kmask < 0 || kmask > 127) 1485 { 1486 error_message = _(": invalid membar mask number"); 1487 goto error; 1488 } 1489 } 1490 1491 opcode |= MEMBAR (kmask); 1492 continue; 1493 } 1494 1495 case '3': 1496 { 1497 int smask = 0; 1498 1499 if (! parse_const_expr_arg (&s, &smask)) 1500 { 1501 error_message = _(": invalid siam mode expression"); 1502 goto error; 1503 } 1504 if (smask < 0 || smask > 7) 1505 { 1506 error_message = _(": invalid siam mode number"); 1507 goto error; 1508 } 1509 opcode |= smask; 1510 continue; 1511 } 1512 1513 case '*': 1514 { 1515 int fcn = 0; 1516 1517 /* Parse a prefetch function. */ 1518 if (*s == '#') 1519 { 1520 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1521 { 1522 error_message = _(": invalid prefetch function name"); 1523 goto error; 1524 } 1525 } 1526 else 1527 { 1528 if (! parse_const_expr_arg (&s, &fcn)) 1529 { 1530 error_message = _(": invalid prefetch function expression"); 1531 goto error; 1532 } 1533 if (fcn < 0 || fcn > 31) 1534 { 1535 error_message = _(": invalid prefetch function number"); 1536 goto error; 1537 } 1538 } 1539 opcode |= RD (fcn); 1540 continue; 1541 } 1542 1543 case '!': 1544 case '?': 1545 /* Parse a sparc64 privileged register. */ 1546 if (*s == '%') 1547 { 1548 struct priv_reg_entry *p = priv_reg_table; 1549 unsigned int len = 9999999; /* Init to make gcc happy. */ 1550 1551 s += 1; 1552 while (p->name[0] > s[0]) 1553 p++; 1554 while (p->name[0] == s[0]) 1555 { 1556 len = strlen (p->name); 1557 if (strncmp (p->name, s, len) == 0) 1558 break; 1559 p++; 1560 } 1561 if (p->name[0] != s[0]) 1562 { 1563 error_message = _(": unrecognizable privileged register"); 1564 goto error; 1565 } 1566 if (*args == '?') 1567 opcode |= (p->regnum << 14); 1568 else 1569 opcode |= (p->regnum << 25); 1570 s += len; 1571 continue; 1572 } 1573 else 1574 { 1575 error_message = _(": unrecognizable privileged register"); 1576 goto error; 1577 } 1578 1579 case '$': 1580 case '%': 1581 /* Parse a sparc64 hyperprivileged register. */ 1582 if (*s == '%') 1583 { 1584 struct priv_reg_entry *p = hpriv_reg_table; 1585 unsigned int len = 9999999; /* Init to make gcc happy. */ 1586 1587 s += 1; 1588 while (p->name[0] > s[0]) 1589 p++; 1590 while (p->name[0] == s[0]) 1591 { 1592 len = strlen (p->name); 1593 if (strncmp (p->name, s, len) == 0) 1594 break; 1595 p++; 1596 } 1597 if (p->name[0] != s[0]) 1598 { 1599 error_message = _(": unrecognizable hyperprivileged register"); 1600 goto error; 1601 } 1602 if (*args == '$') 1603 opcode |= (p->regnum << 14); 1604 else 1605 opcode |= (p->regnum << 25); 1606 s += len; 1607 continue; 1608 } 1609 else 1610 { 1611 error_message = _(": unrecognizable hyperprivileged register"); 1612 goto error; 1613 } 1614 1615 case '_': 1616 case '/': 1617 /* Parse a v9a/v9b ancillary state register. */ 1618 if (*s == '%') 1619 { 1620 struct priv_reg_entry *p = v9a_asr_table; 1621 unsigned int len = 9999999; /* Init to make gcc happy. */ 1622 1623 s += 1; 1624 while (p->name[0] > s[0]) 1625 p++; 1626 while (p->name[0] == s[0]) 1627 { 1628 len = strlen (p->name); 1629 if (strncmp (p->name, s, len) == 0) 1630 break; 1631 p++; 1632 } 1633 if (p->name[0] != s[0]) 1634 { 1635 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1636 goto error; 1637 } 1638 if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) 1639 { 1640 error_message = _(": rd on write only ancillary state register"); 1641 goto error; 1642 } 1643 if (p->regnum >= 24 1644 && (insn->architecture 1645 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) 1646 { 1647 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ 1648 error_message = _(": unrecognizable v9a ancillary state register"); 1649 goto error; 1650 } 1651 if (*args == '/') 1652 opcode |= (p->regnum << 14); 1653 else 1654 opcode |= (p->regnum << 25); 1655 s += len; 1656 continue; 1657 } 1658 else 1659 { 1660 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1661 goto error; 1662 } 1663 1664 case 'M': 1665 case 'm': 1666 if (strncmp (s, "%asr", 4) == 0) 1667 { 1668 s += 4; 1669 1670 if (ISDIGIT (*s)) 1671 { 1672 long num = 0; 1673 1674 while (ISDIGIT (*s)) 1675 { 1676 num = num * 10 + *s - '0'; 1677 ++s; 1678 } 1679 1680 if (current_architecture >= SPARC_OPCODE_ARCH_V9) 1681 { 1682 if (num < 16 || 31 < num) 1683 { 1684 error_message = _(": asr number must be between 16 and 31"); 1685 goto error; 1686 } 1687 } 1688 else 1689 { 1690 if (num < 0 || 31 < num) 1691 { 1692 error_message = _(": asr number must be between 0 and 31"); 1693 goto error; 1694 } 1695 } 1696 1697 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 1698 continue; 1699 } 1700 else 1701 { 1702 error_message = _(": expecting %asrN"); 1703 goto error; 1704 } 1705 } /* if %asr */ 1706 break; 1707 1708 case 'I': 1709 the_insn.reloc = BFD_RELOC_SPARC_11; 1710 goto immediate; 1711 1712 case 'j': 1713 the_insn.reloc = BFD_RELOC_SPARC_10; 1714 goto immediate; 1715 1716 case 'X': 1717 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 1718 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1719 the_insn.reloc = BFD_RELOC_SPARC_5; 1720 else 1721 the_insn.reloc = BFD_RELOC_SPARC13; 1722 /* These fields are unsigned, but for upward compatibility, 1723 allow negative values as well. */ 1724 goto immediate; 1725 1726 case 'Y': 1727 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 1728 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1729 the_insn.reloc = BFD_RELOC_SPARC_6; 1730 else 1731 the_insn.reloc = BFD_RELOC_SPARC13; 1732 /* These fields are unsigned, but for upward compatibility, 1733 allow negative values as well. */ 1734 goto immediate; 1735 1736 case 'k': 1737 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 1738 the_insn.pcrel = 1; 1739 goto immediate; 1740 1741 case 'G': 1742 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 1743 the_insn.pcrel = 1; 1744 goto immediate; 1745 1746 case 'N': 1747 if (*s == 'p' && s[1] == 'n') 1748 { 1749 s += 2; 1750 continue; 1751 } 1752 break; 1753 1754 case 'T': 1755 if (*s == 'p' && s[1] == 't') 1756 { 1757 s += 2; 1758 continue; 1759 } 1760 break; 1761 1762 case 'z': 1763 if (*s == ' ') 1764 { 1765 ++s; 1766 } 1767 if (strncmp (s, "%icc", 4) == 0) 1768 { 1769 s += 4; 1770 continue; 1771 } 1772 break; 1773 1774 case 'Z': 1775 if (*s == ' ') 1776 { 1777 ++s; 1778 } 1779 if (strncmp (s, "%xcc", 4) == 0) 1780 { 1781 s += 4; 1782 continue; 1783 } 1784 break; 1785 1786 case '6': 1787 if (*s == ' ') 1788 { 1789 ++s; 1790 } 1791 if (strncmp (s, "%fcc0", 5) == 0) 1792 { 1793 s += 5; 1794 continue; 1795 } 1796 break; 1797 1798 case '7': 1799 if (*s == ' ') 1800 { 1801 ++s; 1802 } 1803 if (strncmp (s, "%fcc1", 5) == 0) 1804 { 1805 s += 5; 1806 continue; 1807 } 1808 break; 1809 1810 case '8': 1811 if (*s == ' ') 1812 { 1813 ++s; 1814 } 1815 if (strncmp (s, "%fcc2", 5) == 0) 1816 { 1817 s += 5; 1818 continue; 1819 } 1820 break; 1821 1822 case '9': 1823 if (*s == ' ') 1824 { 1825 ++s; 1826 } 1827 if (strncmp (s, "%fcc3", 5) == 0) 1828 { 1829 s += 5; 1830 continue; 1831 } 1832 break; 1833 1834 case 'P': 1835 if (strncmp (s, "%pc", 3) == 0) 1836 { 1837 s += 3; 1838 continue; 1839 } 1840 break; 1841 1842 case 'W': 1843 if (strncmp (s, "%tick", 5) == 0) 1844 { 1845 s += 5; 1846 continue; 1847 } 1848 break; 1849 1850 case '\0': /* End of args. */ 1851 if (s[0] == ',' && s[1] == '%') 1852 { 1853 static const struct tls_ops { 1854 /* The name as it appears in assembler. */ 1855 char *name; 1856 /* strlen (name), precomputed for speed */ 1857 int len; 1858 /* The reloc this pseudo-op translates to. */ 1859 int reloc; 1860 /* 1 if call. */ 1861 int call; 1862 } tls_ops[] = { 1863 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, 1864 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, 1865 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, 1866 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, 1867 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, 1868 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, 1869 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, 1870 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 } 1871 }; 1872 const struct tls_ops *o; 1873 char *s1; 1874 int npar = 0; 1875 1876 for (o = tls_ops; o->name; o++) 1877 if (strncmp (s + 2, o->name, o->len) == 0) 1878 break; 1879 if (o->name == NULL) 1880 break; 1881 1882 if (s[o->len + 2] != '(') 1883 { 1884 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 1885 return special_case; 1886 } 1887 1888 if (! o->call && the_insn.reloc != BFD_RELOC_NONE) 1889 { 1890 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), 1891 o->name); 1892 return special_case; 1893 } 1894 1895 if (o->call 1896 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 1897 || the_insn.exp.X_add_number != 0 1898 || the_insn.exp.X_add_symbol 1899 != symbol_find_or_make ("__tls_get_addr"))) 1900 { 1901 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), 1902 o->name); 1903 return special_case; 1904 } 1905 1906 the_insn.reloc = o->reloc; 1907 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 1908 s += o->len + 3; 1909 1910 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 1911 if (*s1 == '(') 1912 npar++; 1913 else if (*s1 == ')') 1914 { 1915 if (!npar) 1916 break; 1917 npar--; 1918 } 1919 1920 if (*s1 != ')') 1921 { 1922 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 1923 return special_case; 1924 } 1925 1926 *s1 = '\0'; 1927 (void) get_expression (s); 1928 *s1 = ')'; 1929 s = s1 + 1; 1930 } 1931 if (*s == '\0') 1932 match = 1; 1933 break; 1934 1935 case '+': 1936 if (*s == '+') 1937 { 1938 ++s; 1939 continue; 1940 } 1941 if (*s == '-') 1942 { 1943 continue; 1944 } 1945 break; 1946 1947 case '[': /* These must match exactly. */ 1948 case ']': 1949 case ',': 1950 case ' ': 1951 if (*s++ == *args) 1952 continue; 1953 break; 1954 1955 case '#': /* Must be at least one digit. */ 1956 if (ISDIGIT (*s++)) 1957 { 1958 while (ISDIGIT (*s)) 1959 { 1960 ++s; 1961 } 1962 continue; 1963 } 1964 break; 1965 1966 case 'C': /* Coprocessor state register. */ 1967 if (strncmp (s, "%csr", 4) == 0) 1968 { 1969 s += 4; 1970 continue; 1971 } 1972 break; 1973 1974 case 'b': /* Next operand is a coprocessor register. */ 1975 case 'c': 1976 case 'D': 1977 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) 1978 { 1979 mask = *s++; 1980 if (ISDIGIT (*s)) 1981 { 1982 mask = 10 * (mask - '0') + (*s++ - '0'); 1983 if (mask >= 32) 1984 { 1985 break; 1986 } 1987 } 1988 else 1989 { 1990 mask -= '0'; 1991 } 1992 switch (*args) 1993 { 1994 1995 case 'b': 1996 opcode |= mask << 14; 1997 continue; 1998 1999 case 'c': 2000 opcode |= mask; 2001 continue; 2002 2003 case 'D': 2004 opcode |= mask << 25; 2005 continue; 2006 } 2007 } 2008 break; 2009 2010 case 'r': /* next operand must be a register */ 2011 case 'O': 2012 case '1': 2013 case '2': 2014 case 'd': 2015 if (*s++ == '%') 2016 { 2017 switch (c = *s++) 2018 { 2019 2020 case 'f': /* frame pointer */ 2021 if (*s++ == 'p') 2022 { 2023 mask = 0x1e; 2024 break; 2025 } 2026 goto error; 2027 2028 case 'g': /* global register */ 2029 c = *s++; 2030 if (isoctal (c)) 2031 { 2032 mask = c - '0'; 2033 break; 2034 } 2035 goto error; 2036 2037 case 'i': /* in register */ 2038 c = *s++; 2039 if (isoctal (c)) 2040 { 2041 mask = c - '0' + 24; 2042 break; 2043 } 2044 goto error; 2045 2046 case 'l': /* local register */ 2047 c = *s++; 2048 if (isoctal (c)) 2049 { 2050 mask = (c - '0' + 16); 2051 break; 2052 } 2053 goto error; 2054 2055 case 'o': /* out register */ 2056 c = *s++; 2057 if (isoctal (c)) 2058 { 2059 mask = (c - '0' + 8); 2060 break; 2061 } 2062 goto error; 2063 2064 case 's': /* stack pointer */ 2065 if (*s++ == 'p') 2066 { 2067 mask = 0xe; 2068 break; 2069 } 2070 goto error; 2071 2072 case 'r': /* any register */ 2073 if (!ISDIGIT ((c = *s++))) 2074 { 2075 goto error; 2076 } 2077 /* FALLTHROUGH */ 2078 case '0': 2079 case '1': 2080 case '2': 2081 case '3': 2082 case '4': 2083 case '5': 2084 case '6': 2085 case '7': 2086 case '8': 2087 case '9': 2088 if (ISDIGIT (*s)) 2089 { 2090 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 2091 { 2092 goto error; 2093 } 2094 } 2095 else 2096 { 2097 c -= '0'; 2098 } 2099 mask = c; 2100 break; 2101 2102 default: 2103 goto error; 2104 } 2105 2106 if ((mask & ~1) == 2 && sparc_arch_size == 64 2107 && no_undeclared_regs && ! globals[mask]) 2108 as_bad (_("detected global register use not covered by .register pseudo-op")); 2109 2110 /* Got the register, now figure out where 2111 it goes in the opcode. */ 2112 switch (*args) 2113 { 2114 case '1': 2115 opcode |= mask << 14; 2116 continue; 2117 2118 case '2': 2119 opcode |= mask; 2120 continue; 2121 2122 case 'd': 2123 opcode |= mask << 25; 2124 continue; 2125 2126 case 'r': 2127 opcode |= (mask << 25) | (mask << 14); 2128 continue; 2129 2130 case 'O': 2131 opcode |= (mask << 25) | (mask << 0); 2132 continue; 2133 } 2134 } 2135 break; 2136 2137 case 'e': /* next operand is a floating point register */ 2138 case 'v': 2139 case 'V': 2140 2141 case 'f': 2142 case 'B': 2143 case 'R': 2144 2145 case 'g': 2146 case 'H': 2147 case 'J': 2148 { 2149 char format; 2150 2151 if (*s++ == '%' 2152 && ((format = *s) == 'f') 2153 && ISDIGIT (*++s)) 2154 { 2155 for (mask = 0; ISDIGIT (*s); ++s) 2156 { 2157 mask = 10 * mask + (*s - '0'); 2158 } /* read the number */ 2159 2160 if ((*args == 'v' 2161 || *args == 'B' 2162 || *args == 'H') 2163 && (mask & 1)) 2164 { 2165 break; 2166 } /* register must be even numbered */ 2167 2168 if ((*args == 'V' 2169 || *args == 'R' 2170 || *args == 'J') 2171 && (mask & 3)) 2172 { 2173 break; 2174 } /* register must be multiple of 4 */ 2175 2176 if (mask >= 64) 2177 { 2178 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2179 error_message = _(": There are only 64 f registers; [0-63]"); 2180 else 2181 error_message = _(": There are only 32 f registers; [0-31]"); 2182 goto error; 2183 } /* on error */ 2184 else if (mask >= 32) 2185 { 2186 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2187 { 2188 #if !defined(TE_OpenBSD) 2189 if (*args == 'e' || *args == 'f' || *args == 'g') 2190 { 2191 error_message 2192 = _(": There are only 32 single precision f registers; [0-31]"); 2193 goto error; 2194 } 2195 #endif 2196 v9_arg_p = 1; 2197 mask -= 31; /* wrap high bit */ 2198 } 2199 else 2200 { 2201 error_message = _(": There are only 32 f registers; [0-31]"); 2202 goto error; 2203 } 2204 } 2205 } 2206 else 2207 { 2208 break; 2209 } /* if not an 'f' register. */ 2210 2211 switch (*args) 2212 { 2213 case 'v': 2214 case 'V': 2215 case 'e': 2216 opcode |= RS1 (mask); 2217 continue; 2218 2219 case 'f': 2220 case 'B': 2221 case 'R': 2222 opcode |= RS2 (mask); 2223 continue; 2224 2225 case 'g': 2226 case 'H': 2227 case 'J': 2228 opcode |= RD (mask); 2229 continue; 2230 } /* Pack it in. */ 2231 2232 know (0); 2233 break; 2234 } /* float arg */ 2235 2236 case 'F': 2237 if (strncmp (s, "%fsr", 4) == 0) 2238 { 2239 s += 4; 2240 continue; 2241 } 2242 break; 2243 2244 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2245 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2246 goto immediate; 2247 2248 case 'l': /* 22 bit PC relative immediate */ 2249 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2250 the_insn.pcrel = 1; 2251 goto immediate; 2252 2253 case 'L': /* 30 bit immediate */ 2254 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2255 the_insn.pcrel = 1; 2256 goto immediate; 2257 2258 case 'h': 2259 case 'n': /* 22 bit immediate */ 2260 the_insn.reloc = BFD_RELOC_SPARC22; 2261 goto immediate; 2262 2263 case 'i': /* 13 bit immediate */ 2264 the_insn.reloc = BFD_RELOC_SPARC13; 2265 2266 /* fallthrough */ 2267 2268 immediate: 2269 if (*s == ' ') 2270 s++; 2271 2272 { 2273 char *s1; 2274 char *op_arg = NULL; 2275 static expressionS op_exp; 2276 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2277 2278 /* Check for %hi, etc. */ 2279 if (*s == '%') 2280 { 2281 static const struct ops { 2282 /* The name as it appears in assembler. */ 2283 char *name; 2284 /* strlen (name), precomputed for speed */ 2285 int len; 2286 /* The reloc this pseudo-op translates to. */ 2287 int reloc; 2288 /* Non-zero if for v9 only. */ 2289 int v9_p; 2290 /* Non-zero if can be used in pc-relative contexts. */ 2291 int pcrel_p;/*FIXME:wip*/ 2292 } ops[] = { 2293 /* hix/lox must appear before hi/lo so %hix won't be 2294 mistaken for %hi. */ 2295 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, 2296 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, 2297 { "hi", 2, BFD_RELOC_HI22, 0, 1 }, 2298 { "lo", 2, BFD_RELOC_LO10, 0, 1 }, 2299 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, 2300 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, 2301 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, 2302 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, 2303 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, 2304 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2305 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, 2306 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, 2307 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, 2308 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, 2309 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, 2310 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, 2311 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, 2312 0 }, 2313 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, 2314 0 }, 2315 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, 2316 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, 2317 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, 2318 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, 2319 { NULL, 0, 0, 0, 0 } 2320 }; 2321 const struct ops *o; 2322 2323 for (o = ops; o->name; o++) 2324 if (strncmp (s + 1, o->name, o->len) == 0) 2325 break; 2326 if (o->name == NULL) 2327 break; 2328 2329 if (s[o->len + 1] != '(') 2330 { 2331 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2332 return special_case; 2333 } 2334 2335 op_arg = o->name; 2336 the_insn.reloc = o->reloc; 2337 s += o->len + 2; 2338 v9_arg_p = o->v9_p; 2339 } 2340 2341 /* Note that if the get_expression() fails, we will still 2342 have created U entries in the symbol table for the 2343 'symbols' in the input string. Try not to create U 2344 symbols for registers, etc. */ 2345 2346 /* This stuff checks to see if the expression ends in 2347 +%reg. If it does, it removes the register from 2348 the expression, and re-sets 's' to point to the 2349 right place. */ 2350 2351 if (op_arg) 2352 { 2353 int npar = 0; 2354 2355 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2356 if (*s1 == '(') 2357 npar++; 2358 else if (*s1 == ')') 2359 { 2360 if (!npar) 2361 break; 2362 npar--; 2363 } 2364 2365 if (*s1 != ')') 2366 { 2367 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2368 return special_case; 2369 } 2370 2371 *s1 = '\0'; 2372 (void) get_expression (s); 2373 *s1 = ')'; 2374 s = s1 + 1; 2375 if (*s == ',' || *s == ']' || !*s) 2376 continue; 2377 if (*s != '+' && *s != '-') 2378 { 2379 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2380 return special_case; 2381 } 2382 *s1 = '0'; 2383 s = s1; 2384 op_exp = the_insn.exp; 2385 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2386 } 2387 2388 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2389 ; 2390 2391 if (s1 != s && ISDIGIT (s1[-1])) 2392 { 2393 if (s1[-2] == '%' && s1[-3] == '+') 2394 s1 -= 3; 2395 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2396 s1 -= 4; 2397 else 2398 s1 = NULL; 2399 if (s1) 2400 { 2401 *s1 = '\0'; 2402 if (op_arg && s1 == s + 1) 2403 the_insn.exp.X_op = O_absent; 2404 else 2405 (void) get_expression (s); 2406 *s1 = '+'; 2407 if (op_arg) 2408 *s = ')'; 2409 s = s1; 2410 } 2411 } 2412 else 2413 s1 = NULL; 2414 2415 if (!s1) 2416 { 2417 (void) get_expression (s); 2418 if (op_arg) 2419 *s = ')'; 2420 s = expr_end; 2421 } 2422 2423 if (op_arg) 2424 { 2425 the_insn.exp2 = the_insn.exp; 2426 the_insn.exp = op_exp; 2427 if (the_insn.exp2.X_op == O_absent) 2428 the_insn.exp2.X_op = O_illegal; 2429 else if (the_insn.exp.X_op == O_absent) 2430 { 2431 the_insn.exp = the_insn.exp2; 2432 the_insn.exp2.X_op = O_illegal; 2433 } 2434 else if (the_insn.exp.X_op == O_constant) 2435 { 2436 valueT val = the_insn.exp.X_add_number; 2437 switch (the_insn.reloc) 2438 { 2439 default: 2440 break; 2441 2442 case BFD_RELOC_SPARC_HH22: 2443 val = BSR (val, 32); 2444 /* Fall through. */ 2445 2446 case BFD_RELOC_SPARC_LM22: 2447 case BFD_RELOC_HI22: 2448 val = (val >> 10) & 0x3fffff; 2449 break; 2450 2451 case BFD_RELOC_SPARC_HM10: 2452 val = BSR (val, 32); 2453 /* Fall through. */ 2454 2455 case BFD_RELOC_LO10: 2456 val &= 0x3ff; 2457 break; 2458 2459 case BFD_RELOC_SPARC_H44: 2460 val >>= 22; 2461 val &= 0x3fffff; 2462 break; 2463 2464 case BFD_RELOC_SPARC_M44: 2465 val >>= 12; 2466 val &= 0x3ff; 2467 break; 2468 2469 case BFD_RELOC_SPARC_L44: 2470 val &= 0xfff; 2471 break; 2472 2473 case BFD_RELOC_SPARC_HIX22: 2474 val = ~val; 2475 val = (val >> 10) & 0x3fffff; 2476 break; 2477 2478 case BFD_RELOC_SPARC_LOX10: 2479 val = (val & 0x3ff) | 0x1c00; 2480 break; 2481 } 2482 the_insn.exp = the_insn.exp2; 2483 the_insn.exp.X_add_number += val; 2484 the_insn.exp2.X_op = O_illegal; 2485 the_insn.reloc = old_reloc; 2486 } 2487 else if (the_insn.exp2.X_op != O_constant) 2488 { 2489 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2490 return special_case; 2491 } 2492 else 2493 { 2494 if (old_reloc != BFD_RELOC_SPARC13 2495 || the_insn.reloc != BFD_RELOC_LO10 2496 || sparc_arch_size != 64 2497 || sparc_pic_code) 2498 { 2499 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2500 return special_case; 2501 } 2502 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2503 } 2504 } 2505 } 2506 /* Check for constants that don't require emitting a reloc. */ 2507 if (the_insn.exp.X_op == O_constant 2508 && the_insn.exp.X_add_symbol == 0 2509 && the_insn.exp.X_op_symbol == 0) 2510 { 2511 /* For pc-relative call instructions, we reject 2512 constants to get better code. */ 2513 if (the_insn.pcrel 2514 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2515 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2516 { 2517 error_message = _(": PC-relative operand can't be a constant"); 2518 goto error; 2519 } 2520 2521 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 2522 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) 2523 { 2524 error_message = _(": TLS operand can't be a constant"); 2525 goto error; 2526 } 2527 2528 /* Constants that won't fit are checked in md_apply_fix 2529 and bfd_install_relocation. 2530 ??? It would be preferable to install the constants 2531 into the insn here and save having to create a fixS 2532 for each one. There already exists code to handle 2533 all the various cases (e.g. in md_apply_fix and 2534 bfd_install_relocation) so duplicating all that code 2535 here isn't right. */ 2536 } 2537 2538 continue; 2539 2540 case 'a': 2541 if (*s++ == 'a') 2542 { 2543 opcode |= ANNUL; 2544 continue; 2545 } 2546 break; 2547 2548 case 'A': 2549 { 2550 int asi = 0; 2551 2552 /* Parse an asi. */ 2553 if (*s == '#') 2554 { 2555 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2556 { 2557 error_message = _(": invalid ASI name"); 2558 goto error; 2559 } 2560 } 2561 else 2562 { 2563 if (! parse_const_expr_arg (&s, &asi)) 2564 { 2565 error_message = _(": invalid ASI expression"); 2566 goto error; 2567 } 2568 if (asi < 0 || asi > 255) 2569 { 2570 error_message = _(": invalid ASI number"); 2571 goto error; 2572 } 2573 } 2574 opcode |= ASI (asi); 2575 continue; 2576 } /* Alternate space. */ 2577 2578 case 'p': 2579 if (strncmp (s, "%psr", 4) == 0) 2580 { 2581 s += 4; 2582 continue; 2583 } 2584 break; 2585 2586 case 'q': /* Floating point queue. */ 2587 if (strncmp (s, "%fq", 3) == 0) 2588 { 2589 s += 3; 2590 continue; 2591 } 2592 break; 2593 2594 case 'Q': /* Coprocessor queue. */ 2595 if (strncmp (s, "%cq", 3) == 0) 2596 { 2597 s += 3; 2598 continue; 2599 } 2600 break; 2601 2602 case 'S': 2603 if (strcmp (str, "set") == 0 2604 || strcmp (str, "setuw") == 0) 2605 { 2606 special_case = SPECIAL_CASE_SET; 2607 continue; 2608 } 2609 else if (strcmp (str, "setsw") == 0) 2610 { 2611 special_case = SPECIAL_CASE_SETSW; 2612 continue; 2613 } 2614 else if (strcmp (str, "setx") == 0) 2615 { 2616 special_case = SPECIAL_CASE_SETX; 2617 continue; 2618 } 2619 else if (strncmp (str, "fdiv", 4) == 0) 2620 { 2621 special_case = SPECIAL_CASE_FDIV; 2622 continue; 2623 } 2624 break; 2625 2626 case 'o': 2627 if (strncmp (s, "%asi", 4) != 0) 2628 break; 2629 s += 4; 2630 continue; 2631 2632 case 's': 2633 if (strncmp (s, "%fprs", 5) != 0) 2634 break; 2635 s += 5; 2636 continue; 2637 2638 case 'E': 2639 if (strncmp (s, "%ccr", 4) != 0) 2640 break; 2641 s += 4; 2642 continue; 2643 2644 case 't': 2645 if (strncmp (s, "%tbr", 4) != 0) 2646 break; 2647 s += 4; 2648 continue; 2649 2650 case 'w': 2651 if (strncmp (s, "%wim", 4) != 0) 2652 break; 2653 s += 4; 2654 continue; 2655 2656 case 'x': 2657 { 2658 char *push = input_line_pointer; 2659 expressionS e; 2660 2661 input_line_pointer = s; 2662 expression (&e); 2663 if (e.X_op == O_constant) 2664 { 2665 int n = e.X_add_number; 2666 if (n != e.X_add_number || (n & ~0x1ff) != 0) 2667 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 2668 else 2669 opcode |= e.X_add_number << 5; 2670 } 2671 else 2672 as_bad (_("non-immediate OPF operand, ignored")); 2673 s = input_line_pointer; 2674 input_line_pointer = push; 2675 continue; 2676 } 2677 2678 case 'y': 2679 if (strncmp (s, "%y", 2) != 0) 2680 break; 2681 s += 2; 2682 continue; 2683 2684 case 'u': 2685 case 'U': 2686 { 2687 /* Parse a sparclet cpreg. */ 2688 int cpreg; 2689 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 2690 { 2691 error_message = _(": invalid cpreg name"); 2692 goto error; 2693 } 2694 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 2695 continue; 2696 } 2697 2698 default: 2699 as_fatal (_("failed sanity check.")); 2700 } /* switch on arg code. */ 2701 2702 /* Break out of for() loop. */ 2703 break; 2704 } /* For each arg that we expect. */ 2705 2706 error: 2707 if (match == 0) 2708 { 2709 /* Args don't match. */ 2710 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 2711 && (insn->name == insn[1].name 2712 || !strcmp (insn->name, insn[1].name))) 2713 { 2714 ++insn; 2715 s = argsStart; 2716 continue; 2717 } 2718 else 2719 { 2720 as_bad (_("Illegal operands%s"), error_message); 2721 return special_case; 2722 } 2723 } 2724 else 2725 { 2726 /* We have a match. Now see if the architecture is OK. */ 2727 int needed_arch_mask = insn->architecture; 2728 2729 if (v9_arg_p) 2730 { 2731 needed_arch_mask &= 2732 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 2733 if (! needed_arch_mask) 2734 needed_arch_mask = 2735 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 2736 } 2737 2738 if (needed_arch_mask 2739 & SPARC_OPCODE_SUPPORTED (current_architecture)) 2740 /* OK. */ 2741 ; 2742 /* Can we bump up the architecture? */ 2743 else if (needed_arch_mask 2744 & SPARC_OPCODE_SUPPORTED (max_architecture)) 2745 { 2746 enum sparc_opcode_arch_val needed_architecture = 2747 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 2748 & needed_arch_mask); 2749 2750 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 2751 if (warn_on_bump 2752 && needed_architecture > warn_after_architecture) 2753 { 2754 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 2755 sparc_opcode_archs[current_architecture].name, 2756 sparc_opcode_archs[needed_architecture].name, 2757 str); 2758 warn_after_architecture = needed_architecture; 2759 } 2760 current_architecture = needed_architecture; 2761 } 2762 /* Conflict. */ 2763 /* ??? This seems to be a bit fragile. What if the next entry in 2764 the opcode table is the one we want and it is supported? 2765 It is possible to arrange the table today so that this can't 2766 happen but what about tomorrow? */ 2767 else 2768 { 2769 int arch, printed_one_p = 0; 2770 char *p; 2771 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 2772 2773 /* Create a list of the architectures that support the insn. */ 2774 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 2775 p = required_archs; 2776 arch = sparc_ffs (needed_arch_mask); 2777 while ((1 << arch) <= needed_arch_mask) 2778 { 2779 if ((1 << arch) & needed_arch_mask) 2780 { 2781 if (printed_one_p) 2782 *p++ = '|'; 2783 strcpy (p, sparc_opcode_archs[arch].name); 2784 p += strlen (p); 2785 printed_one_p = 1; 2786 } 2787 ++arch; 2788 } 2789 2790 as_bad (_("Architecture mismatch on \"%s\"."), str); 2791 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 2792 required_archs, 2793 sparc_opcode_archs[max_architecture].name); 2794 return special_case; 2795 } 2796 } /* If no match. */ 2797 2798 break; 2799 } /* Forever looking for a match. */ 2800 2801 the_insn.opcode = opcode; 2802 return special_case; 2803 } 2804 2805 /* Parse an argument that can be expressed as a keyword. 2806 (eg: #StoreStore or %ccfr). 2807 The result is a boolean indicating success. 2808 If successful, INPUT_POINTER is updated. */ 2809 2810 static int 2811 parse_keyword_arg (lookup_fn, input_pointerP, valueP) 2812 int (*lookup_fn) PARAMS ((const char *)); 2813 char **input_pointerP; 2814 int *valueP; 2815 { 2816 int value; 2817 char c, *p, *q; 2818 2819 p = *input_pointerP; 2820 for (q = p + (*p == '#' || *p == '%'); 2821 ISALNUM (*q) || *q == '_'; 2822 ++q) 2823 continue; 2824 c = *q; 2825 *q = 0; 2826 value = (*lookup_fn) (p); 2827 *q = c; 2828 if (value == -1) 2829 return 0; 2830 *valueP = value; 2831 *input_pointerP = q; 2832 return 1; 2833 } 2834 2835 /* Parse an argument that is a constant expression. 2836 The result is a boolean indicating success. */ 2837 2838 static int 2839 parse_const_expr_arg (input_pointerP, valueP) 2840 char **input_pointerP; 2841 int *valueP; 2842 { 2843 char *save = input_line_pointer; 2844 expressionS exp; 2845 2846 input_line_pointer = *input_pointerP; 2847 /* The next expression may be something other than a constant 2848 (say if we're not processing the right variant of the insn). 2849 Don't call expression unless we're sure it will succeed as it will 2850 signal an error (which we want to defer until later). */ 2851 /* FIXME: It might be better to define md_operand and have it recognize 2852 things like %asi, etc. but continuing that route through to the end 2853 is a lot of work. */ 2854 if (*input_line_pointer == '%') 2855 { 2856 input_line_pointer = save; 2857 return 0; 2858 } 2859 expression (&exp); 2860 *input_pointerP = input_line_pointer; 2861 input_line_pointer = save; 2862 if (exp.X_op != O_constant) 2863 return 0; 2864 *valueP = exp.X_add_number; 2865 return 1; 2866 } 2867 2868 /* Subroutine of sparc_ip to parse an expression. */ 2869 2870 static int 2871 get_expression (str) 2872 char *str; 2873 { 2874 char *save_in; 2875 segT seg; 2876 2877 save_in = input_line_pointer; 2878 input_line_pointer = str; 2879 seg = expression (&the_insn.exp); 2880 if (seg != absolute_section 2881 && seg != text_section 2882 && seg != data_section 2883 && seg != bss_section 2884 && seg != undefined_section) 2885 { 2886 the_insn.error = _("bad segment"); 2887 expr_end = input_line_pointer; 2888 input_line_pointer = save_in; 2889 return 1; 2890 } 2891 expr_end = input_line_pointer; 2892 input_line_pointer = save_in; 2893 return 0; 2894 } 2895 2896 /* Subroutine of md_assemble to output one insn. */ 2897 2898 static void 2899 output_insn (insn, the_insn) 2900 const struct sparc_opcode *insn; 2901 struct sparc_it *the_insn; 2902 { 2903 char *toP = frag_more (4); 2904 2905 /* Put out the opcode. */ 2906 if (INSN_BIG_ENDIAN) 2907 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); 2908 else 2909 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); 2910 2911 /* Put out the symbol-dependent stuff. */ 2912 if (the_insn->reloc != BFD_RELOC_NONE) 2913 { 2914 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 2915 (toP - frag_now->fr_literal), /* Where. */ 2916 4, /* Size. */ 2917 &the_insn->exp, 2918 the_insn->pcrel, 2919 the_insn->reloc); 2920 /* Turn off overflow checking in fixup_segment. We'll do our 2921 own overflow checking in md_apply_fix. This is necessary because 2922 the insn size is 4 and fixup_segment will signal an overflow for 2923 large 8 byte quantities. */ 2924 fixP->fx_no_overflow = 1; 2925 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10) 2926 fixP->tc_fix_data = the_insn->exp2.X_add_number; 2927 } 2928 2929 last_insn = insn; 2930 last_opcode = the_insn->opcode; 2931 2932 #ifdef OBJ_ELF 2933 dwarf2_emit_insn (4); 2934 #endif 2935 } 2936 2937 /* This is identical to the md_atof in m68k.c. I think this is right, 2938 but I'm not sure. 2939 2940 Turn a string in input_line_pointer into a floating point constant 2941 of type TYPE, and store the appropriate bytes in *LITP. The number 2942 of LITTLENUMS emitted is stored in *SIZEP. An error message is 2943 returned, or NULL on OK. */ 2944 2945 /* Equal to MAX_PRECISION in atof-ieee.c. */ 2946 #define MAX_LITTLENUMS 6 2947 2948 char * 2949 md_atof (type, litP, sizeP) 2950 char type; 2951 char *litP; 2952 int *sizeP; 2953 { 2954 int i, prec; 2955 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 2956 char *t; 2957 2958 switch (type) 2959 { 2960 case 'f': 2961 case 'F': 2962 case 's': 2963 case 'S': 2964 prec = 2; 2965 break; 2966 2967 case 'd': 2968 case 'D': 2969 case 'r': 2970 case 'R': 2971 prec = 4; 2972 break; 2973 2974 case 'x': 2975 case 'X': 2976 prec = 6; 2977 break; 2978 2979 case 'p': 2980 case 'P': 2981 prec = 6; 2982 break; 2983 2984 default: 2985 *sizeP = 0; 2986 return _("Bad call to MD_ATOF()"); 2987 } 2988 2989 t = atof_ieee (input_line_pointer, type, words); 2990 if (t) 2991 input_line_pointer = t; 2992 *sizeP = prec * sizeof (LITTLENUM_TYPE); 2993 2994 if (target_big_endian) 2995 { 2996 for (i = 0; i < prec; i++) 2997 { 2998 md_number_to_chars (litP, (valueT) words[i], 2999 sizeof (LITTLENUM_TYPE)); 3000 litP += sizeof (LITTLENUM_TYPE); 3001 } 3002 } 3003 else 3004 { 3005 for (i = prec - 1; i >= 0; i--) 3006 { 3007 md_number_to_chars (litP, (valueT) words[i], 3008 sizeof (LITTLENUM_TYPE)); 3009 litP += sizeof (LITTLENUM_TYPE); 3010 } 3011 } 3012 3013 return 0; 3014 } 3015 3016 /* Write a value out to the object file, using the appropriate 3017 endianness. */ 3018 3019 void 3020 md_number_to_chars (buf, val, n) 3021 char *buf; 3022 valueT val; 3023 int n; 3024 { 3025 if (target_big_endian) 3026 number_to_chars_bigendian (buf, val, n); 3027 else if (target_little_endian_data 3028 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 3029 /* Output debug words, which are not in allocated sections, as big 3030 endian. */ 3031 number_to_chars_bigendian (buf, val, n); 3032 else if (target_little_endian_data || ! target_big_endian) 3033 number_to_chars_littleendian (buf, val, n); 3034 } 3035 3036 /* Apply a fixS to the frags, now that we know the value it ought to 3037 hold. */ 3038 3039 void 3040 md_apply_fix (fixP, valP, segment) 3041 fixS *fixP; 3042 valueT *valP; 3043 segT segment ATTRIBUTE_UNUSED; 3044 { 3045 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 3046 offsetT val = * (offsetT *) valP; 3047 long insn; 3048 3049 assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 3050 3051 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 3052 3053 #ifdef OBJ_ELF 3054 /* SPARC ELF relocations don't use an addend in the data field. */ 3055 if (fixP->fx_addsy != NULL) 3056 { 3057 switch (fixP->fx_r_type) 3058 { 3059 case BFD_RELOC_SPARC_TLS_GD_HI22: 3060 case BFD_RELOC_SPARC_TLS_GD_LO10: 3061 case BFD_RELOC_SPARC_TLS_GD_ADD: 3062 case BFD_RELOC_SPARC_TLS_GD_CALL: 3063 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3064 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3065 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3066 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3067 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3068 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3069 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3070 case BFD_RELOC_SPARC_TLS_IE_HI22: 3071 case BFD_RELOC_SPARC_TLS_IE_LO10: 3072 case BFD_RELOC_SPARC_TLS_IE_LD: 3073 case BFD_RELOC_SPARC_TLS_IE_LDX: 3074 case BFD_RELOC_SPARC_TLS_IE_ADD: 3075 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3076 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3077 case BFD_RELOC_SPARC_TLS_DTPMOD32: 3078 case BFD_RELOC_SPARC_TLS_DTPMOD64: 3079 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3080 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3081 case BFD_RELOC_SPARC_TLS_TPOFF32: 3082 case BFD_RELOC_SPARC_TLS_TPOFF64: 3083 S_SET_THREAD_LOCAL (fixP->fx_addsy); 3084 3085 default: 3086 break; 3087 } 3088 3089 return; 3090 } 3091 #endif 3092 3093 /* This is a hack. There should be a better way to 3094 handle this. Probably in terms of howto fields, once 3095 we can look at these fixups in terms of howtos. */ 3096 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 3097 val += fixP->fx_where + fixP->fx_frag->fr_address; 3098 3099 #ifdef OBJ_AOUT 3100 /* FIXME: More ridiculous gas reloc hacking. If we are going to 3101 generate a reloc, then we just want to let the reloc addend set 3102 the value. We do not want to also stuff the addend into the 3103 object file. Including the addend in the object file works when 3104 doing a static link, because the linker will ignore the object 3105 file contents. However, the dynamic linker does not ignore the 3106 object file contents. */ 3107 if (fixP->fx_addsy != NULL 3108 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 3109 val = 0; 3110 3111 /* When generating PIC code, we do not want an addend for a reloc 3112 against a local symbol. We adjust fx_addnumber to cancel out the 3113 value already included in val, and to also cancel out the 3114 adjustment which bfd_install_relocation will create. */ 3115 if (sparc_pic_code 3116 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 3117 && fixP->fx_addsy != NULL 3118 && ! S_IS_COMMON (fixP->fx_addsy) 3119 && symbol_section_p (fixP->fx_addsy)) 3120 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3121 3122 /* When generating PIC code, we need to fiddle to get 3123 bfd_install_relocation to do the right thing for a PC relative 3124 reloc against a local symbol which we are going to keep. */ 3125 if (sparc_pic_code 3126 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 3127 && fixP->fx_addsy != NULL 3128 && (S_IS_EXTERNAL (fixP->fx_addsy) 3129 || S_IS_WEAK (fixP->fx_addsy)) 3130 && S_IS_DEFINED (fixP->fx_addsy) 3131 && ! S_IS_COMMON (fixP->fx_addsy)) 3132 { 3133 val = 0; 3134 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3135 } 3136 #endif 3137 3138 /* If this is a data relocation, just output VAL. */ 3139 3140 if (fixP->fx_r_type == BFD_RELOC_16 3141 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 3142 { 3143 md_number_to_chars (buf, val, 2); 3144 } 3145 else if (fixP->fx_r_type == BFD_RELOC_32 3146 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 3147 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 3148 { 3149 md_number_to_chars (buf, val, 4); 3150 } 3151 else if (fixP->fx_r_type == BFD_RELOC_64 3152 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 3153 { 3154 md_number_to_chars (buf, val, 8); 3155 } 3156 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3157 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3158 { 3159 fixP->fx_done = 0; 3160 return; 3161 } 3162 else 3163 { 3164 /* It's a relocation against an instruction. */ 3165 3166 if (INSN_BIG_ENDIAN) 3167 insn = bfd_getb32 ((unsigned char *) buf); 3168 else 3169 insn = bfd_getl32 ((unsigned char *) buf); 3170 3171 switch (fixP->fx_r_type) 3172 { 3173 case BFD_RELOC_32_PCREL_S2: 3174 val = val >> 2; 3175 /* FIXME: This increment-by-one deserves a comment of why it's 3176 being done! */ 3177 if (! sparc_pic_code 3178 || fixP->fx_addsy == NULL 3179 || symbol_section_p (fixP->fx_addsy)) 3180 ++val; 3181 3182 insn |= val & 0x3fffffff; 3183 3184 /* See if we have a delay slot. */ 3185 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3186 { 3187 #define G0 0 3188 #define O7 15 3189 #define XCC (2 << 20) 3190 #define COND(x) (((x)&0xf)<<25) 3191 #define CONDA COND(0x8) 3192 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3193 #define INSN_BA (F2(0,2) | CONDA) 3194 #define INSN_OR F3(2, 0x2, 0) 3195 #define INSN_NOP F2(0,4) 3196 3197 long delay; 3198 3199 /* If the instruction is a call with either: 3200 restore 3201 arithmetic instruction with rd == %o7 3202 where rs1 != %o7 and rs2 if it is register != %o7 3203 then we can optimize if the call destination is near 3204 by changing the call into a branch always. */ 3205 if (INSN_BIG_ENDIAN) 3206 delay = bfd_getb32 ((unsigned char *) buf + 4); 3207 else 3208 delay = bfd_getl32 ((unsigned char *) buf + 4); 3209 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3210 break; 3211 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3212 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3213 || ((delay & RD (~0)) != RD (O7)))) 3214 break; 3215 if ((delay & RS1 (~0)) == RS1 (O7) 3216 || ((delay & F3I (~0)) == 0 3217 && (delay & RS2 (~0)) == RS2 (O7))) 3218 break; 3219 /* Ensure the branch will fit into simm22. */ 3220 if ((val & 0x3fe00000) 3221 && (val & 0x3fe00000) != 0x3fe00000) 3222 break; 3223 /* Check if the arch is v9 and branch will fit 3224 into simm19. */ 3225 if (((val & 0x3c0000) == 0 3226 || (val & 0x3c0000) == 0x3c0000) 3227 && (sparc_arch_size == 64 3228 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3229 /* ba,pt %xcc */ 3230 insn = INSN_BPA | (val & 0x7ffff); 3231 else 3232 /* ba */ 3233 insn = INSN_BA | (val & 0x3fffff); 3234 if (fixP->fx_where >= 4 3235 && ((delay & (0xffffffff ^ RS1 (~0))) 3236 == (INSN_OR | RD (O7) | RS2 (G0)))) 3237 { 3238 long setter; 3239 int reg; 3240 3241 if (INSN_BIG_ENDIAN) 3242 setter = bfd_getb32 ((unsigned char *) buf - 4); 3243 else 3244 setter = bfd_getl32 ((unsigned char *) buf - 4); 3245 if ((setter & (0xffffffff ^ RD (~0))) 3246 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3247 break; 3248 /* The sequence was 3249 or %o7, %g0, %rN 3250 call foo 3251 or %rN, %g0, %o7 3252 3253 If call foo was replaced with ba, replace 3254 or %rN, %g0, %o7 with nop. */ 3255 reg = (delay & RS1 (~0)) >> 14; 3256 if (reg != ((setter & RD (~0)) >> 25) 3257 || reg == G0 || reg == O7) 3258 break; 3259 3260 if (INSN_BIG_ENDIAN) 3261 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3262 else 3263 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3264 } 3265 } 3266 break; 3267 3268 case BFD_RELOC_SPARC_11: 3269 if (! in_signed_range (val, 0x7ff)) 3270 as_bad_where (fixP->fx_file, fixP->fx_line, 3271 _("relocation overflow")); 3272 insn |= val & 0x7ff; 3273 break; 3274 3275 case BFD_RELOC_SPARC_10: 3276 if (! in_signed_range (val, 0x3ff)) 3277 as_bad_where (fixP->fx_file, fixP->fx_line, 3278 _("relocation overflow")); 3279 insn |= val & 0x3ff; 3280 break; 3281 3282 case BFD_RELOC_SPARC_7: 3283 if (! in_bitfield_range (val, 0x7f)) 3284 as_bad_where (fixP->fx_file, fixP->fx_line, 3285 _("relocation overflow")); 3286 insn |= val & 0x7f; 3287 break; 3288 3289 case BFD_RELOC_SPARC_6: 3290 if (! in_bitfield_range (val, 0x3f)) 3291 as_bad_where (fixP->fx_file, fixP->fx_line, 3292 _("relocation overflow")); 3293 insn |= val & 0x3f; 3294 break; 3295 3296 case BFD_RELOC_SPARC_5: 3297 if (! in_bitfield_range (val, 0x1f)) 3298 as_bad_where (fixP->fx_file, fixP->fx_line, 3299 _("relocation overflow")); 3300 insn |= val & 0x1f; 3301 break; 3302 3303 case BFD_RELOC_SPARC_WDISP16: 3304 /* FIXME: simplify. */ 3305 if (((val > 0) && (val & ~0x3fffc)) 3306 || ((val < 0) && (~(val - 1) & ~0x3fffc))) 3307 as_bad_where (fixP->fx_file, fixP->fx_line, 3308 _("relocation overflow")); 3309 /* FIXME: The +1 deserves a comment. */ 3310 val = (val >> 2) + 1; 3311 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3312 break; 3313 3314 case BFD_RELOC_SPARC_WDISP19: 3315 /* FIXME: simplify. */ 3316 if (((val > 0) && (val & ~0x1ffffc)) 3317 || ((val < 0) && (~(val - 1) & ~0x1ffffc))) 3318 as_bad_where (fixP->fx_file, fixP->fx_line, 3319 _("relocation overflow")); 3320 /* FIXME: The +1 deserves a comment. */ 3321 val = (val >> 2) + 1; 3322 insn |= val & 0x7ffff; 3323 break; 3324 3325 case BFD_RELOC_SPARC_HH22: 3326 val = BSR (val, 32); 3327 /* Fall through. */ 3328 3329 case BFD_RELOC_SPARC_LM22: 3330 case BFD_RELOC_HI22: 3331 if (!fixP->fx_addsy) 3332 insn |= (val >> 10) & 0x3fffff; 3333 else 3334 /* FIXME: Need comment explaining why we do this. */ 3335 insn &= ~0xffff; 3336 break; 3337 3338 case BFD_RELOC_SPARC22: 3339 if (val & ~0x003fffff) 3340 as_bad_where (fixP->fx_file, fixP->fx_line, 3341 _("relocation overflow")); 3342 insn |= (val & 0x3fffff); 3343 break; 3344 3345 case BFD_RELOC_SPARC_HM10: 3346 val = BSR (val, 32); 3347 /* Fall through. */ 3348 3349 case BFD_RELOC_LO10: 3350 if (!fixP->fx_addsy) 3351 insn |= val & 0x3ff; 3352 else 3353 /* FIXME: Need comment explaining why we do this. */ 3354 insn &= ~0xff; 3355 break; 3356 3357 case BFD_RELOC_SPARC_OLO10: 3358 val &= 0x3ff; 3359 val += fixP->tc_fix_data; 3360 /* Fall through. */ 3361 3362 case BFD_RELOC_SPARC13: 3363 if (! in_signed_range (val, 0x1fff)) 3364 as_bad_where (fixP->fx_file, fixP->fx_line, 3365 _("relocation overflow")); 3366 insn |= val & 0x1fff; 3367 break; 3368 3369 case BFD_RELOC_SPARC_WDISP22: 3370 val = (val >> 2) + 1; 3371 /* Fall through. */ 3372 case BFD_RELOC_SPARC_BASE22: 3373 insn |= val & 0x3fffff; 3374 break; 3375 3376 case BFD_RELOC_SPARC_H44: 3377 if (!fixP->fx_addsy) 3378 { 3379 bfd_vma tval = val; 3380 tval >>= 22; 3381 insn |= tval & 0x3fffff; 3382 } 3383 break; 3384 3385 case BFD_RELOC_SPARC_M44: 3386 if (!fixP->fx_addsy) 3387 insn |= (val >> 12) & 0x3ff; 3388 break; 3389 3390 case BFD_RELOC_SPARC_L44: 3391 if (!fixP->fx_addsy) 3392 insn |= val & 0xfff; 3393 break; 3394 3395 case BFD_RELOC_SPARC_HIX22: 3396 if (!fixP->fx_addsy) 3397 { 3398 val ^= ~(offsetT) 0; 3399 insn |= (val >> 10) & 0x3fffff; 3400 } 3401 break; 3402 3403 case BFD_RELOC_SPARC_LOX10: 3404 if (!fixP->fx_addsy) 3405 insn |= 0x1c00 | (val & 0x3ff); 3406 break; 3407 3408 case BFD_RELOC_NONE: 3409 default: 3410 as_bad_where (fixP->fx_file, fixP->fx_line, 3411 _("bad or unhandled relocation type: 0x%02x"), 3412 fixP->fx_r_type); 3413 break; 3414 } 3415 3416 if (INSN_BIG_ENDIAN) 3417 bfd_putb32 (insn, (unsigned char *) buf); 3418 else 3419 bfd_putl32 (insn, (unsigned char *) buf); 3420 } 3421 3422 /* Are we finished with this relocation now? */ 3423 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3424 fixP->fx_done = 1; 3425 } 3426 3427 /* Translate internal representation of relocation info to BFD target 3428 format. */ 3429 3430 arelent ** 3431 tc_gen_reloc (section, fixp) 3432 asection *section ATTRIBUTE_UNUSED; 3433 fixS *fixp; 3434 { 3435 static arelent *relocs[3]; 3436 arelent *reloc; 3437 bfd_reloc_code_real_type code; 3438 3439 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3440 relocs[1] = NULL; 3441 3442 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3443 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3444 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3445 3446 switch (fixp->fx_r_type) 3447 { 3448 case BFD_RELOC_16: 3449 case BFD_RELOC_32: 3450 case BFD_RELOC_HI22: 3451 case BFD_RELOC_LO10: 3452 case BFD_RELOC_32_PCREL_S2: 3453 case BFD_RELOC_SPARC13: 3454 case BFD_RELOC_SPARC22: 3455 case BFD_RELOC_SPARC_BASE13: 3456 case BFD_RELOC_SPARC_WDISP16: 3457 case BFD_RELOC_SPARC_WDISP19: 3458 case BFD_RELOC_SPARC_WDISP22: 3459 case BFD_RELOC_64: 3460 case BFD_RELOC_SPARC_5: 3461 case BFD_RELOC_SPARC_6: 3462 case BFD_RELOC_SPARC_7: 3463 case BFD_RELOC_SPARC_10: 3464 case BFD_RELOC_SPARC_11: 3465 case BFD_RELOC_SPARC_HH22: 3466 case BFD_RELOC_SPARC_HM10: 3467 case BFD_RELOC_SPARC_LM22: 3468 case BFD_RELOC_SPARC_PC_HH22: 3469 case BFD_RELOC_SPARC_PC_HM10: 3470 case BFD_RELOC_SPARC_PC_LM22: 3471 case BFD_RELOC_SPARC_H44: 3472 case BFD_RELOC_SPARC_M44: 3473 case BFD_RELOC_SPARC_L44: 3474 case BFD_RELOC_SPARC_HIX22: 3475 case BFD_RELOC_SPARC_LOX10: 3476 case BFD_RELOC_SPARC_REV32: 3477 case BFD_RELOC_SPARC_OLO10: 3478 case BFD_RELOC_SPARC_UA16: 3479 case BFD_RELOC_SPARC_UA32: 3480 case BFD_RELOC_SPARC_UA64: 3481 case BFD_RELOC_8_PCREL: 3482 case BFD_RELOC_16_PCREL: 3483 case BFD_RELOC_32_PCREL: 3484 case BFD_RELOC_64_PCREL: 3485 case BFD_RELOC_SPARC_PLT32: 3486 case BFD_RELOC_SPARC_PLT64: 3487 case BFD_RELOC_VTABLE_ENTRY: 3488 case BFD_RELOC_VTABLE_INHERIT: 3489 case BFD_RELOC_SPARC_TLS_GD_HI22: 3490 case BFD_RELOC_SPARC_TLS_GD_LO10: 3491 case BFD_RELOC_SPARC_TLS_GD_ADD: 3492 case BFD_RELOC_SPARC_TLS_GD_CALL: 3493 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3494 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3495 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3496 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3497 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3498 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3499 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3500 case BFD_RELOC_SPARC_TLS_IE_HI22: 3501 case BFD_RELOC_SPARC_TLS_IE_LO10: 3502 case BFD_RELOC_SPARC_TLS_IE_LD: 3503 case BFD_RELOC_SPARC_TLS_IE_LDX: 3504 case BFD_RELOC_SPARC_TLS_IE_ADD: 3505 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3506 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3507 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3508 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3509 code = fixp->fx_r_type; 3510 break; 3511 default: 3512 abort (); 3513 return NULL; 3514 } 3515 3516 #if defined (OBJ_ELF) || defined (OBJ_AOUT) 3517 /* If we are generating PIC code, we need to generate a different 3518 set of relocs. */ 3519 3520 #ifdef OBJ_ELF 3521 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3522 #else 3523 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3524 #endif 3525 #ifdef TE_VXWORKS 3526 #define GOTT_BASE "__GOTT_BASE__" 3527 #define GOTT_INDEX "__GOTT_INDEX__" 3528 #endif 3529 3530 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3531 3532 if (sparc_pic_code) 3533 { 3534 switch (code) 3535 { 3536 case BFD_RELOC_32_PCREL_S2: 3537 if (generic_force_reloc (fixp)) 3538 code = BFD_RELOC_SPARC_WPLT30; 3539 break; 3540 case BFD_RELOC_HI22: 3541 code = BFD_RELOC_SPARC_GOT22; 3542 if (fixp->fx_addsy != NULL) 3543 { 3544 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3545 code = BFD_RELOC_SPARC_PC22; 3546 #ifdef TE_VXWORKS 3547 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3548 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3549 code = BFD_RELOC_HI22; /* Unchanged. */ 3550 #endif 3551 } 3552 break; 3553 case BFD_RELOC_LO10: 3554 code = BFD_RELOC_SPARC_GOT10; 3555 if (fixp->fx_addsy != NULL) 3556 { 3557 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3558 code = BFD_RELOC_SPARC_PC10; 3559 #ifdef TE_VXWORKS 3560 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3561 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3562 code = BFD_RELOC_LO10; /* Unchanged. */ 3563 #endif 3564 } 3565 break; 3566 case BFD_RELOC_SPARC13: 3567 code = BFD_RELOC_SPARC_GOT13; 3568 break; 3569 default: 3570 break; 3571 } 3572 } 3573 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3574 3575 if (code == BFD_RELOC_SPARC_OLO10) 3576 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3577 else 3578 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3579 if (reloc->howto == 0) 3580 { 3581 as_bad_where (fixp->fx_file, fixp->fx_line, 3582 _("internal error: can't export reloc type %d (`%s')"), 3583 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3584 xfree (reloc); 3585 relocs[0] = NULL; 3586 return relocs; 3587 } 3588 3589 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3590 #ifdef OBJ_AOUT 3591 3592 if (reloc->howto->pc_relative == 0 3593 || code == BFD_RELOC_SPARC_PC10 3594 || code == BFD_RELOC_SPARC_PC22) 3595 reloc->addend = fixp->fx_addnumber; 3596 else if (sparc_pic_code 3597 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3598 && fixp->fx_addsy != NULL 3599 && (S_IS_EXTERNAL (fixp->fx_addsy) 3600 || S_IS_WEAK (fixp->fx_addsy)) 3601 && S_IS_DEFINED (fixp->fx_addsy) 3602 && ! S_IS_COMMON (fixp->fx_addsy)) 3603 reloc->addend = fixp->fx_addnumber; 3604 else 3605 reloc->addend = fixp->fx_offset - reloc->address; 3606 3607 #else /* elf or coff */ 3608 3609 if (code != BFD_RELOC_32_PCREL_S2 3610 && code != BFD_RELOC_SPARC_WDISP22 3611 && code != BFD_RELOC_SPARC_WDISP16 3612 && code != BFD_RELOC_SPARC_WDISP19 3613 && code != BFD_RELOC_SPARC_WPLT30 3614 && code != BFD_RELOC_SPARC_TLS_GD_CALL 3615 && code != BFD_RELOC_SPARC_TLS_LDM_CALL) 3616 reloc->addend = fixp->fx_addnumber; 3617 else if (symbol_section_p (fixp->fx_addsy)) 3618 reloc->addend = (section->vma 3619 + fixp->fx_addnumber 3620 + md_pcrel_from (fixp)); 3621 else 3622 reloc->addend = fixp->fx_offset; 3623 #endif 3624 3625 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 3626 on the same location. */ 3627 if (code == BFD_RELOC_SPARC_OLO10) 3628 { 3629 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3630 relocs[2] = NULL; 3631 3632 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3633 *reloc->sym_ptr_ptr 3634 = symbol_get_bfdsym (section_symbol (absolute_section)); 3635 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3636 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 3637 reloc->addend = fixp->tc_fix_data; 3638 } 3639 3640 return relocs; 3641 } 3642 3643 /* We have no need to default values of symbols. */ 3644 3645 symbolS * 3646 md_undefined_symbol (name) 3647 char *name ATTRIBUTE_UNUSED; 3648 { 3649 return 0; 3650 } 3651 3652 /* Round up a section size to the appropriate boundary. */ 3653 3654 valueT 3655 md_section_align (segment, size) 3656 segT segment ATTRIBUTE_UNUSED; 3657 valueT size; 3658 { 3659 #ifndef OBJ_ELF 3660 /* This is not right for ELF; a.out wants it, and COFF will force 3661 the alignment anyways. */ 3662 valueT align = ((valueT) 1 3663 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 3664 valueT newsize; 3665 3666 /* Turn alignment value into a mask. */ 3667 align--; 3668 newsize = (size + align) & ~align; 3669 return newsize; 3670 #else 3671 return size; 3672 #endif 3673 } 3674 3675 /* Exactly what point is a PC-relative offset relative TO? 3676 On the sparc, they're relative to the address of the offset, plus 3677 its size. This gets us to the following instruction. 3678 (??? Is this right? FIXME-SOON) */ 3679 long 3680 md_pcrel_from (fixP) 3681 fixS *fixP; 3682 { 3683 long ret; 3684 3685 ret = fixP->fx_where + fixP->fx_frag->fr_address; 3686 if (! sparc_pic_code 3687 || fixP->fx_addsy == NULL 3688 || symbol_section_p (fixP->fx_addsy)) 3689 ret += fixP->fx_size; 3690 return ret; 3691 } 3692 3693 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 3694 of two. */ 3695 3696 static int 3697 mylog2 (value) 3698 int value; 3699 { 3700 int shift; 3701 3702 if (value <= 0) 3703 return -1; 3704 3705 for (shift = 0; (value & 1) == 0; value >>= 1) 3706 ++shift; 3707 3708 return (value == 1) ? shift : -1; 3709 } 3710 3711 /* Sort of like s_lcomm. */ 3712 3713 #ifndef OBJ_ELF 3714 static int max_alignment = 15; 3715 #endif 3716 3717 static void 3718 s_reserve (ignore) 3719 int ignore ATTRIBUTE_UNUSED; 3720 { 3721 char *name; 3722 char *p; 3723 char c; 3724 int align; 3725 int size; 3726 int temp; 3727 symbolS *symbolP; 3728 3729 name = input_line_pointer; 3730 c = get_symbol_end (); 3731 p = input_line_pointer; 3732 *p = c; 3733 SKIP_WHITESPACE (); 3734 3735 if (*input_line_pointer != ',') 3736 { 3737 as_bad (_("Expected comma after name")); 3738 ignore_rest_of_line (); 3739 return; 3740 } 3741 3742 ++input_line_pointer; 3743 3744 if ((size = get_absolute_expression ()) < 0) 3745 { 3746 as_bad (_("BSS length (%d.) <0! Ignored."), size); 3747 ignore_rest_of_line (); 3748 return; 3749 } /* Bad length. */ 3750 3751 *p = 0; 3752 symbolP = symbol_find_or_make (name); 3753 *p = c; 3754 3755 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 3756 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 3757 { 3758 as_bad (_("bad .reserve segment -- expected BSS segment")); 3759 return; 3760 } 3761 3762 if (input_line_pointer[2] == '.') 3763 input_line_pointer += 7; 3764 else 3765 input_line_pointer += 6; 3766 SKIP_WHITESPACE (); 3767 3768 if (*input_line_pointer == ',') 3769 { 3770 ++input_line_pointer; 3771 3772 SKIP_WHITESPACE (); 3773 if (*input_line_pointer == '\n') 3774 { 3775 as_bad (_("missing alignment")); 3776 ignore_rest_of_line (); 3777 return; 3778 } 3779 3780 align = (int) get_absolute_expression (); 3781 3782 #ifndef OBJ_ELF 3783 if (align > max_alignment) 3784 { 3785 align = max_alignment; 3786 as_warn (_("alignment too large; assuming %d"), align); 3787 } 3788 #endif 3789 3790 if (align < 0) 3791 { 3792 as_bad (_("negative alignment")); 3793 ignore_rest_of_line (); 3794 return; 3795 } 3796 3797 if (align != 0) 3798 { 3799 temp = mylog2 (align); 3800 if (temp < 0) 3801 { 3802 as_bad (_("alignment not a power of 2")); 3803 ignore_rest_of_line (); 3804 return; 3805 } 3806 3807 align = temp; 3808 } 3809 3810 record_alignment (bss_section, align); 3811 } 3812 else 3813 align = 0; 3814 3815 if (!S_IS_DEFINED (symbolP) 3816 #ifdef OBJ_AOUT 3817 && S_GET_OTHER (symbolP) == 0 3818 && S_GET_DESC (symbolP) == 0 3819 #endif 3820 ) 3821 { 3822 if (! need_pass_2) 3823 { 3824 char *pfrag; 3825 segT current_seg = now_seg; 3826 subsegT current_subseg = now_subseg; 3827 3828 /* Switch to bss. */ 3829 subseg_set (bss_section, 1); 3830 3831 if (align) 3832 /* Do alignment. */ 3833 frag_align (align, 0, 0); 3834 3835 /* Detach from old frag. */ 3836 if (S_GET_SEGMENT (symbolP) == bss_section) 3837 symbol_get_frag (symbolP)->fr_symbol = NULL; 3838 3839 symbol_set_frag (symbolP, frag_now); 3840 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3841 (offsetT) size, (char *) 0); 3842 *pfrag = 0; 3843 3844 S_SET_SEGMENT (symbolP, bss_section); 3845 3846 subseg_set (current_seg, current_subseg); 3847 3848 #ifdef OBJ_ELF 3849 S_SET_SIZE (symbolP, size); 3850 #endif 3851 } 3852 } 3853 else 3854 { 3855 as_warn ("Ignoring attempt to re-define symbol %s", 3856 S_GET_NAME (symbolP)); 3857 } /* if not redefining. */ 3858 3859 demand_empty_rest_of_line (); 3860 } 3861 3862 static void 3863 s_common (ignore) 3864 int ignore ATTRIBUTE_UNUSED; 3865 { 3866 char *name; 3867 char c; 3868 char *p; 3869 offsetT temp, size; 3870 symbolS *symbolP; 3871 3872 name = input_line_pointer; 3873 c = get_symbol_end (); 3874 /* Just after name is now '\0'. */ 3875 p = input_line_pointer; 3876 *p = c; 3877 SKIP_WHITESPACE (); 3878 if (*input_line_pointer != ',') 3879 { 3880 as_bad (_("Expected comma after symbol-name")); 3881 ignore_rest_of_line (); 3882 return; 3883 } 3884 3885 /* Skip ','. */ 3886 input_line_pointer++; 3887 3888 if ((temp = get_absolute_expression ()) < 0) 3889 { 3890 as_bad (_(".COMMon length (%lu) out of range ignored"), 3891 (unsigned long) temp); 3892 ignore_rest_of_line (); 3893 return; 3894 } 3895 size = temp; 3896 *p = 0; 3897 symbolP = symbol_find_or_make (name); 3898 *p = c; 3899 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 3900 { 3901 as_bad (_("Ignoring attempt to re-define symbol")); 3902 ignore_rest_of_line (); 3903 return; 3904 } 3905 if (S_GET_VALUE (symbolP) != 0) 3906 { 3907 if (S_GET_VALUE (symbolP) != (valueT) size) 3908 { 3909 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), 3910 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); 3911 } 3912 } 3913 else 3914 { 3915 #ifndef OBJ_ELF 3916 S_SET_VALUE (symbolP, (valueT) size); 3917 S_SET_EXTERNAL (symbolP); 3918 #endif 3919 } 3920 know (symbol_get_frag (symbolP) == &zero_address_frag); 3921 if (*input_line_pointer != ',') 3922 { 3923 as_bad (_("Expected comma after common length")); 3924 ignore_rest_of_line (); 3925 return; 3926 } 3927 input_line_pointer++; 3928 SKIP_WHITESPACE (); 3929 if (*input_line_pointer != '"') 3930 { 3931 temp = get_absolute_expression (); 3932 3933 #ifndef OBJ_ELF 3934 if (temp > max_alignment) 3935 { 3936 temp = max_alignment; 3937 as_warn (_("alignment too large; assuming %ld"), (long) temp); 3938 } 3939 #endif 3940 3941 if (temp < 0) 3942 { 3943 as_bad (_("negative alignment")); 3944 ignore_rest_of_line (); 3945 return; 3946 } 3947 3948 #ifdef OBJ_ELF 3949 if (symbol_get_obj (symbolP)->local) 3950 { 3951 segT old_sec; 3952 int old_subsec; 3953 char *p; 3954 int align; 3955 3956 old_sec = now_seg; 3957 old_subsec = now_subseg; 3958 3959 if (temp == 0) 3960 align = 0; 3961 else 3962 align = mylog2 (temp); 3963 3964 if (align < 0) 3965 { 3966 as_bad (_("alignment not a power of 2")); 3967 ignore_rest_of_line (); 3968 return; 3969 } 3970 3971 record_alignment (bss_section, align); 3972 subseg_set (bss_section, 0); 3973 if (align) 3974 frag_align (align, 0, 0); 3975 if (S_GET_SEGMENT (symbolP) == bss_section) 3976 symbol_get_frag (symbolP)->fr_symbol = 0; 3977 symbol_set_frag (symbolP, frag_now); 3978 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3979 (offsetT) size, (char *) 0); 3980 *p = 0; 3981 S_SET_SEGMENT (symbolP, bss_section); 3982 S_CLEAR_EXTERNAL (symbolP); 3983 S_SET_SIZE (symbolP, size); 3984 subseg_set (old_sec, old_subsec); 3985 } 3986 else 3987 #endif /* OBJ_ELF */ 3988 { 3989 allocate_common: 3990 S_SET_VALUE (symbolP, (valueT) size); 3991 #ifdef OBJ_ELF 3992 S_SET_ALIGN (symbolP, temp); 3993 S_SET_SIZE (symbolP, size); 3994 #endif 3995 S_SET_EXTERNAL (symbolP); 3996 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 3997 } 3998 } 3999 else 4000 { 4001 input_line_pointer++; 4002 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 4003 if (*input_line_pointer == '.') 4004 input_line_pointer++; 4005 /* @@ Some say data, some say bss. */ 4006 if (strncmp (input_line_pointer, "bss\"", 4) 4007 && strncmp (input_line_pointer, "data\"", 5)) 4008 { 4009 while (*--input_line_pointer != '"') 4010 ; 4011 input_line_pointer--; 4012 goto bad_common_segment; 4013 } 4014 while (*input_line_pointer++ != '"') 4015 ; 4016 goto allocate_common; 4017 } 4018 4019 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 4020 4021 demand_empty_rest_of_line (); 4022 return; 4023 4024 { 4025 bad_common_segment: 4026 p = input_line_pointer; 4027 while (*p && *p != '\n') 4028 p++; 4029 c = *p; 4030 *p = '\0'; 4031 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 4032 *p = c; 4033 input_line_pointer = p; 4034 ignore_rest_of_line (); 4035 return; 4036 } 4037 } 4038 4039 /* Handle the .empty pseudo-op. This suppresses the warnings about 4040 invalid delay slot usage. */ 4041 4042 static void 4043 s_empty (ignore) 4044 int ignore ATTRIBUTE_UNUSED; 4045 { 4046 /* The easy way to implement is to just forget about the last 4047 instruction. */ 4048 last_insn = NULL; 4049 } 4050 4051 static void 4052 s_seg (ignore) 4053 int ignore ATTRIBUTE_UNUSED; 4054 { 4055 4056 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 4057 { 4058 input_line_pointer += 6; 4059 s_text (0); 4060 return; 4061 } 4062 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 4063 { 4064 input_line_pointer += 6; 4065 s_data (0); 4066 return; 4067 } 4068 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 4069 { 4070 input_line_pointer += 7; 4071 s_data1 (); 4072 return; 4073 } 4074 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 4075 { 4076 input_line_pointer += 5; 4077 /* We only support 2 segments -- text and data -- for now, so 4078 things in the "bss segment" will have to go into data for now. 4079 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 4080 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 4081 return; 4082 } 4083 as_bad (_("Unknown segment type")); 4084 demand_empty_rest_of_line (); 4085 } 4086 4087 static void 4088 s_data1 () 4089 { 4090 subseg_set (data_section, 1); 4091 demand_empty_rest_of_line (); 4092 } 4093 4094 static void 4095 s_proc (ignore) 4096 int ignore ATTRIBUTE_UNUSED; 4097 { 4098 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 4099 { 4100 ++input_line_pointer; 4101 } 4102 ++input_line_pointer; 4103 } 4104 4105 /* This static variable is set by s_uacons to tell sparc_cons_align 4106 that the expression does not need to be aligned. */ 4107 4108 static int sparc_no_align_cons = 0; 4109 4110 /* This static variable is set by sparc_cons to emit requested types 4111 of relocations in cons_fix_new_sparc. */ 4112 4113 static const char *sparc_cons_special_reloc; 4114 4115 /* This handles the unaligned space allocation pseudo-ops, such as 4116 .uaword. .uaword is just like .word, but the value does not need 4117 to be aligned. */ 4118 4119 static void 4120 s_uacons (bytes) 4121 int bytes; 4122 { 4123 /* Tell sparc_cons_align not to align this value. */ 4124 sparc_no_align_cons = 1; 4125 cons (bytes); 4126 sparc_no_align_cons = 0; 4127 } 4128 4129 /* This handles the native word allocation pseudo-op .nword. 4130 For sparc_arch_size 32 it is equivalent to .word, for 4131 sparc_arch_size 64 it is equivalent to .xword. */ 4132 4133 static void 4134 s_ncons (bytes) 4135 int bytes ATTRIBUTE_UNUSED; 4136 { 4137 cons (sparc_arch_size == 32 ? 4 : 8); 4138 } 4139 4140 #ifdef OBJ_ELF 4141 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 4142 global register. 4143 The syntax is: 4144 4145 .register %g[2367],{#scratch|symbolname|#ignore} 4146 */ 4147 4148 static void 4149 s_register (ignore) 4150 int ignore ATTRIBUTE_UNUSED; 4151 { 4152 char c; 4153 int reg; 4154 int flags; 4155 const char *regname; 4156 4157 if (input_line_pointer[0] != '%' 4158 || input_line_pointer[1] != 'g' 4159 || ((input_line_pointer[2] & ~1) != '2' 4160 && (input_line_pointer[2] & ~1) != '6') 4161 || input_line_pointer[3] != ',') 4162 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4163 reg = input_line_pointer[2] - '0'; 4164 input_line_pointer += 4; 4165 4166 if (*input_line_pointer == '#') 4167 { 4168 ++input_line_pointer; 4169 regname = input_line_pointer; 4170 c = get_symbol_end (); 4171 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 4172 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4173 if (regname[0] == 'i') 4174 regname = NULL; 4175 else 4176 regname = ""; 4177 } 4178 else 4179 { 4180 regname = input_line_pointer; 4181 c = get_symbol_end (); 4182 } 4183 if (sparc_arch_size == 64) 4184 { 4185 if (globals[reg]) 4186 { 4187 if ((regname && globals[reg] != (symbolS *) 1 4188 && strcmp (S_GET_NAME (globals[reg]), regname)) 4189 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 4190 as_bad (_("redefinition of global register")); 4191 } 4192 else 4193 { 4194 if (regname == NULL) 4195 globals[reg] = (symbolS *) 1; 4196 else 4197 { 4198 if (*regname) 4199 { 4200 if (symbol_find (regname)) 4201 as_bad (_("Register symbol %s already defined."), 4202 regname); 4203 } 4204 globals[reg] = symbol_make (regname); 4205 flags = symbol_get_bfdsym (globals[reg])->flags; 4206 if (! *regname) 4207 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4208 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4209 flags |= BSF_GLOBAL; 4210 symbol_get_bfdsym (globals[reg])->flags = flags; 4211 S_SET_VALUE (globals[reg], (valueT) reg); 4212 S_SET_ALIGN (globals[reg], reg); 4213 S_SET_SIZE (globals[reg], 0); 4214 /* Although we actually want undefined_section here, 4215 we have to use absolute_section, because otherwise 4216 generic as code will make it a COM section. 4217 We fix this up in sparc_adjust_symtab. */ 4218 S_SET_SEGMENT (globals[reg], absolute_section); 4219 S_SET_OTHER (globals[reg], 0); 4220 elf_symbol (symbol_get_bfdsym (globals[reg])) 4221 ->internal_elf_sym.st_info = 4222 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4223 elf_symbol (symbol_get_bfdsym (globals[reg])) 4224 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4225 } 4226 } 4227 } 4228 4229 *input_line_pointer = c; 4230 4231 demand_empty_rest_of_line (); 4232 } 4233 4234 /* Adjust the symbol table. We set undefined sections for STT_REGISTER 4235 symbols which need it. */ 4236 4237 void 4238 sparc_adjust_symtab () 4239 { 4240 symbolS *sym; 4241 4242 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4243 { 4244 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4245 ->internal_elf_sym.st_info) != STT_REGISTER) 4246 continue; 4247 4248 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4249 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4250 continue; 4251 4252 S_SET_SEGMENT (sym, undefined_section); 4253 } 4254 } 4255 #endif 4256 4257 /* If the --enforce-aligned-data option is used, we require .word, 4258 et. al., to be aligned correctly. We do it by setting up an 4259 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4260 no unexpected alignment was introduced. 4261 4262 The SunOS and Solaris native assemblers enforce aligned data by 4263 default. We don't want to do that, because gcc can deliberately 4264 generate misaligned data if the packed attribute is used. Instead, 4265 we permit misaligned data by default, and permit the user to set an 4266 option to check for it. */ 4267 4268 void 4269 sparc_cons_align (nbytes) 4270 int nbytes; 4271 { 4272 int nalign; 4273 char *p; 4274 4275 /* Only do this if we are enforcing aligned data. */ 4276 if (! enforce_aligned_data) 4277 return; 4278 4279 /* Don't align if this is an unaligned pseudo-op. */ 4280 if (sparc_no_align_cons) 4281 return; 4282 4283 nalign = mylog2 (nbytes); 4284 if (nalign == 0) 4285 return; 4286 4287 assert (nalign > 0); 4288 4289 if (now_seg == absolute_section) 4290 { 4291 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4292 as_bad (_("misaligned data")); 4293 return; 4294 } 4295 4296 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4297 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4298 4299 record_alignment (now_seg, nalign); 4300 } 4301 4302 /* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4303 4304 void 4305 sparc_handle_align (fragp) 4306 fragS *fragp; 4307 { 4308 int count, fix; 4309 char *p; 4310 4311 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4312 4313 switch (fragp->fr_type) 4314 { 4315 case rs_align_test: 4316 if (count != 0) 4317 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4318 break; 4319 4320 case rs_align_code: 4321 p = fragp->fr_literal + fragp->fr_fix; 4322 fix = 0; 4323 4324 if (count & 3) 4325 { 4326 fix = count & 3; 4327 memset (p, 0, fix); 4328 p += fix; 4329 count -= fix; 4330 } 4331 4332 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4333 { 4334 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4335 if (INSN_BIG_ENDIAN) 4336 number_to_chars_bigendian (p, wval, 4); 4337 else 4338 number_to_chars_littleendian (p, wval, 4); 4339 p += 4; 4340 count -= 4; 4341 fix += 4; 4342 } 4343 4344 if (INSN_BIG_ENDIAN) 4345 number_to_chars_bigendian (p, 0x01000000, 4); 4346 else 4347 number_to_chars_littleendian (p, 0x01000000, 4); 4348 4349 fragp->fr_fix += fix; 4350 fragp->fr_var = 4; 4351 break; 4352 4353 default: 4354 break; 4355 } 4356 } 4357 4358 #ifdef OBJ_ELF 4359 /* Some special processing for a Sparc ELF file. */ 4360 4361 void 4362 sparc_elf_final_processing () 4363 { 4364 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4365 sort of BFD interface for this. */ 4366 if (sparc_arch_size == 64) 4367 { 4368 switch (sparc_memory_model) 4369 { 4370 case MM_RMO: 4371 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4372 break; 4373 case MM_PSO: 4374 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4375 break; 4376 default: 4377 break; 4378 } 4379 } 4380 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4381 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4382 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4383 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4384 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4385 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4386 } 4387 4388 void 4389 sparc_cons (exp, size) 4390 expressionS *exp; 4391 int size; 4392 { 4393 char *save; 4394 4395 SKIP_WHITESPACE (); 4396 sparc_cons_special_reloc = NULL; 4397 save = input_line_pointer; 4398 if (input_line_pointer[0] == '%' 4399 && input_line_pointer[1] == 'r' 4400 && input_line_pointer[2] == '_') 4401 { 4402 if (strncmp (input_line_pointer + 3, "disp", 4) == 0) 4403 { 4404 input_line_pointer += 7; 4405 sparc_cons_special_reloc = "disp"; 4406 } 4407 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) 4408 { 4409 if (size != 4 && size != 8) 4410 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); 4411 else 4412 { 4413 input_line_pointer += 6; 4414 sparc_cons_special_reloc = "plt"; 4415 } 4416 } 4417 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) 4418 { 4419 if (size != 4 && size != 8) 4420 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); 4421 else 4422 { 4423 input_line_pointer += 13; 4424 sparc_cons_special_reloc = "tls_dtpoff"; 4425 } 4426 } 4427 if (sparc_cons_special_reloc) 4428 { 4429 int bad = 0; 4430 4431 switch (size) 4432 { 4433 case 1: 4434 if (*input_line_pointer != '8') 4435 bad = 1; 4436 input_line_pointer--; 4437 break; 4438 case 2: 4439 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') 4440 bad = 1; 4441 break; 4442 case 4: 4443 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') 4444 bad = 1; 4445 break; 4446 case 8: 4447 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') 4448 bad = 1; 4449 break; 4450 default: 4451 bad = 1; 4452 break; 4453 } 4454 4455 if (bad) 4456 { 4457 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), 4458 sparc_cons_special_reloc, size * 8, size); 4459 } 4460 else 4461 { 4462 input_line_pointer += 2; 4463 if (*input_line_pointer != '(') 4464 { 4465 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4466 sparc_cons_special_reloc, size * 8); 4467 bad = 1; 4468 } 4469 } 4470 4471 if (bad) 4472 { 4473 input_line_pointer = save; 4474 sparc_cons_special_reloc = NULL; 4475 } 4476 else 4477 { 4478 int c; 4479 char *end = ++input_line_pointer; 4480 int npar = 0; 4481 4482 while (! is_end_of_line[(c = *end)]) 4483 { 4484 if (c == '(') 4485 npar++; 4486 else if (c == ')') 4487 { 4488 if (!npar) 4489 break; 4490 npar--; 4491 } 4492 end++; 4493 } 4494 4495 if (c != ')') 4496 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4497 sparc_cons_special_reloc, size * 8); 4498 else 4499 { 4500 *end = '\0'; 4501 expression (exp); 4502 *end = c; 4503 if (input_line_pointer != end) 4504 { 4505 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4506 sparc_cons_special_reloc, size * 8); 4507 } 4508 else 4509 { 4510 input_line_pointer++; 4511 SKIP_WHITESPACE (); 4512 c = *input_line_pointer; 4513 if (! is_end_of_line[c] && c != ',') 4514 as_bad (_("Illegal operands: garbage after %%r_%s%d()"), 4515 sparc_cons_special_reloc, size * 8); 4516 } 4517 } 4518 } 4519 } 4520 } 4521 if (sparc_cons_special_reloc == NULL) 4522 expression (exp); 4523 } 4524 4525 #endif 4526 4527 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4528 reloc for a cons. We could use the definition there, except that 4529 we want to handle little endian relocs specially. */ 4530 4531 void 4532 cons_fix_new_sparc (frag, where, nbytes, exp) 4533 fragS *frag; 4534 int where; 4535 unsigned int nbytes; 4536 expressionS *exp; 4537 { 4538 bfd_reloc_code_real_type r; 4539 4540 r = (nbytes == 1 ? BFD_RELOC_8 : 4541 (nbytes == 2 ? BFD_RELOC_16 : 4542 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4543 4544 if (target_little_endian_data 4545 && nbytes == 4 4546 && now_seg->flags & SEC_ALLOC) 4547 r = BFD_RELOC_SPARC_REV32; 4548 4549 if (sparc_cons_special_reloc) 4550 { 4551 if (*sparc_cons_special_reloc == 'd') 4552 switch (nbytes) 4553 { 4554 case 1: r = BFD_RELOC_8_PCREL; break; 4555 case 2: r = BFD_RELOC_16_PCREL; break; 4556 case 4: r = BFD_RELOC_32_PCREL; break; 4557 case 8: r = BFD_RELOC_64_PCREL; break; 4558 default: abort (); 4559 } 4560 else if (*sparc_cons_special_reloc == 'p') 4561 switch (nbytes) 4562 { 4563 case 4: r = BFD_RELOC_SPARC_PLT32; break; 4564 case 8: r = BFD_RELOC_SPARC_PLT64; break; 4565 } 4566 else 4567 switch (nbytes) 4568 { 4569 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; 4570 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; 4571 } 4572 } 4573 else if (sparc_no_align_cons) 4574 { 4575 switch (nbytes) 4576 { 4577 case 2: r = BFD_RELOC_SPARC_UA16; break; 4578 case 4: r = BFD_RELOC_SPARC_UA32; break; 4579 case 8: r = BFD_RELOC_SPARC_UA64; break; 4580 default: abort (); 4581 } 4582 } 4583 4584 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4585 sparc_cons_special_reloc = NULL; 4586 } 4587 4588 void 4589 sparc_cfi_frame_initial_instructions () 4590 { 4591 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); 4592 } 4593 4594 int 4595 sparc_regname_to_dw2regnum (const char *regname) 4596 { 4597 char *p, *q; 4598 4599 if (!regname[0]) 4600 return -1; 4601 4602 q = "goli"; 4603 p = strchr (q, regname[0]); 4604 if (p) 4605 { 4606 if (regname[1] < '0' || regname[1] > '8' || regname[2]) 4607 return -1; 4608 return (p - q) * 8 + regname[1] - '0'; 4609 } 4610 if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) 4611 return 14; 4612 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) 4613 return 30; 4614 if (regname[0] == 'f' || regname[0] == 'r') 4615 { 4616 unsigned int regnum; 4617 4618 regnum = strtoul (regname + 1, &q, 10); 4619 if (p == q || *q) 4620 return -1; 4621 if (regnum >= ((regname[0] == 'f' 4622 && SPARC_OPCODE_ARCH_V9_P (max_architecture)) 4623 ? 64 : 32)) 4624 return -1; 4625 if (regname[0] == 'f') 4626 { 4627 regnum += 32; 4628 if (regnum >= 64 && (regnum & 1)) 4629 return -1; 4630 } 4631 return regnum; 4632 } 4633 return -1; 4634 } 4635 4636 void 4637 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) 4638 { 4639 sparc_cons_special_reloc = "disp"; 4640 sparc_no_align_cons = 1; 4641 emit_expr (exp, nbytes); 4642 sparc_no_align_cons = 0; 4643 sparc_cons_special_reloc = NULL; 4644 } 4645