1 /* tc-xtensa.c -- Assemble Xtensa instructions. 2 Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 #include <string.h> 22 #include <limits.h> 23 #include "as.h" 24 #include "sb.h" 25 #include "safe-ctype.h" 26 #include "tc-xtensa.h" 27 #include "frags.h" 28 #include "subsegs.h" 29 #include "xtensa-relax.h" 30 #include "xtensa-istack.h" 31 #include "dwarf2dbg.h" 32 #include "struc-symbol.h" 33 #include "xtensa-config.h" 34 35 #ifndef uint32 36 #define uint32 unsigned int 37 #endif 38 #ifndef int32 39 #define int32 signed int 40 #endif 41 42 /* Notes: 43 44 Naming conventions (used somewhat inconsistently): 45 The xtensa_ functions are exported 46 The xg_ functions are internal 47 48 We also have a couple of different extensibility mechanisms. 49 1) The idiom replacement: 50 This is used when a line is first parsed to 51 replace an instruction pattern with another instruction 52 It is currently limited to replacements of instructions 53 with constant operands. 54 2) The xtensa-relax.c mechanism that has stronger instruction 55 replacement patterns. When an instruction's immediate field 56 does not fit the next instruction sequence is attempted. 57 In addition, "narrow" opcodes are supported this way. */ 58 59 60 /* Define characters with special meanings to GAS. */ 61 const char comment_chars[] = "#"; 62 const char line_comment_chars[] = "#"; 63 const char line_separator_chars[] = ";"; 64 const char EXP_CHARS[] = "eE"; 65 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 66 67 68 /* Flags to indicate whether the hardware supports the density and 69 absolute literals options. */ 70 71 bfd_boolean density_supported = XCHAL_HAVE_DENSITY; 72 bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; 73 74 /* Maximum width we would pad an unreachable frag to get alignment. */ 75 #define UNREACHABLE_MAX_WIDTH 8 76 77 static vliw_insn cur_vinsn; 78 79 unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; 80 81 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; 82 83 /* Some functions are only valid in the front end. This variable 84 allows us to assert that we haven't crossed over into the 85 back end. */ 86 static bfd_boolean past_xtensa_end = FALSE; 87 88 /* Flags for properties of the last instruction in a segment. */ 89 #define FLAG_IS_A0_WRITER 0x1 90 #define FLAG_IS_BAD_LOOPEND 0x2 91 92 93 /* We define a special segment names ".literal" to place literals 94 into. The .fini and .init sections are special because they 95 contain code that is moved together by the linker. We give them 96 their own special .fini.literal and .init.literal sections. */ 97 98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") 99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") 100 #define FINI_SECTION_NAME xtensa_section_rename (".fini") 101 #define INIT_SECTION_NAME xtensa_section_rename (".init") 102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal") 103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal") 104 105 106 /* This type is used for the directive_stack to keep track of the 107 state of the literal collection pools. */ 108 109 typedef struct lit_state_struct 110 { 111 const char *lit_seg_name; 112 const char *lit4_seg_name; 113 const char *init_lit_seg_name; 114 const char *fini_lit_seg_name; 115 segT lit_seg; 116 segT lit4_seg; 117 segT init_lit_seg; 118 segT fini_lit_seg; 119 } lit_state; 120 121 static lit_state default_lit_sections; 122 123 124 /* We keep lists of literal segments. The seg_list type is the node 125 for such a list. The *_literal_head locals are the heads of the 126 various lists. All of these lists have a dummy node at the start. */ 127 128 typedef struct seg_list_struct 129 { 130 struct seg_list_struct *next; 131 segT seg; 132 } seg_list; 133 134 static seg_list literal_head_h; 135 static seg_list *literal_head = &literal_head_h; 136 static seg_list init_literal_head_h; 137 static seg_list *init_literal_head = &init_literal_head_h; 138 static seg_list fini_literal_head_h; 139 static seg_list *fini_literal_head = &fini_literal_head_h; 140 141 142 /* Lists of symbols. We keep a list of symbols that label the current 143 instruction, so that we can adjust the symbols when inserting alignment 144 for various instructions. We also keep a list of all the symbols on 145 literals, so that we can fix up those symbols when the literals are 146 later moved into the text sections. */ 147 148 typedef struct sym_list_struct 149 { 150 struct sym_list_struct *next; 151 symbolS *sym; 152 } sym_list; 153 154 static sym_list *insn_labels = NULL; 155 static sym_list *free_insn_labels = NULL; 156 static sym_list *saved_insn_labels = NULL; 157 158 static sym_list *literal_syms; 159 160 161 /* Flags to determine whether to prefer const16 or l32r 162 if both options are available. */ 163 int prefer_const16 = 0; 164 int prefer_l32r = 0; 165 166 /* Global flag to indicate when we are emitting literals. */ 167 int generating_literals = 0; 168 169 /* The following PROPERTY table definitions are copied from 170 <elf/xtensa.h> and must be kept in sync with the code there. */ 171 172 /* Flags in the property tables to specify whether blocks of memory 173 are literals, instructions, data, or unreachable. For 174 instructions, blocks that begin loop targets and branch targets are 175 designated. Blocks that do not allow density, instruction 176 reordering or transformation are also specified. Finally, for 177 branch targets, branch target alignment priority is included. 178 Alignment of the next block is specified in the current block 179 and the size of the current block does not include any fill required 180 to align to the next block. */ 181 182 #define XTENSA_PROP_LITERAL 0x00000001 183 #define XTENSA_PROP_INSN 0x00000002 184 #define XTENSA_PROP_DATA 0x00000004 185 #define XTENSA_PROP_UNREACHABLE 0x00000008 186 /* Instruction only properties at beginning of code. */ 187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 189 /* Instruction only properties about code. */ 190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100 193 194 /* Branch target alignment information. This transmits information 195 to the linker optimization about the priority of aligning a 196 particular block for branch target alignment: None, low priority, 197 high priority, or required. These only need to be checked in 198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. 199 Common usage is 200 201 switch (GET_XTENSA_PROP_BT_ALIGN (flags)) 202 case XTENSA_PROP_BT_ALIGN_NONE: 203 case XTENSA_PROP_BT_ALIGN_LOW: 204 case XTENSA_PROP_BT_ALIGN_HIGH: 205 case XTENSA_PROP_BT_ALIGN_REQUIRE: 206 */ 207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 208 209 /* No branch target alignment. */ 210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0 211 /* Low priority branch target alignment. */ 212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1 213 /* High priority branch target alignment. */ 214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 215 /* Required branch target alignment. */ 216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 217 218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \ 219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) 220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ 221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ 222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) 223 224 225 /* Alignment is specified in the block BEFORE the one that needs 226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to 227 get the required alignment specified as a power of 2. Use 228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required 229 alignment. Be careful of side effects since the SET will evaluate 230 flags twice. Also, note that the SIZE of a block in the property 231 table does not include the alignment size, so the alignment fill 232 must be calculated to determine if two blocks are contiguous. 233 TEXT_ALIGN is not currently implemented but is a placeholder for a 234 possible future implementation. */ 235 236 #define XTENSA_PROP_ALIGN 0x00000800 237 238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 239 240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \ 241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) 242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ 243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ 244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) 245 246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000 247 248 249 /* Structure for saving instruction and alignment per-fragment data 250 that will be written to the object file. This structure is 251 equivalent to the actual data that will be written out to the file 252 but is easier to use. We provide a conversion to file flags 253 in frag_flags_to_number. */ 254 255 typedef struct frag_flags_struct frag_flags; 256 257 struct frag_flags_struct 258 { 259 /* is_literal should only be used after xtensa_move_literals. 260 If you need to check if you are generating a literal fragment, 261 then use the generating_literals global. */ 262 263 unsigned is_literal : 1; 264 unsigned is_insn : 1; 265 unsigned is_data : 1; 266 unsigned is_unreachable : 1; 267 268 struct 269 { 270 unsigned is_loop_target : 1; 271 unsigned is_branch_target : 1; /* Branch targets have a priority. */ 272 unsigned bt_align_priority : 2; 273 274 unsigned is_no_density : 1; 275 /* no_longcalls flag does not need to be placed in the object file. */ 276 /* is_specific_opcode implies no_transform. */ 277 unsigned is_no_transform : 1; 278 279 unsigned is_no_reorder : 1; 280 281 /* Uses absolute literal addressing for l32r. */ 282 unsigned is_abslit : 1; 283 } insn; 284 unsigned is_align : 1; 285 unsigned alignment : 5; 286 }; 287 288 289 /* Structure for saving information about a block of property data 290 for frags that have the same flags. */ 291 struct xtensa_block_info_struct 292 { 293 segT sec; 294 bfd_vma offset; 295 size_t size; 296 frag_flags flags; 297 struct xtensa_block_info_struct *next; 298 }; 299 300 301 /* Structure for saving the current state before emitting literals. */ 302 typedef struct emit_state_struct 303 { 304 const char *name; 305 segT now_seg; 306 subsegT now_subseg; 307 int generating_literals; 308 } emit_state; 309 310 311 /* Opcode placement information */ 312 313 typedef unsigned long long bitfield; 314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) 315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) 316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) 317 318 #define MAX_FORMATS 32 319 320 typedef struct op_placement_info_struct 321 { 322 int num_formats; 323 /* A number describing how restrictive the issue is for this 324 opcode. For example, an opcode that fits lots of different 325 formats has a high freedom, as does an opcode that fits 326 only one format but many slots in that format. The most 327 restrictive is the opcode that fits only one slot in one 328 format. */ 329 int issuef; 330 xtensa_format narrowest; 331 char narrowest_size; 332 char narrowest_slot; 333 334 /* formats is a bitfield with the Nth bit set 335 if the opcode fits in the Nth xtensa_format. */ 336 bitfield formats; 337 338 /* slots[N]'s Mth bit is set if the op fits in the 339 Mth slot of the Nth xtensa_format. */ 340 bitfield slots[MAX_FORMATS]; 341 342 /* A count of the number of slots in a given format 343 an op can fit (i.e., the bitcount of the slot field above). */ 344 char slots_in_format[MAX_FORMATS]; 345 346 } op_placement_info, *op_placement_info_table; 347 348 op_placement_info_table op_placement_table; 349 350 351 /* Extra expression types. */ 352 353 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ 354 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ 355 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ 356 357 358 /* Directives. */ 359 360 typedef enum 361 { 362 directive_none = 0, 363 directive_literal, 364 directive_density, 365 directive_transform, 366 directive_freeregs, 367 directive_longcalls, 368 directive_literal_prefix, 369 directive_schedule, 370 directive_absolute_literals, 371 directive_last_directive 372 } directiveE; 373 374 typedef struct 375 { 376 const char *name; 377 bfd_boolean can_be_negated; 378 } directive_infoS; 379 380 const directive_infoS directive_info[] = 381 { 382 { "none", FALSE }, 383 { "literal", FALSE }, 384 { "density", TRUE }, 385 { "transform", TRUE }, 386 { "freeregs", FALSE }, 387 { "longcalls", TRUE }, 388 { "literal_prefix", FALSE }, 389 { "schedule", TRUE }, 390 { "absolute-literals", TRUE } 391 }; 392 393 bfd_boolean directive_state[] = 394 { 395 FALSE, /* none */ 396 FALSE, /* literal */ 397 #if !XCHAL_HAVE_DENSITY 398 FALSE, /* density */ 399 #else 400 TRUE, /* density */ 401 #endif 402 TRUE, /* transform */ 403 FALSE, /* freeregs */ 404 FALSE, /* longcalls */ 405 FALSE, /* literal_prefix */ 406 TRUE, /* schedule */ 407 #if XSHAL_USE_ABSOLUTE_LITERALS 408 TRUE /* absolute_literals */ 409 #else 410 FALSE /* absolute_literals */ 411 #endif 412 }; 413 414 415 /* Directive functions. */ 416 417 static void xtensa_begin_directive (int); 418 static void xtensa_end_directive (int); 419 static void xtensa_literal_prefix (char const *, int); 420 static void xtensa_literal_position (int); 421 static void xtensa_literal_pseudo (int); 422 static void xtensa_frequency_pseudo (int); 423 static void xtensa_elf_cons (int); 424 425 /* Parsing and Idiom Translation. */ 426 427 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); 428 429 /* Various Other Internal Functions. */ 430 431 extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); 432 static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); 433 static void xtensa_mark_literal_pool_location (void); 434 static addressT get_expanded_loop_offset (xtensa_opcode); 435 static fragS *get_literal_pool_location (segT); 436 static void set_literal_pool_location (segT, fragS *); 437 static void xtensa_set_frag_assembly_state (fragS *); 438 static void finish_vinsn (vliw_insn *); 439 static bfd_boolean emit_single_op (TInsn *); 440 static int total_frag_text_expansion (fragS *); 441 442 /* Alignment Functions. */ 443 444 static int get_text_align_power (unsigned); 445 static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); 446 static int branch_align_power (segT); 447 448 /* Helpers for xtensa_relax_frag(). */ 449 450 static long relax_frag_add_nop (fragS *); 451 452 /* Accessors for additional per-subsegment information. */ 453 454 static unsigned get_last_insn_flags (segT, subsegT); 455 static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); 456 static float get_subseg_total_freq (segT, subsegT); 457 static float get_subseg_target_freq (segT, subsegT); 458 static void set_subseg_freq (segT, subsegT, float, float); 459 460 /* Segment list functions. */ 461 462 static void xtensa_move_literals (void); 463 static void xtensa_reorder_segments (void); 464 static void xtensa_switch_to_literal_fragment (emit_state *); 465 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); 466 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); 467 static void xtensa_restore_emit_state (emit_state *); 468 static void cache_literal_section 469 (seg_list *, const char *, segT *, bfd_boolean); 470 471 /* Import from elf32-xtensa.c in BFD library. */ 472 473 extern char *xtensa_get_property_section_name (asection *, const char *); 474 475 /* op_placement_info functions. */ 476 477 static void init_op_placement_info_table (void); 478 extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); 479 static int xg_get_single_size (xtensa_opcode); 480 static xtensa_format xg_get_single_format (xtensa_opcode); 481 static int xg_get_single_slot (xtensa_opcode); 482 483 /* TInsn and IStack functions. */ 484 485 static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); 486 static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); 487 static bfd_boolean tinsn_has_complex_operands (const TInsn *); 488 static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); 489 static bfd_boolean tinsn_check_arguments (const TInsn *); 490 static void tinsn_from_chars (TInsn *, char *, int); 491 static void tinsn_immed_from_frag (TInsn *, fragS *, int); 492 static int get_num_stack_text_bytes (IStack *); 493 static int get_num_stack_literal_bytes (IStack *); 494 495 /* vliw_insn functions. */ 496 497 static void xg_init_vinsn (vliw_insn *); 498 static void xg_clear_vinsn (vliw_insn *); 499 static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); 500 static void xg_free_vinsn (vliw_insn *); 501 static bfd_boolean vinsn_to_insnbuf 502 (vliw_insn *, char *, fragS *, bfd_boolean); 503 static void vinsn_from_chars (vliw_insn *, char *); 504 505 /* Expression Utilities. */ 506 507 bfd_boolean expr_is_const (const expressionS *); 508 offsetT get_expr_const (const expressionS *); 509 void set_expr_const (expressionS *, offsetT); 510 bfd_boolean expr_is_register (const expressionS *); 511 offsetT get_expr_register (const expressionS *); 512 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); 513 bfd_boolean expr_is_equal (expressionS *, expressionS *); 514 static void copy_expr (expressionS *, const expressionS *); 515 516 /* Section renaming. */ 517 518 static void build_section_rename (const char *); 519 520 521 /* ISA imported from bfd. */ 522 extern xtensa_isa xtensa_default_isa; 523 524 extern int target_big_endian; 525 526 static xtensa_opcode xtensa_addi_opcode; 527 static xtensa_opcode xtensa_addmi_opcode; 528 static xtensa_opcode xtensa_call0_opcode; 529 static xtensa_opcode xtensa_call4_opcode; 530 static xtensa_opcode xtensa_call8_opcode; 531 static xtensa_opcode xtensa_call12_opcode; 532 static xtensa_opcode xtensa_callx0_opcode; 533 static xtensa_opcode xtensa_callx4_opcode; 534 static xtensa_opcode xtensa_callx8_opcode; 535 static xtensa_opcode xtensa_callx12_opcode; 536 static xtensa_opcode xtensa_const16_opcode; 537 static xtensa_opcode xtensa_entry_opcode; 538 static xtensa_opcode xtensa_movi_opcode; 539 static xtensa_opcode xtensa_movi_n_opcode; 540 static xtensa_opcode xtensa_isync_opcode; 541 static xtensa_opcode xtensa_jx_opcode; 542 static xtensa_opcode xtensa_l32r_opcode; 543 static xtensa_opcode xtensa_loop_opcode; 544 static xtensa_opcode xtensa_loopnez_opcode; 545 static xtensa_opcode xtensa_loopgtz_opcode; 546 static xtensa_opcode xtensa_nop_opcode; 547 static xtensa_opcode xtensa_nop_n_opcode; 548 static xtensa_opcode xtensa_or_opcode; 549 static xtensa_opcode xtensa_ret_opcode; 550 static xtensa_opcode xtensa_ret_n_opcode; 551 static xtensa_opcode xtensa_retw_opcode; 552 static xtensa_opcode xtensa_retw_n_opcode; 553 static xtensa_opcode xtensa_rsr_lcount_opcode; 554 static xtensa_opcode xtensa_waiti_opcode; 555 556 557 /* Command-line Options. */ 558 559 bfd_boolean use_literal_section = TRUE; 560 static bfd_boolean align_targets = TRUE; 561 static bfd_boolean warn_unaligned_branch_targets = FALSE; 562 static bfd_boolean has_a0_b_retw = FALSE; 563 static bfd_boolean workaround_a0_b_retw = FALSE; 564 static bfd_boolean workaround_b_j_loop_end = FALSE; 565 static bfd_boolean workaround_short_loop = FALSE; 566 static bfd_boolean maybe_has_short_loop = FALSE; 567 static bfd_boolean workaround_close_loop_end = FALSE; 568 static bfd_boolean maybe_has_close_loop_end = FALSE; 569 static bfd_boolean enforce_three_byte_loop_align = FALSE; 570 571 /* When workaround_short_loops is TRUE, all loops with early exits must 572 have at least 3 instructions. workaround_all_short_loops is a modifier 573 to the workaround_short_loop flag. In addition to the 574 workaround_short_loop actions, all straightline loopgtz and loopnez 575 must have at least 3 instructions. */ 576 577 static bfd_boolean workaround_all_short_loops = FALSE; 578 579 580 static void 581 xtensa_setup_hw_workarounds (int earliest, int latest) 582 { 583 if (earliest > latest) 584 as_fatal (_("illegal range of target hardware versions")); 585 586 /* Enable all workarounds for pre-T1050.0 hardware. */ 587 if (earliest < 105000 || latest < 105000) 588 { 589 workaround_a0_b_retw |= TRUE; 590 workaround_b_j_loop_end |= TRUE; 591 workaround_short_loop |= TRUE; 592 workaround_close_loop_end |= TRUE; 593 workaround_all_short_loops |= TRUE; 594 enforce_three_byte_loop_align = TRUE; 595 } 596 } 597 598 599 enum 600 { 601 option_density = OPTION_MD_BASE, 602 option_no_density, 603 604 option_relax, 605 option_no_relax, 606 607 option_link_relax, 608 option_no_link_relax, 609 610 option_generics, 611 option_no_generics, 612 613 option_transform, 614 option_no_transform, 615 616 option_text_section_literals, 617 option_no_text_section_literals, 618 619 option_absolute_literals, 620 option_no_absolute_literals, 621 622 option_align_targets, 623 option_no_align_targets, 624 625 option_warn_unaligned_targets, 626 627 option_longcalls, 628 option_no_longcalls, 629 630 option_workaround_a0_b_retw, 631 option_no_workaround_a0_b_retw, 632 633 option_workaround_b_j_loop_end, 634 option_no_workaround_b_j_loop_end, 635 636 option_workaround_short_loop, 637 option_no_workaround_short_loop, 638 639 option_workaround_all_short_loops, 640 option_no_workaround_all_short_loops, 641 642 option_workaround_close_loop_end, 643 option_no_workaround_close_loop_end, 644 645 option_no_workarounds, 646 647 option_rename_section_name, 648 649 option_prefer_l32r, 650 option_prefer_const16, 651 652 option_target_hardware 653 }; 654 655 const char *md_shortopts = ""; 656 657 struct option md_longopts[] = 658 { 659 { "density", no_argument, NULL, option_density }, 660 { "no-density", no_argument, NULL, option_no_density }, 661 662 /* Both "relax" and "generics" are deprecated and treated as equivalent 663 to the "transform" option. */ 664 { "relax", no_argument, NULL, option_relax }, 665 { "no-relax", no_argument, NULL, option_no_relax }, 666 { "generics", no_argument, NULL, option_generics }, 667 { "no-generics", no_argument, NULL, option_no_generics }, 668 669 { "transform", no_argument, NULL, option_transform }, 670 { "no-transform", no_argument, NULL, option_no_transform }, 671 { "text-section-literals", no_argument, NULL, option_text_section_literals }, 672 { "no-text-section-literals", no_argument, NULL, 673 option_no_text_section_literals }, 674 { "absolute-literals", no_argument, NULL, option_absolute_literals }, 675 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, 676 /* This option was changed from -align-target to -target-align 677 because it conflicted with the "-al" option. */ 678 { "target-align", no_argument, NULL, option_align_targets }, 679 { "no-target-align", no_argument, NULL, option_no_align_targets }, 680 { "warn-unaligned-targets", no_argument, NULL, 681 option_warn_unaligned_targets }, 682 { "longcalls", no_argument, NULL, option_longcalls }, 683 { "no-longcalls", no_argument, NULL, option_no_longcalls }, 684 685 { "no-workaround-a0-b-retw", no_argument, NULL, 686 option_no_workaround_a0_b_retw }, 687 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, 688 689 { "no-workaround-b-j-loop-end", no_argument, NULL, 690 option_no_workaround_b_j_loop_end }, 691 { "workaround-b-j-loop-end", no_argument, NULL, 692 option_workaround_b_j_loop_end }, 693 694 { "no-workaround-short-loops", no_argument, NULL, 695 option_no_workaround_short_loop }, 696 { "workaround-short-loops", no_argument, NULL, 697 option_workaround_short_loop }, 698 699 { "no-workaround-all-short-loops", no_argument, NULL, 700 option_no_workaround_all_short_loops }, 701 { "workaround-all-short-loop", no_argument, NULL, 702 option_workaround_all_short_loops }, 703 704 { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, 705 { "prefer-const16", no_argument, NULL, option_prefer_const16 }, 706 707 { "no-workarounds", no_argument, NULL, option_no_workarounds }, 708 709 { "no-workaround-close-loop-end", no_argument, NULL, 710 option_no_workaround_close_loop_end }, 711 { "workaround-close-loop-end", no_argument, NULL, 712 option_workaround_close_loop_end }, 713 714 { "rename-section", required_argument, NULL, option_rename_section_name }, 715 716 { "link-relax", no_argument, NULL, option_link_relax }, 717 { "no-link-relax", no_argument, NULL, option_no_link_relax }, 718 719 { "target-hardware", required_argument, NULL, option_target_hardware }, 720 721 { NULL, no_argument, NULL, 0 } 722 }; 723 724 size_t md_longopts_size = sizeof md_longopts; 725 726 727 int 728 md_parse_option (int c, char *arg) 729 { 730 switch (c) 731 { 732 case option_density: 733 as_warn (_("--density option is ignored")); 734 return 1; 735 case option_no_density: 736 as_warn (_("--no-density option is ignored")); 737 return 1; 738 case option_link_relax: 739 linkrelax = 1; 740 return 1; 741 case option_no_link_relax: 742 linkrelax = 0; 743 return 1; 744 case option_generics: 745 as_warn (_("--generics is deprecated; use --transform instead")); 746 return md_parse_option (option_transform, arg); 747 case option_no_generics: 748 as_warn (_("--no-generics is deprecated; use --no-transform instead")); 749 return md_parse_option (option_no_transform, arg); 750 case option_relax: 751 as_warn (_("--relax is deprecated; use --transform instead")); 752 return md_parse_option (option_transform, arg); 753 case option_no_relax: 754 as_warn (_("--no-relax is deprecated; use --no-transform instead")); 755 return md_parse_option (option_no_transform, arg); 756 case option_longcalls: 757 directive_state[directive_longcalls] = TRUE; 758 return 1; 759 case option_no_longcalls: 760 directive_state[directive_longcalls] = FALSE; 761 return 1; 762 case option_text_section_literals: 763 use_literal_section = FALSE; 764 return 1; 765 case option_no_text_section_literals: 766 use_literal_section = TRUE; 767 return 1; 768 case option_absolute_literals: 769 if (!absolute_literals_supported) 770 { 771 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); 772 return 0; 773 } 774 directive_state[directive_absolute_literals] = TRUE; 775 return 1; 776 case option_no_absolute_literals: 777 directive_state[directive_absolute_literals] = FALSE; 778 return 1; 779 780 case option_workaround_a0_b_retw: 781 workaround_a0_b_retw = TRUE; 782 return 1; 783 case option_no_workaround_a0_b_retw: 784 workaround_a0_b_retw = FALSE; 785 return 1; 786 case option_workaround_b_j_loop_end: 787 workaround_b_j_loop_end = TRUE; 788 return 1; 789 case option_no_workaround_b_j_loop_end: 790 workaround_b_j_loop_end = FALSE; 791 return 1; 792 793 case option_workaround_short_loop: 794 workaround_short_loop = TRUE; 795 return 1; 796 case option_no_workaround_short_loop: 797 workaround_short_loop = FALSE; 798 return 1; 799 800 case option_workaround_all_short_loops: 801 workaround_all_short_loops = TRUE; 802 return 1; 803 case option_no_workaround_all_short_loops: 804 workaround_all_short_loops = FALSE; 805 return 1; 806 807 case option_workaround_close_loop_end: 808 workaround_close_loop_end = TRUE; 809 return 1; 810 case option_no_workaround_close_loop_end: 811 workaround_close_loop_end = FALSE; 812 return 1; 813 814 case option_no_workarounds: 815 workaround_a0_b_retw = FALSE; 816 workaround_b_j_loop_end = FALSE; 817 workaround_short_loop = FALSE; 818 workaround_all_short_loops = FALSE; 819 workaround_close_loop_end = FALSE; 820 return 1; 821 822 case option_align_targets: 823 align_targets = TRUE; 824 return 1; 825 case option_no_align_targets: 826 align_targets = FALSE; 827 return 1; 828 829 case option_warn_unaligned_targets: 830 warn_unaligned_branch_targets = TRUE; 831 return 1; 832 833 case option_rename_section_name: 834 build_section_rename (arg); 835 return 1; 836 837 case 'Q': 838 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 839 should be emitted or not. FIXME: Not implemented. */ 840 return 1; 841 842 case option_prefer_l32r: 843 if (prefer_const16) 844 as_fatal (_("prefer-l32r conflicts with prefer-const16")); 845 prefer_l32r = 1; 846 return 1; 847 848 case option_prefer_const16: 849 if (prefer_l32r) 850 as_fatal (_("prefer-const16 conflicts with prefer-l32r")); 851 prefer_const16 = 1; 852 return 1; 853 854 case option_target_hardware: 855 { 856 int earliest, latest = 0; 857 if (*arg == 0 || *arg == '-') 858 as_fatal (_("invalid target hardware version")); 859 860 earliest = strtol (arg, &arg, 0); 861 862 if (*arg == 0) 863 latest = earliest; 864 else if (*arg == '-') 865 { 866 if (*++arg == 0) 867 as_fatal (_("invalid target hardware version")); 868 latest = strtol (arg, &arg, 0); 869 } 870 if (*arg != 0) 871 as_fatal (_("invalid target hardware version")); 872 873 xtensa_setup_hw_workarounds (earliest, latest); 874 return 1; 875 } 876 877 case option_transform: 878 /* This option has no affect other than to use the defaults, 879 which are already set. */ 880 return 1; 881 882 case option_no_transform: 883 /* This option turns off all transformations of any kind. 884 However, because we want to preserve the state of other 885 directives, we only change its own field. Thus, before 886 you perform any transformation, always check if transform 887 is available. If you use the functions we provide for this 888 purpose, you will be ok. */ 889 directive_state[directive_transform] = FALSE; 890 return 1; 891 892 default: 893 return 0; 894 } 895 } 896 897 898 void 899 md_show_usage (FILE *stream) 900 { 901 fputs ("\n\ 902 Xtensa options:\n\ 903 --[no-]text-section-literals\n\ 904 [Do not] put literals in the text section\n\ 905 --[no-]absolute-literals\n\ 906 [Do not] default to use non-PC-relative literals\n\ 907 --[no-]target-align [Do not] try to align branch targets\n\ 908 --[no-]longcalls [Do not] emit 32-bit call sequences\n\ 909 --[no-]transform [Do not] transform instructions\n\ 910 --rename-section old=new Rename section 'old' to 'new'\n", stream); 911 } 912 913 914 /* Functions related to the list of current label symbols. */ 915 916 static void 917 xtensa_add_insn_label (symbolS *sym) 918 { 919 sym_list *l; 920 921 if (!free_insn_labels) 922 l = (sym_list *) xmalloc (sizeof (sym_list)); 923 else 924 { 925 l = free_insn_labels; 926 free_insn_labels = l->next; 927 } 928 929 l->sym = sym; 930 l->next = insn_labels; 931 insn_labels = l; 932 } 933 934 935 static void 936 xtensa_clear_insn_labels (void) 937 { 938 sym_list **pl; 939 940 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 941 ; 942 *pl = insn_labels; 943 insn_labels = NULL; 944 } 945 946 947 /* The "loops_ok" argument is provided to allow ignoring labels that 948 define loop ends. This fixes a bug where the NOPs to align a 949 loop opcode were included in a previous zero-cost loop: 950 951 loop a0, loopend 952 <loop1 body> 953 loopend: 954 955 loop a2, loopend2 956 <loop2 body> 957 958 would become: 959 960 loop a0, loopend 961 <loop1 body> 962 nop.n <===== bad! 963 loopend: 964 965 loop a2, loopend2 966 <loop2 body> 967 968 This argument is used to prevent moving the NOP to before the 969 loop-end label, which is what you want in this special case. */ 970 971 static void 972 xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok) 973 { 974 sym_list *lit; 975 976 for (lit = insn_labels; lit; lit = lit->next) 977 { 978 symbolS *lit_sym = lit->sym; 979 if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target) 980 { 981 S_SET_VALUE (lit_sym, new_offset); 982 symbol_set_frag (lit_sym, new_frag); 983 } 984 } 985 } 986 987 988 /* Directive data and functions. */ 989 990 typedef struct state_stackS_struct 991 { 992 directiveE directive; 993 bfd_boolean negated; 994 bfd_boolean old_state; 995 const char *file; 996 unsigned int line; 997 const void *datum; 998 struct state_stackS_struct *prev; 999 } state_stackS; 1000 1001 state_stackS *directive_state_stack; 1002 1003 const pseudo_typeS md_pseudo_table[] = 1004 { 1005 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ 1006 { "literal_position", xtensa_literal_position, 0 }, 1007 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ 1008 { "long", xtensa_elf_cons, 4 }, 1009 { "word", xtensa_elf_cons, 4 }, 1010 { "short", xtensa_elf_cons, 2 }, 1011 { "begin", xtensa_begin_directive, 0 }, 1012 { "end", xtensa_end_directive, 0 }, 1013 { "literal", xtensa_literal_pseudo, 0 }, 1014 { "frequency", xtensa_frequency_pseudo, 0 }, 1015 { NULL, 0, 0 }, 1016 }; 1017 1018 1019 static bfd_boolean 1020 use_transform (void) 1021 { 1022 /* After md_end, you should be checking frag by frag, rather 1023 than state directives. */ 1024 assert (!past_xtensa_end); 1025 return directive_state[directive_transform]; 1026 } 1027 1028 1029 static bfd_boolean 1030 do_align_targets (void) 1031 { 1032 /* Do not use this function after md_end; just look at align_targets 1033 instead. There is no target-align directive, so alignment is either 1034 enabled for all frags or not done at all. */ 1035 assert (!past_xtensa_end); 1036 return align_targets && use_transform (); 1037 } 1038 1039 1040 static void 1041 directive_push (directiveE directive, bfd_boolean negated, const void *datum) 1042 { 1043 char *file; 1044 unsigned int line; 1045 state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); 1046 1047 as_where (&file, &line); 1048 1049 stack->directive = directive; 1050 stack->negated = negated; 1051 stack->old_state = directive_state[directive]; 1052 stack->file = file; 1053 stack->line = line; 1054 stack->datum = datum; 1055 stack->prev = directive_state_stack; 1056 directive_state_stack = stack; 1057 1058 directive_state[directive] = !negated; 1059 } 1060 1061 1062 static void 1063 directive_pop (directiveE *directive, 1064 bfd_boolean *negated, 1065 const char **file, 1066 unsigned int *line, 1067 const void **datum) 1068 { 1069 state_stackS *top = directive_state_stack; 1070 1071 if (!directive_state_stack) 1072 { 1073 as_bad (_("unmatched end directive")); 1074 *directive = directive_none; 1075 return; 1076 } 1077 1078 directive_state[directive_state_stack->directive] = top->old_state; 1079 *directive = top->directive; 1080 *negated = top->negated; 1081 *file = top->file; 1082 *line = top->line; 1083 *datum = top->datum; 1084 directive_state_stack = top->prev; 1085 free (top); 1086 } 1087 1088 1089 static void 1090 directive_balance (void) 1091 { 1092 while (directive_state_stack) 1093 { 1094 directiveE directive; 1095 bfd_boolean negated; 1096 const char *file; 1097 unsigned int line; 1098 const void *datum; 1099 1100 directive_pop (&directive, &negated, &file, &line, &datum); 1101 as_warn_where ((char *) file, line, 1102 _(".begin directive with no matching .end directive")); 1103 } 1104 } 1105 1106 1107 static bfd_boolean 1108 inside_directive (directiveE dir) 1109 { 1110 state_stackS *top = directive_state_stack; 1111 1112 while (top && top->directive != dir) 1113 top = top->prev; 1114 1115 return (top != NULL); 1116 } 1117 1118 1119 static void 1120 get_directive (directiveE *directive, bfd_boolean *negated) 1121 { 1122 int len; 1123 unsigned i; 1124 char *directive_string; 1125 1126 if (strncmp (input_line_pointer, "no-", 3) != 0) 1127 *negated = FALSE; 1128 else 1129 { 1130 *negated = TRUE; 1131 input_line_pointer += 3; 1132 } 1133 1134 len = strspn (input_line_pointer, 1135 "abcdefghijklmnopqrstuvwxyz_-/0123456789."); 1136 1137 /* This code is a hack to make .begin [no-][generics|relax] exactly 1138 equivalent to .begin [no-]transform. We should remove it when 1139 we stop accepting those options. */ 1140 1141 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) 1142 { 1143 as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); 1144 directive_string = "transform"; 1145 } 1146 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) 1147 { 1148 as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); 1149 directive_string = "transform"; 1150 } 1151 else 1152 directive_string = input_line_pointer; 1153 1154 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) 1155 { 1156 if (strncmp (directive_string, directive_info[i].name, len) == 0) 1157 { 1158 input_line_pointer += len; 1159 *directive = (directiveE) i; 1160 if (*negated && !directive_info[i].can_be_negated) 1161 as_bad (_("directive %s cannot be negated"), 1162 directive_info[i].name); 1163 return; 1164 } 1165 } 1166 1167 as_bad (_("unknown directive")); 1168 *directive = (directiveE) XTENSA_UNDEFINED; 1169 } 1170 1171 1172 static void 1173 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) 1174 { 1175 directiveE directive; 1176 bfd_boolean negated; 1177 emit_state *state; 1178 int len; 1179 lit_state *ls; 1180 1181 get_directive (&directive, &negated); 1182 if (directive == (directiveE) XTENSA_UNDEFINED) 1183 { 1184 discard_rest_of_line (); 1185 return; 1186 } 1187 1188 if (cur_vinsn.inside_bundle) 1189 as_bad (_("directives are not valid inside bundles")); 1190 1191 switch (directive) 1192 { 1193 case directive_literal: 1194 if (!inside_directive (directive_literal)) 1195 { 1196 /* Previous labels go with whatever follows this directive, not with 1197 the literal, so save them now. */ 1198 saved_insn_labels = insn_labels; 1199 insn_labels = NULL; 1200 } 1201 as_warn (_(".begin literal is deprecated; use .literal instead")); 1202 state = (emit_state *) xmalloc (sizeof (emit_state)); 1203 xtensa_switch_to_literal_fragment (state); 1204 directive_push (directive_literal, negated, state); 1205 break; 1206 1207 case directive_literal_prefix: 1208 /* Have to flush pending output because a movi relaxed to an l32r 1209 might produce a literal. */ 1210 md_flush_pending_output (); 1211 /* Check to see if the current fragment is a literal 1212 fragment. If it is, then this operation is not allowed. */ 1213 if (generating_literals) 1214 { 1215 as_bad (_("cannot set literal_prefix inside literal fragment")); 1216 return; 1217 } 1218 1219 /* Allocate the literal state for this section and push 1220 onto the directive stack. */ 1221 ls = xmalloc (sizeof (lit_state)); 1222 assert (ls); 1223 1224 *ls = default_lit_sections; 1225 1226 directive_push (directive_literal_prefix, negated, ls); 1227 1228 /* Parse the new prefix from the input_line_pointer. */ 1229 SKIP_WHITESPACE (); 1230 len = strspn (input_line_pointer, 1231 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 1232 "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); 1233 1234 /* Process the new prefix. */ 1235 xtensa_literal_prefix (input_line_pointer, len); 1236 1237 /* Skip the name in the input line. */ 1238 input_line_pointer += len; 1239 break; 1240 1241 case directive_freeregs: 1242 /* This information is currently unused, but we'll accept the statement 1243 and just discard the rest of the line. This won't check the syntax, 1244 but it will accept every correct freeregs directive. */ 1245 input_line_pointer += strcspn (input_line_pointer, "\n"); 1246 directive_push (directive_freeregs, negated, 0); 1247 break; 1248 1249 case directive_schedule: 1250 md_flush_pending_output (); 1251 frag_var (rs_fill, 0, 0, frag_now->fr_subtype, 1252 frag_now->fr_symbol, frag_now->fr_offset, NULL); 1253 directive_push (directive_schedule, negated, 0); 1254 xtensa_set_frag_assembly_state (frag_now); 1255 break; 1256 1257 case directive_density: 1258 as_warn (_(".begin [no-]density is ignored")); 1259 break; 1260 1261 case directive_absolute_literals: 1262 md_flush_pending_output (); 1263 if (!absolute_literals_supported && !negated) 1264 { 1265 as_warn (_("Xtensa absolute literals option not supported; ignored")); 1266 break; 1267 } 1268 xtensa_set_frag_assembly_state (frag_now); 1269 directive_push (directive, negated, 0); 1270 break; 1271 1272 default: 1273 md_flush_pending_output (); 1274 xtensa_set_frag_assembly_state (frag_now); 1275 directive_push (directive, negated, 0); 1276 break; 1277 } 1278 1279 demand_empty_rest_of_line (); 1280 } 1281 1282 1283 static void 1284 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) 1285 { 1286 directiveE begin_directive, end_directive; 1287 bfd_boolean begin_negated, end_negated; 1288 const char *file; 1289 unsigned int line; 1290 emit_state *state; 1291 emit_state **state_ptr; 1292 lit_state *s; 1293 1294 if (cur_vinsn.inside_bundle) 1295 as_bad (_("directives are not valid inside bundles")); 1296 1297 get_directive (&end_directive, &end_negated); 1298 1299 md_flush_pending_output (); 1300 1301 switch (end_directive) 1302 { 1303 case (directiveE) XTENSA_UNDEFINED: 1304 discard_rest_of_line (); 1305 return; 1306 1307 case directive_density: 1308 as_warn (_(".end [no-]density is ignored")); 1309 demand_empty_rest_of_line (); 1310 break; 1311 1312 case directive_absolute_literals: 1313 if (!absolute_literals_supported && !end_negated) 1314 { 1315 as_warn (_("Xtensa absolute literals option not supported; ignored")); 1316 demand_empty_rest_of_line (); 1317 return; 1318 } 1319 break; 1320 1321 default: 1322 break; 1323 } 1324 1325 state_ptr = &state; /* use state_ptr to avoid type-punning warning */ 1326 directive_pop (&begin_directive, &begin_negated, &file, &line, 1327 (const void **) state_ptr); 1328 1329 if (begin_directive != directive_none) 1330 { 1331 if (begin_directive != end_directive || begin_negated != end_negated) 1332 { 1333 as_bad (_("does not match begin %s%s at %s:%d"), 1334 begin_negated ? "no-" : "", 1335 directive_info[begin_directive].name, file, line); 1336 } 1337 else 1338 { 1339 switch (end_directive) 1340 { 1341 case directive_literal: 1342 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); 1343 xtensa_restore_emit_state (state); 1344 xtensa_set_frag_assembly_state (frag_now); 1345 free (state); 1346 if (!inside_directive (directive_literal)) 1347 { 1348 /* Restore the list of current labels. */ 1349 xtensa_clear_insn_labels (); 1350 insn_labels = saved_insn_labels; 1351 } 1352 break; 1353 1354 case directive_literal_prefix: 1355 /* Restore the default collection sections from saved state. */ 1356 s = (lit_state *) state; 1357 assert (s); 1358 1359 default_lit_sections = *s; 1360 1361 /* free the state storage */ 1362 free (s); 1363 break; 1364 1365 case directive_schedule: 1366 case directive_freeregs: 1367 break; 1368 1369 default: 1370 xtensa_set_frag_assembly_state (frag_now); 1371 break; 1372 } 1373 } 1374 } 1375 1376 demand_empty_rest_of_line (); 1377 } 1378 1379 1380 /* Place an aligned literal fragment at the current location. */ 1381 1382 static void 1383 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) 1384 { 1385 md_flush_pending_output (); 1386 1387 if (inside_directive (directive_literal)) 1388 as_warn (_(".literal_position inside literal directive; ignoring")); 1389 xtensa_mark_literal_pool_location (); 1390 1391 demand_empty_rest_of_line (); 1392 xtensa_clear_insn_labels (); 1393 } 1394 1395 1396 /* Support .literal label, expr, ... */ 1397 1398 static void 1399 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) 1400 { 1401 emit_state state; 1402 char *p, *base_name; 1403 char c; 1404 segT dest_seg; 1405 1406 if (inside_directive (directive_literal)) 1407 { 1408 as_bad (_(".literal not allowed inside .begin literal region")); 1409 ignore_rest_of_line (); 1410 return; 1411 } 1412 1413 md_flush_pending_output (); 1414 1415 /* Previous labels go with whatever follows this directive, not with 1416 the literal, so save them now. */ 1417 saved_insn_labels = insn_labels; 1418 insn_labels = NULL; 1419 1420 /* If we are using text-section literals, then this is the right value... */ 1421 dest_seg = now_seg; 1422 1423 base_name = input_line_pointer; 1424 1425 xtensa_switch_to_literal_fragment (&state); 1426 1427 /* ...but if we aren't using text-section-literals, then we 1428 need to put them in the section we just switched to. */ 1429 if (use_literal_section || directive_state[directive_absolute_literals]) 1430 dest_seg = now_seg; 1431 1432 /* All literals are aligned to four-byte boundaries. */ 1433 frag_align (2, 0, 0); 1434 record_alignment (now_seg, 2); 1435 1436 c = get_symbol_end (); 1437 /* Just after name is now '\0'. */ 1438 p = input_line_pointer; 1439 *p = c; 1440 SKIP_WHITESPACE (); 1441 1442 if (*input_line_pointer != ',' && *input_line_pointer != ':') 1443 { 1444 as_bad (_("expected comma or colon after symbol name; " 1445 "rest of line ignored")); 1446 ignore_rest_of_line (); 1447 xtensa_restore_emit_state (&state); 1448 return; 1449 } 1450 *p = 0; 1451 1452 colon (base_name); 1453 1454 *p = c; 1455 input_line_pointer++; /* skip ',' or ':' */ 1456 1457 xtensa_elf_cons (4); 1458 1459 xtensa_restore_emit_state (&state); 1460 1461 /* Restore the list of current labels. */ 1462 xtensa_clear_insn_labels (); 1463 insn_labels = saved_insn_labels; 1464 } 1465 1466 1467 static void 1468 xtensa_literal_prefix (char const *start, int len) 1469 { 1470 char *name, *linkonce_suffix; 1471 char *newname, *newname4; 1472 size_t linkonce_len; 1473 1474 /* Get a null-terminated copy of the name. */ 1475 name = xmalloc (len + 1); 1476 assert (name); 1477 1478 strncpy (name, start, len); 1479 name[len] = 0; 1480 1481 /* Allocate the sections (interesting note: the memory pointing to 1482 the name is actually used for the name by the new section). */ 1483 1484 newname = xmalloc (len + strlen (".literal") + 1); 1485 newname4 = xmalloc (len + strlen (".lit4") + 1); 1486 1487 linkonce_len = sizeof (".gnu.linkonce.") - 1; 1488 if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0 1489 && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0) 1490 { 1491 strcpy (newname, ".gnu.linkonce.literal"); 1492 strcpy (newname4, ".gnu.linkonce.lit4"); 1493 1494 strcat (newname, linkonce_suffix); 1495 strcat (newname4, linkonce_suffix); 1496 } 1497 else 1498 { 1499 int suffix_pos = len; 1500 1501 /* If the section name ends with ".text", then replace that suffix 1502 instead of appending an additional suffix. */ 1503 if (len >= 5 && strcmp (name + len - 5, ".text") == 0) 1504 suffix_pos -= 5; 1505 1506 strcpy (newname, name); 1507 strcpy (newname4, name); 1508 1509 strcpy (newname + suffix_pos, ".literal"); 1510 strcpy (newname4 + suffix_pos, ".lit4"); 1511 } 1512 1513 /* Note that cache_literal_section does not create a segment if 1514 it already exists. */ 1515 default_lit_sections.lit_seg = NULL; 1516 default_lit_sections.lit4_seg = NULL; 1517 1518 /* Canonicalizing section names allows renaming literal 1519 sections to occur correctly. */ 1520 default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname); 1521 default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4); 1522 1523 free (name); 1524 } 1525 1526 1527 /* Support ".frequency branch_target_frequency fall_through_frequency". */ 1528 1529 static void 1530 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) 1531 { 1532 float fall_through_f, target_f; 1533 1534 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); 1535 if (fall_through_f < 0) 1536 { 1537 as_bad (_("fall through frequency must be greater than 0")); 1538 ignore_rest_of_line (); 1539 return; 1540 } 1541 1542 target_f = (float) strtod (input_line_pointer, &input_line_pointer); 1543 if (target_f < 0) 1544 { 1545 as_bad (_("branch target frequency must be greater than 0")); 1546 ignore_rest_of_line (); 1547 return; 1548 } 1549 1550 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); 1551 1552 demand_empty_rest_of_line (); 1553 } 1554 1555 1556 /* Like normal .long/.short/.word, except support @plt, etc. 1557 Clobbers input_line_pointer, checks end-of-line. */ 1558 1559 static void 1560 xtensa_elf_cons (int nbytes) 1561 { 1562 expressionS exp; 1563 bfd_reloc_code_real_type reloc; 1564 1565 md_flush_pending_output (); 1566 1567 if (cur_vinsn.inside_bundle) 1568 as_bad (_("directives are not valid inside bundles")); 1569 1570 if (is_it_end_of_statement ()) 1571 { 1572 demand_empty_rest_of_line (); 1573 return; 1574 } 1575 1576 do 1577 { 1578 expression (&exp); 1579 if (exp.X_op == O_symbol 1580 && *input_line_pointer == '@' 1581 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) 1582 != BFD_RELOC_NONE)) 1583 { 1584 reloc_howto_type *reloc_howto = 1585 bfd_reloc_type_lookup (stdoutput, reloc); 1586 1587 if (reloc == BFD_RELOC_UNUSED || !reloc_howto) 1588 as_bad (_("unsupported relocation")); 1589 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP 1590 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) 1591 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT 1592 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) 1593 as_bad (_("opcode-specific %s relocation used outside " 1594 "an instruction"), reloc_howto->name); 1595 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) 1596 as_bad (_("%s relocations do not fit in %d bytes"), 1597 reloc_howto->name, nbytes); 1598 else 1599 { 1600 char *p = frag_more ((int) nbytes); 1601 xtensa_set_frag_assembly_state (frag_now); 1602 fix_new_exp (frag_now, p - frag_now->fr_literal, 1603 nbytes, &exp, 0, reloc); 1604 } 1605 } 1606 else 1607 emit_expr (&exp, (unsigned int) nbytes); 1608 } 1609 while (*input_line_pointer++ == ','); 1610 1611 input_line_pointer--; /* Put terminator back into stream. */ 1612 demand_empty_rest_of_line (); 1613 } 1614 1615 1616 /* Parsing and Idiom Translation. */ 1617 1618 /* Parse @plt, etc. and return the desired relocation. */ 1619 static bfd_reloc_code_real_type 1620 xtensa_elf_suffix (char **str_p, expressionS *exp_p) 1621 { 1622 struct map_bfd 1623 { 1624 char *string; 1625 int length; 1626 bfd_reloc_code_real_type reloc; 1627 }; 1628 1629 char ident[20]; 1630 char *str = *str_p; 1631 char *str2; 1632 int ch; 1633 int len; 1634 struct map_bfd *ptr; 1635 1636 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc } 1637 1638 static struct map_bfd mapping[] = 1639 { 1640 MAP ("l", BFD_RELOC_LO16), 1641 MAP ("h", BFD_RELOC_HI16), 1642 MAP ("plt", BFD_RELOC_XTENSA_PLT), 1643 { (char *) 0, 0, BFD_RELOC_UNUSED } 1644 }; 1645 1646 if (*str++ != '@') 1647 return BFD_RELOC_NONE; 1648 1649 for (ch = *str, str2 = ident; 1650 (str2 < ident + sizeof (ident) - 1 1651 && (ISALNUM (ch) || ch == '@')); 1652 ch = *++str) 1653 { 1654 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); 1655 } 1656 1657 *str2 = '\0'; 1658 len = str2 - ident; 1659 1660 ch = ident[0]; 1661 for (ptr = &mapping[0]; ptr->length > 0; ptr++) 1662 if (ch == ptr->string[0] 1663 && len == ptr->length 1664 && memcmp (ident, ptr->string, ptr->length) == 0) 1665 { 1666 /* Now check for "identifier@suffix+constant". */ 1667 if (*str == '-' || *str == '+') 1668 { 1669 char *orig_line = input_line_pointer; 1670 expressionS new_exp; 1671 1672 input_line_pointer = str; 1673 expression (&new_exp); 1674 if (new_exp.X_op == O_constant) 1675 { 1676 exp_p->X_add_number += new_exp.X_add_number; 1677 str = input_line_pointer; 1678 } 1679 1680 if (&input_line_pointer != str_p) 1681 input_line_pointer = orig_line; 1682 } 1683 1684 *str_p = str; 1685 return ptr->reloc; 1686 } 1687 1688 return BFD_RELOC_UNUSED; 1689 } 1690 1691 1692 static const char * 1693 expression_end (const char *name) 1694 { 1695 while (1) 1696 { 1697 switch (*name) 1698 { 1699 case '}': 1700 case ';': 1701 case '\0': 1702 case ',': 1703 case ':': 1704 return name; 1705 case ' ': 1706 case '\t': 1707 ++name; 1708 continue; 1709 default: 1710 return 0; 1711 } 1712 } 1713 } 1714 1715 1716 #define ERROR_REG_NUM ((unsigned) -1) 1717 1718 static unsigned 1719 tc_get_register (const char *prefix) 1720 { 1721 unsigned reg; 1722 const char *next_expr; 1723 const char *old_line_pointer; 1724 1725 SKIP_WHITESPACE (); 1726 old_line_pointer = input_line_pointer; 1727 1728 if (*input_line_pointer == '$') 1729 ++input_line_pointer; 1730 1731 /* Accept "sp" as a synonym for "a1". */ 1732 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' 1733 && expression_end (input_line_pointer + 2)) 1734 { 1735 input_line_pointer += 2; 1736 return 1; /* AR[1] */ 1737 } 1738 1739 while (*input_line_pointer++ == *prefix++) 1740 ; 1741 --input_line_pointer; 1742 --prefix; 1743 1744 if (*prefix) 1745 { 1746 as_bad (_("bad register name: %s"), old_line_pointer); 1747 return ERROR_REG_NUM; 1748 } 1749 1750 if (!ISDIGIT ((unsigned char) *input_line_pointer)) 1751 { 1752 as_bad (_("bad register number: %s"), input_line_pointer); 1753 return ERROR_REG_NUM; 1754 } 1755 1756 reg = 0; 1757 1758 while (ISDIGIT ((int) *input_line_pointer)) 1759 reg = reg * 10 + *input_line_pointer++ - '0'; 1760 1761 if (!(next_expr = expression_end (input_line_pointer))) 1762 { 1763 as_bad (_("bad register name: %s"), old_line_pointer); 1764 return ERROR_REG_NUM; 1765 } 1766 1767 input_line_pointer = (char *) next_expr; 1768 1769 return reg; 1770 } 1771 1772 1773 static void 1774 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) 1775 { 1776 xtensa_isa isa = xtensa_default_isa; 1777 1778 /* Check if this is an immediate operand. */ 1779 if (xtensa_operand_is_register (isa, opc, opnd) == 0) 1780 { 1781 bfd_reloc_code_real_type reloc; 1782 segT t = expression (tok); 1783 if (t == absolute_section 1784 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) 1785 { 1786 assert (tok->X_op == O_constant); 1787 tok->X_op = O_symbol; 1788 tok->X_add_symbol = &abs_symbol; 1789 } 1790 1791 if ((tok->X_op == O_constant || tok->X_op == O_symbol) 1792 && (reloc = xtensa_elf_suffix (&input_line_pointer, tok)) 1793 && (reloc != BFD_RELOC_NONE)) 1794 { 1795 switch (reloc) 1796 { 1797 default: 1798 case BFD_RELOC_UNUSED: 1799 as_bad (_("unsupported relocation")); 1800 break; 1801 1802 case BFD_RELOC_XTENSA_PLT: 1803 tok->X_op = O_pltrel; 1804 break; 1805 1806 case BFD_RELOC_LO16: 1807 if (tok->X_op == O_constant) 1808 tok->X_add_number &= 0xffff; 1809 else 1810 tok->X_op = O_lo16; 1811 break; 1812 1813 case BFD_RELOC_HI16: 1814 if (tok->X_op == O_constant) 1815 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; 1816 else 1817 tok->X_op = O_hi16; 1818 break; 1819 } 1820 } 1821 } 1822 else 1823 { 1824 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); 1825 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); 1826 1827 if (reg != ERROR_REG_NUM) /* Already errored */ 1828 { 1829 uint32 buf = reg; 1830 if (xtensa_operand_encode (isa, opc, opnd, &buf)) 1831 as_bad (_("register number out of range")); 1832 } 1833 1834 tok->X_op = O_register; 1835 tok->X_add_symbol = 0; 1836 tok->X_add_number = reg; 1837 } 1838 } 1839 1840 1841 /* Split up the arguments for an opcode or pseudo-op. */ 1842 1843 static int 1844 tokenize_arguments (char **args, char *str) 1845 { 1846 char *old_input_line_pointer; 1847 bfd_boolean saw_comma = FALSE; 1848 bfd_boolean saw_arg = FALSE; 1849 bfd_boolean saw_colon = FALSE; 1850 int num_args = 0; 1851 char *arg_end, *arg; 1852 int arg_len; 1853 1854 /* Save and restore input_line_pointer around this function. */ 1855 old_input_line_pointer = input_line_pointer; 1856 input_line_pointer = str; 1857 1858 while (*input_line_pointer) 1859 { 1860 SKIP_WHITESPACE (); 1861 switch (*input_line_pointer) 1862 { 1863 case '\0': 1864 case '}': 1865 goto fini; 1866 1867 case ':': 1868 input_line_pointer++; 1869 if (saw_comma || saw_colon || !saw_arg) 1870 goto err; 1871 saw_colon = TRUE; 1872 break; 1873 1874 case ',': 1875 input_line_pointer++; 1876 if (saw_comma || saw_colon || !saw_arg) 1877 goto err; 1878 saw_comma = TRUE; 1879 break; 1880 1881 default: 1882 if (!saw_comma && !saw_colon && saw_arg) 1883 goto err; 1884 1885 arg_end = input_line_pointer + 1; 1886 while (!expression_end (arg_end)) 1887 arg_end += 1; 1888 1889 arg_len = arg_end - input_line_pointer; 1890 arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); 1891 args[num_args] = arg; 1892 1893 if (saw_colon) 1894 *arg++ = ':'; 1895 strncpy (arg, input_line_pointer, arg_len); 1896 arg[arg_len] = '\0'; 1897 1898 input_line_pointer = arg_end; 1899 num_args += 1; 1900 saw_comma = FALSE; 1901 saw_colon = FALSE; 1902 saw_arg = TRUE; 1903 break; 1904 } 1905 } 1906 1907 fini: 1908 if (saw_comma || saw_colon) 1909 goto err; 1910 input_line_pointer = old_input_line_pointer; 1911 return num_args; 1912 1913 err: 1914 if (saw_comma) 1915 as_bad (_("extra comma")); 1916 else if (saw_colon) 1917 as_bad (_("extra colon")); 1918 else if (!saw_arg) 1919 as_bad (_("missing argument")); 1920 else 1921 as_bad (_("missing comma or colon")); 1922 input_line_pointer = old_input_line_pointer; 1923 return -1; 1924 } 1925 1926 1927 /* Parse the arguments to an opcode. Return TRUE on error. */ 1928 1929 static bfd_boolean 1930 parse_arguments (TInsn *insn, int num_args, char **arg_strings) 1931 { 1932 expressionS *tok, *last_tok; 1933 xtensa_opcode opcode = insn->opcode; 1934 bfd_boolean had_error = TRUE; 1935 xtensa_isa isa = xtensa_default_isa; 1936 int n, num_regs = 0; 1937 int opcode_operand_count; 1938 int opnd_cnt, last_opnd_cnt; 1939 unsigned int next_reg = 0; 1940 char *old_input_line_pointer; 1941 1942 if (insn->insn_type == ITYPE_LITERAL) 1943 opcode_operand_count = 1; 1944 else 1945 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); 1946 1947 tok = insn->tok; 1948 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); 1949 1950 /* Save and restore input_line_pointer around this function. */ 1951 old_input_line_pointer = input_line_pointer; 1952 1953 last_tok = 0; 1954 last_opnd_cnt = -1; 1955 opnd_cnt = 0; 1956 1957 /* Skip invisible operands. */ 1958 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) 1959 { 1960 opnd_cnt += 1; 1961 tok++; 1962 } 1963 1964 for (n = 0; n < num_args; n++) 1965 { 1966 input_line_pointer = arg_strings[n]; 1967 if (*input_line_pointer == ':') 1968 { 1969 xtensa_regfile opnd_rf; 1970 input_line_pointer++; 1971 if (num_regs == 0) 1972 goto err; 1973 assert (opnd_cnt > 0); 1974 num_regs--; 1975 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); 1976 if (next_reg 1977 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) 1978 as_warn (_("incorrect register number, ignoring")); 1979 next_reg++; 1980 } 1981 else 1982 { 1983 if (opnd_cnt >= opcode_operand_count) 1984 { 1985 as_warn (_("too many arguments")); 1986 goto err; 1987 } 1988 assert (opnd_cnt < MAX_INSN_ARGS); 1989 1990 expression_maybe_register (opcode, opnd_cnt, tok); 1991 next_reg = tok->X_add_number + 1; 1992 1993 if (tok->X_op == O_illegal || tok->X_op == O_absent) 1994 goto err; 1995 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) 1996 { 1997 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; 1998 /* minus 1 because we are seeing one right now */ 1999 } 2000 else 2001 num_regs = 0; 2002 2003 last_tok = tok; 2004 last_opnd_cnt = opnd_cnt; 2005 2006 do 2007 { 2008 opnd_cnt += 1; 2009 tok++; 2010 } 2011 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); 2012 } 2013 } 2014 2015 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) 2016 goto err; 2017 2018 insn->ntok = tok - insn->tok; 2019 had_error = FALSE; 2020 2021 err: 2022 input_line_pointer = old_input_line_pointer; 2023 return had_error; 2024 } 2025 2026 2027 static int 2028 get_invisible_operands (TInsn *insn) 2029 { 2030 xtensa_isa isa = xtensa_default_isa; 2031 static xtensa_insnbuf slotbuf = NULL; 2032 xtensa_format fmt; 2033 xtensa_opcode opc = insn->opcode; 2034 int slot, opnd, fmt_found; 2035 unsigned val; 2036 2037 if (!slotbuf) 2038 slotbuf = xtensa_insnbuf_alloc (isa); 2039 2040 /* Find format/slot where this can be encoded. */ 2041 fmt_found = 0; 2042 slot = 0; 2043 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) 2044 { 2045 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 2046 { 2047 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) 2048 { 2049 fmt_found = 1; 2050 break; 2051 } 2052 } 2053 if (fmt_found) break; 2054 } 2055 2056 if (!fmt_found) 2057 { 2058 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); 2059 return -1; 2060 } 2061 2062 /* First encode all the visible operands 2063 (to deal with shared field operands). */ 2064 for (opnd = 0; opnd < insn->ntok; opnd++) 2065 { 2066 if (xtensa_operand_is_visible (isa, opc, opnd) == 1 2067 && (insn->tok[opnd].X_op == O_register 2068 || insn->tok[opnd].X_op == O_constant)) 2069 { 2070 val = insn->tok[opnd].X_add_number; 2071 xtensa_operand_encode (isa, opc, opnd, &val); 2072 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); 2073 } 2074 } 2075 2076 /* Then pull out the values for the invisible ones. */ 2077 for (opnd = 0; opnd < insn->ntok; opnd++) 2078 { 2079 if (xtensa_operand_is_visible (isa, opc, opnd) == 0) 2080 { 2081 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); 2082 xtensa_operand_decode (isa, opc, opnd, &val); 2083 insn->tok[opnd].X_add_number = val; 2084 if (xtensa_operand_is_register (isa, opc, opnd) == 1) 2085 insn->tok[opnd].X_op = O_register; 2086 else 2087 insn->tok[opnd].X_op = O_constant; 2088 } 2089 } 2090 2091 return 0; 2092 } 2093 2094 2095 static void 2096 xg_reverse_shift_count (char **cnt_argp) 2097 { 2098 char *cnt_arg, *new_arg; 2099 cnt_arg = *cnt_argp; 2100 2101 /* replace the argument with "31-(argument)" */ 2102 new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); 2103 sprintf (new_arg, "31-(%s)", cnt_arg); 2104 2105 free (cnt_arg); 2106 *cnt_argp = new_arg; 2107 } 2108 2109 2110 /* If "arg" is a constant expression, return non-zero with the value 2111 in *valp. */ 2112 2113 static int 2114 xg_arg_is_constant (char *arg, offsetT *valp) 2115 { 2116 expressionS exp; 2117 char *save_ptr = input_line_pointer; 2118 2119 input_line_pointer = arg; 2120 expression (&exp); 2121 input_line_pointer = save_ptr; 2122 2123 if (exp.X_op == O_constant) 2124 { 2125 *valp = exp.X_add_number; 2126 return 1; 2127 } 2128 2129 return 0; 2130 } 2131 2132 2133 static void 2134 xg_replace_opname (char **popname, char *newop) 2135 { 2136 free (*popname); 2137 *popname = (char *) xmalloc (strlen (newop) + 1); 2138 strcpy (*popname, newop); 2139 } 2140 2141 2142 static int 2143 xg_check_num_args (int *pnum_args, 2144 int expected_num, 2145 char *opname, 2146 char **arg_strings) 2147 { 2148 int num_args = *pnum_args; 2149 2150 if (num_args < expected_num) 2151 { 2152 as_bad (_("not enough operands (%d) for '%s'; expected %d"), 2153 num_args, opname, expected_num); 2154 return -1; 2155 } 2156 2157 if (num_args > expected_num) 2158 { 2159 as_warn (_("too many operands (%d) for '%s'; expected %d"), 2160 num_args, opname, expected_num); 2161 while (num_args-- > expected_num) 2162 { 2163 free (arg_strings[num_args]); 2164 arg_strings[num_args] = 0; 2165 } 2166 *pnum_args = expected_num; 2167 return -1; 2168 } 2169 2170 return 0; 2171 } 2172 2173 2174 /* If the register is not specified as part of the opcode, 2175 then get it from the operand and move it to the opcode. */ 2176 2177 static int 2178 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) 2179 { 2180 xtensa_isa isa = xtensa_default_isa; 2181 xtensa_sysreg sr; 2182 char *opname, *new_opname; 2183 const char *sr_name; 2184 int is_user, is_write; 2185 2186 opname = *popname; 2187 if (*opname == '_') 2188 opname += 1; 2189 is_user = (opname[1] == 'u'); 2190 is_write = (opname[0] == 'w'); 2191 2192 /* Opname == [rw]ur or [rwx]sr... */ 2193 2194 if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) 2195 return -1; 2196 2197 /* Check if the argument is a symbolic register name. */ 2198 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); 2199 /* Handle WSR to "INTSET" as a special case. */ 2200 if (sr == XTENSA_UNDEFINED && is_write && !is_user 2201 && !strcasecmp (arg_strings[1], "intset")) 2202 sr = xtensa_sysreg_lookup_name (isa, "interrupt"); 2203 if (sr == XTENSA_UNDEFINED 2204 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) 2205 { 2206 /* Maybe it's a register number.... */ 2207 offsetT val; 2208 if (!xg_arg_is_constant (arg_strings[1], &val)) 2209 { 2210 as_bad (_("invalid register '%s' for '%s' instruction"), 2211 arg_strings[1], opname); 2212 return -1; 2213 } 2214 sr = xtensa_sysreg_lookup (isa, val, is_user); 2215 if (sr == XTENSA_UNDEFINED) 2216 { 2217 as_bad (_("invalid register number (%ld) for '%s' instruction"), 2218 (long) val, opname); 2219 return -1; 2220 } 2221 } 2222 2223 /* Remove the last argument, which is now part of the opcode. */ 2224 free (arg_strings[1]); 2225 arg_strings[1] = 0; 2226 *pnum_args = 1; 2227 2228 /* Translate the opcode. */ 2229 sr_name = xtensa_sysreg_name (isa, sr); 2230 /* Another special case for "WSR.INTSET".... */ 2231 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) 2232 sr_name = "intset"; 2233 new_opname = (char *) xmalloc (strlen (sr_name) + 6); 2234 sprintf (new_opname, "%s.%s", *popname, sr_name); 2235 free (*popname); 2236 *popname = new_opname; 2237 2238 return 0; 2239 } 2240 2241 2242 static int 2243 xtensa_translate_old_userreg_ops (char **popname) 2244 { 2245 xtensa_isa isa = xtensa_default_isa; 2246 xtensa_sysreg sr; 2247 char *opname, *new_opname; 2248 const char *sr_name; 2249 bfd_boolean has_underbar = FALSE; 2250 2251 opname = *popname; 2252 if (opname[0] == '_') 2253 { 2254 has_underbar = TRUE; 2255 opname += 1; 2256 } 2257 2258 sr = xtensa_sysreg_lookup_name (isa, opname + 1); 2259 if (sr != XTENSA_UNDEFINED) 2260 { 2261 /* The new default name ("nnn") is different from the old default 2262 name ("URnnn"). The old default is handled below, and we don't 2263 want to recognize [RW]nnn, so do nothing if the name is the (new) 2264 default. */ 2265 static char namebuf[10]; 2266 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); 2267 if (strcmp (namebuf, opname + 1) == 0) 2268 return 0; 2269 } 2270 else 2271 { 2272 offsetT val; 2273 char *end; 2274 2275 /* Only continue if the reg name is "URnnn". */ 2276 if (opname[1] != 'u' || opname[2] != 'r') 2277 return 0; 2278 val = strtoul (opname + 3, &end, 10); 2279 if (*end != '\0') 2280 return 0; 2281 2282 sr = xtensa_sysreg_lookup (isa, val, 1); 2283 if (sr == XTENSA_UNDEFINED) 2284 { 2285 as_bad (_("invalid register number (%ld) for '%s'"), 2286 (long) val, opname); 2287 return -1; 2288 } 2289 } 2290 2291 /* Translate the opcode. */ 2292 sr_name = xtensa_sysreg_name (isa, sr); 2293 new_opname = (char *) xmalloc (strlen (sr_name) + 6); 2294 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), 2295 opname[0], sr_name); 2296 free (*popname); 2297 *popname = new_opname; 2298 2299 return 0; 2300 } 2301 2302 2303 static int 2304 xtensa_translate_zero_immed (char *old_op, 2305 char *new_op, 2306 char **popname, 2307 int *pnum_args, 2308 char **arg_strings) 2309 { 2310 char *opname; 2311 offsetT val; 2312 2313 opname = *popname; 2314 assert (opname[0] != '_'); 2315 2316 if (strcmp (opname, old_op) != 0) 2317 return 0; 2318 2319 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2320 return -1; 2321 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) 2322 { 2323 xg_replace_opname (popname, new_op); 2324 free (arg_strings[1]); 2325 arg_strings[1] = arg_strings[2]; 2326 arg_strings[2] = 0; 2327 *pnum_args = 2; 2328 } 2329 2330 return 0; 2331 } 2332 2333 2334 /* If the instruction is an idiom (i.e., a built-in macro), translate it. 2335 Returns non-zero if an error was found. */ 2336 2337 static int 2338 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) 2339 { 2340 char *opname = *popname; 2341 bfd_boolean has_underbar = FALSE; 2342 2343 if (cur_vinsn.inside_bundle) 2344 return 0; 2345 2346 if (*opname == '_') 2347 { 2348 has_underbar = TRUE; 2349 opname += 1; 2350 } 2351 2352 if (strcmp (opname, "mov") == 0) 2353 { 2354 if (use_transform () && !has_underbar && density_supported) 2355 xg_replace_opname (popname, "mov.n"); 2356 else 2357 { 2358 if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) 2359 return -1; 2360 xg_replace_opname (popname, (has_underbar ? "_or" : "or")); 2361 arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); 2362 strcpy (arg_strings[2], arg_strings[1]); 2363 *pnum_args = 3; 2364 } 2365 return 0; 2366 } 2367 2368 if (strcmp (opname, "bbsi.l") == 0) 2369 { 2370 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2371 return -1; 2372 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); 2373 if (target_big_endian) 2374 xg_reverse_shift_count (&arg_strings[1]); 2375 return 0; 2376 } 2377 2378 if (strcmp (opname, "bbci.l") == 0) 2379 { 2380 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2381 return -1; 2382 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); 2383 if (target_big_endian) 2384 xg_reverse_shift_count (&arg_strings[1]); 2385 return 0; 2386 } 2387 2388 if (xtensa_nop_opcode == XTENSA_UNDEFINED 2389 && strcmp (opname, "nop") == 0) 2390 { 2391 if (use_transform () && !has_underbar && density_supported) 2392 xg_replace_opname (popname, "nop.n"); 2393 else 2394 { 2395 if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) 2396 return -1; 2397 xg_replace_opname (popname, (has_underbar ? "_or" : "or")); 2398 arg_strings[0] = (char *) xmalloc (3); 2399 arg_strings[1] = (char *) xmalloc (3); 2400 arg_strings[2] = (char *) xmalloc (3); 2401 strcpy (arg_strings[0], "a1"); 2402 strcpy (arg_strings[1], "a1"); 2403 strcpy (arg_strings[2], "a1"); 2404 *pnum_args = 3; 2405 } 2406 return 0; 2407 } 2408 2409 /* Recognize [RW]UR and [RWX]SR. */ 2410 if ((((opname[0] == 'r' || opname[0] == 'w') 2411 && (opname[1] == 'u' || opname[1] == 's')) 2412 || (opname[0] == 'x' && opname[1] == 's')) 2413 && opname[2] == 'r' 2414 && opname[3] == '\0') 2415 return xg_translate_sysreg_op (popname, pnum_args, arg_strings); 2416 2417 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and 2418 [RW]<name> if <name> is the non-default name of a user register. */ 2419 if ((opname[0] == 'r' || opname[0] == 'w') 2420 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) 2421 return xtensa_translate_old_userreg_ops (popname); 2422 2423 /* Relax branches that don't allow comparisons against an immediate value 2424 of zero to the corresponding branches with implicit zero immediates. */ 2425 if (!has_underbar && use_transform ()) 2426 { 2427 if (xtensa_translate_zero_immed ("bnei", "bnez", popname, 2428 pnum_args, arg_strings)) 2429 return -1; 2430 2431 if (xtensa_translate_zero_immed ("beqi", "beqz", popname, 2432 pnum_args, arg_strings)) 2433 return -1; 2434 2435 if (xtensa_translate_zero_immed ("bgei", "bgez", popname, 2436 pnum_args, arg_strings)) 2437 return -1; 2438 2439 if (xtensa_translate_zero_immed ("blti", "bltz", popname, 2440 pnum_args, arg_strings)) 2441 return -1; 2442 } 2443 2444 return 0; 2445 } 2446 2447 2448 /* Functions for dealing with the Xtensa ISA. */ 2449 2450 /* Currently the assembler only allows us to use a single target per 2451 fragment. Because of this, only one operand for a given 2452 instruction may be symbolic. If there is a PC-relative operand, 2453 the last one is chosen. Otherwise, the result is the number of the 2454 last immediate operand, and if there are none of those, we fail and 2455 return -1. */ 2456 2457 static int 2458 get_relaxable_immed (xtensa_opcode opcode) 2459 { 2460 int last_immed = -1; 2461 int noperands, opi; 2462 2463 if (opcode == XTENSA_UNDEFINED) 2464 return -1; 2465 2466 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); 2467 for (opi = noperands - 1; opi >= 0; opi--) 2468 { 2469 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) 2470 continue; 2471 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) 2472 return opi; 2473 if (last_immed == -1 2474 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) 2475 last_immed = opi; 2476 } 2477 return last_immed; 2478 } 2479 2480 2481 static xtensa_opcode 2482 get_opcode_from_buf (const char *buf, int slot) 2483 { 2484 static xtensa_insnbuf insnbuf = NULL; 2485 static xtensa_insnbuf slotbuf = NULL; 2486 xtensa_isa isa = xtensa_default_isa; 2487 xtensa_format fmt; 2488 2489 if (!insnbuf) 2490 { 2491 insnbuf = xtensa_insnbuf_alloc (isa); 2492 slotbuf = xtensa_insnbuf_alloc (isa); 2493 } 2494 2495 xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); 2496 fmt = xtensa_format_decode (isa, insnbuf); 2497 if (fmt == XTENSA_UNDEFINED) 2498 return XTENSA_UNDEFINED; 2499 2500 if (slot >= xtensa_format_num_slots (isa, fmt)) 2501 return XTENSA_UNDEFINED; 2502 2503 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 2504 return xtensa_opcode_decode (isa, fmt, slot, slotbuf); 2505 } 2506 2507 2508 #ifdef TENSILICA_DEBUG 2509 2510 /* For debugging, print out the mapping of opcode numbers to opcodes. */ 2511 2512 static void 2513 xtensa_print_insn_table (void) 2514 { 2515 int num_opcodes, num_operands; 2516 xtensa_opcode opcode; 2517 xtensa_isa isa = xtensa_default_isa; 2518 2519 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); 2520 for (opcode = 0; opcode < num_opcodes; opcode++) 2521 { 2522 int opn; 2523 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); 2524 num_operands = xtensa_opcode_num_operands (isa, opcode); 2525 for (opn = 0; opn < num_operands; opn++) 2526 { 2527 if (xtensa_operand_is_visible (isa, opcode, opn) == 0) 2528 continue; 2529 if (xtensa_operand_is_register (isa, opcode, opn) == 1) 2530 { 2531 xtensa_regfile opnd_rf = 2532 xtensa_operand_regfile (isa, opcode, opn); 2533 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); 2534 } 2535 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) 2536 fputs ("[lLr] ", stderr); 2537 else 2538 fputs ("i ", stderr); 2539 } 2540 fprintf (stderr, "\n"); 2541 } 2542 } 2543 2544 2545 static void 2546 print_vliw_insn (xtensa_insnbuf vbuf) 2547 { 2548 xtensa_isa isa = xtensa_default_isa; 2549 xtensa_format f = xtensa_format_decode (isa, vbuf); 2550 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); 2551 int op; 2552 2553 fprintf (stderr, "format = %d\n", f); 2554 2555 for (op = 0; op < xtensa_format_num_slots (isa, f); op++) 2556 { 2557 xtensa_opcode opcode; 2558 const char *opname; 2559 int operands; 2560 2561 xtensa_format_get_slot (isa, f, op, vbuf, sbuf); 2562 opcode = xtensa_opcode_decode (isa, f, op, sbuf); 2563 opname = xtensa_opcode_name (isa, opcode); 2564 2565 fprintf (stderr, "op in slot %i is %s;\n", op, opname); 2566 fprintf (stderr, " operands = "); 2567 for (operands = 0; 2568 operands < xtensa_opcode_num_operands (isa, opcode); 2569 operands++) 2570 { 2571 unsigned int val; 2572 if (xtensa_operand_is_visible (isa, opcode, operands) == 0) 2573 continue; 2574 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); 2575 xtensa_operand_decode (isa, opcode, operands, &val); 2576 fprintf (stderr, "%d ", val); 2577 } 2578 fprintf (stderr, "\n"); 2579 } 2580 xtensa_insnbuf_free (isa, sbuf); 2581 } 2582 2583 #endif /* TENSILICA_DEBUG */ 2584 2585 2586 static bfd_boolean 2587 is_direct_call_opcode (xtensa_opcode opcode) 2588 { 2589 xtensa_isa isa = xtensa_default_isa; 2590 int n, num_operands; 2591 2592 if (xtensa_opcode_is_call (isa, opcode) == 0) 2593 return FALSE; 2594 2595 num_operands = xtensa_opcode_num_operands (isa, opcode); 2596 for (n = 0; n < num_operands; n++) 2597 { 2598 if (xtensa_operand_is_register (isa, opcode, n) == 0 2599 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) 2600 return TRUE; 2601 } 2602 return FALSE; 2603 } 2604 2605 2606 /* Convert from BFD relocation type code to slot and operand number. 2607 Returns non-zero on failure. */ 2608 2609 static int 2610 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) 2611 { 2612 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP 2613 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) 2614 { 2615 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; 2616 *is_alt = FALSE; 2617 } 2618 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT 2619 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) 2620 { 2621 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; 2622 *is_alt = TRUE; 2623 } 2624 else 2625 return -1; 2626 2627 return 0; 2628 } 2629 2630 2631 /* Convert from slot number to BFD relocation type code for the 2632 standard PC-relative relocations. Return BFD_RELOC_NONE on 2633 failure. */ 2634 2635 static bfd_reloc_code_real_type 2636 encode_reloc (int slot) 2637 { 2638 if (slot < 0 || slot > 14) 2639 return BFD_RELOC_NONE; 2640 2641 return BFD_RELOC_XTENSA_SLOT0_OP + slot; 2642 } 2643 2644 2645 /* Convert from slot numbers to BFD relocation type code for the 2646 "alternate" relocations. Return BFD_RELOC_NONE on failure. */ 2647 2648 static bfd_reloc_code_real_type 2649 encode_alt_reloc (int slot) 2650 { 2651 if (slot < 0 || slot > 14) 2652 return BFD_RELOC_NONE; 2653 2654 return BFD_RELOC_XTENSA_SLOT0_ALT + slot; 2655 } 2656 2657 2658 static void 2659 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, 2660 xtensa_format fmt, 2661 int slot, 2662 xtensa_opcode opcode, 2663 int operand, 2664 uint32 value, 2665 const char *file, 2666 unsigned int line) 2667 { 2668 uint32 valbuf = value; 2669 2670 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) 2671 { 2672 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) 2673 == 1) 2674 as_bad_where ((char *) file, line, 2675 _("operand %d of '%s' has out of range value '%u'"), 2676 operand + 1, 2677 xtensa_opcode_name (xtensa_default_isa, opcode), 2678 value); 2679 else 2680 as_bad_where ((char *) file, line, 2681 _("operand %d of '%s' has invalid value '%u'"), 2682 operand + 1, 2683 xtensa_opcode_name (xtensa_default_isa, opcode), 2684 value); 2685 return; 2686 } 2687 2688 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, 2689 slotbuf, valbuf); 2690 } 2691 2692 2693 static uint32 2694 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, 2695 xtensa_format fmt, 2696 int slot, 2697 xtensa_opcode opcode, 2698 int opnum) 2699 { 2700 uint32 val = 0; 2701 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, 2702 fmt, slot, slotbuf, &val); 2703 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); 2704 return val; 2705 } 2706 2707 2708 /* Checks for rules from xtensa-relax tables. */ 2709 2710 /* The routine xg_instruction_matches_option_term must return TRUE 2711 when a given option term is true. The meaning of all of the option 2712 terms is given interpretation by this function. This is needed when 2713 an option depends on the state of a directive, but there are no such 2714 options in use right now. */ 2715 2716 static bfd_boolean 2717 xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED, 2718 const ReqOrOption *option) 2719 { 2720 if (strcmp (option->option_name, "realnop") == 0 2721 || strncmp (option->option_name, "IsaUse", 6) == 0) 2722 { 2723 /* These conditions were evaluated statically when building the 2724 relaxation table. There's no need to reevaluate them now. */ 2725 return TRUE; 2726 } 2727 else 2728 { 2729 as_fatal (_("internal error: unknown option name '%s'"), 2730 option->option_name); 2731 } 2732 } 2733 2734 2735 static bfd_boolean 2736 xg_instruction_matches_or_options (TInsn *insn, 2737 const ReqOrOptionList *or_option) 2738 { 2739 const ReqOrOption *option; 2740 /* Must match each of the AND terms. */ 2741 for (option = or_option; option != NULL; option = option->next) 2742 { 2743 if (xg_instruction_matches_option_term (insn, option)) 2744 return TRUE; 2745 } 2746 return FALSE; 2747 } 2748 2749 2750 static bfd_boolean 2751 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) 2752 { 2753 const ReqOption *req_options; 2754 /* Must match each of the AND terms. */ 2755 for (req_options = options; 2756 req_options != NULL; 2757 req_options = req_options->next) 2758 { 2759 /* Must match one of the OR clauses. */ 2760 if (!xg_instruction_matches_or_options (insn, 2761 req_options->or_option_terms)) 2762 return FALSE; 2763 } 2764 return TRUE; 2765 } 2766 2767 2768 /* Return the transition rule that matches or NULL if none matches. */ 2769 2770 static bfd_boolean 2771 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) 2772 { 2773 PreconditionList *condition_l; 2774 2775 if (rule->opcode != insn->opcode) 2776 return FALSE; 2777 2778 for (condition_l = rule->conditions; 2779 condition_l != NULL; 2780 condition_l = condition_l->next) 2781 { 2782 expressionS *exp1; 2783 expressionS *exp2; 2784 Precondition *cond = condition_l->precond; 2785 2786 switch (cond->typ) 2787 { 2788 case OP_CONSTANT: 2789 /* The expression must be the constant. */ 2790 assert (cond->op_num < insn->ntok); 2791 exp1 = &insn->tok[cond->op_num]; 2792 if (expr_is_const (exp1)) 2793 { 2794 switch (cond->cmp) 2795 { 2796 case OP_EQUAL: 2797 if (get_expr_const (exp1) != cond->op_data) 2798 return FALSE; 2799 break; 2800 case OP_NOTEQUAL: 2801 if (get_expr_const (exp1) == cond->op_data) 2802 return FALSE; 2803 break; 2804 default: 2805 return FALSE; 2806 } 2807 } 2808 else if (expr_is_register (exp1)) 2809 { 2810 switch (cond->cmp) 2811 { 2812 case OP_EQUAL: 2813 if (get_expr_register (exp1) != cond->op_data) 2814 return FALSE; 2815 break; 2816 case OP_NOTEQUAL: 2817 if (get_expr_register (exp1) == cond->op_data) 2818 return FALSE; 2819 break; 2820 default: 2821 return FALSE; 2822 } 2823 } 2824 else 2825 return FALSE; 2826 break; 2827 2828 case OP_OPERAND: 2829 assert (cond->op_num < insn->ntok); 2830 assert (cond->op_data < insn->ntok); 2831 exp1 = &insn->tok[cond->op_num]; 2832 exp2 = &insn->tok[cond->op_data]; 2833 2834 switch (cond->cmp) 2835 { 2836 case OP_EQUAL: 2837 if (!expr_is_equal (exp1, exp2)) 2838 return FALSE; 2839 break; 2840 case OP_NOTEQUAL: 2841 if (expr_is_equal (exp1, exp2)) 2842 return FALSE; 2843 break; 2844 } 2845 break; 2846 2847 case OP_LITERAL: 2848 case OP_LABEL: 2849 default: 2850 return FALSE; 2851 } 2852 } 2853 if (!xg_instruction_matches_options (insn, rule->options)) 2854 return FALSE; 2855 2856 return TRUE; 2857 } 2858 2859 2860 static int 2861 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) 2862 { 2863 bfd_boolean a_greater = FALSE; 2864 bfd_boolean b_greater = FALSE; 2865 2866 ReqOptionList *l_a = a->options; 2867 ReqOptionList *l_b = b->options; 2868 2869 /* We only care if they both are the same except for 2870 a const16 vs. an l32r. */ 2871 2872 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) 2873 { 2874 ReqOrOptionList *l_or_a = l_a->or_option_terms; 2875 ReqOrOptionList *l_or_b = l_b->or_option_terms; 2876 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) 2877 { 2878 if (l_or_a->is_true != l_or_b->is_true) 2879 return 0; 2880 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) 2881 { 2882 /* This is the case we care about. */ 2883 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 2884 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) 2885 { 2886 if (prefer_const16) 2887 a_greater = TRUE; 2888 else 2889 b_greater = TRUE; 2890 } 2891 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 2892 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) 2893 { 2894 if (prefer_const16) 2895 b_greater = TRUE; 2896 else 2897 a_greater = TRUE; 2898 } 2899 else 2900 return 0; 2901 } 2902 l_or_a = l_or_a->next; 2903 l_or_b = l_or_b->next; 2904 } 2905 if (l_or_a || l_or_b) 2906 return 0; 2907 2908 l_a = l_a->next; 2909 l_b = l_b->next; 2910 } 2911 if (l_a || l_b) 2912 return 0; 2913 2914 /* Incomparable if the substitution was used differently in two cases. */ 2915 if (a_greater && b_greater) 2916 return 0; 2917 2918 if (b_greater) 2919 return 1; 2920 if (a_greater) 2921 return -1; 2922 2923 return 0; 2924 } 2925 2926 2927 static TransitionRule * 2928 xg_instruction_match (TInsn *insn) 2929 { 2930 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); 2931 TransitionList *l; 2932 assert (insn->opcode < table->num_opcodes); 2933 2934 /* Walk through all of the possible transitions. */ 2935 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 2936 { 2937 TransitionRule *rule = l->rule; 2938 if (xg_instruction_matches_rule (insn, rule)) 2939 return rule; 2940 } 2941 return NULL; 2942 } 2943 2944 2945 /* Various Other Internal Functions. */ 2946 2947 static bfd_boolean 2948 is_unique_insn_expansion (TransitionRule *r) 2949 { 2950 if (!r->to_instr || r->to_instr->next != NULL) 2951 return FALSE; 2952 if (r->to_instr->typ != INSTR_INSTR) 2953 return FALSE; 2954 return TRUE; 2955 } 2956 2957 2958 /* Check if there is exactly one relaxation for INSN that converts it to 2959 another instruction of equal or larger size. If so, and if TARG is 2960 non-null, go ahead and generate the relaxed instruction into TARG. If 2961 NARROW_ONLY is true, then only consider relaxations that widen a narrow 2962 instruction, i.e., ignore relaxations that convert to an instruction of 2963 equal size. In some contexts where this function is used, only 2964 a single widening is allowed and the NARROW_ONLY argument is used to 2965 exclude cases like ADDI being "widened" to an ADDMI, which may 2966 later be relaxed to an ADDMI/ADDI pair. */ 2967 2968 bfd_boolean 2969 xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) 2970 { 2971 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 2972 TransitionList *l; 2973 TransitionRule *match = 0; 2974 2975 assert (insn->insn_type == ITYPE_INSN); 2976 assert (insn->opcode < table->num_opcodes); 2977 2978 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 2979 { 2980 TransitionRule *rule = l->rule; 2981 2982 if (xg_instruction_matches_rule (insn, rule) 2983 && is_unique_insn_expansion (rule) 2984 && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) 2985 <= xg_get_single_size (rule->to_instr->opcode))) 2986 { 2987 if (match) 2988 return FALSE; 2989 match = rule; 2990 } 2991 } 2992 if (!match) 2993 return FALSE; 2994 2995 if (targ) 2996 xg_build_to_insn (targ, insn, match->to_instr); 2997 return TRUE; 2998 } 2999 3000 3001 /* Return the maximum number of bytes this opcode can expand to. */ 3002 3003 static int 3004 xg_get_max_insn_widen_size (xtensa_opcode opcode) 3005 { 3006 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3007 TransitionList *l; 3008 int max_size = xg_get_single_size (opcode); 3009 3010 assert (opcode < table->num_opcodes); 3011 3012 for (l = table->table[opcode]; l != NULL; l = l->next) 3013 { 3014 TransitionRule *rule = l->rule; 3015 BuildInstr *build_list; 3016 int this_size = 0; 3017 3018 if (!rule) 3019 continue; 3020 build_list = rule->to_instr; 3021 if (is_unique_insn_expansion (rule)) 3022 { 3023 assert (build_list->typ == INSTR_INSTR); 3024 this_size = xg_get_max_insn_widen_size (build_list->opcode); 3025 } 3026 else 3027 for (; build_list != NULL; build_list = build_list->next) 3028 { 3029 switch (build_list->typ) 3030 { 3031 case INSTR_INSTR: 3032 this_size += xg_get_single_size (build_list->opcode); 3033 break; 3034 case INSTR_LITERAL_DEF: 3035 case INSTR_LABEL_DEF: 3036 default: 3037 break; 3038 } 3039 } 3040 if (this_size > max_size) 3041 max_size = this_size; 3042 } 3043 return max_size; 3044 } 3045 3046 3047 /* Return the maximum number of literal bytes this opcode can generate. */ 3048 3049 static int 3050 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) 3051 { 3052 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3053 TransitionList *l; 3054 int max_size = 0; 3055 3056 assert (opcode < table->num_opcodes); 3057 3058 for (l = table->table[opcode]; l != NULL; l = l->next) 3059 { 3060 TransitionRule *rule = l->rule; 3061 BuildInstr *build_list; 3062 int this_size = 0; 3063 3064 if (!rule) 3065 continue; 3066 build_list = rule->to_instr; 3067 if (is_unique_insn_expansion (rule)) 3068 { 3069 assert (build_list->typ == INSTR_INSTR); 3070 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); 3071 } 3072 else 3073 for (; build_list != NULL; build_list = build_list->next) 3074 { 3075 switch (build_list->typ) 3076 { 3077 case INSTR_LITERAL_DEF: 3078 /* Hard-coded 4-byte literal. */ 3079 this_size += 4; 3080 break; 3081 case INSTR_INSTR: 3082 case INSTR_LABEL_DEF: 3083 default: 3084 break; 3085 } 3086 } 3087 if (this_size > max_size) 3088 max_size = this_size; 3089 } 3090 return max_size; 3091 } 3092 3093 3094 static bfd_boolean 3095 xg_is_relaxable_insn (TInsn *insn, int lateral_steps) 3096 { 3097 int steps_taken = 0; 3098 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3099 TransitionList *l; 3100 3101 assert (insn->insn_type == ITYPE_INSN); 3102 assert (insn->opcode < table->num_opcodes); 3103 3104 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3105 { 3106 TransitionRule *rule = l->rule; 3107 3108 if (xg_instruction_matches_rule (insn, rule)) 3109 { 3110 if (steps_taken == lateral_steps) 3111 return TRUE; 3112 steps_taken++; 3113 } 3114 } 3115 return FALSE; 3116 } 3117 3118 3119 static symbolS * 3120 get_special_literal_symbol (void) 3121 { 3122 static symbolS *sym = NULL; 3123 3124 if (sym == NULL) 3125 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); 3126 return sym; 3127 } 3128 3129 3130 static symbolS * 3131 get_special_label_symbol (void) 3132 { 3133 static symbolS *sym = NULL; 3134 3135 if (sym == NULL) 3136 sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); 3137 return sym; 3138 } 3139 3140 3141 static bfd_boolean 3142 xg_valid_literal_expression (const expressionS *exp) 3143 { 3144 switch (exp->X_op) 3145 { 3146 case O_constant: 3147 case O_symbol: 3148 case O_big: 3149 case O_uminus: 3150 case O_subtract: 3151 case O_pltrel: 3152 return TRUE; 3153 default: 3154 return FALSE; 3155 } 3156 } 3157 3158 3159 /* This will check to see if the value can be converted into the 3160 operand type. It will return TRUE if it does not fit. */ 3161 3162 static bfd_boolean 3163 xg_check_operand (int32 value, xtensa_opcode opcode, int operand) 3164 { 3165 uint32 valbuf = value; 3166 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) 3167 return TRUE; 3168 return FALSE; 3169 } 3170 3171 3172 /* Assumes: All immeds are constants. Check that all constants fit 3173 into their immeds; return FALSE if not. */ 3174 3175 static bfd_boolean 3176 xg_immeds_fit (const TInsn *insn) 3177 { 3178 xtensa_isa isa = xtensa_default_isa; 3179 int i; 3180 3181 int n = insn->ntok; 3182 assert (insn->insn_type == ITYPE_INSN); 3183 for (i = 0; i < n; ++i) 3184 { 3185 const expressionS *expr = &insn->tok[i]; 3186 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) 3187 continue; 3188 3189 switch (expr->X_op) 3190 { 3191 case O_register: 3192 case O_constant: 3193 if (xg_check_operand (expr->X_add_number, insn->opcode, i)) 3194 return FALSE; 3195 break; 3196 3197 default: 3198 /* The symbol should have a fixup associated with it. */ 3199 assert (FALSE); 3200 break; 3201 } 3202 } 3203 return TRUE; 3204 } 3205 3206 3207 /* This should only be called after we have an initial 3208 estimate of the addresses. */ 3209 3210 static bfd_boolean 3211 xg_symbolic_immeds_fit (const TInsn *insn, 3212 segT pc_seg, 3213 fragS *pc_frag, 3214 offsetT pc_offset, 3215 long stretch) 3216 { 3217 xtensa_isa isa = xtensa_default_isa; 3218 symbolS *symbolP; 3219 fragS *sym_frag; 3220 offsetT target, pc; 3221 uint32 new_offset; 3222 int i; 3223 int n = insn->ntok; 3224 3225 assert (insn->insn_type == ITYPE_INSN); 3226 3227 for (i = 0; i < n; ++i) 3228 { 3229 const expressionS *expr = &insn->tok[i]; 3230 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) 3231 continue; 3232 3233 switch (expr->X_op) 3234 { 3235 case O_register: 3236 case O_constant: 3237 if (xg_check_operand (expr->X_add_number, insn->opcode, i)) 3238 return FALSE; 3239 break; 3240 3241 case O_lo16: 3242 case O_hi16: 3243 /* Check for the worst case. */ 3244 if (xg_check_operand (0xffff, insn->opcode, i)) 3245 return FALSE; 3246 break; 3247 3248 case O_symbol: 3249 /* We only allow symbols for PC-relative references. 3250 If pc_frag == 0, then we don't have frag locations yet. */ 3251 if (pc_frag == 0 3252 || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) 3253 return FALSE; 3254 3255 /* If it is a weak symbol, then assume it won't reach. */ 3256 if (S_IS_WEAK (expr->X_add_symbol)) 3257 return FALSE; 3258 3259 if (is_direct_call_opcode (insn->opcode) 3260 && ! pc_frag->tc_frag_data.use_longcalls) 3261 { 3262 /* If callee is undefined or in a different segment, be 3263 optimistic and assume it will be in range. */ 3264 if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) 3265 return TRUE; 3266 } 3267 3268 /* Only references within a segment can be known to fit in the 3269 operands at assembly time. */ 3270 if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) 3271 return FALSE; 3272 3273 symbolP = expr->X_add_symbol; 3274 sym_frag = symbol_get_frag (symbolP); 3275 target = S_GET_VALUE (symbolP) + expr->X_add_number; 3276 pc = pc_frag->fr_address + pc_offset; 3277 3278 /* If frag has yet to be reached on this pass, assume it 3279 will move by STRETCH just as we did. If this is not so, 3280 it will be because some frag between grows, and that will 3281 force another pass. Beware zero-length frags. There 3282 should be a faster way to do this. */ 3283 3284 if (stretch != 0 3285 && sym_frag->relax_marker != pc_frag->relax_marker 3286 && S_GET_SEGMENT (symbolP) == pc_seg) 3287 { 3288 target += stretch; 3289 } 3290 3291 new_offset = target; 3292 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); 3293 if (xg_check_operand (new_offset, insn->opcode, i)) 3294 return FALSE; 3295 break; 3296 3297 default: 3298 /* The symbol should have a fixup associated with it. */ 3299 return FALSE; 3300 } 3301 } 3302 3303 return TRUE; 3304 } 3305 3306 3307 /* Return TRUE on success. */ 3308 3309 static bfd_boolean 3310 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) 3311 { 3312 BuildOp *op; 3313 symbolS *sym; 3314 3315 memset (targ, 0, sizeof (TInsn)); 3316 targ->linenum = insn->linenum; 3317 switch (bi->typ) 3318 { 3319 case INSTR_INSTR: 3320 op = bi->ops; 3321 targ->opcode = bi->opcode; 3322 targ->insn_type = ITYPE_INSN; 3323 targ->is_specific_opcode = FALSE; 3324 3325 for (; op != NULL; op = op->next) 3326 { 3327 int op_num = op->op_num; 3328 int op_data = op->op_data; 3329 3330 assert (op->op_num < MAX_INSN_ARGS); 3331 3332 if (targ->ntok <= op_num) 3333 targ->ntok = op_num + 1; 3334 3335 switch (op->typ) 3336 { 3337 case OP_CONSTANT: 3338 set_expr_const (&targ->tok[op_num], op_data); 3339 break; 3340 case OP_OPERAND: 3341 assert (op_data < insn->ntok); 3342 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3343 break; 3344 case OP_LITERAL: 3345 sym = get_special_literal_symbol (); 3346 set_expr_symbol_offset (&targ->tok[op_num], sym, 0); 3347 break; 3348 case OP_LABEL: 3349 sym = get_special_label_symbol (); 3350 set_expr_symbol_offset (&targ->tok[op_num], sym, 0); 3351 break; 3352 case OP_OPERAND_HI16U: 3353 case OP_OPERAND_LOW16U: 3354 assert (op_data < insn->ntok); 3355 if (expr_is_const (&insn->tok[op_data])) 3356 { 3357 long val; 3358 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3359 val = xg_apply_userdef_op_fn (op->typ, 3360 targ->tok[op_num]. 3361 X_add_number); 3362 targ->tok[op_num].X_add_number = val; 3363 } 3364 else 3365 { 3366 /* For const16 we can create relocations for these. */ 3367 if (targ->opcode == XTENSA_UNDEFINED 3368 || (targ->opcode != xtensa_const16_opcode)) 3369 return FALSE; 3370 assert (op_data < insn->ntok); 3371 /* Need to build a O_lo16 or O_hi16. */ 3372 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3373 if (targ->tok[op_num].X_op == O_symbol) 3374 { 3375 if (op->typ == OP_OPERAND_HI16U) 3376 targ->tok[op_num].X_op = O_hi16; 3377 else if (op->typ == OP_OPERAND_LOW16U) 3378 targ->tok[op_num].X_op = O_lo16; 3379 else 3380 return FALSE; 3381 } 3382 } 3383 break; 3384 default: 3385 /* currently handles: 3386 OP_OPERAND_LOW8 3387 OP_OPERAND_HI24S 3388 OP_OPERAND_F32MINUS */ 3389 if (xg_has_userdef_op_fn (op->typ)) 3390 { 3391 assert (op_data < insn->ntok); 3392 if (expr_is_const (&insn->tok[op_data])) 3393 { 3394 long val; 3395 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3396 val = xg_apply_userdef_op_fn (op->typ, 3397 targ->tok[op_num]. 3398 X_add_number); 3399 targ->tok[op_num].X_add_number = val; 3400 } 3401 else 3402 return FALSE; /* We cannot use a relocation for this. */ 3403 break; 3404 } 3405 assert (0); 3406 break; 3407 } 3408 } 3409 break; 3410 3411 case INSTR_LITERAL_DEF: 3412 op = bi->ops; 3413 targ->opcode = XTENSA_UNDEFINED; 3414 targ->insn_type = ITYPE_LITERAL; 3415 targ->is_specific_opcode = FALSE; 3416 for (; op != NULL; op = op->next) 3417 { 3418 int op_num = op->op_num; 3419 int op_data = op->op_data; 3420 assert (op->op_num < MAX_INSN_ARGS); 3421 3422 if (targ->ntok <= op_num) 3423 targ->ntok = op_num + 1; 3424 3425 switch (op->typ) 3426 { 3427 case OP_OPERAND: 3428 assert (op_data < insn->ntok); 3429 /* We can only pass resolvable literals through. */ 3430 if (!xg_valid_literal_expression (&insn->tok[op_data])) 3431 return FALSE; 3432 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3433 break; 3434 case OP_LITERAL: 3435 case OP_CONSTANT: 3436 case OP_LABEL: 3437 default: 3438 assert (0); 3439 break; 3440 } 3441 } 3442 break; 3443 3444 case INSTR_LABEL_DEF: 3445 op = bi->ops; 3446 targ->opcode = XTENSA_UNDEFINED; 3447 targ->insn_type = ITYPE_LABEL; 3448 targ->is_specific_opcode = FALSE; 3449 /* Literal with no ops is a label? */ 3450 assert (op == NULL); 3451 break; 3452 3453 default: 3454 assert (0); 3455 } 3456 3457 return TRUE; 3458 } 3459 3460 3461 /* Return TRUE on success. */ 3462 3463 static bfd_boolean 3464 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) 3465 { 3466 for (; bi != NULL; bi = bi->next) 3467 { 3468 TInsn *next_insn = istack_push_space (istack); 3469 3470 if (!xg_build_to_insn (next_insn, insn, bi)) 3471 return FALSE; 3472 } 3473 return TRUE; 3474 } 3475 3476 3477 /* Return TRUE on valid expansion. */ 3478 3479 static bfd_boolean 3480 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) 3481 { 3482 int stack_size = istack->ninsn; 3483 int steps_taken = 0; 3484 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3485 TransitionList *l; 3486 3487 assert (insn->insn_type == ITYPE_INSN); 3488 assert (insn->opcode < table->num_opcodes); 3489 3490 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3491 { 3492 TransitionRule *rule = l->rule; 3493 3494 if (xg_instruction_matches_rule (insn, rule)) 3495 { 3496 if (lateral_steps == steps_taken) 3497 { 3498 int i; 3499 3500 /* This is it. Expand the rule to the stack. */ 3501 if (!xg_build_to_stack (istack, insn, rule->to_instr)) 3502 return FALSE; 3503 3504 /* Check to see if it fits. */ 3505 for (i = stack_size; i < istack->ninsn; i++) 3506 { 3507 TInsn *insn = &istack->insn[i]; 3508 3509 if (insn->insn_type == ITYPE_INSN 3510 && !tinsn_has_symbolic_operands (insn) 3511 && !xg_immeds_fit (insn)) 3512 { 3513 istack->ninsn = stack_size; 3514 return FALSE; 3515 } 3516 } 3517 return TRUE; 3518 } 3519 steps_taken++; 3520 } 3521 } 3522 return FALSE; 3523 } 3524 3525 3526 /* Relax the assembly instruction at least "min_steps". 3527 Return the number of steps taken. */ 3528 3529 static int 3530 xg_assembly_relax (IStack *istack, 3531 TInsn *insn, 3532 segT pc_seg, 3533 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ 3534 offsetT pc_offset, /* offset in fragment */ 3535 int min_steps, /* minimum conversion steps */ 3536 long stretch) /* number of bytes stretched so far */ 3537 { 3538 int steps_taken = 0; 3539 3540 /* assert (has no symbolic operands) 3541 Some of its immeds don't fit. 3542 Try to build a relaxed version. 3543 This may go through a couple of stages 3544 of single instruction transformations before 3545 we get there. */ 3546 3547 TInsn single_target; 3548 TInsn current_insn; 3549 int lateral_steps = 0; 3550 int istack_size = istack->ninsn; 3551 3552 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) 3553 && steps_taken >= min_steps) 3554 { 3555 istack_push (istack, insn); 3556 return steps_taken; 3557 } 3558 current_insn = *insn; 3559 3560 /* Walk through all of the single instruction expansions. */ 3561 while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) 3562 { 3563 steps_taken++; 3564 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, 3565 stretch)) 3566 { 3567 if (steps_taken >= min_steps) 3568 { 3569 istack_push (istack, &single_target); 3570 return steps_taken; 3571 } 3572 } 3573 current_insn = single_target; 3574 } 3575 3576 /* Now check for a multi-instruction expansion. */ 3577 while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) 3578 { 3579 if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, 3580 stretch)) 3581 { 3582 if (steps_taken >= min_steps) 3583 { 3584 istack_push (istack, ¤t_insn); 3585 return steps_taken; 3586 } 3587 } 3588 steps_taken++; 3589 if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) 3590 { 3591 if (steps_taken >= min_steps) 3592 return steps_taken; 3593 } 3594 lateral_steps++; 3595 istack->ninsn = istack_size; 3596 } 3597 3598 /* It's not going to work -- use the original. */ 3599 istack_push (istack, insn); 3600 return steps_taken; 3601 } 3602 3603 3604 static void 3605 xg_force_frag_space (int size) 3606 { 3607 /* This may have the side effect of creating a new fragment for the 3608 space to go into. I just do not like the name of the "frag" 3609 functions. */ 3610 frag_grow (size); 3611 } 3612 3613 3614 static void 3615 xg_finish_frag (char *last_insn, 3616 enum xtensa_relax_statesE frag_state, 3617 enum xtensa_relax_statesE slot0_state, 3618 int max_growth, 3619 bfd_boolean is_insn) 3620 { 3621 /* Finish off this fragment so that it has at LEAST the desired 3622 max_growth. If it doesn't fit in this fragment, close this one 3623 and start a new one. In either case, return a pointer to the 3624 beginning of the growth area. */ 3625 3626 fragS *old_frag; 3627 3628 xg_force_frag_space (max_growth); 3629 3630 old_frag = frag_now; 3631 3632 frag_now->fr_opcode = last_insn; 3633 if (is_insn) 3634 frag_now->tc_frag_data.is_insn = TRUE; 3635 3636 frag_var (rs_machine_dependent, max_growth, max_growth, 3637 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); 3638 3639 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; 3640 xtensa_set_frag_assembly_state (frag_now); 3641 3642 /* Just to make sure that we did not split it up. */ 3643 assert (old_frag->fr_next == frag_now); 3644 } 3645 3646 3647 /* Return TRUE if the target frag is one of the next non-empty frags. */ 3648 3649 static bfd_boolean 3650 is_next_frag_target (const fragS *fragP, const fragS *target) 3651 { 3652 if (fragP == NULL) 3653 return FALSE; 3654 3655 for (; fragP; fragP = fragP->fr_next) 3656 { 3657 if (fragP == target) 3658 return TRUE; 3659 if (fragP->fr_fix != 0) 3660 return FALSE; 3661 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) 3662 return FALSE; 3663 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) 3664 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) 3665 return FALSE; 3666 if (fragP->fr_type == rs_space) 3667 return FALSE; 3668 } 3669 return FALSE; 3670 } 3671 3672 3673 static bfd_boolean 3674 is_branch_jmp_to_next (TInsn *insn, fragS *fragP) 3675 { 3676 xtensa_isa isa = xtensa_default_isa; 3677 int i; 3678 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 3679 int target_op = -1; 3680 symbolS *sym; 3681 fragS *target_frag; 3682 3683 if (xtensa_opcode_is_branch (isa, insn->opcode) == 0 3684 && xtensa_opcode_is_jump (isa, insn->opcode) == 0) 3685 return FALSE; 3686 3687 for (i = 0; i < num_ops; i++) 3688 { 3689 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) 3690 { 3691 target_op = i; 3692 break; 3693 } 3694 } 3695 if (target_op == -1) 3696 return FALSE; 3697 3698 if (insn->ntok <= target_op) 3699 return FALSE; 3700 3701 if (insn->tok[target_op].X_op != O_symbol) 3702 return FALSE; 3703 3704 sym = insn->tok[target_op].X_add_symbol; 3705 if (sym == NULL) 3706 return FALSE; 3707 3708 if (insn->tok[target_op].X_add_number != 0) 3709 return FALSE; 3710 3711 target_frag = symbol_get_frag (sym); 3712 if (target_frag == NULL) 3713 return FALSE; 3714 3715 if (is_next_frag_target (fragP->fr_next, target_frag) 3716 && S_GET_VALUE (sym) == target_frag->fr_address) 3717 return TRUE; 3718 3719 return FALSE; 3720 } 3721 3722 3723 static void 3724 xg_add_branch_and_loop_targets (TInsn *insn) 3725 { 3726 xtensa_isa isa = xtensa_default_isa; 3727 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 3728 3729 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) 3730 { 3731 int i = 1; 3732 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 3733 && insn->tok[i].X_op == O_symbol) 3734 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; 3735 return; 3736 } 3737 3738 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 3739 || xtensa_opcode_is_loop (isa, insn->opcode) == 1) 3740 { 3741 int i; 3742 3743 for (i = 0; i < insn->ntok && i < num_ops; i++) 3744 { 3745 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 3746 && insn->tok[i].X_op == O_symbol) 3747 { 3748 symbolS *sym = insn->tok[i].X_add_symbol; 3749 symbol_get_tc (sym)->is_branch_target = TRUE; 3750 if (S_IS_DEFINED (sym)) 3751 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; 3752 } 3753 } 3754 } 3755 } 3756 3757 3758 /* Return FALSE if no error. */ 3759 3760 static bfd_boolean 3761 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) 3762 { 3763 int num_ops = 0; 3764 BuildOp *b_op; 3765 3766 switch (instr_spec->typ) 3767 { 3768 case INSTR_INSTR: 3769 new_insn->insn_type = ITYPE_INSN; 3770 new_insn->opcode = instr_spec->opcode; 3771 new_insn->is_specific_opcode = FALSE; 3772 new_insn->linenum = old_insn->linenum; 3773 break; 3774 case INSTR_LITERAL_DEF: 3775 new_insn->insn_type = ITYPE_LITERAL; 3776 new_insn->opcode = XTENSA_UNDEFINED; 3777 new_insn->is_specific_opcode = FALSE; 3778 new_insn->linenum = old_insn->linenum; 3779 break; 3780 case INSTR_LABEL_DEF: 3781 as_bad (_("INSTR_LABEL_DEF not supported yet")); 3782 break; 3783 } 3784 3785 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) 3786 { 3787 expressionS *exp; 3788 const expressionS *src_exp; 3789 3790 num_ops++; 3791 switch (b_op->typ) 3792 { 3793 case OP_CONSTANT: 3794 /* The expression must be the constant. */ 3795 assert (b_op->op_num < MAX_INSN_ARGS); 3796 exp = &new_insn->tok[b_op->op_num]; 3797 set_expr_const (exp, b_op->op_data); 3798 break; 3799 3800 case OP_OPERAND: 3801 assert (b_op->op_num < MAX_INSN_ARGS); 3802 assert (b_op->op_data < (unsigned) old_insn->ntok); 3803 src_exp = &old_insn->tok[b_op->op_data]; 3804 exp = &new_insn->tok[b_op->op_num]; 3805 copy_expr (exp, src_exp); 3806 break; 3807 3808 case OP_LITERAL: 3809 case OP_LABEL: 3810 as_bad (_("can't handle generation of literal/labels yet")); 3811 assert (0); 3812 3813 default: 3814 as_bad (_("can't handle undefined OP TYPE")); 3815 assert (0); 3816 } 3817 } 3818 3819 new_insn->ntok = num_ops; 3820 return FALSE; 3821 } 3822 3823 3824 /* Return TRUE if it was simplified. */ 3825 3826 static bfd_boolean 3827 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) 3828 { 3829 TransitionRule *rule; 3830 BuildInstr *insn_spec; 3831 3832 if (old_insn->is_specific_opcode || !density_supported) 3833 return FALSE; 3834 3835 rule = xg_instruction_match (old_insn); 3836 if (rule == NULL) 3837 return FALSE; 3838 3839 insn_spec = rule->to_instr; 3840 /* There should only be one. */ 3841 assert (insn_spec != NULL); 3842 assert (insn_spec->next == NULL); 3843 if (insn_spec->next != NULL) 3844 return FALSE; 3845 3846 xg_build_token_insn (insn_spec, old_insn, new_insn); 3847 3848 return TRUE; 3849 } 3850 3851 3852 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> 3853 l32i.n. (2) Check the number of operands. (3) Place the instruction 3854 tokens into the stack or relax it and place multiple 3855 instructions/literals onto the stack. Return FALSE if no error. */ 3856 3857 static bfd_boolean 3858 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) 3859 { 3860 int noperands; 3861 TInsn new_insn; 3862 bfd_boolean do_expand; 3863 3864 memset (&new_insn, 0, sizeof (TInsn)); 3865 3866 /* Narrow it if we can. xg_simplify_insn now does all the 3867 appropriate checking (e.g., for the density option). */ 3868 if (xg_simplify_insn (orig_insn, &new_insn)) 3869 orig_insn = &new_insn; 3870 3871 noperands = xtensa_opcode_num_operands (xtensa_default_isa, 3872 orig_insn->opcode); 3873 if (orig_insn->ntok < noperands) 3874 { 3875 as_bad (_("found %d operands for '%s': Expected %d"), 3876 orig_insn->ntok, 3877 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), 3878 noperands); 3879 return TRUE; 3880 } 3881 if (orig_insn->ntok > noperands) 3882 as_warn (_("found too many (%d) operands for '%s': Expected %d"), 3883 orig_insn->ntok, 3884 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), 3885 noperands); 3886 3887 /* If there are not enough operands, we will assert above. If there 3888 are too many, just cut out the extras here. */ 3889 orig_insn->ntok = noperands; 3890 3891 if (tinsn_has_invalid_symbolic_operands (orig_insn)) 3892 return TRUE; 3893 3894 /* If the instruction will definitely need to be relaxed, it is better 3895 to expand it now for better scheduling. Decide whether to expand 3896 now.... */ 3897 do_expand = (!orig_insn->is_specific_opcode && use_transform ()); 3898 3899 /* Calls should be expanded to longcalls only in the backend relaxation 3900 so that the assembly scheduler will keep the L32R/CALLX instructions 3901 adjacent. */ 3902 if (is_direct_call_opcode (orig_insn->opcode)) 3903 do_expand = FALSE; 3904 3905 if (tinsn_has_symbolic_operands (orig_insn)) 3906 { 3907 /* The values of symbolic operands are not known yet, so only expand 3908 now if an operand is "complex" (e.g., difference of symbols) and 3909 will have to be stored as a literal regardless of the value. */ 3910 if (!tinsn_has_complex_operands (orig_insn)) 3911 do_expand = FALSE; 3912 } 3913 else if (xg_immeds_fit (orig_insn)) 3914 do_expand = FALSE; 3915 3916 if (do_expand) 3917 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); 3918 else 3919 istack_push (istack, orig_insn); 3920 3921 return FALSE; 3922 } 3923 3924 3925 /* Return TRUE if the section flags are marked linkonce 3926 or the name is .gnu.linkonce*. */ 3927 3928 static bfd_boolean 3929 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) 3930 { 3931 flagword flags, link_once_flags; 3932 3933 flags = bfd_get_section_flags (abfd, sec); 3934 link_once_flags = (flags & SEC_LINK_ONCE); 3935 3936 /* Flags might not be set yet. */ 3937 if (!link_once_flags) 3938 { 3939 static size_t len = sizeof ".gnu.linkonce.t."; 3940 3941 if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0) 3942 link_once_flags = SEC_LINK_ONCE; 3943 } 3944 return (link_once_flags != 0); 3945 } 3946 3947 3948 static void 3949 xtensa_add_literal_sym (symbolS *sym) 3950 { 3951 sym_list *l; 3952 3953 l = (sym_list *) xmalloc (sizeof (sym_list)); 3954 l->sym = sym; 3955 l->next = literal_syms; 3956 literal_syms = l; 3957 } 3958 3959 3960 static symbolS * 3961 xtensa_create_literal_symbol (segT sec, fragS *frag) 3962 { 3963 static int lit_num = 0; 3964 static char name[256]; 3965 symbolS *symbolP; 3966 3967 sprintf (name, ".L_lit_sym%d", lit_num); 3968 3969 /* Create a local symbol. If it is in a linkonce section, we have to 3970 be careful to make sure that if it is used in a relocation that the 3971 symbol will be in the output file. */ 3972 if (get_is_linkonce_section (stdoutput, sec)) 3973 { 3974 symbolP = symbol_new (name, sec, 0, frag); 3975 S_CLEAR_EXTERNAL (symbolP); 3976 /* symbolP->local = 1; */ 3977 } 3978 else 3979 symbolP = symbol_new (name, sec, 0, frag); 3980 3981 xtensa_add_literal_sym (symbolP); 3982 3983 lit_num++; 3984 return symbolP; 3985 } 3986 3987 3988 /* Currently all literals that are generated here are 32-bit L32R targets. */ 3989 3990 static symbolS * 3991 xg_assemble_literal (/* const */ TInsn *insn) 3992 { 3993 emit_state state; 3994 symbolS *lit_sym = NULL; 3995 3996 /* size = 4 for L32R. It could easily be larger when we move to 3997 larger constants. Add a parameter later. */ 3998 offsetT litsize = 4; 3999 offsetT litalign = 2; /* 2^2 = 4 */ 4000 expressionS saved_loc; 4001 expressionS * emit_val; 4002 4003 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); 4004 4005 assert (insn->insn_type == ITYPE_LITERAL); 4006 assert (insn->ntok == 1); /* must be only one token here */ 4007 4008 xtensa_switch_to_literal_fragment (&state); 4009 4010 emit_val = &insn->tok[0]; 4011 if (emit_val->X_op == O_big) 4012 { 4013 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; 4014 if (size > litsize) 4015 { 4016 /* This happens when someone writes a "movi a2, big_number". */ 4017 as_bad_where (frag_now->fr_file, frag_now->fr_line, 4018 _("invalid immediate")); 4019 xtensa_restore_emit_state (&state); 4020 return NULL; 4021 } 4022 } 4023 4024 /* Force a 4-byte align here. Note that this opens a new frag, so all 4025 literals done with this function have a frag to themselves. That's 4026 important for the way text section literals work. */ 4027 frag_align (litalign, 0, 0); 4028 record_alignment (now_seg, litalign); 4029 4030 if (emit_val->X_op == O_pltrel) 4031 { 4032 char *p = frag_more (litsize); 4033 xtensa_set_frag_assembly_state (frag_now); 4034 if (emit_val->X_add_symbol) 4035 emit_val->X_op = O_symbol; 4036 else 4037 emit_val->X_op = O_constant; 4038 fix_new_exp (frag_now, p - frag_now->fr_literal, 4039 litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT); 4040 } 4041 else 4042 emit_expr (emit_val, litsize); 4043 4044 assert (frag_now->tc_frag_data.literal_frag == NULL); 4045 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); 4046 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); 4047 lit_sym = frag_now->fr_symbol; 4048 4049 /* Go back. */ 4050 xtensa_restore_emit_state (&state); 4051 return lit_sym; 4052 } 4053 4054 4055 static void 4056 xg_assemble_literal_space (/* const */ int size, int slot) 4057 { 4058 emit_state state; 4059 /* We might have to do something about this alignment. It only 4060 takes effect if something is placed here. */ 4061 offsetT litalign = 2; /* 2^2 = 4 */ 4062 fragS *lit_saved_frag; 4063 4064 assert (size % 4 == 0); 4065 4066 xtensa_switch_to_literal_fragment (&state); 4067 4068 /* Force a 4-byte align here. */ 4069 frag_align (litalign, 0, 0); 4070 record_alignment (now_seg, litalign); 4071 4072 xg_force_frag_space (size); 4073 4074 lit_saved_frag = frag_now; 4075 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); 4076 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); 4077 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); 4078 4079 /* Go back. */ 4080 xtensa_restore_emit_state (&state); 4081 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; 4082 } 4083 4084 4085 /* Put in a fixup record based on the opcode. 4086 Return TRUE on success. */ 4087 4088 static bfd_boolean 4089 xg_add_opcode_fix (TInsn *tinsn, 4090 int opnum, 4091 xtensa_format fmt, 4092 int slot, 4093 expressionS *expr, 4094 fragS *fragP, 4095 offsetT offset) 4096 { 4097 xtensa_opcode opcode = tinsn->opcode; 4098 bfd_reloc_code_real_type reloc; 4099 reloc_howto_type *howto; 4100 int fmt_length; 4101 fixS *the_fix; 4102 4103 reloc = BFD_RELOC_NONE; 4104 4105 /* First try the special cases for "alternate" relocs. */ 4106 if (opcode == xtensa_l32r_opcode) 4107 { 4108 if (fragP->tc_frag_data.use_absolute_literals) 4109 reloc = encode_alt_reloc (slot); 4110 } 4111 else if (opcode == xtensa_const16_opcode) 4112 { 4113 if (expr->X_op == O_lo16) 4114 { 4115 reloc = encode_reloc (slot); 4116 expr->X_op = O_symbol; 4117 } 4118 else if (expr->X_op == O_hi16) 4119 { 4120 reloc = encode_alt_reloc (slot); 4121 expr->X_op = O_symbol; 4122 } 4123 } 4124 4125 if (opnum != get_relaxable_immed (opcode)) 4126 { 4127 as_bad (_("invalid relocation for operand %i of '%s'"), 4128 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); 4129 return FALSE; 4130 } 4131 4132 /* Handle erroneous "@h" and "@l" expressions here before they propagate 4133 into the symbol table where the generic portions of the assembler 4134 won't know what to do with them. */ 4135 if (expr->X_op == O_lo16 || expr->X_op == O_hi16) 4136 { 4137 as_bad (_("invalid expression for operand %i of '%s'"), 4138 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); 4139 return FALSE; 4140 } 4141 4142 /* Next try the generic relocs. */ 4143 if (reloc == BFD_RELOC_NONE) 4144 reloc = encode_reloc (slot); 4145 if (reloc == BFD_RELOC_NONE) 4146 { 4147 as_bad (_("invalid relocation in instruction slot %i"), slot); 4148 return FALSE; 4149 } 4150 4151 howto = bfd_reloc_type_lookup (stdoutput, reloc); 4152 if (!howto) 4153 { 4154 as_bad (_("undefined symbol for opcode \"%s\""), 4155 xtensa_opcode_name (xtensa_default_isa, opcode)); 4156 return FALSE; 4157 } 4158 4159 fmt_length = xtensa_format_length (xtensa_default_isa, fmt); 4160 the_fix = fix_new_exp (fragP, offset, fmt_length, expr, 4161 howto->pc_relative, reloc); 4162 the_fix->fx_no_overflow = 1; 4163 4164 if (expr->X_add_symbol 4165 && (S_IS_EXTERNAL (expr->X_add_symbol) 4166 || S_IS_WEAK (expr->X_add_symbol))) 4167 the_fix->fx_plt = TRUE; 4168 4169 the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; 4170 the_fix->tc_fix_data.X_add_number = expr->X_add_number; 4171 the_fix->tc_fix_data.slot = slot; 4172 4173 return TRUE; 4174 } 4175 4176 4177 static bfd_boolean 4178 xg_emit_insn_to_buf (TInsn *tinsn, 4179 char *buf, 4180 fragS *fragP, 4181 offsetT offset, 4182 bfd_boolean build_fix) 4183 { 4184 static xtensa_insnbuf insnbuf = NULL; 4185 bfd_boolean has_symbolic_immed = FALSE; 4186 bfd_boolean ok = TRUE; 4187 4188 if (!insnbuf) 4189 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 4190 4191 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); 4192 if (has_symbolic_immed && build_fix) 4193 { 4194 /* Add a fixup. */ 4195 xtensa_format fmt = xg_get_single_format (tinsn->opcode); 4196 int slot = xg_get_single_slot (tinsn->opcode); 4197 int opnum = get_relaxable_immed (tinsn->opcode); 4198 expressionS *exp = &tinsn->tok[opnum]; 4199 4200 if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) 4201 ok = FALSE; 4202 } 4203 fragP->tc_frag_data.is_insn = TRUE; 4204 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, 4205 (unsigned char *) buf, 0); 4206 return ok; 4207 } 4208 4209 4210 static void 4211 xg_resolve_literals (TInsn *insn, symbolS *lit_sym) 4212 { 4213 symbolS *sym = get_special_literal_symbol (); 4214 int i; 4215 if (lit_sym == 0) 4216 return; 4217 assert (insn->insn_type == ITYPE_INSN); 4218 for (i = 0; i < insn->ntok; i++) 4219 if (insn->tok[i].X_add_symbol == sym) 4220 insn->tok[i].X_add_symbol = lit_sym; 4221 4222 } 4223 4224 4225 static void 4226 xg_resolve_labels (TInsn *insn, symbolS *label_sym) 4227 { 4228 symbolS *sym = get_special_label_symbol (); 4229 int i; 4230 for (i = 0; i < insn->ntok; i++) 4231 if (insn->tok[i].X_add_symbol == sym) 4232 insn->tok[i].X_add_symbol = label_sym; 4233 4234 } 4235 4236 4237 /* Return TRUE if the instruction can write to the specified 4238 integer register. */ 4239 4240 static bfd_boolean 4241 is_register_writer (const TInsn *insn, const char *regset, int regnum) 4242 { 4243 int i; 4244 int num_ops; 4245 xtensa_isa isa = xtensa_default_isa; 4246 4247 num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 4248 4249 for (i = 0; i < num_ops; i++) 4250 { 4251 char inout; 4252 inout = xtensa_operand_inout (isa, insn->opcode, i); 4253 if ((inout == 'o' || inout == 'm') 4254 && xtensa_operand_is_register (isa, insn->opcode, i) == 1) 4255 { 4256 xtensa_regfile opnd_rf = 4257 xtensa_operand_regfile (isa, insn->opcode, i); 4258 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) 4259 { 4260 if ((insn->tok[i].X_op == O_register) 4261 && (insn->tok[i].X_add_number == regnum)) 4262 return TRUE; 4263 } 4264 } 4265 } 4266 return FALSE; 4267 } 4268 4269 4270 static bfd_boolean 4271 is_bad_loopend_opcode (const TInsn *tinsn) 4272 { 4273 xtensa_opcode opcode = tinsn->opcode; 4274 4275 if (opcode == XTENSA_UNDEFINED) 4276 return FALSE; 4277 4278 if (opcode == xtensa_call0_opcode 4279 || opcode == xtensa_callx0_opcode 4280 || opcode == xtensa_call4_opcode 4281 || opcode == xtensa_callx4_opcode 4282 || opcode == xtensa_call8_opcode 4283 || opcode == xtensa_callx8_opcode 4284 || opcode == xtensa_call12_opcode 4285 || opcode == xtensa_callx12_opcode 4286 || opcode == xtensa_isync_opcode 4287 || opcode == xtensa_ret_opcode 4288 || opcode == xtensa_ret_n_opcode 4289 || opcode == xtensa_retw_opcode 4290 || opcode == xtensa_retw_n_opcode 4291 || opcode == xtensa_waiti_opcode 4292 || opcode == xtensa_rsr_lcount_opcode) 4293 return TRUE; 4294 4295 return FALSE; 4296 } 4297 4298 4299 /* Labels that begin with ".Ln" or ".LM" are unaligned. 4300 This allows the debugger to add unaligned labels. 4301 Also, the assembler generates stabs labels that need 4302 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ 4303 4304 static bfd_boolean 4305 is_unaligned_label (symbolS *sym) 4306 { 4307 const char *name = S_GET_NAME (sym); 4308 static size_t fake_size = 0; 4309 4310 if (name 4311 && name[0] == '.' 4312 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) 4313 return TRUE; 4314 4315 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ 4316 if (fake_size == 0) 4317 fake_size = strlen (FAKE_LABEL_NAME); 4318 4319 if (name 4320 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 4321 && (name[fake_size] == 'F' 4322 || name[fake_size] == 'L' 4323 || (name[fake_size] == 'e' 4324 && strncmp ("endfunc", name+fake_size, 7) == 0))) 4325 return TRUE; 4326 4327 return FALSE; 4328 } 4329 4330 4331 static fragS * 4332 next_non_empty_frag (const fragS *fragP) 4333 { 4334 fragS *next_fragP = fragP->fr_next; 4335 4336 /* Sometimes an empty will end up here due storage allocation issues. 4337 So we have to skip until we find something legit. */ 4338 while (next_fragP && next_fragP->fr_fix == 0) 4339 next_fragP = next_fragP->fr_next; 4340 4341 if (next_fragP == NULL || next_fragP->fr_fix == 0) 4342 return NULL; 4343 4344 return next_fragP; 4345 } 4346 4347 4348 static bfd_boolean 4349 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) 4350 { 4351 xtensa_opcode out_opcode; 4352 const fragS *next_fragP = next_non_empty_frag (fragP); 4353 4354 if (next_fragP == NULL) 4355 return FALSE; 4356 4357 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); 4358 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) 4359 { 4360 *opcode = out_opcode; 4361 return TRUE; 4362 } 4363 return FALSE; 4364 } 4365 4366 4367 static int 4368 frag_format_size (const fragS *fragP) 4369 { 4370 static xtensa_insnbuf insnbuf = NULL; 4371 xtensa_isa isa = xtensa_default_isa; 4372 xtensa_format fmt; 4373 int fmt_size; 4374 4375 if (!insnbuf) 4376 insnbuf = xtensa_insnbuf_alloc (isa); 4377 4378 if (fragP == NULL) 4379 return XTENSA_UNDEFINED; 4380 4381 xtensa_insnbuf_from_chars (isa, insnbuf, 4382 (unsigned char *) fragP->fr_literal, 0); 4383 4384 fmt = xtensa_format_decode (isa, insnbuf); 4385 if (fmt == XTENSA_UNDEFINED) 4386 return XTENSA_UNDEFINED; 4387 fmt_size = xtensa_format_length (isa, fmt); 4388 4389 /* If the next format won't be changing due to relaxation, just 4390 return the length of the first format. */ 4391 if (fragP->fr_opcode != fragP->fr_literal) 4392 return fmt_size; 4393 4394 /* If during relaxation we have to pull an instruction out of a 4395 multi-slot instruction, we will return the more conservative 4396 number. This works because alignment on bigger instructions 4397 is more restrictive than alignment on smaller instructions. 4398 This is more conservative than we would like, but it happens 4399 infrequently. */ 4400 4401 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) 4402 return fmt_size; 4403 4404 /* If we aren't doing one of our own relaxations or it isn't 4405 slot-based, then the insn size won't change. */ 4406 if (fragP->fr_type != rs_machine_dependent) 4407 return fmt_size; 4408 if (fragP->fr_subtype != RELAX_SLOTS) 4409 return fmt_size; 4410 4411 /* If an instruction is about to grow, return the longer size. */ 4412 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 4413 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2) 4414 return 3; 4415 4416 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 4417 return 2 + fragP->tc_frag_data.text_expansion[0]; 4418 4419 return fmt_size; 4420 } 4421 4422 4423 static int 4424 next_frag_format_size (const fragS *fragP) 4425 { 4426 const fragS *next_fragP = next_non_empty_frag (fragP); 4427 return frag_format_size (next_fragP); 4428 } 4429 4430 4431 /* In early Xtensa Processors, for reasons that are unclear, the ISA 4432 required two-byte instructions to be treated as three-byte instructions 4433 for loop instruction alignment. This restriction was removed beginning 4434 with Xtensa LX. Now the only requirement on loop instruction alignment 4435 is that the first instruction of the loop must appear at an address that 4436 does not cross a fetch boundary. */ 4437 4438 static int 4439 get_loop_align_size (int insn_size) 4440 { 4441 if (insn_size == XTENSA_UNDEFINED) 4442 return xtensa_fetch_width; 4443 4444 if (enforce_three_byte_loop_align && insn_size == 2) 4445 return 3; 4446 4447 return insn_size; 4448 } 4449 4450 4451 /* If the next legit fragment is an end-of-loop marker, 4452 switch its state so it will instantiate a NOP. */ 4453 4454 static void 4455 update_next_frag_state (fragS *fragP) 4456 { 4457 fragS *next_fragP = fragP->fr_next; 4458 fragS *new_target = NULL; 4459 4460 if (align_targets) 4461 { 4462 /* We are guaranteed there will be one of these... */ 4463 while (!(next_fragP->fr_type == rs_machine_dependent 4464 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE 4465 || next_fragP->fr_subtype == RELAX_UNREACHABLE))) 4466 next_fragP = next_fragP->fr_next; 4467 4468 assert (next_fragP->fr_type == rs_machine_dependent 4469 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE 4470 || next_fragP->fr_subtype == RELAX_UNREACHABLE)); 4471 4472 /* ...and one of these. */ 4473 new_target = next_fragP->fr_next; 4474 while (!(new_target->fr_type == rs_machine_dependent 4475 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN 4476 || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) 4477 new_target = new_target->fr_next; 4478 4479 assert (new_target->fr_type == rs_machine_dependent 4480 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN 4481 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); 4482 } 4483 4484 while (next_fragP && next_fragP->fr_fix == 0) 4485 { 4486 if (next_fragP->fr_type == rs_machine_dependent 4487 && next_fragP->fr_subtype == RELAX_LOOP_END) 4488 { 4489 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; 4490 return; 4491 } 4492 4493 next_fragP = next_fragP->fr_next; 4494 } 4495 } 4496 4497 4498 static bfd_boolean 4499 next_frag_is_branch_target (const fragS *fragP) 4500 { 4501 /* Sometimes an empty will end up here due to storage allocation issues, 4502 so we have to skip until we find something legit. */ 4503 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) 4504 { 4505 if (fragP->tc_frag_data.is_branch_target) 4506 return TRUE; 4507 if (fragP->fr_fix != 0) 4508 break; 4509 } 4510 return FALSE; 4511 } 4512 4513 4514 static bfd_boolean 4515 next_frag_is_loop_target (const fragS *fragP) 4516 { 4517 /* Sometimes an empty will end up here due storage allocation issues. 4518 So we have to skip until we find something legit. */ 4519 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) 4520 { 4521 if (fragP->tc_frag_data.is_loop_target) 4522 return TRUE; 4523 if (fragP->fr_fix != 0) 4524 break; 4525 } 4526 return FALSE; 4527 } 4528 4529 4530 static addressT 4531 next_frag_pre_opcode_bytes (const fragS *fragp) 4532 { 4533 const fragS *next_fragp = fragp->fr_next; 4534 xtensa_opcode next_opcode; 4535 4536 if (!next_frag_opcode_is_loop (fragp, &next_opcode)) 4537 return 0; 4538 4539 /* Sometimes an empty will end up here due to storage allocation issues, 4540 so we have to skip until we find something legit. */ 4541 while (next_fragp->fr_fix == 0) 4542 next_fragp = next_fragp->fr_next; 4543 4544 if (next_fragp->fr_type != rs_machine_dependent) 4545 return 0; 4546 4547 /* There is some implicit knowledge encoded in here. 4548 The LOOP instructions that are NOT RELAX_IMMED have 4549 been relaxed. Note that we can assume that the LOOP 4550 instruction is in slot 0 because loops aren't bundleable. */ 4551 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) 4552 return get_expanded_loop_offset (next_opcode); 4553 4554 return 0; 4555 } 4556 4557 4558 /* Mark a location where we can later insert literal frags. Update 4559 the section's literal_pool_loc, so subsequent literals can be 4560 placed nearest to their use. */ 4561 4562 static void 4563 xtensa_mark_literal_pool_location (void) 4564 { 4565 /* Any labels pointing to the current location need 4566 to be adjusted to after the literal pool. */ 4567 emit_state s; 4568 fragS *pool_location; 4569 4570 if (use_literal_section && !directive_state[directive_absolute_literals]) 4571 return; 4572 4573 frag_align (2, 0, 0); 4574 record_alignment (now_seg, 2); 4575 4576 /* We stash info in these frags so we can later move the literal's 4577 fixes into this frchain's fix list. */ 4578 pool_location = frag_now; 4579 frag_now->tc_frag_data.lit_frchain = frchain_now; 4580 frag_variant (rs_machine_dependent, 0, 0, 4581 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); 4582 xtensa_set_frag_assembly_state (frag_now); 4583 frag_now->tc_frag_data.lit_seg = now_seg; 4584 frag_variant (rs_machine_dependent, 0, 0, 4585 RELAX_LITERAL_POOL_END, NULL, 0, NULL); 4586 xtensa_set_frag_assembly_state (frag_now); 4587 4588 /* Now put a frag into the literal pool that points to this location. */ 4589 set_literal_pool_location (now_seg, pool_location); 4590 xtensa_switch_to_non_abs_literal_fragment (&s); 4591 frag_align (2, 0, 0); 4592 record_alignment (now_seg, 2); 4593 4594 /* Close whatever frag is there. */ 4595 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 4596 xtensa_set_frag_assembly_state (frag_now); 4597 frag_now->tc_frag_data.literal_frag = pool_location; 4598 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 4599 xtensa_restore_emit_state (&s); 4600 xtensa_set_frag_assembly_state (frag_now); 4601 } 4602 4603 4604 /* Build a nop of the correct size into tinsn. */ 4605 4606 static void 4607 build_nop (TInsn *tinsn, int size) 4608 { 4609 tinsn_init (tinsn); 4610 switch (size) 4611 { 4612 case 2: 4613 tinsn->opcode = xtensa_nop_n_opcode; 4614 tinsn->ntok = 0; 4615 if (tinsn->opcode == XTENSA_UNDEFINED) 4616 as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); 4617 break; 4618 4619 case 3: 4620 if (xtensa_nop_opcode == XTENSA_UNDEFINED) 4621 { 4622 tinsn->opcode = xtensa_or_opcode; 4623 set_expr_const (&tinsn->tok[0], 1); 4624 set_expr_const (&tinsn->tok[1], 1); 4625 set_expr_const (&tinsn->tok[2], 1); 4626 tinsn->ntok = 3; 4627 } 4628 else 4629 tinsn->opcode = xtensa_nop_opcode; 4630 4631 assert (tinsn->opcode != XTENSA_UNDEFINED); 4632 } 4633 } 4634 4635 4636 /* Assemble a NOP of the requested size in the buffer. User must have 4637 allocated "buf" with at least "size" bytes. */ 4638 4639 static void 4640 assemble_nop (int size, char *buf) 4641 { 4642 static xtensa_insnbuf insnbuf = NULL; 4643 TInsn tinsn; 4644 4645 build_nop (&tinsn, size); 4646 4647 if (!insnbuf) 4648 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 4649 4650 tinsn_to_insnbuf (&tinsn, insnbuf); 4651 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, 4652 (unsigned char *) buf, 0); 4653 } 4654 4655 4656 /* Return the number of bytes for the offset of the expanded loop 4657 instruction. This should be incorporated into the relaxation 4658 specification but is hard-coded here. This is used to auto-align 4659 the loop instruction. It is invalid to call this function if the 4660 configuration does not have loops or if the opcode is not a loop 4661 opcode. */ 4662 4663 static addressT 4664 get_expanded_loop_offset (xtensa_opcode opcode) 4665 { 4666 /* This is the OFFSET of the loop instruction in the expanded loop. 4667 This MUST correspond directly to the specification of the loop 4668 expansion. It will be validated on fragment conversion. */ 4669 assert (opcode != XTENSA_UNDEFINED); 4670 if (opcode == xtensa_loop_opcode) 4671 return 0; 4672 if (opcode == xtensa_loopnez_opcode) 4673 return 3; 4674 if (opcode == xtensa_loopgtz_opcode) 4675 return 6; 4676 as_fatal (_("get_expanded_loop_offset: invalid opcode")); 4677 return 0; 4678 } 4679 4680 4681 static fragS * 4682 get_literal_pool_location (segT seg) 4683 { 4684 return seg_info (seg)->tc_segment_info_data.literal_pool_loc; 4685 } 4686 4687 4688 static void 4689 set_literal_pool_location (segT seg, fragS *literal_pool_loc) 4690 { 4691 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; 4692 } 4693 4694 4695 /* Set frag assembly state should be called when a new frag is 4696 opened and after a frag has been closed. */ 4697 4698 static void 4699 xtensa_set_frag_assembly_state (fragS *fragP) 4700 { 4701 if (!density_supported) 4702 fragP->tc_frag_data.is_no_density = TRUE; 4703 4704 /* This function is called from subsegs_finish, which is called 4705 after xtensa_end, so we can't use "use_transform" or 4706 "use_schedule" here. */ 4707 if (!directive_state[directive_transform]) 4708 fragP->tc_frag_data.is_no_transform = TRUE; 4709 if (directive_state[directive_longcalls]) 4710 fragP->tc_frag_data.use_longcalls = TRUE; 4711 fragP->tc_frag_data.use_absolute_literals = 4712 directive_state[directive_absolute_literals]; 4713 fragP->tc_frag_data.is_assembly_state_set = TRUE; 4714 } 4715 4716 4717 static bfd_boolean 4718 relaxable_section (asection *sec) 4719 { 4720 return (sec->flags & SEC_DEBUGGING) == 0; 4721 } 4722 4723 4724 static void 4725 xtensa_find_unmarked_state_frags (void) 4726 { 4727 segT *seclist; 4728 4729 /* Walk over each fragment of all of the current segments. For each 4730 unmarked fragment, mark it with the same info as the previous 4731 fragment. */ 4732 for (seclist = &stdoutput->sections; 4733 seclist && *seclist; 4734 seclist = &(*seclist)->next) 4735 { 4736 segT sec = *seclist; 4737 segment_info_type *seginfo; 4738 fragS *fragP; 4739 flagword flags; 4740 flags = bfd_get_section_flags (stdoutput, sec); 4741 if (flags & SEC_DEBUGGING) 4742 continue; 4743 if (!(flags & SEC_ALLOC)) 4744 continue; 4745 4746 seginfo = seg_info (sec); 4747 if (seginfo && seginfo->frchainP) 4748 { 4749 fragS *last_fragP = 0; 4750 for (fragP = seginfo->frchainP->frch_root; fragP; 4751 fragP = fragP->fr_next) 4752 { 4753 if (fragP->fr_fix != 0 4754 && !fragP->tc_frag_data.is_assembly_state_set) 4755 { 4756 if (last_fragP == 0) 4757 { 4758 as_warn_where (fragP->fr_file, fragP->fr_line, 4759 _("assembly state not set for first frag in section %s"), 4760 sec->name); 4761 } 4762 else 4763 { 4764 fragP->tc_frag_data.is_assembly_state_set = TRUE; 4765 fragP->tc_frag_data.is_no_density = 4766 last_fragP->tc_frag_data.is_no_density; 4767 fragP->tc_frag_data.is_no_transform = 4768 last_fragP->tc_frag_data.is_no_transform; 4769 fragP->tc_frag_data.use_longcalls = 4770 last_fragP->tc_frag_data.use_longcalls; 4771 fragP->tc_frag_data.use_absolute_literals = 4772 last_fragP->tc_frag_data.use_absolute_literals; 4773 } 4774 } 4775 if (fragP->tc_frag_data.is_assembly_state_set) 4776 last_fragP = fragP; 4777 } 4778 } 4779 } 4780 } 4781 4782 4783 static void 4784 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, 4785 asection *sec, 4786 void *unused ATTRIBUTE_UNUSED) 4787 { 4788 flagword flags = bfd_get_section_flags (abfd, sec); 4789 segment_info_type *seginfo = seg_info (sec); 4790 fragS *frag = seginfo->frchainP->frch_root; 4791 4792 if (flags & SEC_CODE) 4793 { 4794 xtensa_isa isa = xtensa_default_isa; 4795 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); 4796 while (frag != NULL) 4797 { 4798 if (frag->tc_frag_data.is_branch_target) 4799 { 4800 int op_size; 4801 addressT branch_align, frag_addr; 4802 xtensa_format fmt; 4803 4804 xtensa_insnbuf_from_chars 4805 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); 4806 fmt = xtensa_format_decode (isa, insnbuf); 4807 op_size = xtensa_format_length (isa, fmt); 4808 branch_align = 1 << branch_align_power (sec); 4809 frag_addr = frag->fr_address % branch_align; 4810 if (frag_addr + op_size > branch_align) 4811 as_warn_where (frag->fr_file, frag->fr_line, 4812 _("unaligned branch target: %d bytes at 0x%lx"), 4813 op_size, (long) frag->fr_address); 4814 } 4815 frag = frag->fr_next; 4816 } 4817 xtensa_insnbuf_free (isa, insnbuf); 4818 } 4819 } 4820 4821 4822 static void 4823 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, 4824 asection *sec, 4825 void *unused ATTRIBUTE_UNUSED) 4826 { 4827 flagword flags = bfd_get_section_flags (abfd, sec); 4828 segment_info_type *seginfo = seg_info (sec); 4829 fragS *frag = seginfo->frchainP->frch_root; 4830 xtensa_isa isa = xtensa_default_isa; 4831 4832 if (flags & SEC_CODE) 4833 { 4834 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); 4835 while (frag != NULL) 4836 { 4837 if (frag->tc_frag_data.is_first_loop_insn) 4838 { 4839 int op_size; 4840 addressT frag_addr; 4841 xtensa_format fmt; 4842 4843 xtensa_insnbuf_from_chars 4844 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); 4845 fmt = xtensa_format_decode (isa, insnbuf); 4846 op_size = xtensa_format_length (isa, fmt); 4847 frag_addr = frag->fr_address % xtensa_fetch_width; 4848 4849 if (frag_addr + op_size > xtensa_fetch_width) 4850 as_warn_where (frag->fr_file, frag->fr_line, 4851 _("unaligned loop: %d bytes at 0x%lx"), 4852 op_size, (long) frag->fr_address); 4853 } 4854 frag = frag->fr_next; 4855 } 4856 xtensa_insnbuf_free (isa, insnbuf); 4857 } 4858 } 4859 4860 4861 static int 4862 xg_apply_fix_value (fixS *fixP, valueT val) 4863 { 4864 xtensa_isa isa = xtensa_default_isa; 4865 static xtensa_insnbuf insnbuf = NULL; 4866 static xtensa_insnbuf slotbuf = NULL; 4867 xtensa_format fmt; 4868 int slot; 4869 bfd_boolean alt_reloc; 4870 xtensa_opcode opcode; 4871 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; 4872 4873 (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc); 4874 if (alt_reloc) 4875 as_fatal (_("unexpected fix")); 4876 4877 if (!insnbuf) 4878 { 4879 insnbuf = xtensa_insnbuf_alloc (isa); 4880 slotbuf = xtensa_insnbuf_alloc (isa); 4881 } 4882 4883 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); 4884 fmt = xtensa_format_decode (isa, insnbuf); 4885 if (fmt == XTENSA_UNDEFINED) 4886 as_fatal (_("undecodable fix")); 4887 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 4888 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 4889 if (opcode == XTENSA_UNDEFINED) 4890 as_fatal (_("undecodable fix")); 4891 4892 /* CONST16 immediates are not PC-relative, despite the fact that we 4893 reuse the normal PC-relative operand relocations for the low part 4894 of a CONST16 operand. */ 4895 if (opcode == xtensa_const16_opcode) 4896 return 0; 4897 4898 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, 4899 get_relaxable_immed (opcode), val, 4900 fixP->fx_file, fixP->fx_line); 4901 4902 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); 4903 xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); 4904 4905 return 1; 4906 } 4907 4908 4909 /* External Functions and Other GAS Hooks. */ 4910 4911 const char * 4912 xtensa_target_format (void) 4913 { 4914 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); 4915 } 4916 4917 4918 void 4919 xtensa_file_arch_init (bfd *abfd) 4920 { 4921 bfd_set_private_flags (abfd, 0x100 | 0x200); 4922 } 4923 4924 4925 void 4926 md_number_to_chars (char *buf, valueT val, int n) 4927 { 4928 if (target_big_endian) 4929 number_to_chars_bigendian (buf, val, n); 4930 else 4931 number_to_chars_littleendian (buf, val, n); 4932 } 4933 4934 4935 /* This function is called once, at assembler startup time. It should 4936 set up all the tables, etc. that the MD part of the assembler will 4937 need. */ 4938 4939 void 4940 md_begin (void) 4941 { 4942 segT current_section = now_seg; 4943 int current_subsec = now_subseg; 4944 xtensa_isa isa; 4945 4946 xtensa_default_isa = xtensa_isa_init (0, 0); 4947 isa = xtensa_default_isa; 4948 4949 linkrelax = 1; 4950 4951 /* Set up the .literal, .fini.literal and .init.literal sections. */ 4952 memset (&default_lit_sections, 0, sizeof (default_lit_sections)); 4953 default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME; 4954 default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME; 4955 default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME; 4956 default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME; 4957 4958 subseg_set (current_section, current_subsec); 4959 4960 xg_init_vinsn (&cur_vinsn); 4961 4962 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); 4963 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); 4964 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); 4965 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); 4966 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); 4967 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); 4968 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); 4969 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); 4970 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); 4971 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); 4972 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); 4973 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); 4974 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); 4975 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); 4976 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); 4977 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); 4978 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); 4979 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); 4980 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); 4981 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); 4982 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); 4983 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); 4984 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); 4985 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); 4986 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); 4987 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); 4988 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); 4989 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); 4990 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); 4991 4992 init_op_placement_info_table (); 4993 4994 /* Set up the assembly state. */ 4995 if (!frag_now->tc_frag_data.is_assembly_state_set) 4996 xtensa_set_frag_assembly_state (frag_now); 4997 } 4998 4999 5000 /* TC_INIT_FIX_DATA hook */ 5001 5002 void 5003 xtensa_init_fix_data (fixS *x) 5004 { 5005 x->tc_fix_data.slot = 0; 5006 x->tc_fix_data.X_add_symbol = NULL; 5007 x->tc_fix_data.X_add_number = 0; 5008 } 5009 5010 5011 /* tc_frob_label hook */ 5012 5013 void 5014 xtensa_frob_label (symbolS *sym) 5015 { 5016 float freq; 5017 5018 if (cur_vinsn.inside_bundle) 5019 { 5020 as_bad (_("labels are not valid inside bundles")); 5021 return; 5022 } 5023 5024 freq = get_subseg_target_freq (now_seg, now_subseg); 5025 5026 /* Since the label was already attached to a frag associated with the 5027 previous basic block, it now needs to be reset to the current frag. */ 5028 symbol_set_frag (sym, frag_now); 5029 S_SET_VALUE (sym, (valueT) frag_now_fix ()); 5030 5031 if (generating_literals) 5032 xtensa_add_literal_sym (sym); 5033 else 5034 xtensa_add_insn_label (sym); 5035 5036 if (symbol_get_tc (sym)->is_loop_target) 5037 { 5038 if ((get_last_insn_flags (now_seg, now_subseg) 5039 & FLAG_IS_BAD_LOOPEND) != 0) 5040 as_bad (_("invalid last instruction for a zero-overhead loop")); 5041 5042 xtensa_set_frag_assembly_state (frag_now); 5043 frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, 5044 frag_now->fr_symbol, frag_now->fr_offset, NULL); 5045 5046 xtensa_set_frag_assembly_state (frag_now); 5047 xtensa_move_labels (frag_now, 0, TRUE); 5048 } 5049 5050 /* No target aligning in the absolute section. */ 5051 if (now_seg != absolute_section 5052 && do_align_targets () 5053 && !is_unaligned_label (sym) 5054 && !generating_literals) 5055 { 5056 xtensa_set_frag_assembly_state (frag_now); 5057 5058 frag_var (rs_machine_dependent, 5059 0, (int) freq, 5060 RELAX_DESIRE_ALIGN_IF_TARGET, 5061 frag_now->fr_symbol, frag_now->fr_offset, NULL); 5062 xtensa_set_frag_assembly_state (frag_now); 5063 xtensa_move_labels (frag_now, 0, TRUE); 5064 } 5065 5066 /* We need to mark the following properties even if we aren't aligning. */ 5067 5068 /* If the label is already known to be a branch target, i.e., a 5069 forward branch, mark the frag accordingly. Backward branches 5070 are handled by xg_add_branch_and_loop_targets. */ 5071 if (symbol_get_tc (sym)->is_branch_target) 5072 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; 5073 5074 /* Loops only go forward, so they can be identified here. */ 5075 if (symbol_get_tc (sym)->is_loop_target) 5076 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; 5077 5078 dwarf2_emit_label (sym); 5079 } 5080 5081 5082 /* tc_unrecognized_line hook */ 5083 5084 int 5085 xtensa_unrecognized_line (int ch) 5086 { 5087 switch (ch) 5088 { 5089 case '{' : 5090 if (cur_vinsn.inside_bundle == 0) 5091 { 5092 /* PR8110: Cannot emit line number info inside a FLIX bundle 5093 when using --gstabs. Temporarily disable debug info. */ 5094 generate_lineno_debug (); 5095 if (debug_type == DEBUG_STABS) 5096 { 5097 xt_saved_debug_type = debug_type; 5098 debug_type = DEBUG_NONE; 5099 } 5100 5101 cur_vinsn.inside_bundle = 1; 5102 } 5103 else 5104 { 5105 as_bad (_("extra opening brace")); 5106 return 0; 5107 } 5108 break; 5109 5110 case '}' : 5111 if (cur_vinsn.inside_bundle) 5112 finish_vinsn (&cur_vinsn); 5113 else 5114 { 5115 as_bad (_("extra closing brace")); 5116 return 0; 5117 } 5118 break; 5119 default: 5120 as_bad (_("syntax error")); 5121 return 0; 5122 } 5123 return 1; 5124 } 5125 5126 5127 /* md_flush_pending_output hook */ 5128 5129 void 5130 xtensa_flush_pending_output (void) 5131 { 5132 if (cur_vinsn.inside_bundle) 5133 as_bad (_("missing closing brace")); 5134 5135 /* If there is a non-zero instruction fragment, close it. */ 5136 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) 5137 { 5138 frag_wane (frag_now); 5139 frag_new (0); 5140 xtensa_set_frag_assembly_state (frag_now); 5141 } 5142 frag_now->tc_frag_data.is_insn = FALSE; 5143 5144 xtensa_clear_insn_labels (); 5145 } 5146 5147 5148 /* We had an error while parsing an instruction. The string might look 5149 like this: "insn arg1, arg2 }". If so, we need to see the closing 5150 brace and reset some fields. Otherwise, the vinsn never gets closed 5151 and the num_slots field will grow past the end of the array of slots, 5152 and bad things happen. */ 5153 5154 static void 5155 error_reset_cur_vinsn (void) 5156 { 5157 if (cur_vinsn.inside_bundle) 5158 { 5159 if (*input_line_pointer == '}' 5160 || *(input_line_pointer - 1) == '}' 5161 || *(input_line_pointer - 2) == '}') 5162 xg_clear_vinsn (&cur_vinsn); 5163 } 5164 } 5165 5166 5167 void 5168 md_assemble (char *str) 5169 { 5170 xtensa_isa isa = xtensa_default_isa; 5171 char *opname, *file_name; 5172 unsigned opnamelen; 5173 bfd_boolean has_underbar = FALSE; 5174 char *arg_strings[MAX_INSN_ARGS]; 5175 int num_args; 5176 TInsn orig_insn; /* Original instruction from the input. */ 5177 5178 tinsn_init (&orig_insn); 5179 5180 /* Split off the opcode. */ 5181 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); 5182 opname = xmalloc (opnamelen + 1); 5183 memcpy (opname, str, opnamelen); 5184 opname[opnamelen] = '\0'; 5185 5186 num_args = tokenize_arguments (arg_strings, str + opnamelen); 5187 if (num_args == -1) 5188 { 5189 as_bad (_("syntax error")); 5190 return; 5191 } 5192 5193 if (xg_translate_idioms (&opname, &num_args, arg_strings)) 5194 return; 5195 5196 /* Check for an underbar prefix. */ 5197 if (*opname == '_') 5198 { 5199 has_underbar = TRUE; 5200 opname += 1; 5201 } 5202 5203 orig_insn.insn_type = ITYPE_INSN; 5204 orig_insn.ntok = 0; 5205 orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); 5206 5207 orig_insn.opcode = xtensa_opcode_lookup (isa, opname); 5208 if (orig_insn.opcode == XTENSA_UNDEFINED) 5209 { 5210 xtensa_format fmt = xtensa_format_lookup (isa, opname); 5211 if (fmt == XTENSA_UNDEFINED) 5212 { 5213 as_bad (_("unknown opcode or format name '%s'"), opname); 5214 error_reset_cur_vinsn (); 5215 return; 5216 } 5217 if (!cur_vinsn.inside_bundle) 5218 { 5219 as_bad (_("format names only valid inside bundles")); 5220 error_reset_cur_vinsn (); 5221 return; 5222 } 5223 if (cur_vinsn.format != XTENSA_UNDEFINED) 5224 as_warn (_("multiple formats specified for one bundle; using '%s'"), 5225 opname); 5226 cur_vinsn.format = fmt; 5227 free (has_underbar ? opname - 1 : opname); 5228 error_reset_cur_vinsn (); 5229 return; 5230 } 5231 5232 /* Parse the arguments. */ 5233 if (parse_arguments (&orig_insn, num_args, arg_strings)) 5234 { 5235 as_bad (_("syntax error")); 5236 error_reset_cur_vinsn (); 5237 return; 5238 } 5239 5240 /* Free the opcode and argument strings, now that they've been parsed. */ 5241 free (has_underbar ? opname - 1 : opname); 5242 opname = 0; 5243 while (num_args-- > 0) 5244 free (arg_strings[num_args]); 5245 5246 /* Get expressions for invisible operands. */ 5247 if (get_invisible_operands (&orig_insn)) 5248 { 5249 error_reset_cur_vinsn (); 5250 return; 5251 } 5252 5253 /* Check for the right number and type of arguments. */ 5254 if (tinsn_check_arguments (&orig_insn)) 5255 { 5256 error_reset_cur_vinsn (); 5257 return; 5258 } 5259 5260 /* A FLIX bundle may be spread across multiple input lines. We want to 5261 report the first such line in the debug information. Record the line 5262 number for each TInsn (assume the file name doesn't change), so the 5263 first line can be found later. */ 5264 as_where (&file_name, &orig_insn.linenum); 5265 5266 xg_add_branch_and_loop_targets (&orig_insn); 5267 5268 /* Check that immediate value for ENTRY is >= 16. */ 5269 if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) 5270 { 5271 expressionS *exp = &orig_insn.tok[2]; 5272 if (exp->X_op == O_constant && exp->X_add_number < 16) 5273 as_warn (_("entry instruction with stack decrement < 16")); 5274 } 5275 5276 /* Finish it off: 5277 assemble_tokens (opcode, tok, ntok); 5278 expand the tokens from the orig_insn into the 5279 stack of instructions that will not expand 5280 unless required at relaxation time. */ 5281 5282 if (!cur_vinsn.inside_bundle) 5283 emit_single_op (&orig_insn); 5284 else /* We are inside a bundle. */ 5285 { 5286 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; 5287 cur_vinsn.num_slots++; 5288 if (*input_line_pointer == '}' 5289 || *(input_line_pointer - 1) == '}' 5290 || *(input_line_pointer - 2) == '}') 5291 finish_vinsn (&cur_vinsn); 5292 } 5293 5294 /* We've just emitted a new instruction so clear the list of labels. */ 5295 xtensa_clear_insn_labels (); 5296 } 5297 5298 5299 /* HANDLE_ALIGN hook */ 5300 5301 /* For a .align directive, we mark the previous block with the alignment 5302 information. This will be placed in the object file in the 5303 property section corresponding to this section. */ 5304 5305 void 5306 xtensa_handle_align (fragS *fragP) 5307 { 5308 if (linkrelax 5309 && ! fragP->tc_frag_data.is_literal 5310 && (fragP->fr_type == rs_align 5311 || fragP->fr_type == rs_align_code) 5312 && fragP->fr_address + fragP->fr_fix > 0 5313 && fragP->fr_offset > 0 5314 && now_seg != bss_section) 5315 { 5316 fragP->tc_frag_data.is_align = TRUE; 5317 fragP->tc_frag_data.alignment = fragP->fr_offset; 5318 } 5319 5320 if (fragP->fr_type == rs_align_test) 5321 { 5322 int count; 5323 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 5324 if (count != 0) 5325 as_bad_where (fragP->fr_file, fragP->fr_line, 5326 _("unaligned entry instruction")); 5327 } 5328 } 5329 5330 5331 /* TC_FRAG_INIT hook */ 5332 5333 void 5334 xtensa_frag_init (fragS *frag) 5335 { 5336 xtensa_set_frag_assembly_state (frag); 5337 } 5338 5339 5340 symbolS * 5341 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 5342 { 5343 return NULL; 5344 } 5345 5346 5347 /* Round up a section size to the appropriate boundary. */ 5348 5349 valueT 5350 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 5351 { 5352 return size; /* Byte alignment is fine. */ 5353 } 5354 5355 5356 long 5357 md_pcrel_from (fixS *fixP) 5358 { 5359 char *insn_p; 5360 static xtensa_insnbuf insnbuf = NULL; 5361 static xtensa_insnbuf slotbuf = NULL; 5362 int opnum; 5363 uint32 opnd_value; 5364 xtensa_opcode opcode; 5365 xtensa_format fmt; 5366 int slot; 5367 xtensa_isa isa = xtensa_default_isa; 5368 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 5369 bfd_boolean alt_reloc; 5370 5371 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) 5372 return 0; 5373 5374 if (!insnbuf) 5375 { 5376 insnbuf = xtensa_insnbuf_alloc (isa); 5377 slotbuf = xtensa_insnbuf_alloc (isa); 5378 } 5379 5380 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; 5381 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); 5382 fmt = xtensa_format_decode (isa, insnbuf); 5383 5384 if (fmt == XTENSA_UNDEFINED) 5385 as_fatal (_("bad instruction format")); 5386 5387 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) 5388 as_fatal (_("invalid relocation")); 5389 5390 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 5391 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 5392 5393 /* Check for "alternate" relocations (operand not specified). None 5394 of the current uses for these are really PC-relative. */ 5395 if (alt_reloc || opcode == xtensa_const16_opcode) 5396 { 5397 if (opcode != xtensa_l32r_opcode 5398 && opcode != xtensa_const16_opcode) 5399 as_fatal (_("invalid relocation for '%s' instruction"), 5400 xtensa_opcode_name (isa, opcode)); 5401 return 0; 5402 } 5403 5404 opnum = get_relaxable_immed (opcode); 5405 opnd_value = 0; 5406 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 5407 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) 5408 { 5409 as_bad_where (fixP->fx_file, 5410 fixP->fx_line, 5411 _("invalid relocation for operand %d of '%s'"), 5412 opnum, xtensa_opcode_name (isa, opcode)); 5413 return 0; 5414 } 5415 return 0 - opnd_value; 5416 } 5417 5418 5419 /* TC_FORCE_RELOCATION hook */ 5420 5421 int 5422 xtensa_force_relocation (fixS *fix) 5423 { 5424 switch (fix->fx_r_type) 5425 { 5426 case BFD_RELOC_XTENSA_ASM_EXPAND: 5427 case BFD_RELOC_XTENSA_SLOT0_ALT: 5428 case BFD_RELOC_XTENSA_SLOT1_ALT: 5429 case BFD_RELOC_XTENSA_SLOT2_ALT: 5430 case BFD_RELOC_XTENSA_SLOT3_ALT: 5431 case BFD_RELOC_XTENSA_SLOT4_ALT: 5432 case BFD_RELOC_XTENSA_SLOT5_ALT: 5433 case BFD_RELOC_XTENSA_SLOT6_ALT: 5434 case BFD_RELOC_XTENSA_SLOT7_ALT: 5435 case BFD_RELOC_XTENSA_SLOT8_ALT: 5436 case BFD_RELOC_XTENSA_SLOT9_ALT: 5437 case BFD_RELOC_XTENSA_SLOT10_ALT: 5438 case BFD_RELOC_XTENSA_SLOT11_ALT: 5439 case BFD_RELOC_XTENSA_SLOT12_ALT: 5440 case BFD_RELOC_XTENSA_SLOT13_ALT: 5441 case BFD_RELOC_XTENSA_SLOT14_ALT: 5442 return 1; 5443 default: 5444 break; 5445 } 5446 5447 if (linkrelax && fix->fx_addsy 5448 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) 5449 return 1; 5450 5451 return generic_force_reloc (fix); 5452 } 5453 5454 5455 /* TC_VALIDATE_FIX_SUB hook */ 5456 5457 int 5458 xtensa_validate_fix_sub (fixS *fix) 5459 { 5460 segT add_symbol_segment, sub_symbol_segment; 5461 5462 /* The difference of two symbols should be resolved by the assembler when 5463 linkrelax is not set. If the linker may relax the section containing 5464 the symbols, then an Xtensa DIFF relocation must be generated so that 5465 the linker knows to adjust the difference value. */ 5466 if (!linkrelax || fix->fx_addsy == NULL) 5467 return 0; 5468 5469 /* Make sure both symbols are in the same segment, and that segment is 5470 "normal" and relaxable. If the segment is not "normal", then the 5471 fix is not valid. If the segment is not "relaxable", then the fix 5472 should have been handled earlier. */ 5473 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); 5474 if (! SEG_NORMAL (add_symbol_segment) || 5475 ! relaxable_section (add_symbol_segment)) 5476 return 0; 5477 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); 5478 return (sub_symbol_segment == add_symbol_segment); 5479 } 5480 5481 5482 /* NO_PSEUDO_DOT hook */ 5483 5484 /* This function has nothing to do with pseudo dots, but this is the 5485 nearest macro to where the check needs to take place. FIXME: This 5486 seems wrong. */ 5487 5488 bfd_boolean 5489 xtensa_check_inside_bundle (void) 5490 { 5491 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') 5492 as_bad (_("directives are not valid inside bundles")); 5493 5494 /* This function must always return FALSE because it is called via a 5495 macro that has nothing to do with bundling. */ 5496 return FALSE; 5497 } 5498 5499 5500 /* md_elf_section_change_hook */ 5501 5502 void 5503 xtensa_elf_section_change_hook (void) 5504 { 5505 /* Set up the assembly state. */ 5506 if (!frag_now->tc_frag_data.is_assembly_state_set) 5507 xtensa_set_frag_assembly_state (frag_now); 5508 } 5509 5510 5511 /* tc_fix_adjustable hook */ 5512 5513 bfd_boolean 5514 xtensa_fix_adjustable (fixS *fixP) 5515 { 5516 /* An offset is not allowed in combination with the difference of two 5517 symbols, but that cannot be easily detected after a local symbol 5518 has been adjusted to a (section+offset) form. Return 0 so that such 5519 an fix will not be adjusted. */ 5520 if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset 5521 && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) 5522 return 0; 5523 5524 /* We need the symbol name for the VTABLE entries. */ 5525 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 5526 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 5527 return 0; 5528 5529 return 1; 5530 } 5531 5532 5533 void 5534 md_apply_fix (fixS *fixP, valueT *valP, segT seg) 5535 { 5536 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; 5537 valueT val = 0; 5538 5539 /* Subtracted symbols are only allowed for a few relocation types, and 5540 unless linkrelax is enabled, they should not make it to this point. */ 5541 if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 5542 || fixP->fx_r_type == BFD_RELOC_16 5543 || fixP->fx_r_type == BFD_RELOC_8))) 5544 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); 5545 5546 switch (fixP->fx_r_type) 5547 { 5548 case BFD_RELOC_32: 5549 case BFD_RELOC_16: 5550 case BFD_RELOC_8: 5551 if (fixP->fx_subsy) 5552 { 5553 switch (fixP->fx_r_type) 5554 { 5555 case BFD_RELOC_8: 5556 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; 5557 break; 5558 case BFD_RELOC_16: 5559 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; 5560 break; 5561 case BFD_RELOC_32: 5562 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; 5563 break; 5564 default: 5565 break; 5566 } 5567 5568 /* An offset is only allowed when it results from adjusting a 5569 local symbol into a section-relative offset. If the offset 5570 came from the original expression, tc_fix_adjustable will have 5571 prevented the fix from being converted to a section-relative 5572 form so that we can flag the error here. */ 5573 if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) 5574 as_bad_where (fixP->fx_file, fixP->fx_line, 5575 _("cannot represent subtraction with an offset")); 5576 5577 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset 5578 - S_GET_VALUE (fixP->fx_subsy)); 5579 5580 /* The difference value gets written out, and the DIFF reloc 5581 identifies the address of the subtracted symbol (i.e., the one 5582 with the lowest address). */ 5583 *valP = val; 5584 fixP->fx_offset -= val; 5585 fixP->fx_subsy = NULL; 5586 } 5587 else if (! fixP->fx_addsy) 5588 { 5589 val = *valP; 5590 fixP->fx_done = 1; 5591 } 5592 /* fall through */ 5593 5594 case BFD_RELOC_XTENSA_PLT: 5595 md_number_to_chars (fixpos, val, fixP->fx_size); 5596 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ 5597 break; 5598 5599 case BFD_RELOC_XTENSA_SLOT0_OP: 5600 case BFD_RELOC_XTENSA_SLOT1_OP: 5601 case BFD_RELOC_XTENSA_SLOT2_OP: 5602 case BFD_RELOC_XTENSA_SLOT3_OP: 5603 case BFD_RELOC_XTENSA_SLOT4_OP: 5604 case BFD_RELOC_XTENSA_SLOT5_OP: 5605 case BFD_RELOC_XTENSA_SLOT6_OP: 5606 case BFD_RELOC_XTENSA_SLOT7_OP: 5607 case BFD_RELOC_XTENSA_SLOT8_OP: 5608 case BFD_RELOC_XTENSA_SLOT9_OP: 5609 case BFD_RELOC_XTENSA_SLOT10_OP: 5610 case BFD_RELOC_XTENSA_SLOT11_OP: 5611 case BFD_RELOC_XTENSA_SLOT12_OP: 5612 case BFD_RELOC_XTENSA_SLOT13_OP: 5613 case BFD_RELOC_XTENSA_SLOT14_OP: 5614 if (linkrelax) 5615 { 5616 /* Write the tentative value of a PC-relative relocation to a 5617 local symbol into the instruction. The value will be ignored 5618 by the linker, and it makes the object file disassembly 5619 readable when all branch targets are encoded in relocations. */ 5620 5621 assert (fixP->fx_addsy); 5622 if (S_GET_SEGMENT (fixP->fx_addsy) == seg && !fixP->fx_plt 5623 && !S_FORCE_RELOC (fixP->fx_addsy, 1)) 5624 { 5625 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset 5626 - md_pcrel_from (fixP)); 5627 (void) xg_apply_fix_value (fixP, val); 5628 } 5629 } 5630 else if (! fixP->fx_addsy) 5631 { 5632 val = *valP; 5633 if (xg_apply_fix_value (fixP, val)) 5634 fixP->fx_done = 1; 5635 } 5636 break; 5637 5638 case BFD_RELOC_XTENSA_ASM_EXPAND: 5639 case BFD_RELOC_XTENSA_SLOT0_ALT: 5640 case BFD_RELOC_XTENSA_SLOT1_ALT: 5641 case BFD_RELOC_XTENSA_SLOT2_ALT: 5642 case BFD_RELOC_XTENSA_SLOT3_ALT: 5643 case BFD_RELOC_XTENSA_SLOT4_ALT: 5644 case BFD_RELOC_XTENSA_SLOT5_ALT: 5645 case BFD_RELOC_XTENSA_SLOT6_ALT: 5646 case BFD_RELOC_XTENSA_SLOT7_ALT: 5647 case BFD_RELOC_XTENSA_SLOT8_ALT: 5648 case BFD_RELOC_XTENSA_SLOT9_ALT: 5649 case BFD_RELOC_XTENSA_SLOT10_ALT: 5650 case BFD_RELOC_XTENSA_SLOT11_ALT: 5651 case BFD_RELOC_XTENSA_SLOT12_ALT: 5652 case BFD_RELOC_XTENSA_SLOT13_ALT: 5653 case BFD_RELOC_XTENSA_SLOT14_ALT: 5654 /* These all need to be resolved at link-time. Do nothing now. */ 5655 break; 5656 5657 case BFD_RELOC_VTABLE_INHERIT: 5658 case BFD_RELOC_VTABLE_ENTRY: 5659 fixP->fx_done = 0; 5660 break; 5661 5662 default: 5663 as_bad (_("unhandled local relocation fix %s"), 5664 bfd_get_reloc_code_name (fixP->fx_r_type)); 5665 } 5666 } 5667 5668 5669 char * 5670 md_atof (int type, char *litP, int *sizeP) 5671 { 5672 int prec; 5673 LITTLENUM_TYPE words[4]; 5674 char *t; 5675 int i; 5676 5677 switch (type) 5678 { 5679 case 'f': 5680 prec = 2; 5681 break; 5682 5683 case 'd': 5684 prec = 4; 5685 break; 5686 5687 default: 5688 *sizeP = 0; 5689 return "bad call to md_atof"; 5690 } 5691 5692 t = atof_ieee (input_line_pointer, type, words); 5693 if (t) 5694 input_line_pointer = t; 5695 5696 *sizeP = prec * 2; 5697 5698 for (i = prec - 1; i >= 0; i--) 5699 { 5700 int idx = i; 5701 if (target_big_endian) 5702 idx = (prec - 1 - i); 5703 5704 md_number_to_chars (litP, (valueT) words[idx], 2); 5705 litP += 2; 5706 } 5707 5708 return NULL; 5709 } 5710 5711 5712 int 5713 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) 5714 { 5715 return total_frag_text_expansion (fragP); 5716 } 5717 5718 5719 /* Translate internal representation of relocation info to BFD target 5720 format. */ 5721 5722 arelent * 5723 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 5724 { 5725 arelent *reloc; 5726 5727 reloc = (arelent *) xmalloc (sizeof (arelent)); 5728 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 5729 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 5730 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 5731 5732 /* Make sure none of our internal relocations make it this far. 5733 They'd better have been fully resolved by this point. */ 5734 assert ((int) fixp->fx_r_type > 0); 5735 5736 reloc->addend = fixp->fx_offset; 5737 5738 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 5739 if (reloc->howto == NULL) 5740 { 5741 as_bad_where (fixp->fx_file, fixp->fx_line, 5742 _("cannot represent `%s' relocation in object file"), 5743 bfd_get_reloc_code_name (fixp->fx_r_type)); 5744 free (reloc->sym_ptr_ptr); 5745 free (reloc); 5746 return NULL; 5747 } 5748 5749 if (!fixp->fx_pcrel != !reloc->howto->pc_relative) 5750 as_fatal (_("internal error? cannot generate `%s' relocation"), 5751 bfd_get_reloc_code_name (fixp->fx_r_type)); 5752 5753 return reloc; 5754 } 5755 5756 5757 /* Checks for resource conflicts between instructions. */ 5758 5759 /* The func unit stuff could be implemented as bit-vectors rather 5760 than the iterative approach here. If it ends up being too 5761 slow, we will switch it. */ 5762 5763 resource_table * 5764 new_resource_table (void *data, 5765 int cycles, 5766 int nu, 5767 unit_num_copies_func uncf, 5768 opcode_num_units_func onuf, 5769 opcode_funcUnit_use_unit_func ouuf, 5770 opcode_funcUnit_use_stage_func ousf) 5771 { 5772 int i; 5773 resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); 5774 rt->data = data; 5775 rt->cycles = cycles; 5776 rt->allocated_cycles = cycles; 5777 rt->num_units = nu; 5778 rt->unit_num_copies = uncf; 5779 rt->opcode_num_units = onuf; 5780 rt->opcode_unit_use = ouuf; 5781 rt->opcode_unit_stage = ousf; 5782 5783 rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); 5784 for (i = 0; i < cycles; i++) 5785 rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); 5786 5787 return rt; 5788 } 5789 5790 5791 void 5792 clear_resource_table (resource_table *rt) 5793 { 5794 int i, j; 5795 for (i = 0; i < rt->allocated_cycles; i++) 5796 for (j = 0; j < rt->num_units; j++) 5797 rt->units[i][j] = 0; 5798 } 5799 5800 5801 /* We never shrink it, just fake it into thinking so. */ 5802 5803 void 5804 resize_resource_table (resource_table *rt, int cycles) 5805 { 5806 int i, old_cycles; 5807 5808 rt->cycles = cycles; 5809 if (cycles <= rt->allocated_cycles) 5810 return; 5811 5812 old_cycles = rt->allocated_cycles; 5813 rt->allocated_cycles = cycles; 5814 5815 rt->units = xrealloc (rt->units, 5816 rt->allocated_cycles * sizeof (unsigned char *)); 5817 for (i = 0; i < old_cycles; i++) 5818 rt->units[i] = xrealloc (rt->units[i], 5819 rt->num_units * sizeof (unsigned char)); 5820 for (i = old_cycles; i < cycles; i++) 5821 rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); 5822 } 5823 5824 5825 bfd_boolean 5826 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) 5827 { 5828 int i; 5829 int uses = (rt->opcode_num_units) (rt->data, opcode); 5830 5831 for (i = 0; i < uses; i++) 5832 { 5833 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 5834 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 5835 int copies_in_use = rt->units[stage + cycle][unit]; 5836 int copies = (rt->unit_num_copies) (rt->data, unit); 5837 if (copies_in_use >= copies) 5838 return FALSE; 5839 } 5840 return TRUE; 5841 } 5842 5843 5844 void 5845 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) 5846 { 5847 int i; 5848 int uses = (rt->opcode_num_units) (rt->data, opcode); 5849 5850 for (i = 0; i < uses; i++) 5851 { 5852 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 5853 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 5854 /* Note that this allows resources to be oversubscribed. That's 5855 essential to the way the optional scheduler works. 5856 resources_available reports when a resource is over-subscribed, 5857 so it's easy to tell. */ 5858 rt->units[stage + cycle][unit]++; 5859 } 5860 } 5861 5862 5863 void 5864 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) 5865 { 5866 int i; 5867 int uses = (rt->opcode_num_units) (rt->data, opcode); 5868 5869 for (i = 0; i < uses; i++) 5870 { 5871 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 5872 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 5873 assert (rt->units[stage + cycle][unit] > 0); 5874 rt->units[stage + cycle][unit]--; 5875 } 5876 } 5877 5878 5879 /* Wrapper functions make parameterized resource reservation 5880 more convenient. */ 5881 5882 int 5883 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) 5884 { 5885 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); 5886 return use->unit; 5887 } 5888 5889 5890 int 5891 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) 5892 { 5893 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); 5894 return use->stage; 5895 } 5896 5897 5898 /* Note that this function does not check issue constraints, but 5899 solely whether the hardware is available to execute the given 5900 instructions together. It also doesn't check if the tinsns 5901 write the same state, or access the same tieports. That is 5902 checked by check_t1_t2_reads_and_writes. */ 5903 5904 static bfd_boolean 5905 resources_conflict (vliw_insn *vinsn) 5906 { 5907 int i; 5908 static resource_table *rt = NULL; 5909 5910 /* This is the most common case by far. Optimize it. */ 5911 if (vinsn->num_slots == 1) 5912 return FALSE; 5913 5914 if (rt == NULL) 5915 { 5916 xtensa_isa isa = xtensa_default_isa; 5917 rt = new_resource_table 5918 (isa, xtensa_isa_num_pipe_stages (isa), 5919 xtensa_isa_num_funcUnits (isa), 5920 (unit_num_copies_func) xtensa_funcUnit_num_copies, 5921 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, 5922 opcode_funcUnit_use_unit, 5923 opcode_funcUnit_use_stage); 5924 } 5925 5926 clear_resource_table (rt); 5927 5928 for (i = 0; i < vinsn->num_slots; i++) 5929 { 5930 if (!resources_available (rt, vinsn->slots[i].opcode, 0)) 5931 return TRUE; 5932 reserve_resources (rt, vinsn->slots[i].opcode, 0); 5933 } 5934 5935 return FALSE; 5936 } 5937 5938 5939 /* finish_vinsn, emit_single_op and helper functions. */ 5940 5941 static bfd_boolean find_vinsn_conflicts (vliw_insn *); 5942 static xtensa_format xg_find_narrowest_format (vliw_insn *); 5943 static void xg_assemble_vliw_tokens (vliw_insn *); 5944 5945 5946 /* We have reached the end of a bundle; emit into the frag. */ 5947 5948 static void 5949 finish_vinsn (vliw_insn *vinsn) 5950 { 5951 IStack slotstack; 5952 int i; 5953 char *file_name; 5954 unsigned line; 5955 5956 if (find_vinsn_conflicts (vinsn)) 5957 { 5958 xg_clear_vinsn (vinsn); 5959 return; 5960 } 5961 5962 /* First, find a format that works. */ 5963 if (vinsn->format == XTENSA_UNDEFINED) 5964 vinsn->format = xg_find_narrowest_format (vinsn); 5965 5966 if (vinsn->format == XTENSA_UNDEFINED) 5967 { 5968 as_where (&file_name, &line); 5969 as_bad_where (file_name, line, 5970 _("couldn't find a valid instruction format")); 5971 fprintf (stderr, _(" ops were: ")); 5972 for (i = 0; i < vinsn->num_slots; i++) 5973 fprintf (stderr, _(" %s;"), 5974 xtensa_opcode_name (xtensa_default_isa, 5975 vinsn->slots[i].opcode)); 5976 fprintf (stderr, _("\n")); 5977 xg_clear_vinsn (vinsn); 5978 return; 5979 } 5980 5981 if (vinsn->num_slots 5982 != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) 5983 { 5984 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), 5985 xtensa_format_name (xtensa_default_isa, vinsn->format), 5986 xtensa_format_num_slots (xtensa_default_isa, vinsn->format), 5987 vinsn->num_slots); 5988 xg_clear_vinsn (vinsn); 5989 return; 5990 } 5991 5992 if (resources_conflict (vinsn)) 5993 { 5994 as_where (&file_name, &line); 5995 as_bad_where (file_name, line, _("illegal resource usage in bundle")); 5996 fprintf (stderr, " ops were: "); 5997 for (i = 0; i < vinsn->num_slots; i++) 5998 fprintf (stderr, " %s;", 5999 xtensa_opcode_name (xtensa_default_isa, 6000 vinsn->slots[i].opcode)); 6001 fprintf (stderr, "\n"); 6002 xg_clear_vinsn (vinsn); 6003 return; 6004 } 6005 6006 for (i = 0; i < vinsn->num_slots; i++) 6007 { 6008 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) 6009 { 6010 symbolS *lit_sym = NULL; 6011 int j; 6012 bfd_boolean e = FALSE; 6013 bfd_boolean saved_density = density_supported; 6014 6015 /* We don't want to narrow ops inside multi-slot bundles. */ 6016 if (vinsn->num_slots > 1) 6017 density_supported = FALSE; 6018 6019 istack_init (&slotstack); 6020 if (vinsn->slots[i].opcode == xtensa_nop_opcode) 6021 { 6022 vinsn->slots[i].opcode = 6023 xtensa_format_slot_nop_opcode (xtensa_default_isa, 6024 vinsn->format, i); 6025 vinsn->slots[i].ntok = 0; 6026 } 6027 6028 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) 6029 { 6030 e = TRUE; 6031 continue; 6032 } 6033 6034 density_supported = saved_density; 6035 6036 if (e) 6037 { 6038 xg_clear_vinsn (vinsn); 6039 return; 6040 } 6041 6042 for (j = 0; j < slotstack.ninsn; j++) 6043 { 6044 TInsn *insn = &slotstack.insn[j]; 6045 if (insn->insn_type == ITYPE_LITERAL) 6046 { 6047 assert (lit_sym == NULL); 6048 lit_sym = xg_assemble_literal (insn); 6049 } 6050 else 6051 { 6052 assert (insn->insn_type == ITYPE_INSN); 6053 if (lit_sym) 6054 xg_resolve_literals (insn, lit_sym); 6055 if (j != slotstack.ninsn - 1) 6056 emit_single_op (insn); 6057 } 6058 } 6059 6060 if (vinsn->num_slots > 1) 6061 { 6062 if (opcode_fits_format_slot 6063 (slotstack.insn[slotstack.ninsn - 1].opcode, 6064 vinsn->format, i)) 6065 { 6066 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; 6067 } 6068 else 6069 { 6070 emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); 6071 if (vinsn->format == XTENSA_UNDEFINED) 6072 vinsn->slots[i].opcode = xtensa_nop_opcode; 6073 else 6074 vinsn->slots[i].opcode 6075 = xtensa_format_slot_nop_opcode (xtensa_default_isa, 6076 vinsn->format, i); 6077 6078 vinsn->slots[i].ntok = 0; 6079 } 6080 } 6081 else 6082 { 6083 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; 6084 vinsn->format = XTENSA_UNDEFINED; 6085 } 6086 } 6087 } 6088 6089 /* Now check resource conflicts on the modified bundle. */ 6090 if (resources_conflict (vinsn)) 6091 { 6092 as_where (&file_name, &line); 6093 as_bad_where (file_name, line, _("illegal resource usage in bundle")); 6094 fprintf (stderr, " ops were: "); 6095 for (i = 0; i < vinsn->num_slots; i++) 6096 fprintf (stderr, " %s;", 6097 xtensa_opcode_name (xtensa_default_isa, 6098 vinsn->slots[i].opcode)); 6099 fprintf (stderr, "\n"); 6100 xg_clear_vinsn (vinsn); 6101 return; 6102 } 6103 6104 /* First, find a format that works. */ 6105 if (vinsn->format == XTENSA_UNDEFINED) 6106 vinsn->format = xg_find_narrowest_format (vinsn); 6107 6108 xg_assemble_vliw_tokens (vinsn); 6109 6110 xg_clear_vinsn (vinsn); 6111 } 6112 6113 6114 /* Given an vliw instruction, what conflicts are there in register 6115 usage and in writes to states and queues? 6116 6117 This function does two things: 6118 1. Reports an error when a vinsn contains illegal combinations 6119 of writes to registers states or queues. 6120 2. Marks individual tinsns as not relaxable if the combination 6121 contains antidependencies. 6122 6123 Job 2 handles things like swap semantics in instructions that need 6124 to be relaxed. For example, 6125 6126 addi a0, a1, 100000 6127 6128 normally would be relaxed to 6129 6130 l32r a0, some_label 6131 add a0, a1, a0 6132 6133 _but_, if the above instruction is bundled with an a0 reader, e.g., 6134 6135 { addi a0, a1, 10000 ; add a2, a0, a4 ; } 6136 6137 then we can't relax it into 6138 6139 l32r a0, some_label 6140 { add a0, a1, a0 ; add a2, a0, a4 ; } 6141 6142 because the value of a0 is trashed before the second add can read it. */ 6143 6144 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); 6145 6146 static bfd_boolean 6147 find_vinsn_conflicts (vliw_insn *vinsn) 6148 { 6149 int i, j; 6150 int branches = 0; 6151 xtensa_isa isa = xtensa_default_isa; 6152 6153 assert (!past_xtensa_end); 6154 6155 for (i = 0 ; i < vinsn->num_slots; i++) 6156 { 6157 TInsn *op1 = &vinsn->slots[i]; 6158 if (op1->is_specific_opcode) 6159 op1->keep_wide = TRUE; 6160 else 6161 op1->keep_wide = FALSE; 6162 } 6163 6164 for (i = 0 ; i < vinsn->num_slots; i++) 6165 { 6166 TInsn *op1 = &vinsn->slots[i]; 6167 6168 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) 6169 branches++; 6170 6171 for (j = 0; j < vinsn->num_slots; j++) 6172 { 6173 if (i != j) 6174 { 6175 TInsn *op2 = &vinsn->slots[j]; 6176 char conflict_type = check_t1_t2_reads_and_writes (op1, op2); 6177 switch (conflict_type) 6178 { 6179 case 'c': 6180 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), 6181 xtensa_opcode_name (isa, op1->opcode), i, 6182 xtensa_opcode_name (isa, op2->opcode), j); 6183 return TRUE; 6184 case 'd': 6185 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), 6186 xtensa_opcode_name (isa, op1->opcode), i, 6187 xtensa_opcode_name (isa, op2->opcode), j); 6188 return TRUE; 6189 case 'e': 6190 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), 6191 xtensa_opcode_name (isa, op1->opcode), i, 6192 xtensa_opcode_name (isa, op2->opcode), j); 6193 return TRUE; 6194 case 'f': 6195 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), 6196 xtensa_opcode_name (isa, op1->opcode), i, 6197 xtensa_opcode_name (isa, op2->opcode), j); 6198 return TRUE; 6199 default: 6200 /* Everything is OK. */ 6201 break; 6202 } 6203 op2->is_specific_opcode = (op2->is_specific_opcode 6204 || conflict_type == 'a'); 6205 } 6206 } 6207 } 6208 6209 if (branches > 1) 6210 { 6211 as_bad (_("multiple branches or jumps in the same bundle")); 6212 return TRUE; 6213 } 6214 6215 return FALSE; 6216 } 6217 6218 6219 /* Check how the state used by t1 and t2 relate. 6220 Cases found are: 6221 6222 case A: t1 reads a register t2 writes (an antidependency within a bundle) 6223 case B: no relationship between what is read and written (both could 6224 read the same reg though) 6225 case C: t1 writes a register t2 writes (a register conflict within a 6226 bundle) 6227 case D: t1 writes a state that t2 also writes 6228 case E: t1 writes a tie queue that t2 also writes 6229 case F: two volatile queue accesses 6230 */ 6231 6232 static char 6233 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) 6234 { 6235 xtensa_isa isa = xtensa_default_isa; 6236 xtensa_regfile t1_regfile, t2_regfile; 6237 int t1_reg, t2_reg; 6238 int t1_base_reg, t1_last_reg; 6239 int t2_base_reg, t2_last_reg; 6240 char t1_inout, t2_inout; 6241 int i, j; 6242 char conflict = 'b'; 6243 int t1_states; 6244 int t2_states; 6245 int t1_interfaces; 6246 int t2_interfaces; 6247 bfd_boolean t1_volatile = FALSE; 6248 bfd_boolean t2_volatile = FALSE; 6249 6250 /* Check registers. */ 6251 for (j = 0; j < t2->ntok; j++) 6252 { 6253 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) 6254 continue; 6255 6256 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); 6257 t2_base_reg = t2->tok[j].X_add_number; 6258 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); 6259 6260 for (i = 0; i < t1->ntok; i++) 6261 { 6262 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) 6263 continue; 6264 6265 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); 6266 6267 if (t1_regfile != t2_regfile) 6268 continue; 6269 6270 t1_inout = xtensa_operand_inout (isa, t1->opcode, i); 6271 t2_inout = xtensa_operand_inout (isa, t2->opcode, j); 6272 6273 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 6274 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) 6275 { 6276 if (t1_inout == 'm' || t1_inout == 'o' 6277 || t2_inout == 'm' || t2_inout == 'o') 6278 { 6279 conflict = 'a'; 6280 continue; 6281 } 6282 } 6283 6284 t1_base_reg = t1->tok[i].X_add_number; 6285 t1_last_reg = (t1_base_reg 6286 + xtensa_operand_num_regs (isa, t1->opcode, i)); 6287 6288 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) 6289 { 6290 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) 6291 { 6292 if (t1_reg != t2_reg) 6293 continue; 6294 6295 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) 6296 { 6297 conflict = 'a'; 6298 continue; 6299 } 6300 6301 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) 6302 { 6303 conflict = 'a'; 6304 continue; 6305 } 6306 6307 if (t1_inout != 'i' && t2_inout != 'i') 6308 return 'c'; 6309 } 6310 } 6311 } 6312 } 6313 6314 /* Check states. */ 6315 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); 6316 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); 6317 for (j = 0; j < t2_states; j++) 6318 { 6319 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); 6320 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); 6321 for (i = 0; i < t1_states; i++) 6322 { 6323 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); 6324 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); 6325 if (t1_so != t2_so) 6326 continue; 6327 6328 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) 6329 { 6330 conflict = 'a'; 6331 continue; 6332 } 6333 6334 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) 6335 { 6336 conflict = 'a'; 6337 continue; 6338 } 6339 6340 if (t1_inout != 'i' && t2_inout != 'i') 6341 return 'd'; 6342 } 6343 } 6344 6345 /* Check tieports. */ 6346 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); 6347 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); 6348 for (j = 0; j < t2_interfaces; j++) 6349 { 6350 xtensa_interface t2_int 6351 = xtensa_interfaceOperand_interface (isa, t2->opcode, j); 6352 int t2_class = xtensa_interface_class_id (isa, t2_int); 6353 6354 t2_inout = xtensa_interface_inout (isa, t2_int); 6355 if (xtensa_interface_has_side_effect (isa, t2_int) == 1) 6356 t2_volatile = TRUE; 6357 6358 for (i = 0; i < t1_interfaces; i++) 6359 { 6360 xtensa_interface t1_int 6361 = xtensa_interfaceOperand_interface (isa, t1->opcode, j); 6362 int t1_class = xtensa_interface_class_id (isa, t1_int); 6363 6364 t1_inout = xtensa_interface_inout (isa, t1_int); 6365 if (xtensa_interface_has_side_effect (isa, t1_int) == 1) 6366 t1_volatile = TRUE; 6367 6368 if (t1_volatile && t2_volatile && (t1_class == t2_class)) 6369 return 'f'; 6370 6371 if (t1_int != t2_int) 6372 continue; 6373 6374 if (t2_inout == 'i' && t1_inout == 'o') 6375 { 6376 conflict = 'a'; 6377 continue; 6378 } 6379 6380 if (t1_inout == 'i' && t2_inout == 'o') 6381 { 6382 conflict = 'a'; 6383 continue; 6384 } 6385 6386 if (t1_inout != 'i' && t2_inout != 'i') 6387 return 'e'; 6388 } 6389 } 6390 6391 return conflict; 6392 } 6393 6394 6395 static xtensa_format 6396 xg_find_narrowest_format (vliw_insn *vinsn) 6397 { 6398 /* Right now we assume that the ops within the vinsn are properly 6399 ordered for the slots that the programmer wanted them in. In 6400 other words, we don't rearrange the ops in hopes of finding a 6401 better format. The scheduler handles that. */ 6402 6403 xtensa_isa isa = xtensa_default_isa; 6404 xtensa_format format; 6405 vliw_insn v_copy = *vinsn; 6406 xtensa_opcode nop_opcode = xtensa_nop_opcode; 6407 6408 if (vinsn->num_slots == 1) 6409 return xg_get_single_format (vinsn->slots[0].opcode); 6410 6411 for (format = 0; format < xtensa_isa_num_formats (isa); format++) 6412 { 6413 v_copy = *vinsn; 6414 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) 6415 { 6416 int slot; 6417 int fit = 0; 6418 for (slot = 0; slot < v_copy.num_slots; slot++) 6419 { 6420 if (v_copy.slots[slot].opcode == nop_opcode) 6421 { 6422 v_copy.slots[slot].opcode = 6423 xtensa_format_slot_nop_opcode (isa, format, slot); 6424 v_copy.slots[slot].ntok = 0; 6425 } 6426 6427 if (opcode_fits_format_slot (v_copy.slots[slot].opcode, 6428 format, slot)) 6429 fit++; 6430 else if (v_copy.num_slots > 1) 6431 { 6432 TInsn widened; 6433 /* Try the widened version. */ 6434 if (!v_copy.slots[slot].keep_wide 6435 && !v_copy.slots[slot].is_specific_opcode 6436 && xg_is_single_relaxable_insn (&v_copy.slots[slot], 6437 &widened, TRUE) 6438 && opcode_fits_format_slot (widened.opcode, 6439 format, slot)) 6440 { 6441 v_copy.slots[slot] = widened; 6442 fit++; 6443 } 6444 } 6445 } 6446 if (fit == v_copy.num_slots) 6447 { 6448 *vinsn = v_copy; 6449 xtensa_format_encode (isa, format, vinsn->insnbuf); 6450 vinsn->format = format; 6451 break; 6452 } 6453 } 6454 } 6455 6456 if (format == xtensa_isa_num_formats (isa)) 6457 return XTENSA_UNDEFINED; 6458 6459 return format; 6460 } 6461 6462 6463 /* Return the additional space needed in a frag 6464 for possible relaxations of any ops in a VLIW insn. 6465 Also fill out the relaxations that might be required of 6466 each tinsn in the vinsn. */ 6467 6468 static int 6469 relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) 6470 { 6471 bfd_boolean finish_frag = FALSE; 6472 int extra_space = 0; 6473 int slot; 6474 6475 for (slot = 0; slot < vinsn->num_slots; slot++) 6476 { 6477 TInsn *tinsn = &vinsn->slots[slot]; 6478 if (!tinsn_has_symbolic_operands (tinsn)) 6479 { 6480 /* A narrow instruction could be widened later to help 6481 alignment issues. */ 6482 if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) 6483 && !tinsn->is_specific_opcode 6484 && vinsn->num_slots == 1) 6485 { 6486 /* Difference in bytes between narrow and wide insns... */ 6487 extra_space += 1; 6488 tinsn->subtype = RELAX_NARROW; 6489 } 6490 } 6491 else 6492 { 6493 if (workaround_b_j_loop_end 6494 && tinsn->opcode == xtensa_jx_opcode 6495 && use_transform ()) 6496 { 6497 /* Add 2 of these. */ 6498 extra_space += 3; /* for the nop size */ 6499 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; 6500 } 6501 6502 /* Need to assemble it with space for the relocation. */ 6503 if (xg_is_relaxable_insn (tinsn, 0) 6504 && !tinsn->is_specific_opcode) 6505 { 6506 int max_size = xg_get_max_insn_widen_size (tinsn->opcode); 6507 int max_literal_size = 6508 xg_get_max_insn_widen_literal_size (tinsn->opcode); 6509 6510 tinsn->literal_space = max_literal_size; 6511 6512 tinsn->subtype = RELAX_IMMED; 6513 extra_space += max_size; 6514 } 6515 else 6516 { 6517 /* A fix record will be added for this instruction prior 6518 to relaxation, so make it end the frag. */ 6519 finish_frag = TRUE; 6520 } 6521 } 6522 } 6523 *pfinish_frag = finish_frag; 6524 return extra_space; 6525 } 6526 6527 6528 static void 6529 bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) 6530 { 6531 xtensa_isa isa = xtensa_default_isa; 6532 int slot, chosen_slot; 6533 6534 vinsn->format = xg_get_single_format (tinsn->opcode); 6535 assert (vinsn->format != XTENSA_UNDEFINED); 6536 vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); 6537 6538 chosen_slot = xg_get_single_slot (tinsn->opcode); 6539 for (slot = 0; slot < vinsn->num_slots; slot++) 6540 { 6541 if (slot == chosen_slot) 6542 vinsn->slots[slot] = *tinsn; 6543 else 6544 { 6545 vinsn->slots[slot].opcode = 6546 xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); 6547 vinsn->slots[slot].ntok = 0; 6548 vinsn->slots[slot].insn_type = ITYPE_INSN; 6549 } 6550 } 6551 } 6552 6553 6554 static bfd_boolean 6555 emit_single_op (TInsn *orig_insn) 6556 { 6557 int i; 6558 IStack istack; /* put instructions into here */ 6559 symbolS *lit_sym = NULL; 6560 symbolS *label_sym = NULL; 6561 6562 istack_init (&istack); 6563 6564 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. 6565 Because the scheduling and bundling characteristics of movi and 6566 l32r or const16 are so different, we can do much better if we relax 6567 it prior to scheduling and bundling, rather than after. */ 6568 if ((orig_insn->opcode == xtensa_movi_opcode 6569 || orig_insn->opcode == xtensa_movi_n_opcode) 6570 && !cur_vinsn.inside_bundle 6571 && (orig_insn->tok[1].X_op == O_symbol 6572 || orig_insn->tok[1].X_op == O_pltrel) 6573 && !orig_insn->is_specific_opcode && use_transform ()) 6574 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); 6575 else 6576 if (xg_expand_assembly_insn (&istack, orig_insn)) 6577 return TRUE; 6578 6579 for (i = 0; i < istack.ninsn; i++) 6580 { 6581 TInsn *insn = &istack.insn[i]; 6582 switch (insn->insn_type) 6583 { 6584 case ITYPE_LITERAL: 6585 assert (lit_sym == NULL); 6586 lit_sym = xg_assemble_literal (insn); 6587 break; 6588 case ITYPE_LABEL: 6589 { 6590 static int relaxed_sym_idx = 0; 6591 char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); 6592 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); 6593 colon (label); 6594 assert (label_sym == NULL); 6595 label_sym = symbol_find_or_make (label); 6596 assert (label_sym); 6597 free (label); 6598 } 6599 break; 6600 case ITYPE_INSN: 6601 { 6602 vliw_insn v; 6603 if (lit_sym) 6604 xg_resolve_literals (insn, lit_sym); 6605 if (label_sym) 6606 xg_resolve_labels (insn, label_sym); 6607 xg_init_vinsn (&v); 6608 bundle_tinsn (insn, &v); 6609 finish_vinsn (&v); 6610 xg_free_vinsn (&v); 6611 } 6612 break; 6613 default: 6614 assert (0); 6615 break; 6616 } 6617 } 6618 return FALSE; 6619 } 6620 6621 6622 static int 6623 total_frag_text_expansion (fragS *fragP) 6624 { 6625 int slot; 6626 int total_expansion = 0; 6627 6628 for (slot = 0; slot < MAX_SLOTS; slot++) 6629 total_expansion += fragP->tc_frag_data.text_expansion[slot]; 6630 6631 return total_expansion; 6632 } 6633 6634 6635 /* Emit a vliw instruction to the current fragment. */ 6636 6637 static void 6638 xg_assemble_vliw_tokens (vliw_insn *vinsn) 6639 { 6640 bfd_boolean finish_frag; 6641 bfd_boolean is_jump = FALSE; 6642 bfd_boolean is_branch = FALSE; 6643 xtensa_isa isa = xtensa_default_isa; 6644 int i; 6645 int insn_size; 6646 int extra_space; 6647 char *f = NULL; 6648 int slot; 6649 unsigned current_line, best_linenum; 6650 char *current_file; 6651 6652 best_linenum = UINT_MAX; 6653 6654 if (generating_literals) 6655 { 6656 static int reported = 0; 6657 if (reported < 4) 6658 as_bad_where (frag_now->fr_file, frag_now->fr_line, 6659 _("cannot assemble into a literal fragment")); 6660 if (reported == 3) 6661 as_bad (_("...")); 6662 reported++; 6663 return; 6664 } 6665 6666 if (frag_now_fix () != 0 6667 && (! frag_now->tc_frag_data.is_insn 6668 || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 6669 || !use_transform () != frag_now->tc_frag_data.is_no_transform 6670 || (directive_state[directive_longcalls] 6671 != frag_now->tc_frag_data.use_longcalls) 6672 || (directive_state[directive_absolute_literals] 6673 != frag_now->tc_frag_data.use_absolute_literals))) 6674 { 6675 frag_wane (frag_now); 6676 frag_new (0); 6677 xtensa_set_frag_assembly_state (frag_now); 6678 } 6679 6680 if (workaround_a0_b_retw 6681 && vinsn->num_slots == 1 6682 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 6683 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 6684 && use_transform ()) 6685 { 6686 has_a0_b_retw = TRUE; 6687 6688 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. 6689 After the first assembly pass we will check all of them and 6690 add a nop if needed. */ 6691 frag_now->tc_frag_data.is_insn = TRUE; 6692 frag_var (rs_machine_dependent, 4, 4, 6693 RELAX_ADD_NOP_IF_A0_B_RETW, 6694 frag_now->fr_symbol, 6695 frag_now->fr_offset, 6696 NULL); 6697 xtensa_set_frag_assembly_state (frag_now); 6698 frag_now->tc_frag_data.is_insn = TRUE; 6699 frag_var (rs_machine_dependent, 4, 4, 6700 RELAX_ADD_NOP_IF_A0_B_RETW, 6701 frag_now->fr_symbol, 6702 frag_now->fr_offset, 6703 NULL); 6704 xtensa_set_frag_assembly_state (frag_now); 6705 } 6706 6707 for (i = 0; i < vinsn->num_slots; i++) 6708 { 6709 /* See if the instruction implies an aligned section. */ 6710 if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1) 6711 record_alignment (now_seg, 2); 6712 6713 /* Also determine the best line number for debug info. */ 6714 best_linenum = vinsn->slots[i].linenum < best_linenum 6715 ? vinsn->slots[i].linenum : best_linenum; 6716 } 6717 6718 /* Special cases for instructions that force an alignment... */ 6719 /* None of these opcodes are bundle-able. */ 6720 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) 6721 { 6722 int max_fill; 6723 6724 /* Remember the symbol that marks the end of the loop in the frag 6725 that marks the start of the loop. This way we can easily find 6726 the end of the loop at the beginning, without adding special code 6727 to mark the loop instructions themselves. */ 6728 symbolS *target_sym = NULL; 6729 if (vinsn->slots[0].tok[1].X_op == O_symbol) 6730 target_sym = vinsn->slots[0].tok[1].X_add_symbol; 6731 6732 xtensa_set_frag_assembly_state (frag_now); 6733 frag_now->tc_frag_data.is_insn = TRUE; 6734 6735 max_fill = get_text_align_max_fill_size 6736 (get_text_align_power (xtensa_fetch_width), 6737 TRUE, frag_now->tc_frag_data.is_no_density); 6738 6739 if (use_transform ()) 6740 frag_var (rs_machine_dependent, max_fill, max_fill, 6741 RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); 6742 else 6743 frag_var (rs_machine_dependent, 0, 0, 6744 RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); 6745 xtensa_set_frag_assembly_state (frag_now); 6746 6747 xtensa_move_labels (frag_now, 0, FALSE); 6748 } 6749 6750 if (vinsn->slots[0].opcode == xtensa_entry_opcode 6751 && !vinsn->slots[0].is_specific_opcode) 6752 { 6753 xtensa_mark_literal_pool_location (); 6754 xtensa_move_labels (frag_now, 0, TRUE); 6755 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); 6756 } 6757 6758 if (vinsn->num_slots == 1) 6759 { 6760 if (workaround_a0_b_retw && use_transform ()) 6761 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, 6762 is_register_writer (&vinsn->slots[0], "a", 0)); 6763 6764 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, 6765 is_bad_loopend_opcode (&vinsn->slots[0])); 6766 } 6767 else 6768 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); 6769 6770 insn_size = xtensa_format_length (isa, vinsn->format); 6771 6772 extra_space = relaxation_requirements (vinsn, &finish_frag); 6773 6774 /* vinsn_to_insnbuf will produce the error. */ 6775 if (vinsn->format != XTENSA_UNDEFINED) 6776 { 6777 f = frag_more (insn_size + extra_space); 6778 xtensa_set_frag_assembly_state (frag_now); 6779 frag_now->tc_frag_data.is_insn = TRUE; 6780 } 6781 6782 vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); 6783 if (vinsn->format == XTENSA_UNDEFINED) 6784 return; 6785 6786 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); 6787 6788 /* Temporarily set the logical line number to the one we want to appear 6789 in the debug information. */ 6790 as_where (¤t_file, ¤t_line); 6791 new_logical_line (current_file, best_linenum); 6792 dwarf2_emit_insn (insn_size + extra_space); 6793 new_logical_line (current_file, current_line); 6794 6795 for (slot = 0; slot < vinsn->num_slots; slot++) 6796 { 6797 TInsn *tinsn = &vinsn->slots[slot]; 6798 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; 6799 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; 6800 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; 6801 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; 6802 if (tinsn->literal_space != 0) 6803 xg_assemble_literal_space (tinsn->literal_space, slot); 6804 6805 if (tinsn->subtype == RELAX_NARROW) 6806 assert (vinsn->num_slots == 1); 6807 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) 6808 is_jump = TRUE; 6809 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) 6810 is_branch = TRUE; 6811 6812 if (tinsn->subtype || tinsn->symbol || tinsn->offset 6813 || tinsn->literal_frag || is_jump || is_branch) 6814 finish_frag = TRUE; 6815 } 6816 6817 if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 6818 frag_now->tc_frag_data.is_specific_opcode = TRUE; 6819 6820 if (finish_frag) 6821 { 6822 frag_variant (rs_machine_dependent, 6823 extra_space, extra_space, RELAX_SLOTS, 6824 frag_now->fr_symbol, frag_now->fr_offset, f); 6825 xtensa_set_frag_assembly_state (frag_now); 6826 } 6827 6828 /* Special cases for loops: 6829 close_loop_end should be inserted AFTER short_loop. 6830 Make sure that CLOSE loops are processed BEFORE short_loops 6831 when converting them. */ 6832 6833 /* "short_loop": Add a NOP if the loop is < 4 bytes. */ 6834 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) 6835 && !vinsn->slots[0].is_specific_opcode) 6836 { 6837 if (workaround_short_loop && use_transform ()) 6838 { 6839 maybe_has_short_loop = TRUE; 6840 frag_now->tc_frag_data.is_insn = TRUE; 6841 frag_var (rs_machine_dependent, 4, 4, 6842 RELAX_ADD_NOP_IF_SHORT_LOOP, 6843 frag_now->fr_symbol, frag_now->fr_offset, NULL); 6844 frag_now->tc_frag_data.is_insn = TRUE; 6845 frag_var (rs_machine_dependent, 4, 4, 6846 RELAX_ADD_NOP_IF_SHORT_LOOP, 6847 frag_now->fr_symbol, frag_now->fr_offset, NULL); 6848 } 6849 6850 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a 6851 loop at least 12 bytes away from another loop's end. */ 6852 if (workaround_close_loop_end && use_transform ()) 6853 { 6854 maybe_has_close_loop_end = TRUE; 6855 frag_now->tc_frag_data.is_insn = TRUE; 6856 frag_var (rs_machine_dependent, 12, 12, 6857 RELAX_ADD_NOP_IF_CLOSE_LOOP_END, 6858 frag_now->fr_symbol, frag_now->fr_offset, NULL); 6859 } 6860 } 6861 6862 if (use_transform ()) 6863 { 6864 if (is_jump) 6865 { 6866 assert (finish_frag); 6867 frag_var (rs_machine_dependent, 6868 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, 6869 RELAX_UNREACHABLE, 6870 frag_now->fr_symbol, frag_now->fr_offset, NULL); 6871 xtensa_set_frag_assembly_state (frag_now); 6872 } 6873 else if (is_branch && do_align_targets ()) 6874 { 6875 assert (finish_frag); 6876 frag_var (rs_machine_dependent, 6877 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, 6878 RELAX_MAYBE_UNREACHABLE, 6879 frag_now->fr_symbol, frag_now->fr_offset, NULL); 6880 xtensa_set_frag_assembly_state (frag_now); 6881 frag_var (rs_machine_dependent, 6882 0, 0, 6883 RELAX_MAYBE_DESIRE_ALIGN, 6884 frag_now->fr_symbol, frag_now->fr_offset, NULL); 6885 xtensa_set_frag_assembly_state (frag_now); 6886 } 6887 } 6888 6889 /* Now, if the original opcode was a call... */ 6890 if (do_align_targets () 6891 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) 6892 { 6893 float freq = get_subseg_total_freq (now_seg, now_subseg); 6894 frag_now->tc_frag_data.is_insn = TRUE; 6895 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, 6896 frag_now->fr_symbol, frag_now->fr_offset, NULL); 6897 xtensa_set_frag_assembly_state (frag_now); 6898 } 6899 6900 if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 6901 { 6902 frag_wane (frag_now); 6903 frag_new (0); 6904 xtensa_set_frag_assembly_state (frag_now); 6905 } 6906 } 6907 6908 6909 /* xtensa_end and helper functions. */ 6910 6911 static void xtensa_cleanup_align_frags (void); 6912 static void xtensa_fix_target_frags (void); 6913 static void xtensa_mark_narrow_branches (void); 6914 static void xtensa_mark_zcl_first_insns (void); 6915 static void xtensa_fix_a0_b_retw_frags (void); 6916 static void xtensa_fix_b_j_loop_end_frags (void); 6917 static void xtensa_fix_close_loop_end_frags (void); 6918 static void xtensa_fix_short_loop_frags (void); 6919 static void xtensa_sanity_check (void); 6920 6921 void 6922 xtensa_end (void) 6923 { 6924 directive_balance (); 6925 xtensa_flush_pending_output (); 6926 6927 past_xtensa_end = TRUE; 6928 6929 xtensa_move_literals (); 6930 6931 xtensa_reorder_segments (); 6932 xtensa_cleanup_align_frags (); 6933 xtensa_fix_target_frags (); 6934 if (workaround_a0_b_retw && has_a0_b_retw) 6935 xtensa_fix_a0_b_retw_frags (); 6936 if (workaround_b_j_loop_end) 6937 xtensa_fix_b_j_loop_end_frags (); 6938 6939 /* "close_loop_end" should be processed BEFORE "short_loop". */ 6940 if (workaround_close_loop_end && maybe_has_close_loop_end) 6941 xtensa_fix_close_loop_end_frags (); 6942 6943 if (workaround_short_loop && maybe_has_short_loop) 6944 xtensa_fix_short_loop_frags (); 6945 if (align_targets) 6946 xtensa_mark_narrow_branches (); 6947 xtensa_mark_zcl_first_insns (); 6948 6949 xtensa_sanity_check (); 6950 } 6951 6952 6953 static void 6954 xtensa_cleanup_align_frags (void) 6955 { 6956 frchainS *frchP; 6957 6958 for (frchP = frchain_root; frchP; frchP = frchP->frch_next) 6959 { 6960 fragS *fragP; 6961 /* Walk over all of the fragments in a subsection. */ 6962 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 6963 { 6964 if ((fragP->fr_type == rs_align 6965 || fragP->fr_type == rs_align_code 6966 || (fragP->fr_type == rs_machine_dependent 6967 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN 6968 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) 6969 && fragP->fr_fix == 0) 6970 { 6971 fragS *next = fragP->fr_next; 6972 6973 while (next 6974 && next->fr_fix == 0 6975 && next->fr_type == rs_machine_dependent 6976 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) 6977 { 6978 frag_wane (next); 6979 next = next->fr_next; 6980 } 6981 } 6982 /* If we don't widen branch targets, then they 6983 will be easier to align. */ 6984 if (fragP->tc_frag_data.is_branch_target 6985 && fragP->fr_opcode == fragP->fr_literal 6986 && fragP->fr_type == rs_machine_dependent 6987 && fragP->fr_subtype == RELAX_SLOTS 6988 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 6989 frag_wane (fragP); 6990 if (fragP->fr_type == rs_machine_dependent 6991 && fragP->fr_subtype == RELAX_UNREACHABLE) 6992 fragP->tc_frag_data.is_unreachable = TRUE; 6993 } 6994 } 6995 } 6996 6997 6998 /* Re-process all of the fragments looking to convert all of the 6999 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch 7000 target in the next fragment, convert this to RELAX_DESIRE_ALIGN. 7001 Otherwise, convert to a .fill 0. */ 7002 7003 static void 7004 xtensa_fix_target_frags (void) 7005 { 7006 frchainS *frchP; 7007 7008 /* When this routine is called, all of the subsections are still intact 7009 so we walk over subsections instead of sections. */ 7010 for (frchP = frchain_root; frchP; frchP = frchP->frch_next) 7011 { 7012 fragS *fragP; 7013 7014 /* Walk over all of the fragments in a subsection. */ 7015 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7016 { 7017 if (fragP->fr_type == rs_machine_dependent 7018 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) 7019 { 7020 if (next_frag_is_branch_target (fragP)) 7021 fragP->fr_subtype = RELAX_DESIRE_ALIGN; 7022 else 7023 frag_wane (fragP); 7024 } 7025 } 7026 } 7027 } 7028 7029 7030 static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); 7031 7032 static void 7033 xtensa_mark_narrow_branches (void) 7034 { 7035 frchainS *frchP; 7036 7037 for (frchP = frchain_root; frchP; frchP = frchP->frch_next) 7038 { 7039 fragS *fragP; 7040 /* Walk over all of the fragments in a subsection. */ 7041 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7042 { 7043 if (fragP->fr_type == rs_machine_dependent 7044 && fragP->fr_subtype == RELAX_SLOTS 7045 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) 7046 { 7047 vliw_insn vinsn; 7048 7049 vinsn_from_chars (&vinsn, fragP->fr_opcode); 7050 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); 7051 7052 if (vinsn.num_slots == 1 7053 && xtensa_opcode_is_branch (xtensa_default_isa, 7054 vinsn.slots[0].opcode) 7055 && xg_get_single_size (vinsn.slots[0].opcode) == 2 7056 && is_narrow_branch_guaranteed_in_range (fragP, 7057 &vinsn.slots[0])) 7058 { 7059 fragP->fr_subtype = RELAX_SLOTS; 7060 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; 7061 fragP->tc_frag_data.is_aligning_branch = 1; 7062 } 7063 } 7064 } 7065 } 7066 } 7067 7068 7069 /* A branch is typically widened only when its target is out of 7070 range. However, we would like to widen them to align a subsequent 7071 branch target when possible. 7072 7073 Because the branch relaxation code is so convoluted, the optimal solution 7074 (combining the two cases) is difficult to get right in all circumstances. 7075 We therefore go with an "almost as good" solution, where we only 7076 use for alignment narrow branches that definitely will not expand to a 7077 jump and a branch. These functions find and mark these cases. */ 7078 7079 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded 7080 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. 7081 We start counting beginning with the frag after the 2-byte branch, so the 7082 maximum offset is (4 - 2) + 63 = 65. */ 7083 #define MAX_IMMED6 65 7084 7085 static offsetT unrelaxed_frag_max_size (fragS *); 7086 7087 static bfd_boolean 7088 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) 7089 { 7090 const expressionS *expr = &tinsn->tok[1]; 7091 symbolS *symbolP = expr->X_add_symbol; 7092 offsetT max_distance = expr->X_add_number; 7093 fragS *target_frag; 7094 7095 if (expr->X_op != O_symbol) 7096 return FALSE; 7097 7098 target_frag = symbol_get_frag (symbolP); 7099 7100 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); 7101 if (is_branch_jmp_to_next (tinsn, fragP)) 7102 return FALSE; 7103 7104 /* The branch doesn't branch over it's own frag, 7105 but over the subsequent ones. */ 7106 fragP = fragP->fr_next; 7107 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) 7108 { 7109 max_distance += unrelaxed_frag_max_size (fragP); 7110 fragP = fragP->fr_next; 7111 } 7112 if (max_distance <= MAX_IMMED6 && fragP == target_frag) 7113 return TRUE; 7114 return FALSE; 7115 } 7116 7117 7118 static void 7119 xtensa_mark_zcl_first_insns (void) 7120 { 7121 frchainS *frchP; 7122 7123 for (frchP = frchain_root; frchP; frchP = frchP->frch_next) 7124 { 7125 fragS *fragP; 7126 /* Walk over all of the fragments in a subsection. */ 7127 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7128 { 7129 if (fragP->fr_type == rs_machine_dependent 7130 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE 7131 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) 7132 { 7133 /* Find the loop frag. */ 7134 fragS *targ_frag = next_non_empty_frag (fragP); 7135 /* Find the first insn frag. */ 7136 targ_frag = next_non_empty_frag (targ_frag); 7137 7138 /* Of course, sometimes (mostly for toy test cases) a 7139 zero-cost loop instruction is the last in a section. */ 7140 if (targ_frag) 7141 { 7142 targ_frag->tc_frag_data.is_first_loop_insn = TRUE; 7143 /* Do not widen a frag that is the first instruction of a 7144 zero-cost loop. It makes that loop harder to align. */ 7145 if (targ_frag->fr_type == rs_machine_dependent 7146 && targ_frag->fr_subtype == RELAX_SLOTS 7147 && (targ_frag->tc_frag_data.slot_subtypes[0] 7148 == RELAX_NARROW)) 7149 { 7150 if (targ_frag->tc_frag_data.is_aligning_branch) 7151 targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; 7152 else 7153 { 7154 frag_wane (targ_frag); 7155 targ_frag->tc_frag_data.slot_subtypes[0] = 0; 7156 } 7157 } 7158 } 7159 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) 7160 frag_wane (fragP); 7161 } 7162 } 7163 } 7164 } 7165 7166 7167 /* Re-process all of the fragments looking to convert all of the 7168 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a 7169 conditional branch or a retw/retw.n, convert this frag to one that 7170 will generate a NOP. In any case close it off with a .fill 0. */ 7171 7172 static bfd_boolean next_instrs_are_b_retw (fragS *); 7173 7174 static void 7175 xtensa_fix_a0_b_retw_frags (void) 7176 { 7177 frchainS *frchP; 7178 7179 /* When this routine is called, all of the subsections are still intact 7180 so we walk over subsections instead of sections. */ 7181 for (frchP = frchain_root; frchP; frchP = frchP->frch_next) 7182 { 7183 fragS *fragP; 7184 7185 /* Walk over all of the fragments in a subsection. */ 7186 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7187 { 7188 if (fragP->fr_type == rs_machine_dependent 7189 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) 7190 { 7191 if (next_instrs_are_b_retw (fragP)) 7192 { 7193 if (fragP->tc_frag_data.is_no_transform) 7194 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); 7195 else 7196 relax_frag_add_nop (fragP); 7197 } 7198 frag_wane (fragP); 7199 } 7200 } 7201 } 7202 } 7203 7204 7205 static bfd_boolean 7206 next_instrs_are_b_retw (fragS *fragP) 7207 { 7208 xtensa_opcode opcode; 7209 xtensa_format fmt; 7210 const fragS *next_fragP = next_non_empty_frag (fragP); 7211 static xtensa_insnbuf insnbuf = NULL; 7212 static xtensa_insnbuf slotbuf = NULL; 7213 xtensa_isa isa = xtensa_default_isa; 7214 int offset = 0; 7215 int slot; 7216 bfd_boolean branch_seen = FALSE; 7217 7218 if (!insnbuf) 7219 { 7220 insnbuf = xtensa_insnbuf_alloc (isa); 7221 slotbuf = xtensa_insnbuf_alloc (isa); 7222 } 7223 7224 if (next_fragP == NULL) 7225 return FALSE; 7226 7227 /* Check for the conditional branch. */ 7228 xtensa_insnbuf_from_chars 7229 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); 7230 fmt = xtensa_format_decode (isa, insnbuf); 7231 if (fmt == XTENSA_UNDEFINED) 7232 return FALSE; 7233 7234 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 7235 { 7236 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 7237 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 7238 7239 branch_seen = (branch_seen 7240 || xtensa_opcode_is_branch (isa, opcode) == 1); 7241 } 7242 7243 if (!branch_seen) 7244 return FALSE; 7245 7246 offset += xtensa_format_length (isa, fmt); 7247 if (offset == next_fragP->fr_fix) 7248 { 7249 next_fragP = next_non_empty_frag (next_fragP); 7250 offset = 0; 7251 } 7252 7253 if (next_fragP == NULL) 7254 return FALSE; 7255 7256 /* Check for the retw/retw.n. */ 7257 xtensa_insnbuf_from_chars 7258 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); 7259 fmt = xtensa_format_decode (isa, insnbuf); 7260 7261 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we 7262 have no problems. */ 7263 if (fmt == XTENSA_UNDEFINED 7264 || xtensa_format_num_slots (isa, fmt) != 1) 7265 return FALSE; 7266 7267 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); 7268 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); 7269 7270 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) 7271 return TRUE; 7272 7273 return FALSE; 7274 } 7275 7276 7277 /* Re-process all of the fragments looking to convert all of the 7278 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a 7279 loop end label, convert this frag to one that will generate a NOP. 7280 In any case close it off with a .fill 0. */ 7281 7282 static bfd_boolean next_instr_is_loop_end (fragS *); 7283 7284 static void 7285 xtensa_fix_b_j_loop_end_frags (void) 7286 { 7287 frchainS *frchP; 7288 7289 /* When this routine is called, all of the subsections are still intact 7290 so we walk over subsections instead of sections. */ 7291 for (frchP = frchain_root; frchP; frchP = frchP->frch_next) 7292 { 7293 fragS *fragP; 7294 7295 /* Walk over all of the fragments in a subsection. */ 7296 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7297 { 7298 if (fragP->fr_type == rs_machine_dependent 7299 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) 7300 { 7301 if (next_instr_is_loop_end (fragP)) 7302 { 7303 if (fragP->tc_frag_data.is_no_transform) 7304 as_bad (_("branching or jumping to a loop end may trigger hardware errata")); 7305 else 7306 relax_frag_add_nop (fragP); 7307 } 7308 frag_wane (fragP); 7309 } 7310 } 7311 } 7312 } 7313 7314 7315 static bfd_boolean 7316 next_instr_is_loop_end (fragS *fragP) 7317 { 7318 const fragS *next_fragP; 7319 7320 if (next_frag_is_loop_target (fragP)) 7321 return FALSE; 7322 7323 next_fragP = next_non_empty_frag (fragP); 7324 if (next_fragP == NULL) 7325 return FALSE; 7326 7327 if (!next_frag_is_loop_target (next_fragP)) 7328 return FALSE; 7329 7330 /* If the size is >= 3 then there is more than one instruction here. 7331 The hardware bug will not fire. */ 7332 if (next_fragP->fr_fix > 3) 7333 return FALSE; 7334 7335 return TRUE; 7336 } 7337 7338 7339 /* Re-process all of the fragments looking to convert all of the 7340 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is 7341 not MY loop's loop end within 12 bytes, add enough nops here to 7342 make it at least 12 bytes away. In any case close it off with a 7343 .fill 0. */ 7344 7345 static offsetT min_bytes_to_other_loop_end 7346 (fragS *, fragS *, offsetT); 7347 7348 static void 7349 xtensa_fix_close_loop_end_frags (void) 7350 { 7351 frchainS *frchP; 7352 7353 /* When this routine is called, all of the subsections are still intact 7354 so we walk over subsections instead of sections. */ 7355 for (frchP = frchain_root; frchP; frchP = frchP->frch_next) 7356 { 7357 fragS *fragP; 7358 7359 fragS *current_target = NULL; 7360 7361 /* Walk over all of the fragments in a subsection. */ 7362 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7363 { 7364 if (fragP->fr_type == rs_machine_dependent 7365 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) 7366 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) 7367 current_target = symbol_get_frag (fragP->fr_symbol); 7368 7369 if (current_target 7370 && fragP->fr_type == rs_machine_dependent 7371 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) 7372 { 7373 offsetT min_bytes; 7374 int bytes_added = 0; 7375 7376 #define REQUIRED_LOOP_DIVIDING_BYTES 12 7377 /* Max out at 12. */ 7378 min_bytes = min_bytes_to_other_loop_end 7379 (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); 7380 7381 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) 7382 { 7383 if (fragP->tc_frag_data.is_no_transform) 7384 as_bad (_("loop end too close to another loop end may trigger hardware errata")); 7385 else 7386 { 7387 while (min_bytes + bytes_added 7388 < REQUIRED_LOOP_DIVIDING_BYTES) 7389 { 7390 int length = 3; 7391 7392 if (fragP->fr_var < length) 7393 as_fatal (_("fr_var %lu < length %d"), 7394 (long) fragP->fr_var, length); 7395 else 7396 { 7397 assemble_nop (length, 7398 fragP->fr_literal + fragP->fr_fix); 7399 fragP->fr_fix += length; 7400 fragP->fr_var -= length; 7401 } 7402 bytes_added += length; 7403 } 7404 } 7405 } 7406 frag_wane (fragP); 7407 } 7408 assert (fragP->fr_type != rs_machine_dependent 7409 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); 7410 } 7411 } 7412 } 7413 7414 7415 static offsetT unrelaxed_frag_min_size (fragS *); 7416 7417 static offsetT 7418 min_bytes_to_other_loop_end (fragS *fragP, 7419 fragS *current_target, 7420 offsetT max_size) 7421 { 7422 offsetT offset = 0; 7423 fragS *current_fragP; 7424 7425 for (current_fragP = fragP; 7426 current_fragP; 7427 current_fragP = current_fragP->fr_next) 7428 { 7429 if (current_fragP->tc_frag_data.is_loop_target 7430 && current_fragP != current_target) 7431 return offset; 7432 7433 offset += unrelaxed_frag_min_size (current_fragP); 7434 7435 if (offset >= max_size) 7436 return max_size; 7437 } 7438 return max_size; 7439 } 7440 7441 7442 static offsetT 7443 unrelaxed_frag_min_size (fragS *fragP) 7444 { 7445 offsetT size = fragP->fr_fix; 7446 7447 /* Add fill size. */ 7448 if (fragP->fr_type == rs_fill) 7449 size += fragP->fr_offset; 7450 7451 return size; 7452 } 7453 7454 7455 static offsetT 7456 unrelaxed_frag_max_size (fragS *fragP) 7457 { 7458 offsetT size = fragP->fr_fix; 7459 switch (fragP->fr_type) 7460 { 7461 case 0: 7462 /* Empty frags created by the obstack allocation scheme 7463 end up with type 0. */ 7464 break; 7465 case rs_fill: 7466 case rs_org: 7467 case rs_space: 7468 size += fragP->fr_offset; 7469 break; 7470 case rs_align: 7471 case rs_align_code: 7472 case rs_align_test: 7473 case rs_leb128: 7474 case rs_cfa: 7475 case rs_dwarf2dbg: 7476 /* No further adjustments needed. */ 7477 break; 7478 case rs_machine_dependent: 7479 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) 7480 size += fragP->fr_var; 7481 break; 7482 default: 7483 /* We had darn well better know how big it is. */ 7484 assert (0); 7485 break; 7486 } 7487 7488 return size; 7489 } 7490 7491 7492 /* Re-process all of the fragments looking to convert all 7493 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: 7494 7495 A) 7496 1) the instruction size count to the loop end label 7497 is too short (<= 2 instructions), 7498 2) loop has a jump or branch in it 7499 7500 or B) 7501 1) workaround_all_short_loops is TRUE 7502 2) The generating loop was a 'loopgtz' or 'loopnez' 7503 3) the instruction size count to the loop end label is too short 7504 (<= 2 instructions) 7505 then convert this frag (and maybe the next one) to generate a NOP. 7506 In any case close it off with a .fill 0. */ 7507 7508 static int count_insns_to_loop_end (fragS *, bfd_boolean, int); 7509 static bfd_boolean branch_before_loop_end (fragS *); 7510 7511 static void 7512 xtensa_fix_short_loop_frags (void) 7513 { 7514 frchainS *frchP; 7515 7516 /* When this routine is called, all of the subsections are still intact 7517 so we walk over subsections instead of sections. */ 7518 for (frchP = frchain_root; frchP; frchP = frchP->frch_next) 7519 { 7520 fragS *fragP; 7521 fragS *current_target = NULL; 7522 xtensa_opcode current_opcode = XTENSA_UNDEFINED; 7523 7524 /* Walk over all of the fragments in a subsection. */ 7525 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7526 { 7527 if (fragP->fr_type == rs_machine_dependent 7528 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) 7529 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) 7530 { 7531 TInsn t_insn; 7532 fragS *loop_frag = next_non_empty_frag (fragP); 7533 tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); 7534 current_target = symbol_get_frag (fragP->fr_symbol); 7535 current_opcode = t_insn.opcode; 7536 assert (xtensa_opcode_is_loop (xtensa_default_isa, 7537 current_opcode)); 7538 } 7539 7540 if (fragP->fr_type == rs_machine_dependent 7541 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) 7542 { 7543 if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 7544 && (branch_before_loop_end (fragP->fr_next) 7545 || (workaround_all_short_loops 7546 && current_opcode != XTENSA_UNDEFINED 7547 && current_opcode != xtensa_loop_opcode))) 7548 { 7549 if (fragP->tc_frag_data.is_no_transform) 7550 as_bad (_("loop containing less than three instructions may trigger hardware errata")); 7551 else 7552 relax_frag_add_nop (fragP); 7553 } 7554 frag_wane (fragP); 7555 } 7556 } 7557 } 7558 } 7559 7560 7561 static int unrelaxed_frag_min_insn_count (fragS *); 7562 7563 static int 7564 count_insns_to_loop_end (fragS *base_fragP, 7565 bfd_boolean count_relax_add, 7566 int max_count) 7567 { 7568 fragS *fragP = NULL; 7569 int insn_count = 0; 7570 7571 fragP = base_fragP; 7572 7573 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) 7574 { 7575 insn_count += unrelaxed_frag_min_insn_count (fragP); 7576 if (insn_count >= max_count) 7577 return max_count; 7578 7579 if (count_relax_add) 7580 { 7581 if (fragP->fr_type == rs_machine_dependent 7582 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) 7583 { 7584 /* In order to add the appropriate number of 7585 NOPs, we count an instruction for downstream 7586 occurrences. */ 7587 insn_count++; 7588 if (insn_count >= max_count) 7589 return max_count; 7590 } 7591 } 7592 } 7593 return insn_count; 7594 } 7595 7596 7597 static int 7598 unrelaxed_frag_min_insn_count (fragS *fragP) 7599 { 7600 xtensa_isa isa = xtensa_default_isa; 7601 static xtensa_insnbuf insnbuf = NULL; 7602 int insn_count = 0; 7603 int offset = 0; 7604 7605 if (!fragP->tc_frag_data.is_insn) 7606 return insn_count; 7607 7608 if (!insnbuf) 7609 insnbuf = xtensa_insnbuf_alloc (isa); 7610 7611 /* Decode the fixed instructions. */ 7612 while (offset < fragP->fr_fix) 7613 { 7614 xtensa_format fmt; 7615 7616 xtensa_insnbuf_from_chars 7617 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); 7618 fmt = xtensa_format_decode (isa, insnbuf); 7619 7620 if (fmt == XTENSA_UNDEFINED) 7621 { 7622 as_fatal (_("undecodable instruction in instruction frag")); 7623 return insn_count; 7624 } 7625 offset += xtensa_format_length (isa, fmt); 7626 insn_count++; 7627 } 7628 7629 return insn_count; 7630 } 7631 7632 7633 static bfd_boolean unrelaxed_frag_has_b_j (fragS *); 7634 7635 static bfd_boolean 7636 branch_before_loop_end (fragS *base_fragP) 7637 { 7638 fragS *fragP; 7639 7640 for (fragP = base_fragP; 7641 fragP && !fragP->tc_frag_data.is_loop_target; 7642 fragP = fragP->fr_next) 7643 { 7644 if (unrelaxed_frag_has_b_j (fragP)) 7645 return TRUE; 7646 } 7647 return FALSE; 7648 } 7649 7650 7651 static bfd_boolean 7652 unrelaxed_frag_has_b_j (fragS *fragP) 7653 { 7654 static xtensa_insnbuf insnbuf = NULL; 7655 xtensa_isa isa = xtensa_default_isa; 7656 int offset = 0; 7657 7658 if (!fragP->tc_frag_data.is_insn) 7659 return FALSE; 7660 7661 if (!insnbuf) 7662 insnbuf = xtensa_insnbuf_alloc (isa); 7663 7664 /* Decode the fixed instructions. */ 7665 while (offset < fragP->fr_fix) 7666 { 7667 xtensa_format fmt; 7668 int slot; 7669 7670 xtensa_insnbuf_from_chars 7671 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); 7672 fmt = xtensa_format_decode (isa, insnbuf); 7673 if (fmt == XTENSA_UNDEFINED) 7674 return FALSE; 7675 7676 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 7677 { 7678 xtensa_opcode opcode = 7679 get_opcode_from_buf (fragP->fr_literal + offset, slot); 7680 if (xtensa_opcode_is_branch (isa, opcode) == 1 7681 || xtensa_opcode_is_jump (isa, opcode) == 1) 7682 return TRUE; 7683 } 7684 offset += xtensa_format_length (isa, fmt); 7685 } 7686 return FALSE; 7687 } 7688 7689 7690 /* Checks to be made after initial assembly but before relaxation. */ 7691 7692 static bfd_boolean is_empty_loop (const TInsn *, fragS *); 7693 static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); 7694 7695 static void 7696 xtensa_sanity_check (void) 7697 { 7698 char *file_name; 7699 unsigned line; 7700 7701 frchainS *frchP; 7702 7703 as_where (&file_name, &line); 7704 for (frchP = frchain_root; frchP; frchP = frchP->frch_next) 7705 { 7706 fragS *fragP; 7707 7708 /* Walk over all of the fragments in a subsection. */ 7709 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7710 { 7711 /* Currently we only check for empty loops here. */ 7712 if (fragP->fr_type == rs_machine_dependent 7713 && fragP->fr_subtype == RELAX_IMMED) 7714 { 7715 static xtensa_insnbuf insnbuf = NULL; 7716 TInsn t_insn; 7717 7718 if (fragP->fr_opcode != NULL) 7719 { 7720 if (!insnbuf) 7721 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 7722 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); 7723 tinsn_immed_from_frag (&t_insn, fragP, 0); 7724 7725 if (xtensa_opcode_is_loop (xtensa_default_isa, 7726 t_insn.opcode) == 1) 7727 { 7728 if (is_empty_loop (&t_insn, fragP)) 7729 { 7730 new_logical_line (fragP->fr_file, fragP->fr_line); 7731 as_bad (_("invalid empty loop")); 7732 } 7733 if (!is_local_forward_loop (&t_insn, fragP)) 7734 { 7735 new_logical_line (fragP->fr_file, fragP->fr_line); 7736 as_bad (_("loop target does not follow " 7737 "loop instruction in section")); 7738 } 7739 } 7740 } 7741 } 7742 } 7743 } 7744 new_logical_line (file_name, line); 7745 } 7746 7747 7748 #define LOOP_IMMED_OPN 1 7749 7750 /* Return TRUE if the loop target is the next non-zero fragment. */ 7751 7752 static bfd_boolean 7753 is_empty_loop (const TInsn *insn, fragS *fragP) 7754 { 7755 const expressionS *expr; 7756 symbolS *symbolP; 7757 fragS *next_fragP; 7758 7759 if (insn->insn_type != ITYPE_INSN) 7760 return FALSE; 7761 7762 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) 7763 return FALSE; 7764 7765 if (insn->ntok <= LOOP_IMMED_OPN) 7766 return FALSE; 7767 7768 expr = &insn->tok[LOOP_IMMED_OPN]; 7769 7770 if (expr->X_op != O_symbol) 7771 return FALSE; 7772 7773 symbolP = expr->X_add_symbol; 7774 if (!symbolP) 7775 return FALSE; 7776 7777 if (symbol_get_frag (symbolP) == NULL) 7778 return FALSE; 7779 7780 if (S_GET_VALUE (symbolP) != 0) 7781 return FALSE; 7782 7783 /* Walk through the zero-size fragments from this one. If we find 7784 the target fragment, then this is a zero-size loop. */ 7785 7786 for (next_fragP = fragP->fr_next; 7787 next_fragP != NULL; 7788 next_fragP = next_fragP->fr_next) 7789 { 7790 if (next_fragP == symbol_get_frag (symbolP)) 7791 return TRUE; 7792 if (next_fragP->fr_fix != 0) 7793 return FALSE; 7794 } 7795 return FALSE; 7796 } 7797 7798 7799 static bfd_boolean 7800 is_local_forward_loop (const TInsn *insn, fragS *fragP) 7801 { 7802 const expressionS *expr; 7803 symbolS *symbolP; 7804 fragS *next_fragP; 7805 7806 if (insn->insn_type != ITYPE_INSN) 7807 return FALSE; 7808 7809 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0) 7810 return FALSE; 7811 7812 if (insn->ntok <= LOOP_IMMED_OPN) 7813 return FALSE; 7814 7815 expr = &insn->tok[LOOP_IMMED_OPN]; 7816 7817 if (expr->X_op != O_symbol) 7818 return FALSE; 7819 7820 symbolP = expr->X_add_symbol; 7821 if (!symbolP) 7822 return FALSE; 7823 7824 if (symbol_get_frag (symbolP) == NULL) 7825 return FALSE; 7826 7827 /* Walk through fragments until we find the target. 7828 If we do not find the target, then this is an invalid loop. */ 7829 7830 for (next_fragP = fragP->fr_next; 7831 next_fragP != NULL; 7832 next_fragP = next_fragP->fr_next) 7833 { 7834 if (next_fragP == symbol_get_frag (symbolP)) 7835 return TRUE; 7836 } 7837 7838 return FALSE; 7839 } 7840 7841 7842 /* Alignment Functions. */ 7843 7844 static int 7845 get_text_align_power (unsigned target_size) 7846 { 7847 if (target_size <= 4) 7848 return 2; 7849 assert (target_size == 8); 7850 return 3; 7851 } 7852 7853 7854 static int 7855 get_text_align_max_fill_size (int align_pow, 7856 bfd_boolean use_nops, 7857 bfd_boolean use_no_density) 7858 { 7859 if (!use_nops) 7860 return (1 << align_pow); 7861 if (use_no_density) 7862 return 3 * (1 << align_pow); 7863 7864 return 1 + (1 << align_pow); 7865 } 7866 7867 7868 /* Calculate the minimum bytes of fill needed at "address" to align a 7869 target instruction of size "target_size" so that it does not cross a 7870 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, 7871 the fill can be an arbitrary number of bytes. Otherwise, the space must 7872 be filled by NOP instructions. */ 7873 7874 static int 7875 get_text_align_fill_size (addressT address, 7876 int align_pow, 7877 int target_size, 7878 bfd_boolean use_nops, 7879 bfd_boolean use_no_density) 7880 { 7881 addressT alignment, fill, fill_limit, fill_step; 7882 bfd_boolean skip_one = FALSE; 7883 7884 alignment = (1 << align_pow); 7885 assert (target_size > 0 && alignment >= (addressT) target_size); 7886 7887 if (!use_nops) 7888 { 7889 fill_limit = alignment; 7890 fill_step = 1; 7891 } 7892 else if (!use_no_density) 7893 { 7894 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ 7895 fill_limit = alignment * 2; 7896 fill_step = 1; 7897 skip_one = TRUE; 7898 } 7899 else 7900 { 7901 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ 7902 fill_limit = alignment * 3; 7903 fill_step = 3; 7904 } 7905 7906 /* Try all fill sizes until finding one that works. */ 7907 for (fill = 0; fill < fill_limit; fill += fill_step) 7908 { 7909 if (skip_one && fill == 1) 7910 continue; 7911 if ((address + fill) >> align_pow 7912 == (address + fill + target_size - 1) >> align_pow) 7913 return fill; 7914 } 7915 assert (0); 7916 return 0; 7917 } 7918 7919 7920 static int 7921 branch_align_power (segT sec) 7922 { 7923 /* If the Xtensa processor has a fetch width of 8 bytes, and the section 7924 is aligned to at least an 8-byte boundary, then a branch target need 7925 only fit within an 8-byte aligned block of memory to avoid a stall. 7926 Otherwise, try to fit branch targets within 4-byte aligned blocks 7927 (which may be insufficient, e.g., if the section has no alignment, but 7928 it's good enough). */ 7929 if (xtensa_fetch_width == 8) 7930 { 7931 if (get_recorded_alignment (sec) >= 3) 7932 return 3; 7933 } 7934 else 7935 assert (xtensa_fetch_width == 4); 7936 7937 return 2; 7938 } 7939 7940 7941 /* This will assert if it is not possible. */ 7942 7943 static int 7944 get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) 7945 { 7946 int count = 0; 7947 7948 if (use_no_density) 7949 { 7950 assert (fill_size % 3 == 0); 7951 return (fill_size / 3); 7952 } 7953 7954 assert (fill_size != 1); /* Bad argument. */ 7955 7956 while (fill_size > 1) 7957 { 7958 int insn_size = 3; 7959 if (fill_size == 2 || fill_size == 4) 7960 insn_size = 2; 7961 fill_size -= insn_size; 7962 count++; 7963 } 7964 assert (fill_size != 1); /* Bad algorithm. */ 7965 return count; 7966 } 7967 7968 7969 static int 7970 get_text_align_nth_nop_size (offsetT fill_size, 7971 int n, 7972 bfd_boolean use_no_density) 7973 { 7974 int count = 0; 7975 7976 if (use_no_density) 7977 return 3; 7978 7979 assert (fill_size != 1); /* Bad argument. */ 7980 7981 while (fill_size > 1) 7982 { 7983 int insn_size = 3; 7984 if (fill_size == 2 || fill_size == 4) 7985 insn_size = 2; 7986 fill_size -= insn_size; 7987 count++; 7988 if (n + 1 == count) 7989 return insn_size; 7990 } 7991 assert (0); 7992 return 0; 7993 } 7994 7995 7996 /* For the given fragment, find the appropriate address 7997 for it to begin at if we are using NOPs to align it. */ 7998 7999 static addressT 8000 get_noop_aligned_address (fragS *fragP, addressT address) 8001 { 8002 /* The rule is: get next fragment's FIRST instruction. Find 8003 the smallest number of bytes that need to be added to 8004 ensure that the next fragment's FIRST instruction will fit 8005 in a single word. 8006 8007 E.G., 2 bytes : 0, 1, 2 mod 4 8008 3 bytes: 0, 1 mod 4 8009 8010 If the FIRST instruction MIGHT be relaxed, 8011 assume that it will become a 3-byte instruction. 8012 8013 Note again here that LOOP instructions are not bundleable, 8014 and this relaxation only applies to LOOP opcodes. */ 8015 8016 int fill_size = 0; 8017 int first_insn_size; 8018 int loop_insn_size; 8019 addressT pre_opcode_bytes; 8020 int align_power; 8021 fragS *first_insn; 8022 xtensa_opcode opcode; 8023 bfd_boolean is_loop; 8024 8025 assert (fragP->fr_type == rs_machine_dependent); 8026 assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); 8027 8028 /* Find the loop frag. */ 8029 first_insn = next_non_empty_frag (fragP); 8030 /* Now find the first insn frag. */ 8031 first_insn = next_non_empty_frag (first_insn); 8032 8033 is_loop = next_frag_opcode_is_loop (fragP, &opcode); 8034 assert (is_loop); 8035 loop_insn_size = xg_get_single_size (opcode); 8036 8037 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); 8038 pre_opcode_bytes += loop_insn_size; 8039 8040 /* For loops, the alignment depends on the size of the 8041 instruction following the loop, not the LOOP instruction. */ 8042 8043 if (first_insn == NULL) 8044 first_insn_size = xtensa_fetch_width; 8045 else 8046 first_insn_size = get_loop_align_size (frag_format_size (first_insn)); 8047 8048 /* If it was 8, then we'll need a larger alignment for the section. */ 8049 align_power = get_text_align_power (first_insn_size); 8050 record_alignment (now_seg, align_power); 8051 8052 fill_size = get_text_align_fill_size 8053 (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, 8054 fragP->tc_frag_data.is_no_density); 8055 8056 return address + fill_size; 8057 } 8058 8059 8060 /* 3 mechanisms for relaxing an alignment: 8061 8062 Align to a power of 2. 8063 Align so the next fragment's instruction does not cross a word boundary. 8064 Align the current instruction so that if the next instruction 8065 were 3 bytes, it would not cross a word boundary. 8066 8067 We can align with: 8068 8069 zeros - This is easy; always insert zeros. 8070 nops - 3-byte and 2-byte instructions 8071 2 - 2-byte nop 8072 3 - 3-byte nop 8073 4 - 2 2-byte nops 8074 >=5 : 3-byte instruction + fn (n-3) 8075 widening - widen previous instructions. */ 8076 8077 static offsetT 8078 get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) 8079 { 8080 addressT target_address, loop_insn_offset; 8081 int target_size; 8082 xtensa_opcode loop_opcode; 8083 bfd_boolean is_loop; 8084 int align_power; 8085 offsetT opt_diff; 8086 offsetT branch_align; 8087 8088 assert (fragP->fr_type == rs_machine_dependent); 8089 switch (fragP->fr_subtype) 8090 { 8091 case RELAX_DESIRE_ALIGN: 8092 target_size = next_frag_format_size (fragP); 8093 if (target_size == XTENSA_UNDEFINED) 8094 target_size = 3; 8095 align_power = branch_align_power (now_seg); 8096 branch_align = 1 << align_power; 8097 /* Don't count on the section alignment being as large as the target. */ 8098 if (target_size > branch_align) 8099 target_size = branch_align; 8100 opt_diff = get_text_align_fill_size (address, align_power, 8101 target_size, FALSE, FALSE); 8102 8103 *max_diff = (opt_diff + branch_align 8104 - (target_size + ((address + opt_diff) % branch_align))); 8105 assert (*max_diff >= opt_diff); 8106 return opt_diff; 8107 8108 case RELAX_ALIGN_NEXT_OPCODE: 8109 target_size = get_loop_align_size (next_frag_format_size (fragP)); 8110 loop_insn_offset = 0; 8111 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); 8112 assert (is_loop); 8113 8114 /* If the loop has been expanded then the LOOP instruction 8115 could be at an offset from this fragment. */ 8116 if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0] 8117 != RELAX_IMMED) 8118 loop_insn_offset = get_expanded_loop_offset (loop_opcode); 8119 8120 /* In an ideal world, which is what we are shooting for here, 8121 we wouldn't need to use any NOPs immediately prior to the 8122 LOOP instruction. If this approach fails, relax_frag_loop_align 8123 will call get_noop_aligned_address. */ 8124 target_address = 8125 address + loop_insn_offset + xg_get_single_size (loop_opcode); 8126 align_power = get_text_align_power (target_size), 8127 opt_diff = get_text_align_fill_size (target_address, align_power, 8128 target_size, FALSE, FALSE); 8129 8130 *max_diff = xtensa_fetch_width 8131 - ((target_address + opt_diff) % xtensa_fetch_width) 8132 - target_size + opt_diff; 8133 assert (*max_diff >= opt_diff); 8134 return opt_diff; 8135 8136 default: 8137 break; 8138 } 8139 assert (0); 8140 return 0; 8141 } 8142 8143 8144 /* md_relax_frag Hook and Helper Functions. */ 8145 8146 static long relax_frag_loop_align (fragS *, long); 8147 static long relax_frag_for_align (fragS *, long); 8148 static long relax_frag_immed 8149 (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); 8150 8151 8152 /* Return the number of bytes added to this fragment, given that the 8153 input has been stretched already by "stretch". */ 8154 8155 long 8156 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) 8157 { 8158 xtensa_isa isa = xtensa_default_isa; 8159 int unreported = fragP->tc_frag_data.unreported_expansion; 8160 long new_stretch = 0; 8161 char *file_name; 8162 unsigned line; 8163 int lit_size; 8164 static xtensa_insnbuf vbuf = NULL; 8165 int slot, num_slots; 8166 xtensa_format fmt; 8167 8168 as_where (&file_name, &line); 8169 new_logical_line (fragP->fr_file, fragP->fr_line); 8170 8171 fragP->tc_frag_data.unreported_expansion = 0; 8172 8173 switch (fragP->fr_subtype) 8174 { 8175 case RELAX_ALIGN_NEXT_OPCODE: 8176 /* Always convert. */ 8177 if (fragP->tc_frag_data.relax_seen) 8178 new_stretch = relax_frag_loop_align (fragP, stretch); 8179 break; 8180 8181 case RELAX_LOOP_END: 8182 /* Do nothing. */ 8183 break; 8184 8185 case RELAX_LOOP_END_ADD_NOP: 8186 /* Add a NOP and switch to .fill 0. */ 8187 new_stretch = relax_frag_add_nop (fragP); 8188 frag_wane (fragP); 8189 break; 8190 8191 case RELAX_DESIRE_ALIGN: 8192 /* Do nothing. The narrowing before this frag will either align 8193 it or not. */ 8194 break; 8195 8196 case RELAX_LITERAL: 8197 case RELAX_LITERAL_FINAL: 8198 return 0; 8199 8200 case RELAX_LITERAL_NR: 8201 lit_size = 4; 8202 fragP->fr_subtype = RELAX_LITERAL_FINAL; 8203 assert (unreported == lit_size); 8204 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); 8205 fragP->fr_var -= lit_size; 8206 fragP->fr_fix += lit_size; 8207 new_stretch = 4; 8208 break; 8209 8210 case RELAX_SLOTS: 8211 if (vbuf == NULL) 8212 vbuf = xtensa_insnbuf_alloc (isa); 8213 8214 xtensa_insnbuf_from_chars 8215 (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); 8216 fmt = xtensa_format_decode (isa, vbuf); 8217 num_slots = xtensa_format_num_slots (isa, fmt); 8218 8219 for (slot = 0; slot < num_slots; slot++) 8220 { 8221 switch (fragP->tc_frag_data.slot_subtypes[slot]) 8222 { 8223 case RELAX_NARROW: 8224 if (fragP->tc_frag_data.relax_seen) 8225 new_stretch += relax_frag_for_align (fragP, stretch); 8226 break; 8227 8228 case RELAX_IMMED: 8229 case RELAX_IMMED_STEP1: 8230 case RELAX_IMMED_STEP2: 8231 /* Place the immediate. */ 8232 new_stretch += relax_frag_immed 8233 (now_seg, fragP, stretch, 8234 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, 8235 fmt, slot, stretched_p, FALSE); 8236 break; 8237 8238 default: 8239 /* This is OK; see the note in xg_assemble_vliw_tokens. */ 8240 break; 8241 } 8242 } 8243 break; 8244 8245 case RELAX_LITERAL_POOL_BEGIN: 8246 case RELAX_LITERAL_POOL_END: 8247 case RELAX_MAYBE_UNREACHABLE: 8248 case RELAX_MAYBE_DESIRE_ALIGN: 8249 /* No relaxation required. */ 8250 break; 8251 8252 case RELAX_FILL_NOP: 8253 case RELAX_UNREACHABLE: 8254 if (fragP->tc_frag_data.relax_seen) 8255 new_stretch += relax_frag_for_align (fragP, stretch); 8256 break; 8257 8258 default: 8259 as_bad (_("bad relaxation state")); 8260 } 8261 8262 /* Tell gas we need another relaxation pass. */ 8263 if (! fragP->tc_frag_data.relax_seen) 8264 { 8265 fragP->tc_frag_data.relax_seen = TRUE; 8266 *stretched_p = 1; 8267 } 8268 8269 new_logical_line (file_name, line); 8270 return new_stretch; 8271 } 8272 8273 8274 static long 8275 relax_frag_loop_align (fragS *fragP, long stretch) 8276 { 8277 addressT old_address, old_next_address, old_size; 8278 addressT new_address, new_next_address, new_size; 8279 addressT growth; 8280 8281 /* All the frags with relax_frag_for_alignment prior to this one in the 8282 section have been done, hopefully eliminating the need for a NOP here. 8283 But, this will put it in if necessary. */ 8284 8285 /* Calculate the old address of this fragment and the next fragment. */ 8286 old_address = fragP->fr_address - stretch; 8287 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + 8288 fragP->tc_frag_data.text_expansion[0]); 8289 old_size = old_next_address - old_address; 8290 8291 /* Calculate the new address of this fragment and the next fragment. */ 8292 new_address = fragP->fr_address; 8293 new_next_address = 8294 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); 8295 new_size = new_next_address - new_address; 8296 8297 growth = new_size - old_size; 8298 8299 /* Fix up the text_expansion field and return the new growth. */ 8300 fragP->tc_frag_data.text_expansion[0] += growth; 8301 return growth; 8302 } 8303 8304 8305 /* Add a NOP instruction. */ 8306 8307 static long 8308 relax_frag_add_nop (fragS *fragP) 8309 { 8310 char *nop_buf = fragP->fr_literal + fragP->fr_fix; 8311 int length = fragP->tc_frag_data.is_no_density ? 3 : 2; 8312 assemble_nop (length, nop_buf); 8313 fragP->tc_frag_data.is_insn = TRUE; 8314 8315 if (fragP->fr_var < length) 8316 { 8317 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); 8318 return 0; 8319 } 8320 8321 fragP->fr_fix += length; 8322 fragP->fr_var -= length; 8323 return length; 8324 } 8325 8326 8327 static long future_alignment_required (fragS *, long); 8328 8329 static long 8330 relax_frag_for_align (fragS *fragP, long stretch) 8331 { 8332 /* Overview of the relaxation procedure for alignment: 8333 We can widen with NOPs or by widening instructions or by filling 8334 bytes after jump instructions. Find the opportune places and widen 8335 them if necessary. */ 8336 8337 long stretch_me; 8338 long diff; 8339 8340 assert (fragP->fr_subtype == RELAX_FILL_NOP 8341 || fragP->fr_subtype == RELAX_UNREACHABLE 8342 || (fragP->fr_subtype == RELAX_SLOTS 8343 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); 8344 8345 stretch_me = future_alignment_required (fragP, stretch); 8346 diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; 8347 if (diff == 0) 8348 return 0; 8349 8350 if (diff < 0) 8351 { 8352 /* We expanded on a previous pass. Can we shrink now? */ 8353 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; 8354 if (shrink <= stretch && stretch > 0) 8355 { 8356 fragP->tc_frag_data.text_expansion[0] = stretch_me; 8357 return -shrink; 8358 } 8359 return 0; 8360 } 8361 8362 /* Below here, diff > 0. */ 8363 fragP->tc_frag_data.text_expansion[0] = stretch_me; 8364 8365 return diff; 8366 } 8367 8368 8369 /* Return the address of the next frag that should be aligned. 8370 8371 By "address" we mean the address it _would_ be at if there 8372 is no action taken to align it between here and the target frag. 8373 In other words, if no narrows and no fill nops are used between 8374 here and the frag to align, _even_if_ some of the frags we use 8375 to align targets have already expanded on a previous relaxation 8376 pass. 8377 8378 Also, count each frag that may be used to help align the target. 8379 8380 Return 0 if there are no frags left in the chain that need to be 8381 aligned. */ 8382 8383 static addressT 8384 find_address_of_next_align_frag (fragS **fragPP, 8385 int *wide_nops, 8386 int *narrow_nops, 8387 int *widens, 8388 bfd_boolean *paddable) 8389 { 8390 fragS *fragP = *fragPP; 8391 addressT address = fragP->fr_address; 8392 8393 /* Do not reset the counts to 0. */ 8394 8395 while (fragP) 8396 { 8397 /* Limit this to a small search. */ 8398 if (*widens >= (int) xtensa_fetch_width) 8399 { 8400 *fragPP = fragP; 8401 return 0; 8402 } 8403 address += fragP->fr_fix; 8404 8405 if (fragP->fr_type == rs_fill) 8406 address += fragP->fr_offset * fragP->fr_var; 8407 else if (fragP->fr_type == rs_machine_dependent) 8408 { 8409 switch (fragP->fr_subtype) 8410 { 8411 case RELAX_UNREACHABLE: 8412 *paddable = TRUE; 8413 break; 8414 8415 case RELAX_FILL_NOP: 8416 (*wide_nops)++; 8417 if (!fragP->tc_frag_data.is_no_density) 8418 (*narrow_nops)++; 8419 break; 8420 8421 case RELAX_SLOTS: 8422 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 8423 { 8424 (*widens)++; 8425 break; 8426 } 8427 address += total_frag_text_expansion (fragP);; 8428 break; 8429 8430 case RELAX_IMMED: 8431 address += fragP->tc_frag_data.text_expansion[0]; 8432 break; 8433 8434 case RELAX_ALIGN_NEXT_OPCODE: 8435 case RELAX_DESIRE_ALIGN: 8436 *fragPP = fragP; 8437 return address; 8438 8439 case RELAX_MAYBE_UNREACHABLE: 8440 case RELAX_MAYBE_DESIRE_ALIGN: 8441 /* Do nothing. */ 8442 break; 8443 8444 default: 8445 /* Just punt if we don't know the type. */ 8446 *fragPP = fragP; 8447 return 0; 8448 } 8449 } 8450 else 8451 { 8452 /* Just punt if we don't know the type. */ 8453 *fragPP = fragP; 8454 return 0; 8455 } 8456 fragP = fragP->fr_next; 8457 } 8458 8459 *fragPP = fragP; 8460 return 0; 8461 } 8462 8463 8464 static long bytes_to_stretch (fragS *, int, int, int, int); 8465 8466 static long 8467 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) 8468 { 8469 fragS *this_frag = fragP; 8470 long address; 8471 int num_widens = 0; 8472 int wide_nops = 0; 8473 int narrow_nops = 0; 8474 bfd_boolean paddable = FALSE; 8475 offsetT local_opt_diff; 8476 offsetT opt_diff; 8477 offsetT max_diff; 8478 int stretch_amount = 0; 8479 int local_stretch_amount; 8480 int global_stretch_amount; 8481 8482 address = find_address_of_next_align_frag 8483 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); 8484 8485 if (!address) 8486 { 8487 if (this_frag->tc_frag_data.is_aligning_branch) 8488 this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; 8489 else 8490 frag_wane (this_frag); 8491 } 8492 else 8493 { 8494 local_opt_diff = get_aligned_diff (fragP, address, &max_diff); 8495 opt_diff = local_opt_diff; 8496 assert (opt_diff >= 0); 8497 assert (max_diff >= opt_diff); 8498 if (max_diff == 0) 8499 return 0; 8500 8501 if (fragP) 8502 fragP = fragP->fr_next; 8503 8504 while (fragP && opt_diff < max_diff && address) 8505 { 8506 /* We only use these to determine if we can exit early 8507 because there will be plenty of ways to align future 8508 align frags. */ 8509 int glob_widens = 0; 8510 int dnn = 0; 8511 int dw = 0; 8512 bfd_boolean glob_pad = 0; 8513 address = find_address_of_next_align_frag 8514 (&fragP, &glob_widens, &dnn, &dw, &glob_pad); 8515 /* If there is a padable portion, then skip. */ 8516 if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) 8517 address = 0; 8518 8519 if (address) 8520 { 8521 offsetT next_m_diff; 8522 offsetT next_o_diff; 8523 8524 /* Downrange frags haven't had stretch added to them yet. */ 8525 address += stretch; 8526 8527 /* The address also includes any text expansion from this 8528 frag in a previous pass, but we don't want that. */ 8529 address -= this_frag->tc_frag_data.text_expansion[0]; 8530 8531 /* Assume we are going to move at least opt_diff. In 8532 reality, we might not be able to, but assuming that 8533 we will helps catch cases where moving opt_diff pushes 8534 the next target from aligned to unaligned. */ 8535 address += opt_diff; 8536 8537 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); 8538 8539 /* Now cleanup for the adjustments to address. */ 8540 next_o_diff += opt_diff; 8541 next_m_diff += opt_diff; 8542 if (next_o_diff <= max_diff && next_o_diff > opt_diff) 8543 opt_diff = next_o_diff; 8544 if (next_m_diff < max_diff) 8545 max_diff = next_m_diff; 8546 fragP = fragP->fr_next; 8547 } 8548 } 8549 8550 /* If there are enough wideners in between, do it. */ 8551 if (paddable) 8552 { 8553 if (this_frag->fr_subtype == RELAX_UNREACHABLE) 8554 { 8555 assert (opt_diff <= UNREACHABLE_MAX_WIDTH); 8556 return opt_diff; 8557 } 8558 return 0; 8559 } 8560 local_stretch_amount 8561 = bytes_to_stretch (this_frag, wide_nops, narrow_nops, 8562 num_widens, local_opt_diff); 8563 global_stretch_amount 8564 = bytes_to_stretch (this_frag, wide_nops, narrow_nops, 8565 num_widens, opt_diff); 8566 /* If the condition below is true, then the frag couldn't 8567 stretch the correct amount for the global case, so we just 8568 optimize locally. We'll rely on the subsequent frags to get 8569 the correct alignment in the global case. */ 8570 if (global_stretch_amount < local_stretch_amount) 8571 stretch_amount = local_stretch_amount; 8572 else 8573 stretch_amount = global_stretch_amount; 8574 8575 if (this_frag->fr_subtype == RELAX_SLOTS 8576 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 8577 assert (stretch_amount <= 1); 8578 else if (this_frag->fr_subtype == RELAX_FILL_NOP) 8579 { 8580 if (this_frag->tc_frag_data.is_no_density) 8581 assert (stretch_amount == 3 || stretch_amount == 0); 8582 else 8583 assert (stretch_amount <= 3); 8584 } 8585 } 8586 return stretch_amount; 8587 } 8588 8589 8590 /* The idea: widen everything you can to get a target or loop aligned, 8591 then start using NOPs. 8592 8593 When we must have a NOP, here is a table of how we decide 8594 (so you don't have to fight through the control flow below): 8595 8596 wide_nops = the number of wide NOPs available for aligning 8597 narrow_nops = the number of narrow NOPs available for aligning 8598 (a subset of wide_nops) 8599 widens = the number of narrow instructions that should be widened 8600 8601 Desired wide narrow 8602 Diff nop nop widens 8603 1 0 0 1 8604 2 0 1 0 8605 3a 1 0 0 8606 b 0 1 1 (case 3a makes this case unnecessary) 8607 4a 1 0 1 8608 b 0 2 0 8609 c 0 1 2 (case 4a makes this case unnecessary) 8610 5a 1 0 2 8611 b 1 1 0 8612 c 0 2 1 (case 5b makes this case unnecessary) 8613 6a 2 0 0 8614 b 1 0 3 8615 c 0 1 4 (case 6b makes this case unneccesary) 8616 d 1 1 1 (case 6a makes this case unnecessary) 8617 e 0 2 2 (case 6a makes this case unnecessary) 8618 f 0 3 0 (case 6a makes this case unnecessary) 8619 7a 1 0 4 8620 b 2 0 1 8621 c 1 1 2 (case 7b makes this case unnecessary) 8622 d 0 1 5 (case 7a makes this case unnecessary) 8623 e 0 2 3 (case 7b makes this case unnecessary) 8624 f 0 3 1 (case 7b makes this case unnecessary) 8625 g 1 2 1 (case 7b makes this case unnecessary) 8626 */ 8627 8628 static long 8629 bytes_to_stretch (fragS *this_frag, 8630 int wide_nops, 8631 int narrow_nops, 8632 int num_widens, 8633 int desired_diff) 8634 { 8635 int bytes_short = desired_diff - num_widens; 8636 8637 assert (desired_diff >= 0 && desired_diff < 8); 8638 if (desired_diff == 0) 8639 return 0; 8640 8641 assert (wide_nops > 0 || num_widens > 0); 8642 8643 /* Always prefer widening to NOP-filling. */ 8644 if (bytes_short < 0) 8645 { 8646 /* There are enough RELAX_NARROW frags after this one 8647 to align the target without widening this frag in any way. */ 8648 return 0; 8649 } 8650 8651 if (bytes_short == 0) 8652 { 8653 /* Widen every narrow between here and the align target 8654 and the align target will be properly aligned. */ 8655 if (this_frag->fr_subtype == RELAX_FILL_NOP) 8656 return 0; 8657 else 8658 return 1; 8659 } 8660 8661 /* From here we will need at least one NOP to get an alignment. 8662 However, we may not be able to align at all, in which case, 8663 don't widen. */ 8664 if (this_frag->fr_subtype == RELAX_FILL_NOP) 8665 { 8666 switch (desired_diff) 8667 { 8668 case 1: 8669 return 0; 8670 case 2: 8671 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) 8672 return 2; /* case 2 */ 8673 return 0; 8674 case 3: 8675 if (wide_nops > 1) 8676 return 0; 8677 else 8678 return 3; /* case 3a */ 8679 case 4: 8680 if (num_widens >= 1 && wide_nops == 1) 8681 return 3; /* case 4a */ 8682 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) 8683 return 2; /* case 4b */ 8684 return 0; 8685 case 5: 8686 if (num_widens >= 2 && wide_nops == 1) 8687 return 3; /* case 5a */ 8688 /* We will need two nops. Are there enough nops 8689 between here and the align target? */ 8690 if (wide_nops < 2 || narrow_nops == 0) 8691 return 0; 8692 /* Are there other nops closer that can serve instead? */ 8693 if (wide_nops > 2 && narrow_nops > 1) 8694 return 0; 8695 /* Take the density one first, because there might not be 8696 another density one available. */ 8697 if (!this_frag->tc_frag_data.is_no_density) 8698 return 2; /* case 5b narrow */ 8699 else 8700 return 3; /* case 5b wide */ 8701 return 0; 8702 case 6: 8703 if (wide_nops == 2) 8704 return 3; /* case 6a */ 8705 else if (num_widens >= 3 && wide_nops == 1) 8706 return 3; /* case 6b */ 8707 return 0; 8708 case 7: 8709 if (wide_nops == 1 && num_widens >= 4) 8710 return 3; /* case 7a */ 8711 else if (wide_nops == 2 && num_widens >= 1) 8712 return 3; /* case 7b */ 8713 return 0; 8714 default: 8715 assert (0); 8716 } 8717 } 8718 else 8719 { 8720 /* We will need a NOP no matter what, but should we widen 8721 this instruction to help? 8722 8723 This is a RELAX_NARROW frag. */ 8724 switch (desired_diff) 8725 { 8726 case 1: 8727 assert (0); 8728 return 0; 8729 case 2: 8730 case 3: 8731 return 0; 8732 case 4: 8733 if (wide_nops >= 1 && num_widens == 1) 8734 return 1; /* case 4a */ 8735 return 0; 8736 case 5: 8737 if (wide_nops >= 1 && num_widens == 2) 8738 return 1; /* case 5a */ 8739 return 0; 8740 case 6: 8741 if (wide_nops >= 2) 8742 return 0; /* case 6a */ 8743 else if (wide_nops >= 1 && num_widens == 3) 8744 return 1; /* case 6b */ 8745 return 0; 8746 case 7: 8747 if (wide_nops >= 1 && num_widens == 4) 8748 return 1; /* case 7a */ 8749 else if (wide_nops >= 2 && num_widens == 1) 8750 return 1; /* case 7b */ 8751 return 0; 8752 default: 8753 assert (0); 8754 return 0; 8755 } 8756 } 8757 assert (0); 8758 return 0; 8759 } 8760 8761 8762 static long 8763 relax_frag_immed (segT segP, 8764 fragS *fragP, 8765 long stretch, 8766 int min_steps, 8767 xtensa_format fmt, 8768 int slot, 8769 int *stretched_p, 8770 bfd_boolean estimate_only) 8771 { 8772 TInsn tinsn; 8773 int old_size; 8774 bfd_boolean negatable_branch = FALSE; 8775 bfd_boolean branch_jmp_to_next = FALSE; 8776 bfd_boolean wide_insn = FALSE; 8777 xtensa_isa isa = xtensa_default_isa; 8778 IStack istack; 8779 offsetT frag_offset; 8780 int num_steps; 8781 fragS *lit_fragP; 8782 int num_text_bytes, num_literal_bytes; 8783 int literal_diff, total_text_diff, this_text_diff, first; 8784 8785 assert (fragP->fr_opcode != NULL); 8786 8787 xg_clear_vinsn (&cur_vinsn); 8788 vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); 8789 if (cur_vinsn.num_slots > 1) 8790 wide_insn = TRUE; 8791 8792 tinsn = cur_vinsn.slots[slot]; 8793 tinsn_immed_from_frag (&tinsn, fragP, slot); 8794 8795 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode)) 8796 return 0; 8797 8798 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) 8799 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); 8800 8801 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); 8802 8803 old_size = xtensa_format_length (isa, fmt); 8804 8805 /* Special case: replace a branch to the next instruction with a NOP. 8806 This is required to work around a hardware bug in T1040.0 and also 8807 serves as an optimization. */ 8808 8809 if (branch_jmp_to_next 8810 && ((old_size == 2) || (old_size == 3)) 8811 && !next_frag_is_loop_target (fragP)) 8812 return 0; 8813 8814 /* Here is the fun stuff: Get the immediate field from this 8815 instruction. If it fits, we are done. If not, find the next 8816 instruction sequence that fits. */ 8817 8818 frag_offset = fragP->fr_opcode - fragP->fr_literal; 8819 istack_init (&istack); 8820 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, 8821 min_steps, stretch); 8822 if (num_steps < min_steps) 8823 { 8824 as_fatal (_("internal error: relaxation failed")); 8825 return 0; 8826 } 8827 8828 if (num_steps > RELAX_IMMED_MAXSTEPS) 8829 { 8830 as_fatal (_("internal error: relaxation requires too many steps")); 8831 return 0; 8832 } 8833 8834 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; 8835 8836 /* Figure out the number of bytes needed. */ 8837 lit_fragP = 0; 8838 num_literal_bytes = get_num_stack_literal_bytes (&istack); 8839 literal_diff = 8840 num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; 8841 first = 0; 8842 while (istack.insn[first].opcode == XTENSA_UNDEFINED) 8843 first++; 8844 num_text_bytes = get_num_stack_text_bytes (&istack); 8845 if (wide_insn) 8846 { 8847 num_text_bytes += old_size; 8848 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) 8849 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); 8850 } 8851 total_text_diff = num_text_bytes - old_size; 8852 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; 8853 8854 /* It MUST get larger. If not, we could get an infinite loop. */ 8855 assert (num_text_bytes >= 0); 8856 assert (literal_diff >= 0); 8857 assert (total_text_diff >= 0); 8858 8859 fragP->tc_frag_data.text_expansion[slot] = total_text_diff; 8860 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; 8861 assert (fragP->tc_frag_data.text_expansion[slot] >= 0); 8862 assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); 8863 8864 /* Find the associated expandable literal for this. */ 8865 if (literal_diff != 0) 8866 { 8867 lit_fragP = fragP->tc_frag_data.literal_frags[slot]; 8868 if (lit_fragP) 8869 { 8870 assert (literal_diff == 4); 8871 lit_fragP->tc_frag_data.unreported_expansion += literal_diff; 8872 8873 /* We expect that the literal section state has NOT been 8874 modified yet. */ 8875 assert (lit_fragP->fr_type == rs_machine_dependent 8876 && lit_fragP->fr_subtype == RELAX_LITERAL); 8877 lit_fragP->fr_subtype = RELAX_LITERAL_NR; 8878 8879 /* We need to mark this section for another iteration 8880 of relaxation. */ 8881 (*stretched_p)++; 8882 } 8883 } 8884 8885 if (negatable_branch && istack.ninsn > 1) 8886 update_next_frag_state (fragP); 8887 8888 return this_text_diff; 8889 } 8890 8891 8892 /* md_convert_frag Hook and Helper Functions. */ 8893 8894 static void convert_frag_align_next_opcode (fragS *); 8895 static void convert_frag_narrow (segT, fragS *, xtensa_format, int); 8896 static void convert_frag_fill_nop (fragS *); 8897 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); 8898 8899 void 8900 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) 8901 { 8902 static xtensa_insnbuf vbuf = NULL; 8903 xtensa_isa isa = xtensa_default_isa; 8904 int slot; 8905 int num_slots; 8906 xtensa_format fmt; 8907 char *file_name; 8908 unsigned line; 8909 8910 as_where (&file_name, &line); 8911 new_logical_line (fragp->fr_file, fragp->fr_line); 8912 8913 switch (fragp->fr_subtype) 8914 { 8915 case RELAX_ALIGN_NEXT_OPCODE: 8916 /* Always convert. */ 8917 convert_frag_align_next_opcode (fragp); 8918 break; 8919 8920 case RELAX_DESIRE_ALIGN: 8921 /* Do nothing. If not aligned already, too bad. */ 8922 break; 8923 8924 case RELAX_LITERAL: 8925 case RELAX_LITERAL_FINAL: 8926 break; 8927 8928 case RELAX_SLOTS: 8929 if (vbuf == NULL) 8930 vbuf = xtensa_insnbuf_alloc (isa); 8931 8932 xtensa_insnbuf_from_chars 8933 (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); 8934 fmt = xtensa_format_decode (isa, vbuf); 8935 num_slots = xtensa_format_num_slots (isa, fmt); 8936 8937 for (slot = 0; slot < num_slots; slot++) 8938 { 8939 switch (fragp->tc_frag_data.slot_subtypes[slot]) 8940 { 8941 case RELAX_NARROW: 8942 convert_frag_narrow (sec, fragp, fmt, slot); 8943 break; 8944 8945 case RELAX_IMMED: 8946 case RELAX_IMMED_STEP1: 8947 case RELAX_IMMED_STEP2: 8948 /* Place the immediate. */ 8949 convert_frag_immed 8950 (sec, fragp, 8951 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, 8952 fmt, slot); 8953 break; 8954 8955 default: 8956 /* This is OK because some slots could have 8957 relaxations and others have none. */ 8958 break; 8959 } 8960 } 8961 break; 8962 8963 case RELAX_UNREACHABLE: 8964 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); 8965 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; 8966 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; 8967 frag_wane (fragp); 8968 break; 8969 8970 case RELAX_MAYBE_UNREACHABLE: 8971 case RELAX_MAYBE_DESIRE_ALIGN: 8972 frag_wane (fragp); 8973 break; 8974 8975 case RELAX_FILL_NOP: 8976 convert_frag_fill_nop (fragp); 8977 break; 8978 8979 case RELAX_LITERAL_NR: 8980 if (use_literal_section) 8981 { 8982 /* This should have been handled during relaxation. When 8983 relaxing a code segment, literals sometimes need to be 8984 added to the corresponding literal segment. If that 8985 literal segment has already been relaxed, then we end up 8986 in this situation. Marking the literal segments as data 8987 would make this happen less often (since GAS always relaxes 8988 code before data), but we could still get into trouble if 8989 there are instructions in a segment that is not marked as 8990 containing code. Until we can implement a better solution, 8991 cheat and adjust the addresses of all the following frags. 8992 This could break subsequent alignments, but the linker's 8993 literal coalescing will do that anyway. */ 8994 8995 fragS *f; 8996 fragp->fr_subtype = RELAX_LITERAL_FINAL; 8997 assert (fragp->tc_frag_data.unreported_expansion == 4); 8998 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); 8999 fragp->fr_var -= 4; 9000 fragp->fr_fix += 4; 9001 for (f = fragp->fr_next; f; f = f->fr_next) 9002 f->fr_address += 4; 9003 } 9004 else 9005 as_bad (_("invalid relaxation fragment result")); 9006 break; 9007 } 9008 9009 fragp->fr_var = 0; 9010 new_logical_line (file_name, line); 9011 } 9012 9013 9014 static void 9015 convert_frag_align_next_opcode (fragS *fragp) 9016 { 9017 char *nop_buf; /* Location for Writing. */ 9018 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; 9019 addressT aligned_address; 9020 offsetT fill_size; 9021 int nop, nop_count; 9022 9023 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + 9024 fragp->fr_fix); 9025 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); 9026 nop_count = get_text_align_nop_count (fill_size, use_no_density); 9027 nop_buf = fragp->fr_literal + fragp->fr_fix; 9028 9029 for (nop = 0; nop < nop_count; nop++) 9030 { 9031 int nop_size; 9032 nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); 9033 9034 assemble_nop (nop_size, nop_buf); 9035 nop_buf += nop_size; 9036 } 9037 9038 fragp->fr_fix += fill_size; 9039 fragp->fr_var -= fill_size; 9040 } 9041 9042 9043 static void 9044 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) 9045 { 9046 TInsn tinsn, single_target; 9047 int size, old_size, diff; 9048 offsetT frag_offset; 9049 9050 assert (slot == 0); 9051 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); 9052 9053 if (fragP->tc_frag_data.is_aligning_branch == 1) 9054 { 9055 assert (fragP->tc_frag_data.text_expansion[0] == 1 9056 || fragP->tc_frag_data.text_expansion[0] == 0); 9057 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], 9058 fmt, slot); 9059 return; 9060 } 9061 9062 if (fragP->tc_frag_data.text_expansion[0] == 0) 9063 { 9064 /* No conversion. */ 9065 fragP->fr_var = 0; 9066 return; 9067 } 9068 9069 assert (fragP->fr_opcode != NULL); 9070 9071 /* Frags in this relaxation state should only contain 9072 single instruction bundles. */ 9073 tinsn_immed_from_frag (&tinsn, fragP, 0); 9074 9075 /* Just convert it to a wide form.... */ 9076 size = 0; 9077 old_size = xg_get_single_size (tinsn.opcode); 9078 9079 tinsn_init (&single_target); 9080 frag_offset = fragP->fr_opcode - fragP->fr_literal; 9081 9082 if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) 9083 { 9084 as_bad (_("unable to widen instruction")); 9085 return; 9086 } 9087 9088 size = xg_get_single_size (single_target.opcode); 9089 xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, 9090 frag_offset, TRUE); 9091 9092 diff = size - old_size; 9093 assert (diff >= 0); 9094 assert (diff <= fragP->fr_var); 9095 fragP->fr_var -= diff; 9096 fragP->fr_fix += diff; 9097 9098 /* clean it up */ 9099 fragP->fr_var = 0; 9100 } 9101 9102 9103 static void 9104 convert_frag_fill_nop (fragS *fragP) 9105 { 9106 char *loc = &fragP->fr_literal[fragP->fr_fix]; 9107 int size = fragP->tc_frag_data.text_expansion[0]; 9108 assert ((unsigned) size == (fragP->fr_next->fr_address 9109 - fragP->fr_address - fragP->fr_fix)); 9110 if (size == 0) 9111 { 9112 /* No conversion. */ 9113 fragP->fr_var = 0; 9114 return; 9115 } 9116 assemble_nop (size, loc); 9117 fragP->tc_frag_data.is_insn = TRUE; 9118 fragP->fr_var -= size; 9119 fragP->fr_fix += size; 9120 frag_wane (fragP); 9121 } 9122 9123 9124 static fixS *fix_new_exp_in_seg 9125 (segT, subsegT, fragS *, int, int, expressionS *, int, 9126 bfd_reloc_code_real_type); 9127 static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); 9128 9129 static void 9130 convert_frag_immed (segT segP, 9131 fragS *fragP, 9132 int min_steps, 9133 xtensa_format fmt, 9134 int slot) 9135 { 9136 char *immed_instr = fragP->fr_opcode; 9137 TInsn orig_tinsn; 9138 bfd_boolean expanded = FALSE; 9139 bfd_boolean branch_jmp_to_next = FALSE; 9140 char *fr_opcode = fragP->fr_opcode; 9141 xtensa_isa isa = xtensa_default_isa; 9142 bfd_boolean wide_insn = FALSE; 9143 int bytes; 9144 bfd_boolean is_loop; 9145 9146 assert (fr_opcode != NULL); 9147 9148 xg_clear_vinsn (&cur_vinsn); 9149 9150 vinsn_from_chars (&cur_vinsn, fr_opcode); 9151 if (cur_vinsn.num_slots > 1) 9152 wide_insn = TRUE; 9153 9154 orig_tinsn = cur_vinsn.slots[slot]; 9155 tinsn_immed_from_frag (&orig_tinsn, fragP, slot); 9156 9157 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; 9158 9159 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) 9160 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); 9161 9162 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) 9163 { 9164 /* Conversion just inserts a NOP and marks the fix as completed. */ 9165 bytes = xtensa_format_length (isa, fmt); 9166 if (bytes >= 4) 9167 { 9168 cur_vinsn.slots[slot].opcode = 9169 xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); 9170 cur_vinsn.slots[slot].ntok = 0; 9171 } 9172 else 9173 { 9174 bytes += fragP->tc_frag_data.text_expansion[0]; 9175 assert (bytes == 2 || bytes == 3); 9176 build_nop (&cur_vinsn.slots[0], bytes); 9177 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; 9178 } 9179 vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); 9180 xtensa_insnbuf_to_chars 9181 (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); 9182 fragP->fr_var = 0; 9183 } 9184 else 9185 { 9186 /* Here is the fun stuff: Get the immediate field from this 9187 instruction. If it fits, we're done. If not, find the next 9188 instruction sequence that fits. */ 9189 9190 IStack istack; 9191 int i; 9192 symbolS *lit_sym = NULL; 9193 int total_size = 0; 9194 int target_offset = 0; 9195 int old_size; 9196 int diff; 9197 symbolS *gen_label = NULL; 9198 offsetT frag_offset; 9199 bfd_boolean first = TRUE; 9200 bfd_boolean last_is_jump; 9201 9202 /* It does not fit. Find something that does and 9203 convert immediately. */ 9204 frag_offset = fr_opcode - fragP->fr_literal; 9205 istack_init (&istack); 9206 xg_assembly_relax (&istack, &orig_tinsn, 9207 segP, fragP, frag_offset, min_steps, 0); 9208 9209 old_size = xtensa_format_length (isa, fmt); 9210 9211 /* Assemble this right inline. */ 9212 9213 /* First, create the mapping from a label name to the REAL label. */ 9214 target_offset = 0; 9215 for (i = 0; i < istack.ninsn; i++) 9216 { 9217 TInsn *tinsn = &istack.insn[i]; 9218 fragS *lit_frag; 9219 9220 switch (tinsn->insn_type) 9221 { 9222 case ITYPE_LITERAL: 9223 if (lit_sym != NULL) 9224 as_bad (_("multiple literals in expansion")); 9225 /* First find the appropriate space in the literal pool. */ 9226 lit_frag = fragP->tc_frag_data.literal_frags[slot]; 9227 if (lit_frag == NULL) 9228 as_bad (_("no registered fragment for literal")); 9229 if (tinsn->ntok != 1) 9230 as_bad (_("number of literal tokens != 1")); 9231 9232 /* Set the literal symbol and add a fixup. */ 9233 lit_sym = lit_frag->fr_symbol; 9234 break; 9235 9236 case ITYPE_LABEL: 9237 if (align_targets && !is_loop) 9238 { 9239 fragS *unreach = fragP->fr_next; 9240 while (!(unreach->fr_type == rs_machine_dependent 9241 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE 9242 || unreach->fr_subtype == RELAX_UNREACHABLE))) 9243 { 9244 unreach = unreach->fr_next; 9245 } 9246 9247 assert (unreach->fr_type == rs_machine_dependent 9248 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE 9249 || unreach->fr_subtype == RELAX_UNREACHABLE)); 9250 9251 target_offset += unreach->tc_frag_data.text_expansion[0]; 9252 } 9253 assert (gen_label == NULL); 9254 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, 9255 fr_opcode - fragP->fr_literal 9256 + target_offset, fragP); 9257 break; 9258 9259 case ITYPE_INSN: 9260 if (first && wide_insn) 9261 { 9262 target_offset += xtensa_format_length (isa, fmt); 9263 first = FALSE; 9264 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 9265 target_offset += xg_get_single_size (tinsn->opcode); 9266 } 9267 else 9268 target_offset += xg_get_single_size (tinsn->opcode); 9269 break; 9270 } 9271 } 9272 9273 total_size = 0; 9274 first = TRUE; 9275 last_is_jump = FALSE; 9276 for (i = 0; i < istack.ninsn; i++) 9277 { 9278 TInsn *tinsn = &istack.insn[i]; 9279 fragS *lit_frag; 9280 int size; 9281 segT target_seg; 9282 bfd_reloc_code_real_type reloc_type; 9283 9284 switch (tinsn->insn_type) 9285 { 9286 case ITYPE_LITERAL: 9287 lit_frag = fragP->tc_frag_data.literal_frags[slot]; 9288 /* Already checked. */ 9289 assert (lit_frag != NULL); 9290 assert (lit_sym != NULL); 9291 assert (tinsn->ntok == 1); 9292 /* Add a fixup. */ 9293 target_seg = S_GET_SEGMENT (lit_sym); 9294 assert (target_seg); 9295 if (tinsn->tok[0].X_op == O_pltrel) 9296 reloc_type = BFD_RELOC_XTENSA_PLT; 9297 else 9298 reloc_type = BFD_RELOC_32; 9299 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, 9300 &tinsn->tok[0], FALSE, reloc_type); 9301 break; 9302 9303 case ITYPE_LABEL: 9304 break; 9305 9306 case ITYPE_INSN: 9307 xg_resolve_labels (tinsn, gen_label); 9308 xg_resolve_literals (tinsn, lit_sym); 9309 if (wide_insn && first) 9310 { 9311 first = FALSE; 9312 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 9313 { 9314 cur_vinsn.slots[slot] = *tinsn; 9315 } 9316 else 9317 { 9318 cur_vinsn.slots[slot].opcode = 9319 xtensa_format_slot_nop_opcode (isa, fmt, slot); 9320 cur_vinsn.slots[slot].ntok = 0; 9321 } 9322 vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); 9323 xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, 9324 (unsigned char *) immed_instr, 0); 9325 fragP->tc_frag_data.is_insn = TRUE; 9326 size = xtensa_format_length (isa, fmt); 9327 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 9328 { 9329 xg_emit_insn_to_buf 9330 (tinsn, immed_instr + size, fragP, 9331 immed_instr - fragP->fr_literal + size, TRUE); 9332 size += xg_get_single_size (tinsn->opcode); 9333 } 9334 } 9335 else 9336 { 9337 size = xg_get_single_size (tinsn->opcode); 9338 xg_emit_insn_to_buf (tinsn, immed_instr, fragP, 9339 immed_instr - fragP->fr_literal, TRUE); 9340 } 9341 immed_instr += size; 9342 total_size += size; 9343 break; 9344 } 9345 } 9346 9347 diff = total_size - old_size; 9348 assert (diff >= 0); 9349 if (diff != 0) 9350 expanded = TRUE; 9351 assert (diff <= fragP->fr_var); 9352 fragP->fr_var -= diff; 9353 fragP->fr_fix += diff; 9354 } 9355 9356 /* Check for undefined immediates in LOOP instructions. */ 9357 if (is_loop) 9358 { 9359 symbolS *sym; 9360 sym = orig_tinsn.tok[1].X_add_symbol; 9361 if (sym != NULL && !S_IS_DEFINED (sym)) 9362 { 9363 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); 9364 return; 9365 } 9366 sym = orig_tinsn.tok[1].X_op_symbol; 9367 if (sym != NULL && !S_IS_DEFINED (sym)) 9368 { 9369 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); 9370 return; 9371 } 9372 } 9373 9374 if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) 9375 convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); 9376 9377 if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) 9378 { 9379 /* Add an expansion note on the expanded instruction. */ 9380 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, 9381 &orig_tinsn.tok[0], TRUE, 9382 BFD_RELOC_XTENSA_ASM_EXPAND); 9383 } 9384 } 9385 9386 9387 /* Add a new fix expression into the desired segment. We have to 9388 switch to that segment to do this. */ 9389 9390 static fixS * 9391 fix_new_exp_in_seg (segT new_seg, 9392 subsegT new_subseg, 9393 fragS *frag, 9394 int where, 9395 int size, 9396 expressionS *exp, 9397 int pcrel, 9398 bfd_reloc_code_real_type r_type) 9399 { 9400 fixS *new_fix; 9401 segT seg = now_seg; 9402 subsegT subseg = now_subseg; 9403 9404 assert (new_seg != 0); 9405 subseg_set (new_seg, new_subseg); 9406 9407 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); 9408 subseg_set (seg, subseg); 9409 return new_fix; 9410 } 9411 9412 9413 /* Relax a loop instruction so that it can span loop >256 bytes. 9414 9415 loop as, .L1 9416 .L0: 9417 rsr as, LEND 9418 wsr as, LBEG 9419 addi as, as, lo8 (label-.L1) 9420 addmi as, as, mid8 (label-.L1) 9421 wsr as, LEND 9422 isync 9423 rsr as, LCOUNT 9424 addi as, as, 1 9425 .L1: 9426 <<body>> 9427 label: 9428 */ 9429 9430 static void 9431 convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) 9432 { 9433 TInsn loop_insn; 9434 TInsn addi_insn; 9435 TInsn addmi_insn; 9436 unsigned long target; 9437 static xtensa_insnbuf insnbuf = NULL; 9438 unsigned int loop_length, loop_length_hi, loop_length_lo; 9439 xtensa_isa isa = xtensa_default_isa; 9440 addressT loop_offset; 9441 addressT addi_offset = 9; 9442 addressT addmi_offset = 12; 9443 fragS *next_fragP; 9444 int target_count; 9445 9446 if (!insnbuf) 9447 insnbuf = xtensa_insnbuf_alloc (isa); 9448 9449 /* Get the loop offset. */ 9450 loop_offset = get_expanded_loop_offset (tinsn->opcode); 9451 9452 /* Validate that there really is a LOOP at the loop_offset. Because 9453 loops are not bundleable, we can assume that the instruction will be 9454 in slot 0. */ 9455 tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); 9456 tinsn_immed_from_frag (&loop_insn, fragP, 0); 9457 9458 assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); 9459 addi_offset += loop_offset; 9460 addmi_offset += loop_offset; 9461 9462 assert (tinsn->ntok == 2); 9463 if (tinsn->tok[1].X_op == O_constant) 9464 target = tinsn->tok[1].X_add_number; 9465 else if (tinsn->tok[1].X_op == O_symbol) 9466 { 9467 /* Find the fragment. */ 9468 symbolS *sym = tinsn->tok[1].X_add_symbol; 9469 assert (S_GET_SEGMENT (sym) == segP 9470 || S_GET_SEGMENT (sym) == absolute_section); 9471 target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); 9472 } 9473 else 9474 { 9475 as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); 9476 target = 0; 9477 } 9478 9479 know (symbolP); 9480 know (symbolP->sy_frag); 9481 know (!(S_GET_SEGMENT (symbolP) == absolute_section) 9482 || symbol_get_frag (symbolP) == &zero_address_frag); 9483 9484 loop_length = target - (fragP->fr_address + fragP->fr_fix); 9485 loop_length_hi = loop_length & ~0x0ff; 9486 loop_length_lo = loop_length & 0x0ff; 9487 if (loop_length_lo >= 128) 9488 { 9489 loop_length_lo -= 256; 9490 loop_length_hi += 256; 9491 } 9492 9493 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most 9494 32512. If the loop is larger than that, then we just fail. */ 9495 if (loop_length_hi > 32512) 9496 as_bad_where (fragP->fr_file, fragP->fr_line, 9497 _("loop too long for LOOP instruction")); 9498 9499 tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); 9500 assert (addi_insn.opcode == xtensa_addi_opcode); 9501 9502 tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); 9503 assert (addmi_insn.opcode == xtensa_addmi_opcode); 9504 9505 set_expr_const (&addi_insn.tok[2], loop_length_lo); 9506 tinsn_to_insnbuf (&addi_insn, insnbuf); 9507 9508 fragP->tc_frag_data.is_insn = TRUE; 9509 xtensa_insnbuf_to_chars 9510 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); 9511 9512 set_expr_const (&addmi_insn.tok[2], loop_length_hi); 9513 tinsn_to_insnbuf (&addmi_insn, insnbuf); 9514 xtensa_insnbuf_to_chars 9515 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); 9516 9517 /* Walk through all of the frags from here to the loop end 9518 and mark them as no_transform to keep them from being modified 9519 by the linker. If we ever have a relocation for the 9520 addi/addmi of the difference of two symbols we can remove this. */ 9521 9522 target_count = 0; 9523 for (next_fragP = fragP; next_fragP != NULL; 9524 next_fragP = next_fragP->fr_next) 9525 { 9526 next_fragP->tc_frag_data.is_no_transform = TRUE; 9527 if (next_fragP->tc_frag_data.is_loop_target) 9528 target_count++; 9529 if (target_count == 2) 9530 break; 9531 } 9532 } 9533 9534 9535 /* A map that keeps information on a per-subsegment basis. This is 9536 maintained during initial assembly, but is invalid once the 9537 subsegments are smashed together. I.E., it cannot be used during 9538 the relaxation. */ 9539 9540 typedef struct subseg_map_struct 9541 { 9542 /* the key */ 9543 segT seg; 9544 subsegT subseg; 9545 9546 /* the data */ 9547 unsigned flags; 9548 float total_freq; /* fall-through + branch target frequency */ 9549 float target_freq; /* branch target frequency alone */ 9550 9551 struct subseg_map_struct *next; 9552 } subseg_map; 9553 9554 9555 static subseg_map *sseg_map = NULL; 9556 9557 static subseg_map * 9558 get_subseg_info (segT seg, subsegT subseg) 9559 { 9560 subseg_map *subseg_e; 9561 9562 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) 9563 { 9564 if (seg == subseg_e->seg && subseg == subseg_e->subseg) 9565 break; 9566 } 9567 return subseg_e; 9568 } 9569 9570 9571 static subseg_map * 9572 add_subseg_info (segT seg, subsegT subseg) 9573 { 9574 subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); 9575 memset (subseg_e, 0, sizeof (subseg_map)); 9576 subseg_e->seg = seg; 9577 subseg_e->subseg = subseg; 9578 subseg_e->flags = 0; 9579 /* Start off considering every branch target very important. */ 9580 subseg_e->target_freq = 1.0; 9581 subseg_e->total_freq = 1.0; 9582 subseg_e->next = sseg_map; 9583 sseg_map = subseg_e; 9584 return subseg_e; 9585 } 9586 9587 9588 static unsigned 9589 get_last_insn_flags (segT seg, subsegT subseg) 9590 { 9591 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9592 if (subseg_e) 9593 return subseg_e->flags; 9594 return 0; 9595 } 9596 9597 9598 static void 9599 set_last_insn_flags (segT seg, 9600 subsegT subseg, 9601 unsigned fl, 9602 bfd_boolean val) 9603 { 9604 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9605 if (! subseg_e) 9606 subseg_e = add_subseg_info (seg, subseg); 9607 if (val) 9608 subseg_e->flags |= fl; 9609 else 9610 subseg_e->flags &= ~fl; 9611 } 9612 9613 9614 static float 9615 get_subseg_total_freq (segT seg, subsegT subseg) 9616 { 9617 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9618 if (subseg_e) 9619 return subseg_e->total_freq; 9620 return 1.0; 9621 } 9622 9623 9624 static float 9625 get_subseg_target_freq (segT seg, subsegT subseg) 9626 { 9627 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9628 if (subseg_e) 9629 return subseg_e->target_freq; 9630 return 1.0; 9631 } 9632 9633 9634 static void 9635 set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) 9636 { 9637 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9638 if (! subseg_e) 9639 subseg_e = add_subseg_info (seg, subseg); 9640 subseg_e->total_freq = total_f; 9641 subseg_e->target_freq = target_f; 9642 } 9643 9644 9645 /* Segment Lists and emit_state Stuff. */ 9646 9647 static void 9648 xtensa_move_seg_list_to_beginning (seg_list *head) 9649 { 9650 head = head->next; 9651 while (head) 9652 { 9653 segT literal_section = head->seg; 9654 9655 /* Move the literal section to the front of the section list. */ 9656 assert (literal_section); 9657 if (literal_section != stdoutput->sections) 9658 { 9659 bfd_section_list_remove (stdoutput, literal_section); 9660 bfd_section_list_prepend (stdoutput, literal_section); 9661 } 9662 head = head->next; 9663 } 9664 } 9665 9666 9667 static void mark_literal_frags (seg_list *); 9668 9669 static void 9670 xtensa_move_literals (void) 9671 { 9672 seg_list *segment; 9673 frchainS *frchain_from, *frchain_to; 9674 fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; 9675 fragS **frag_splice; 9676 emit_state state; 9677 segT dest_seg; 9678 fixS *fix, *next_fix, **fix_splice; 9679 sym_list *lit; 9680 9681 mark_literal_frags (literal_head->next); 9682 mark_literal_frags (init_literal_head->next); 9683 mark_literal_frags (fini_literal_head->next); 9684 9685 if (use_literal_section) 9686 return; 9687 9688 segment = literal_head->next; 9689 while (segment) 9690 { 9691 frchain_from = seg_info (segment->seg)->frchainP; 9692 search_frag = frchain_from->frch_root; 9693 literal_pool = NULL; 9694 frchain_to = NULL; 9695 frag_splice = &(frchain_from->frch_root); 9696 9697 while (!search_frag->tc_frag_data.literal_frag) 9698 { 9699 assert (search_frag->fr_fix == 0 9700 || search_frag->fr_type == rs_align); 9701 search_frag = search_frag->fr_next; 9702 } 9703 9704 assert (search_frag->tc_frag_data.literal_frag->fr_subtype 9705 == RELAX_LITERAL_POOL_BEGIN); 9706 xtensa_switch_section_emit_state (&state, segment->seg, 0); 9707 9708 /* Make sure that all the frags in this series are closed, and 9709 that there is at least one left over of zero-size. This 9710 prevents us from making a segment with an frchain without any 9711 frags in it. */ 9712 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 9713 xtensa_set_frag_assembly_state (frag_now); 9714 last_frag = frag_now; 9715 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 9716 xtensa_set_frag_assembly_state (frag_now); 9717 9718 while (search_frag != frag_now) 9719 { 9720 next_frag = search_frag->fr_next; 9721 9722 /* First, move the frag out of the literal section and 9723 to the appropriate place. */ 9724 if (search_frag->tc_frag_data.literal_frag) 9725 { 9726 literal_pool = search_frag->tc_frag_data.literal_frag; 9727 assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); 9728 frchain_to = literal_pool->tc_frag_data.lit_frchain; 9729 assert (frchain_to); 9730 } 9731 insert_after = literal_pool; 9732 9733 while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END) 9734 insert_after = insert_after->fr_next; 9735 9736 dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; 9737 9738 *frag_splice = next_frag; 9739 search_frag->fr_next = insert_after->fr_next; 9740 insert_after->fr_next = search_frag; 9741 search_frag->tc_frag_data.lit_seg = dest_seg; 9742 9743 /* Now move any fixups associated with this frag to the 9744 right section. */ 9745 fix = frchain_from->fix_root; 9746 fix_splice = &(frchain_from->fix_root); 9747 while (fix) 9748 { 9749 next_fix = fix->fx_next; 9750 if (fix->fx_frag == search_frag) 9751 { 9752 *fix_splice = next_fix; 9753 fix->fx_next = frchain_to->fix_root; 9754 frchain_to->fix_root = fix; 9755 if (frchain_to->fix_tail == NULL) 9756 frchain_to->fix_tail = fix; 9757 } 9758 else 9759 fix_splice = &(fix->fx_next); 9760 fix = next_fix; 9761 } 9762 search_frag = next_frag; 9763 } 9764 9765 if (frchain_from->fix_root != NULL) 9766 { 9767 frchain_from = seg_info (segment->seg)->frchainP; 9768 as_warn (_("fixes not all moved from %s"), segment->seg->name); 9769 9770 assert (frchain_from->fix_root == NULL); 9771 } 9772 frchain_from->fix_tail = NULL; 9773 xtensa_restore_emit_state (&state); 9774 segment = segment->next; 9775 } 9776 9777 /* Now fix up the SEGMENT value for all the literal symbols. */ 9778 for (lit = literal_syms; lit; lit = lit->next) 9779 { 9780 symbolS *lit_sym = lit->sym; 9781 segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; 9782 if (dest_seg) 9783 S_SET_SEGMENT (lit_sym, dest_seg); 9784 } 9785 } 9786 9787 9788 /* Walk over all the frags for segments in a list and mark them as 9789 containing literals. As clunky as this is, we can't rely on frag_var 9790 and frag_variant to get called in all situations. */ 9791 9792 static void 9793 mark_literal_frags (seg_list *segment) 9794 { 9795 frchainS *frchain_from; 9796 fragS *search_frag; 9797 9798 while (segment) 9799 { 9800 frchain_from = seg_info (segment->seg)->frchainP; 9801 search_frag = frchain_from->frch_root; 9802 while (search_frag) 9803 { 9804 search_frag->tc_frag_data.is_literal = TRUE; 9805 search_frag = search_frag->fr_next; 9806 } 9807 segment = segment->next; 9808 } 9809 } 9810 9811 9812 static void 9813 xtensa_reorder_seg_list (seg_list *head, segT after) 9814 { 9815 /* Move all of the sections in the section list to come 9816 after "after" in the gnu segment list. */ 9817 9818 head = head->next; 9819 while (head) 9820 { 9821 segT literal_section = head->seg; 9822 9823 /* Move the literal section after "after". */ 9824 assert (literal_section); 9825 if (literal_section != after) 9826 { 9827 bfd_section_list_remove (stdoutput, literal_section); 9828 bfd_section_list_insert_after (stdoutput, after, literal_section); 9829 } 9830 9831 head = head->next; 9832 } 9833 } 9834 9835 9836 /* Push all the literal segments to the end of the gnu list. */ 9837 9838 static void 9839 xtensa_reorder_segments (void) 9840 { 9841 segT sec; 9842 segT last_sec = 0; 9843 int old_count = 0; 9844 int new_count = 0; 9845 9846 for (sec = stdoutput->sections; sec != NULL; sec = sec->next) 9847 { 9848 last_sec = sec; 9849 old_count++; 9850 } 9851 9852 /* Now that we have the last section, push all the literal 9853 sections to the end. */ 9854 xtensa_reorder_seg_list (literal_head, last_sec); 9855 xtensa_reorder_seg_list (init_literal_head, last_sec); 9856 xtensa_reorder_seg_list (fini_literal_head, last_sec); 9857 9858 /* Now perform the final error check. */ 9859 for (sec = stdoutput->sections; sec != NULL; sec = sec->next) 9860 new_count++; 9861 assert (new_count == old_count); 9862 } 9863 9864 9865 /* Change the emit state (seg, subseg, and frag related stuff) to the 9866 correct location. Return a emit_state which can be passed to 9867 xtensa_restore_emit_state to return to current fragment. */ 9868 9869 static void 9870 xtensa_switch_to_literal_fragment (emit_state *result) 9871 { 9872 if (directive_state[directive_absolute_literals]) 9873 { 9874 cache_literal_section (0, default_lit_sections.lit4_seg_name, 9875 &default_lit_sections.lit4_seg, FALSE); 9876 xtensa_switch_section_emit_state (result, 9877 default_lit_sections.lit4_seg, 0); 9878 } 9879 else 9880 xtensa_switch_to_non_abs_literal_fragment (result); 9881 9882 /* Do a 4-byte align here. */ 9883 frag_align (2, 0, 0); 9884 record_alignment (now_seg, 2); 9885 } 9886 9887 9888 static void 9889 xtensa_switch_to_non_abs_literal_fragment (emit_state *result) 9890 { 9891 /* When we mark a literal pool location, we want to put a frag in 9892 the literal pool that points to it. But to do that, we want to 9893 switch_to_literal_fragment. But literal sections don't have 9894 literal pools, so their location is always null, so we would 9895 recurse forever. This is kind of hacky, but it works. */ 9896 9897 static bfd_boolean recursive = FALSE; 9898 fragS *pool_location = get_literal_pool_location (now_seg); 9899 bfd_boolean is_init = 9900 (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); 9901 9902 bfd_boolean is_fini = 9903 (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); 9904 9905 if (pool_location == NULL 9906 && !use_literal_section 9907 && !recursive 9908 && !is_init && ! is_fini) 9909 { 9910 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); 9911 recursive = TRUE; 9912 xtensa_mark_literal_pool_location (); 9913 recursive = FALSE; 9914 } 9915 9916 /* Special case: If we are in the ".fini" or ".init" section, then 9917 we will ALWAYS be generating to the ".fini.literal" and 9918 ".init.literal" sections. */ 9919 9920 if (is_init) 9921 { 9922 cache_literal_section (init_literal_head, 9923 default_lit_sections.init_lit_seg_name, 9924 &default_lit_sections.init_lit_seg, TRUE); 9925 xtensa_switch_section_emit_state (result, 9926 default_lit_sections.init_lit_seg, 0); 9927 } 9928 else if (is_fini) 9929 { 9930 cache_literal_section (fini_literal_head, 9931 default_lit_sections.fini_lit_seg_name, 9932 &default_lit_sections.fini_lit_seg, TRUE); 9933 xtensa_switch_section_emit_state (result, 9934 default_lit_sections.fini_lit_seg, 0); 9935 } 9936 else 9937 { 9938 cache_literal_section (literal_head, 9939 default_lit_sections.lit_seg_name, 9940 &default_lit_sections.lit_seg, TRUE); 9941 xtensa_switch_section_emit_state (result, 9942 default_lit_sections.lit_seg, 0); 9943 } 9944 9945 if (!use_literal_section 9946 && !is_init && !is_fini 9947 && get_literal_pool_location (now_seg) != pool_location) 9948 { 9949 /* Close whatever frag is there. */ 9950 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 9951 xtensa_set_frag_assembly_state (frag_now); 9952 frag_now->tc_frag_data.literal_frag = pool_location; 9953 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 9954 xtensa_set_frag_assembly_state (frag_now); 9955 } 9956 } 9957 9958 9959 /* Call this function before emitting data into the literal section. 9960 This is a helper function for xtensa_switch_to_literal_fragment. 9961 This is similar to a .section new_now_seg subseg. */ 9962 9963 static void 9964 xtensa_switch_section_emit_state (emit_state *state, 9965 segT new_now_seg, 9966 subsegT new_now_subseg) 9967 { 9968 state->name = now_seg->name; 9969 state->now_seg = now_seg; 9970 state->now_subseg = now_subseg; 9971 state->generating_literals = generating_literals; 9972 generating_literals++; 9973 subseg_set (new_now_seg, new_now_subseg); 9974 } 9975 9976 9977 /* Use to restore the emitting into the normal place. */ 9978 9979 static void 9980 xtensa_restore_emit_state (emit_state *state) 9981 { 9982 generating_literals = state->generating_literals; 9983 subseg_set (state->now_seg, state->now_subseg); 9984 } 9985 9986 9987 /* Get a segment of a given name. If the segment is already 9988 present, return it; otherwise, create a new one. */ 9989 9990 static void 9991 cache_literal_section (seg_list *head, 9992 const char *name, 9993 segT *pseg, 9994 bfd_boolean is_code) 9995 { 9996 segT current_section = now_seg; 9997 int current_subsec = now_subseg; 9998 segT seg; 9999 10000 if (*pseg != 0) 10001 return; 10002 10003 /* Check if the named section exists. */ 10004 for (seg = stdoutput->sections; seg; seg = seg->next) 10005 { 10006 if (!strcmp (segment_name (seg), name)) 10007 break; 10008 } 10009 10010 if (!seg) 10011 { 10012 /* Create a new literal section. */ 10013 seg = subseg_new (name, (subsegT) 0); 10014 if (head) 10015 { 10016 /* Add the newly created literal segment to the specified list. */ 10017 seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); 10018 n->seg = seg; 10019 n->next = head->next; 10020 head->next = n; 10021 } 10022 bfd_set_section_flags (stdoutput, seg, SEC_HAS_CONTENTS | 10023 SEC_READONLY | SEC_ALLOC | SEC_LOAD 10024 | (is_code ? SEC_CODE : SEC_DATA)); 10025 bfd_set_section_alignment (stdoutput, seg, 2); 10026 } 10027 10028 *pseg = seg; 10029 subseg_set (current_section, current_subsec); 10030 } 10031 10032 10033 /* Property Tables Stuff. */ 10034 10035 #define XTENSA_INSN_SEC_NAME ".xt.insn" 10036 #define XTENSA_LIT_SEC_NAME ".xt.lit" 10037 #define XTENSA_PROP_SEC_NAME ".xt.prop" 10038 10039 typedef bfd_boolean (*frag_predicate) (const fragS *); 10040 typedef void (*frag_flags_fn) (const fragS *, frag_flags *); 10041 10042 static bfd_boolean get_frag_is_literal (const fragS *); 10043 static void xtensa_create_property_segments 10044 (frag_predicate, frag_predicate, const char *, xt_section_type); 10045 static void xtensa_create_xproperty_segments 10046 (frag_flags_fn, const char *, xt_section_type); 10047 static segment_info_type *retrieve_segment_info (segT); 10048 static segT retrieve_xtensa_section (char *); 10049 static bfd_boolean section_has_property (segT, frag_predicate); 10050 static bfd_boolean section_has_xproperty (segT, frag_flags_fn); 10051 static void add_xt_block_frags 10052 (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate); 10053 static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); 10054 static void xtensa_frag_flags_init (frag_flags *); 10055 static void get_frag_property_flags (const fragS *, frag_flags *); 10056 static bfd_vma frag_flags_to_number (const frag_flags *); 10057 static void add_xt_prop_frags 10058 (segT, segT, xtensa_block_info **, frag_flags_fn); 10059 10060 /* Set up property tables after relaxation. */ 10061 10062 void 10063 xtensa_post_relax_hook (void) 10064 { 10065 xtensa_move_seg_list_to_beginning (literal_head); 10066 xtensa_move_seg_list_to_beginning (init_literal_head); 10067 xtensa_move_seg_list_to_beginning (fini_literal_head); 10068 10069 xtensa_find_unmarked_state_frags (); 10070 10071 xtensa_create_property_segments (get_frag_is_literal, 10072 NULL, 10073 XTENSA_LIT_SEC_NAME, 10074 xt_literal_sec); 10075 xtensa_create_xproperty_segments (get_frag_property_flags, 10076 XTENSA_PROP_SEC_NAME, 10077 xt_prop_sec); 10078 10079 if (warn_unaligned_branch_targets) 10080 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); 10081 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); 10082 } 10083 10084 10085 /* This function is only meaningful after xtensa_move_literals. */ 10086 10087 static bfd_boolean 10088 get_frag_is_literal (const fragS *fragP) 10089 { 10090 assert (fragP != NULL); 10091 return fragP->tc_frag_data.is_literal; 10092 } 10093 10094 10095 static void 10096 xtensa_create_property_segments (frag_predicate property_function, 10097 frag_predicate end_property_function, 10098 const char *section_name_base, 10099 xt_section_type sec_type) 10100 { 10101 segT *seclist; 10102 10103 /* Walk over all of the current segments. 10104 Walk over each fragment 10105 For each non-empty fragment, 10106 Build a property record (append where possible). */ 10107 10108 for (seclist = &stdoutput->sections; 10109 seclist && *seclist; 10110 seclist = &(*seclist)->next) 10111 { 10112 segT sec = *seclist; 10113 flagword flags; 10114 10115 flags = bfd_get_section_flags (stdoutput, sec); 10116 if (flags & SEC_DEBUGGING) 10117 continue; 10118 if (!(flags & SEC_ALLOC)) 10119 continue; 10120 10121 if (section_has_property (sec, property_function)) 10122 { 10123 char *property_section_name = 10124 xtensa_get_property_section_name (sec, section_name_base); 10125 segT insn_sec = retrieve_xtensa_section (property_section_name); 10126 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); 10127 xtensa_block_info **xt_blocks = 10128 &xt_seg_info->tc_segment_info_data.blocks[sec_type]; 10129 /* Walk over all of the frchains here and add new sections. */ 10130 add_xt_block_frags (sec, insn_sec, xt_blocks, property_function, 10131 end_property_function); 10132 } 10133 } 10134 10135 /* Now we fill them out.... */ 10136 10137 for (seclist = &stdoutput->sections; 10138 seclist && *seclist; 10139 seclist = &(*seclist)->next) 10140 { 10141 segment_info_type *seginfo; 10142 xtensa_block_info *block; 10143 segT sec = *seclist; 10144 10145 seginfo = seg_info (sec); 10146 block = seginfo->tc_segment_info_data.blocks[sec_type]; 10147 10148 if (block) 10149 { 10150 xtensa_block_info *cur_block; 10151 /* This is a section with some data. */ 10152 int num_recs = 0; 10153 bfd_size_type rec_size; 10154 10155 for (cur_block = block; cur_block; cur_block = cur_block->next) 10156 num_recs++; 10157 10158 rec_size = num_recs * 8; 10159 bfd_set_section_size (stdoutput, sec, rec_size); 10160 10161 /* In order to make this work with the assembler, we have to 10162 build some frags and then build the "fixups" for it. It 10163 would be easier to just set the contents then set the 10164 arlents. */ 10165 10166 if (num_recs) 10167 { 10168 /* Allocate a fragment and leak it. */ 10169 fragS *fragP; 10170 bfd_size_type frag_size; 10171 fixS *fixes; 10172 frchainS *frchainP; 10173 int i; 10174 char *frag_data; 10175 10176 frag_size = sizeof (fragS) + rec_size; 10177 fragP = (fragS *) xmalloc (frag_size); 10178 10179 memset (fragP, 0, frag_size); 10180 fragP->fr_address = 0; 10181 fragP->fr_next = NULL; 10182 fragP->fr_fix = rec_size; 10183 fragP->fr_var = 0; 10184 fragP->fr_type = rs_fill; 10185 /* The rest are zeros. */ 10186 10187 frchainP = seginfo->frchainP; 10188 frchainP->frch_root = fragP; 10189 frchainP->frch_last = fragP; 10190 10191 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); 10192 memset (fixes, 0, sizeof (fixS) * num_recs); 10193 10194 seginfo->fix_root = fixes; 10195 seginfo->fix_tail = &fixes[num_recs - 1]; 10196 cur_block = block; 10197 frag_data = &fragP->fr_literal[0]; 10198 for (i = 0; i < num_recs; i++) 10199 { 10200 fixS *fix = &fixes[i]; 10201 assert (cur_block); 10202 10203 /* Write the fixup. */ 10204 if (i != num_recs - 1) 10205 fix->fx_next = &fixes[i + 1]; 10206 else 10207 fix->fx_next = NULL; 10208 fix->fx_size = 4; 10209 fix->fx_done = 0; 10210 fix->fx_frag = fragP; 10211 fix->fx_where = i * 8; 10212 fix->fx_addsy = section_symbol (cur_block->sec); 10213 fix->fx_offset = cur_block->offset; 10214 fix->fx_r_type = BFD_RELOC_32; 10215 fix->fx_file = "Internal Assembly"; 10216 fix->fx_line = 0; 10217 10218 /* Write the length. */ 10219 md_number_to_chars (&frag_data[4 + 8 * i], 10220 cur_block->size, 4); 10221 cur_block = cur_block->next; 10222 } 10223 } 10224 } 10225 } 10226 } 10227 10228 10229 static void 10230 xtensa_create_xproperty_segments (frag_flags_fn flag_fn, 10231 const char *section_name_base, 10232 xt_section_type sec_type) 10233 { 10234 segT *seclist; 10235 10236 /* Walk over all of the current segments. 10237 Walk over each fragment. 10238 For each fragment that has instructions, 10239 build an instruction record (append where possible). */ 10240 10241 for (seclist = &stdoutput->sections; 10242 seclist && *seclist; 10243 seclist = &(*seclist)->next) 10244 { 10245 segT sec = *seclist; 10246 flagword flags; 10247 10248 flags = bfd_get_section_flags (stdoutput, sec); 10249 if ((flags & SEC_DEBUGGING) 10250 || !(flags & SEC_ALLOC) 10251 || (flags & SEC_MERGE)) 10252 continue; 10253 10254 if (section_has_xproperty (sec, flag_fn)) 10255 { 10256 char *property_section_name = 10257 xtensa_get_property_section_name (sec, section_name_base); 10258 segT insn_sec = retrieve_xtensa_section (property_section_name); 10259 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); 10260 xtensa_block_info **xt_blocks = 10261 &xt_seg_info->tc_segment_info_data.blocks[sec_type]; 10262 /* Walk over all of the frchains here and add new sections. */ 10263 add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn); 10264 } 10265 } 10266 10267 /* Now we fill them out.... */ 10268 10269 for (seclist = &stdoutput->sections; 10270 seclist && *seclist; 10271 seclist = &(*seclist)->next) 10272 { 10273 segment_info_type *seginfo; 10274 xtensa_block_info *block; 10275 segT sec = *seclist; 10276 10277 seginfo = seg_info (sec); 10278 block = seginfo->tc_segment_info_data.blocks[sec_type]; 10279 10280 if (block) 10281 { 10282 xtensa_block_info *cur_block; 10283 /* This is a section with some data. */ 10284 int num_recs = 0; 10285 bfd_size_type rec_size; 10286 10287 for (cur_block = block; cur_block; cur_block = cur_block->next) 10288 num_recs++; 10289 10290 rec_size = num_recs * (8 + 4); 10291 bfd_set_section_size (stdoutput, sec, rec_size); 10292 10293 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ 10294 10295 /* In order to make this work with the assembler, we have to build 10296 some frags then build the "fixups" for it. It would be easier to 10297 just set the contents then set the arlents. */ 10298 10299 if (num_recs) 10300 { 10301 /* Allocate a fragment and (unfortunately) leak it. */ 10302 fragS *fragP; 10303 bfd_size_type frag_size; 10304 fixS *fixes; 10305 frchainS *frchainP; 10306 int i; 10307 char *frag_data; 10308 10309 frag_size = sizeof (fragS) + rec_size; 10310 fragP = (fragS *) xmalloc (frag_size); 10311 10312 memset (fragP, 0, frag_size); 10313 fragP->fr_address = 0; 10314 fragP->fr_next = NULL; 10315 fragP->fr_fix = rec_size; 10316 fragP->fr_var = 0; 10317 fragP->fr_type = rs_fill; 10318 /* The rest are zeros. */ 10319 10320 frchainP = seginfo->frchainP; 10321 frchainP->frch_root = fragP; 10322 frchainP->frch_last = fragP; 10323 10324 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); 10325 memset (fixes, 0, sizeof (fixS) * num_recs); 10326 10327 seginfo->fix_root = fixes; 10328 seginfo->fix_tail = &fixes[num_recs - 1]; 10329 cur_block = block; 10330 frag_data = &fragP->fr_literal[0]; 10331 for (i = 0; i < num_recs; i++) 10332 { 10333 fixS *fix = &fixes[i]; 10334 assert (cur_block); 10335 10336 /* Write the fixup. */ 10337 if (i != num_recs - 1) 10338 fix->fx_next = &fixes[i + 1]; 10339 else 10340 fix->fx_next = NULL; 10341 fix->fx_size = 4; 10342 fix->fx_done = 0; 10343 fix->fx_frag = fragP; 10344 fix->fx_where = i * (8 + 4); 10345 fix->fx_addsy = section_symbol (cur_block->sec); 10346 fix->fx_offset = cur_block->offset; 10347 fix->fx_r_type = BFD_RELOC_32; 10348 fix->fx_file = "Internal Assembly"; 10349 fix->fx_line = 0; 10350 10351 /* Write the length. */ 10352 md_number_to_chars (&frag_data[4 + (8+4) * i], 10353 cur_block->size, 4); 10354 md_number_to_chars (&frag_data[8 + (8+4) * i], 10355 frag_flags_to_number (&cur_block->flags), 10356 4); 10357 cur_block = cur_block->next; 10358 } 10359 } 10360 } 10361 } 10362 } 10363 10364 10365 static segment_info_type * 10366 retrieve_segment_info (segT seg) 10367 { 10368 segment_info_type *seginfo; 10369 seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg); 10370 if (!seginfo) 10371 { 10372 frchainS *frchainP; 10373 10374 seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo)); 10375 memset ((void *) seginfo, 0, sizeof (*seginfo)); 10376 seginfo->fix_root = NULL; 10377 seginfo->fix_tail = NULL; 10378 seginfo->bfd_section = seg; 10379 seginfo->sym = 0; 10380 /* We will not be dealing with these, only our special ones. */ 10381 bfd_set_section_userdata (stdoutput, seg, (void *) seginfo); 10382 10383 frchainP = (frchainS *) xmalloc (sizeof (frchainS)); 10384 frchainP->frch_root = NULL; 10385 frchainP->frch_last = NULL; 10386 frchainP->frch_next = NULL; 10387 frchainP->frch_seg = seg; 10388 frchainP->frch_subseg = 0; 10389 frchainP->fix_root = NULL; 10390 frchainP->fix_tail = NULL; 10391 /* Do not init the objstack. */ 10392 /* obstack_begin (&frchainP->frch_obstack, chunksize); */ 10393 /* frchainP->frch_frag_now = fragP; */ 10394 frchainP->frch_frag_now = NULL; 10395 10396 seginfo->frchainP = frchainP; 10397 } 10398 10399 return seginfo; 10400 } 10401 10402 10403 static segT 10404 retrieve_xtensa_section (char *sec_name) 10405 { 10406 bfd *abfd = stdoutput; 10407 flagword flags, out_flags, link_once_flags; 10408 segT s; 10409 10410 flags = bfd_get_section_flags (abfd, now_seg); 10411 link_once_flags = (flags & SEC_LINK_ONCE); 10412 if (link_once_flags) 10413 link_once_flags |= (flags & SEC_LINK_DUPLICATES); 10414 out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags); 10415 10416 s = bfd_make_section_old_way (abfd, sec_name); 10417 if (s == NULL) 10418 as_bad (_("could not create section %s"), sec_name); 10419 if (!bfd_set_section_flags (abfd, s, out_flags)) 10420 as_bad (_("invalid flag combination on section %s"), sec_name); 10421 10422 return s; 10423 } 10424 10425 10426 static bfd_boolean 10427 section_has_property (segT sec, frag_predicate property_function) 10428 { 10429 segment_info_type *seginfo = seg_info (sec); 10430 fragS *fragP; 10431 10432 if (seginfo && seginfo->frchainP) 10433 { 10434 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) 10435 { 10436 if (property_function (fragP) 10437 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) 10438 return TRUE; 10439 } 10440 } 10441 return FALSE; 10442 } 10443 10444 10445 static bfd_boolean 10446 section_has_xproperty (segT sec, frag_flags_fn property_function) 10447 { 10448 segment_info_type *seginfo = seg_info (sec); 10449 fragS *fragP; 10450 10451 if (seginfo && seginfo->frchainP) 10452 { 10453 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) 10454 { 10455 frag_flags prop_flags; 10456 property_function (fragP, &prop_flags); 10457 if (!xtensa_frag_flags_is_empty (&prop_flags)) 10458 return TRUE; 10459 } 10460 } 10461 return FALSE; 10462 } 10463 10464 10465 /* Two types of block sections exist right now: literal and insns. */ 10466 10467 static void 10468 add_xt_block_frags (segT sec, 10469 segT xt_block_sec, 10470 xtensa_block_info **xt_block, 10471 frag_predicate property_function, 10472 frag_predicate end_property_function) 10473 { 10474 segment_info_type *seg_info; 10475 segment_info_type *xt_seg_info; 10476 bfd_vma seg_offset; 10477 fragS *fragP; 10478 10479 xt_seg_info = retrieve_segment_info (xt_block_sec); 10480 seg_info = retrieve_segment_info (sec); 10481 10482 /* Build it if needed. */ 10483 while (*xt_block != NULL) 10484 xt_block = &(*xt_block)->next; 10485 /* We are either at NULL at the beginning or at the end. */ 10486 10487 /* Walk through the frags. */ 10488 seg_offset = 0; 10489 10490 if (seg_info->frchainP) 10491 { 10492 for (fragP = seg_info->frchainP->frch_root; 10493 fragP; 10494 fragP = fragP->fr_next) 10495 { 10496 if (property_function (fragP) 10497 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) 10498 { 10499 if (*xt_block != NULL) 10500 { 10501 if ((*xt_block)->offset + (*xt_block)->size 10502 == fragP->fr_address) 10503 (*xt_block)->size += fragP->fr_fix; 10504 else 10505 xt_block = &((*xt_block)->next); 10506 } 10507 if (*xt_block == NULL) 10508 { 10509 xtensa_block_info *new_block = (xtensa_block_info *) 10510 xmalloc (sizeof (xtensa_block_info)); 10511 new_block->sec = sec; 10512 new_block->offset = fragP->fr_address; 10513 new_block->size = fragP->fr_fix; 10514 new_block->next = NULL; 10515 xtensa_frag_flags_init (&new_block->flags); 10516 *xt_block = new_block; 10517 } 10518 if (end_property_function 10519 && end_property_function (fragP)) 10520 { 10521 xt_block = &((*xt_block)->next); 10522 } 10523 } 10524 } 10525 } 10526 } 10527 10528 10529 /* Break the encapsulation of add_xt_prop_frags here. */ 10530 10531 static bfd_boolean 10532 xtensa_frag_flags_is_empty (const frag_flags *prop_flags) 10533 { 10534 if (prop_flags->is_literal 10535 || prop_flags->is_insn 10536 || prop_flags->is_data 10537 || prop_flags->is_unreachable) 10538 return FALSE; 10539 return TRUE; 10540 } 10541 10542 10543 static void 10544 xtensa_frag_flags_init (frag_flags *prop_flags) 10545 { 10546 memset (prop_flags, 0, sizeof (frag_flags)); 10547 } 10548 10549 10550 static void 10551 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) 10552 { 10553 xtensa_frag_flags_init (prop_flags); 10554 if (fragP->tc_frag_data.is_literal) 10555 prop_flags->is_literal = TRUE; 10556 if (fragP->tc_frag_data.is_unreachable) 10557 prop_flags->is_unreachable = TRUE; 10558 else if (fragP->tc_frag_data.is_insn) 10559 { 10560 prop_flags->is_insn = TRUE; 10561 if (fragP->tc_frag_data.is_loop_target) 10562 prop_flags->insn.is_loop_target = TRUE; 10563 if (fragP->tc_frag_data.is_branch_target) 10564 prop_flags->insn.is_branch_target = TRUE; 10565 if (fragP->tc_frag_data.is_specific_opcode 10566 || fragP->tc_frag_data.is_no_transform) 10567 prop_flags->insn.is_no_transform = TRUE; 10568 if (fragP->tc_frag_data.is_no_density) 10569 prop_flags->insn.is_no_density = TRUE; 10570 if (fragP->tc_frag_data.use_absolute_literals) 10571 prop_flags->insn.is_abslit = TRUE; 10572 } 10573 if (fragP->tc_frag_data.is_align) 10574 { 10575 prop_flags->is_align = TRUE; 10576 prop_flags->alignment = fragP->tc_frag_data.alignment; 10577 if (xtensa_frag_flags_is_empty (prop_flags)) 10578 prop_flags->is_data = TRUE; 10579 } 10580 } 10581 10582 10583 static bfd_vma 10584 frag_flags_to_number (const frag_flags *prop_flags) 10585 { 10586 bfd_vma num = 0; 10587 if (prop_flags->is_literal) 10588 num |= XTENSA_PROP_LITERAL; 10589 if (prop_flags->is_insn) 10590 num |= XTENSA_PROP_INSN; 10591 if (prop_flags->is_data) 10592 num |= XTENSA_PROP_DATA; 10593 if (prop_flags->is_unreachable) 10594 num |= XTENSA_PROP_UNREACHABLE; 10595 if (prop_flags->insn.is_loop_target) 10596 num |= XTENSA_PROP_INSN_LOOP_TARGET; 10597 if (prop_flags->insn.is_branch_target) 10598 { 10599 num |= XTENSA_PROP_INSN_BRANCH_TARGET; 10600 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); 10601 } 10602 10603 if (prop_flags->insn.is_no_density) 10604 num |= XTENSA_PROP_INSN_NO_DENSITY; 10605 if (prop_flags->insn.is_no_transform) 10606 num |= XTENSA_PROP_INSN_NO_TRANSFORM; 10607 if (prop_flags->insn.is_no_reorder) 10608 num |= XTENSA_PROP_INSN_NO_REORDER; 10609 if (prop_flags->insn.is_abslit) 10610 num |= XTENSA_PROP_INSN_ABSLIT; 10611 10612 if (prop_flags->is_align) 10613 { 10614 num |= XTENSA_PROP_ALIGN; 10615 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); 10616 } 10617 10618 return num; 10619 } 10620 10621 10622 static bfd_boolean 10623 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, 10624 const frag_flags *prop_flags_2) 10625 { 10626 /* Cannot combine with an end marker. */ 10627 10628 if (prop_flags_1->is_literal != prop_flags_2->is_literal) 10629 return FALSE; 10630 if (prop_flags_1->is_insn != prop_flags_2->is_insn) 10631 return FALSE; 10632 if (prop_flags_1->is_data != prop_flags_2->is_data) 10633 return FALSE; 10634 10635 if (prop_flags_1->is_insn) 10636 { 10637 /* Properties of the beginning of the frag. */ 10638 if (prop_flags_2->insn.is_loop_target) 10639 return FALSE; 10640 if (prop_flags_2->insn.is_branch_target) 10641 return FALSE; 10642 if (prop_flags_1->insn.is_no_density != 10643 prop_flags_2->insn.is_no_density) 10644 return FALSE; 10645 if (prop_flags_1->insn.is_no_transform != 10646 prop_flags_2->insn.is_no_transform) 10647 return FALSE; 10648 if (prop_flags_1->insn.is_no_reorder != 10649 prop_flags_2->insn.is_no_reorder) 10650 return FALSE; 10651 if (prop_flags_1->insn.is_abslit != 10652 prop_flags_2->insn.is_abslit) 10653 return FALSE; 10654 } 10655 10656 if (prop_flags_1->is_align) 10657 return FALSE; 10658 10659 return TRUE; 10660 } 10661 10662 10663 static bfd_vma 10664 xt_block_aligned_size (const xtensa_block_info *xt_block) 10665 { 10666 bfd_vma end_addr; 10667 unsigned align_bits; 10668 10669 if (!xt_block->flags.is_align) 10670 return xt_block->size; 10671 10672 end_addr = xt_block->offset + xt_block->size; 10673 align_bits = xt_block->flags.alignment; 10674 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; 10675 return end_addr - xt_block->offset; 10676 } 10677 10678 10679 static bfd_boolean 10680 xtensa_xt_block_combine (xtensa_block_info *xt_block, 10681 const xtensa_block_info *xt_block_2) 10682 { 10683 if (xt_block->sec != xt_block_2->sec) 10684 return FALSE; 10685 if (xt_block->offset + xt_block_aligned_size (xt_block) 10686 != xt_block_2->offset) 10687 return FALSE; 10688 10689 if (xt_block_2->size == 0 10690 && (!xt_block_2->flags.is_unreachable 10691 || xt_block->flags.is_unreachable)) 10692 { 10693 if (xt_block_2->flags.is_align 10694 && xt_block->flags.is_align) 10695 { 10696 /* Nothing needed. */ 10697 if (xt_block->flags.alignment >= xt_block_2->flags.alignment) 10698 return TRUE; 10699 } 10700 else 10701 { 10702 if (xt_block_2->flags.is_align) 10703 { 10704 /* Push alignment to previous entry. */ 10705 xt_block->flags.is_align = xt_block_2->flags.is_align; 10706 xt_block->flags.alignment = xt_block_2->flags.alignment; 10707 } 10708 return TRUE; 10709 } 10710 } 10711 if (!xtensa_frag_flags_combinable (&xt_block->flags, 10712 &xt_block_2->flags)) 10713 return FALSE; 10714 10715 xt_block->size += xt_block_2->size; 10716 10717 if (xt_block_2->flags.is_align) 10718 { 10719 xt_block->flags.is_align = TRUE; 10720 xt_block->flags.alignment = xt_block_2->flags.alignment; 10721 } 10722 10723 return TRUE; 10724 } 10725 10726 10727 static void 10728 add_xt_prop_frags (segT sec, 10729 segT xt_block_sec, 10730 xtensa_block_info **xt_block, 10731 frag_flags_fn property_function) 10732 { 10733 segment_info_type *seg_info; 10734 segment_info_type *xt_seg_info; 10735 bfd_vma seg_offset; 10736 fragS *fragP; 10737 10738 xt_seg_info = retrieve_segment_info (xt_block_sec); 10739 seg_info = retrieve_segment_info (sec); 10740 /* Build it if needed. */ 10741 while (*xt_block != NULL) 10742 { 10743 xt_block = &(*xt_block)->next; 10744 } 10745 /* We are either at NULL at the beginning or at the end. */ 10746 10747 /* Walk through the frags. */ 10748 seg_offset = 0; 10749 10750 if (seg_info->frchainP) 10751 { 10752 for (fragP = seg_info->frchainP->frch_root; fragP; 10753 fragP = fragP->fr_next) 10754 { 10755 xtensa_block_info tmp_block; 10756 tmp_block.sec = sec; 10757 tmp_block.offset = fragP->fr_address; 10758 tmp_block.size = fragP->fr_fix; 10759 tmp_block.next = NULL; 10760 property_function (fragP, &tmp_block.flags); 10761 10762 if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) 10763 /* && fragP->fr_fix != 0) */ 10764 { 10765 if ((*xt_block) == NULL 10766 || !xtensa_xt_block_combine (*xt_block, &tmp_block)) 10767 { 10768 xtensa_block_info *new_block; 10769 if ((*xt_block) != NULL) 10770 xt_block = &(*xt_block)->next; 10771 new_block = (xtensa_block_info *) 10772 xmalloc (sizeof (xtensa_block_info)); 10773 *new_block = tmp_block; 10774 *xt_block = new_block; 10775 } 10776 } 10777 } 10778 } 10779 } 10780 10781 10782 /* op_placement_info_table */ 10783 10784 /* op_placement_info makes it easier to determine which 10785 ops can go in which slots. */ 10786 10787 static void 10788 init_op_placement_info_table (void) 10789 { 10790 xtensa_isa isa = xtensa_default_isa; 10791 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); 10792 xtensa_opcode opcode; 10793 xtensa_format fmt; 10794 int slot; 10795 int num_opcodes = xtensa_isa_num_opcodes (isa); 10796 10797 op_placement_table = (op_placement_info_table) 10798 xmalloc (sizeof (op_placement_info) * num_opcodes); 10799 assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); 10800 10801 for (opcode = 0; opcode < num_opcodes; opcode++) 10802 { 10803 op_placement_info *opi = &op_placement_table[opcode]; 10804 /* FIXME: Make tinsn allocation dynamic. */ 10805 if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) 10806 as_fatal (_("too many operands in instruction")); 10807 opi->narrowest = XTENSA_UNDEFINED; 10808 opi->narrowest_size = 0x7F; 10809 opi->narrowest_slot = 0; 10810 opi->formats = 0; 10811 opi->num_formats = 0; 10812 opi->issuef = 0; 10813 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) 10814 { 10815 opi->slots[fmt] = 0; 10816 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 10817 { 10818 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) 10819 { 10820 int fmt_length = xtensa_format_length (isa, fmt); 10821 opi->issuef++; 10822 set_bit (fmt, opi->formats); 10823 set_bit (slot, opi->slots[fmt]); 10824 if (fmt_length < opi->narrowest_size 10825 || (fmt_length == opi->narrowest_size 10826 && (xtensa_format_num_slots (isa, fmt) 10827 < xtensa_format_num_slots (isa, 10828 opi->narrowest)))) 10829 { 10830 opi->narrowest = fmt; 10831 opi->narrowest_size = fmt_length; 10832 opi->narrowest_slot = slot; 10833 } 10834 } 10835 } 10836 if (opi->formats) 10837 opi->num_formats++; 10838 } 10839 } 10840 xtensa_insnbuf_free (isa, ibuf); 10841 } 10842 10843 10844 bfd_boolean 10845 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) 10846 { 10847 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); 10848 } 10849 10850 10851 /* If the opcode is available in a single slot format, return its size. */ 10852 10853 static int 10854 xg_get_single_size (xtensa_opcode opcode) 10855 { 10856 return op_placement_table[opcode].narrowest_size; 10857 } 10858 10859 10860 static xtensa_format 10861 xg_get_single_format (xtensa_opcode opcode) 10862 { 10863 return op_placement_table[opcode].narrowest; 10864 } 10865 10866 10867 static int 10868 xg_get_single_slot (xtensa_opcode opcode) 10869 { 10870 return op_placement_table[opcode].narrowest_slot; 10871 } 10872 10873 10874 /* Instruction Stack Functions (from "xtensa-istack.h"). */ 10875 10876 void 10877 istack_init (IStack *stack) 10878 { 10879 memset (stack, 0, sizeof (IStack)); 10880 stack->ninsn = 0; 10881 } 10882 10883 10884 bfd_boolean 10885 istack_empty (IStack *stack) 10886 { 10887 return (stack->ninsn == 0); 10888 } 10889 10890 10891 bfd_boolean 10892 istack_full (IStack *stack) 10893 { 10894 return (stack->ninsn == MAX_ISTACK); 10895 } 10896 10897 10898 /* Return a pointer to the top IStack entry. 10899 It is an error to call this if istack_empty () is TRUE. */ 10900 10901 TInsn * 10902 istack_top (IStack *stack) 10903 { 10904 int rec = stack->ninsn - 1; 10905 assert (!istack_empty (stack)); 10906 return &stack->insn[rec]; 10907 } 10908 10909 10910 /* Add a new TInsn to an IStack. 10911 It is an error to call this if istack_full () is TRUE. */ 10912 10913 void 10914 istack_push (IStack *stack, TInsn *insn) 10915 { 10916 int rec = stack->ninsn; 10917 assert (!istack_full (stack)); 10918 stack->insn[rec] = *insn; 10919 stack->ninsn++; 10920 } 10921 10922 10923 /* Clear space for the next TInsn on the IStack and return a pointer 10924 to it. It is an error to call this if istack_full () is TRUE. */ 10925 10926 TInsn * 10927 istack_push_space (IStack *stack) 10928 { 10929 int rec = stack->ninsn; 10930 TInsn *insn; 10931 assert (!istack_full (stack)); 10932 insn = &stack->insn[rec]; 10933 memset (insn, 0, sizeof (TInsn)); 10934 stack->ninsn++; 10935 return insn; 10936 } 10937 10938 10939 /* Remove the last pushed instruction. It is an error to call this if 10940 istack_empty () returns TRUE. */ 10941 10942 void 10943 istack_pop (IStack *stack) 10944 { 10945 int rec = stack->ninsn - 1; 10946 assert (!istack_empty (stack)); 10947 stack->ninsn--; 10948 memset (&stack->insn[rec], 0, sizeof (TInsn)); 10949 } 10950 10951 10952 /* TInsn functions. */ 10953 10954 void 10955 tinsn_init (TInsn *dst) 10956 { 10957 memset (dst, 0, sizeof (TInsn)); 10958 } 10959 10960 10961 /* Get the ``num''th token of the TInsn. 10962 It is illegal to call this if num > insn->ntoks. */ 10963 10964 expressionS * 10965 tinsn_get_tok (TInsn *insn, int num) 10966 { 10967 assert (num < insn->ntok); 10968 return &insn->tok[num]; 10969 } 10970 10971 10972 /* Return TRUE if ANY of the operands in the insn are symbolic. */ 10973 10974 static bfd_boolean 10975 tinsn_has_symbolic_operands (const TInsn *insn) 10976 { 10977 int i; 10978 int n = insn->ntok; 10979 10980 assert (insn->insn_type == ITYPE_INSN); 10981 10982 for (i = 0; i < n; ++i) 10983 { 10984 switch (insn->tok[i].X_op) 10985 { 10986 case O_register: 10987 case O_constant: 10988 break; 10989 default: 10990 return TRUE; 10991 } 10992 } 10993 return FALSE; 10994 } 10995 10996 10997 bfd_boolean 10998 tinsn_has_invalid_symbolic_operands (const TInsn *insn) 10999 { 11000 xtensa_isa isa = xtensa_default_isa; 11001 int i; 11002 int n = insn->ntok; 11003 11004 assert (insn->insn_type == ITYPE_INSN); 11005 11006 for (i = 0; i < n; ++i) 11007 { 11008 switch (insn->tok[i].X_op) 11009 { 11010 case O_register: 11011 case O_constant: 11012 break; 11013 case O_big: 11014 case O_illegal: 11015 case O_absent: 11016 /* Errors for these types are caught later. */ 11017 break; 11018 case O_hi16: 11019 case O_lo16: 11020 default: 11021 /* Symbolic immediates are only allowed on the last immediate 11022 operand. At this time, CONST16 is the only opcode where we 11023 support non-PC-relative relocations. */ 11024 if (i != get_relaxable_immed (insn->opcode) 11025 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 11026 && insn->opcode != xtensa_const16_opcode)) 11027 { 11028 as_bad (_("invalid symbolic operand")); 11029 return TRUE; 11030 } 11031 } 11032 } 11033 return FALSE; 11034 } 11035 11036 11037 /* For assembly code with complex expressions (e.g. subtraction), 11038 we have to build them in the literal pool so that 11039 their results are calculated correctly after relaxation. 11040 The relaxation only handles expressions that 11041 boil down to SYMBOL + OFFSET. */ 11042 11043 static bfd_boolean 11044 tinsn_has_complex_operands (const TInsn *insn) 11045 { 11046 int i; 11047 int n = insn->ntok; 11048 assert (insn->insn_type == ITYPE_INSN); 11049 for (i = 0; i < n; ++i) 11050 { 11051 switch (insn->tok[i].X_op) 11052 { 11053 case O_register: 11054 case O_constant: 11055 case O_symbol: 11056 case O_lo16: 11057 case O_hi16: 11058 break; 11059 default: 11060 return TRUE; 11061 } 11062 } 11063 return FALSE; 11064 } 11065 11066 11067 /* Encode a TInsn opcode and its constant operands into slotbuf. 11068 Return TRUE if there is a symbol in the immediate field. This 11069 function assumes that: 11070 1) The number of operands are correct. 11071 2) The insn_type is ITYPE_INSN. 11072 3) The opcode can be encoded in the specified format and slot. 11073 4) Operands are either O_constant or O_symbol, and all constants fit. */ 11074 11075 static bfd_boolean 11076 tinsn_to_slotbuf (xtensa_format fmt, 11077 int slot, 11078 TInsn *tinsn, 11079 xtensa_insnbuf slotbuf) 11080 { 11081 xtensa_isa isa = xtensa_default_isa; 11082 xtensa_opcode opcode = tinsn->opcode; 11083 bfd_boolean has_fixup = FALSE; 11084 int noperands = xtensa_opcode_num_operands (isa, opcode); 11085 int i; 11086 11087 assert (tinsn->insn_type == ITYPE_INSN); 11088 if (noperands != tinsn->ntok) 11089 as_fatal (_("operand number mismatch")); 11090 11091 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) 11092 { 11093 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), 11094 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); 11095 return FALSE; 11096 } 11097 11098 for (i = 0; i < noperands; i++) 11099 { 11100 expressionS *expr = &tinsn->tok[i]; 11101 int rc; 11102 unsigned line; 11103 char *file_name; 11104 uint32 opnd_value; 11105 11106 switch (expr->X_op) 11107 { 11108 case O_register: 11109 if (xtensa_operand_is_visible (isa, opcode, i) == 0) 11110 break; 11111 /* The register number has already been checked in 11112 expression_maybe_register, so we don't need to check here. */ 11113 opnd_value = expr->X_add_number; 11114 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); 11115 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, 11116 opnd_value); 11117 if (rc != 0) 11118 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); 11119 break; 11120 11121 case O_constant: 11122 if (xtensa_operand_is_visible (isa, opcode, i) == 0) 11123 break; 11124 as_where (&file_name, &line); 11125 /* It is a constant and we called this function 11126 then we have to try to fit it. */ 11127 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, 11128 expr->X_add_number, file_name, line); 11129 break; 11130 11131 default: 11132 has_fixup = TRUE; 11133 break; 11134 } 11135 } 11136 11137 return has_fixup; 11138 } 11139 11140 11141 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded 11142 into a multi-slot instruction, fill the other slots with NOPs. 11143 Return TRUE if there is a symbol in the immediate field. See also the 11144 assumptions listed for tinsn_to_slotbuf. */ 11145 11146 static bfd_boolean 11147 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) 11148 { 11149 static xtensa_insnbuf slotbuf = 0; 11150 static vliw_insn vinsn; 11151 xtensa_isa isa = xtensa_default_isa; 11152 bfd_boolean has_fixup = FALSE; 11153 int i; 11154 11155 if (!slotbuf) 11156 { 11157 slotbuf = xtensa_insnbuf_alloc (isa); 11158 xg_init_vinsn (&vinsn); 11159 } 11160 11161 xg_clear_vinsn (&vinsn); 11162 11163 bundle_tinsn (tinsn, &vinsn); 11164 11165 xtensa_format_encode (isa, vinsn.format, insnbuf); 11166 11167 for (i = 0; i < vinsn.num_slots; i++) 11168 { 11169 /* Only one slot may have a fix-up because the rest contains NOPs. */ 11170 has_fixup |= 11171 tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); 11172 xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); 11173 } 11174 11175 return has_fixup; 11176 } 11177 11178 11179 /* Check the instruction arguments. Return TRUE on failure. */ 11180 11181 static bfd_boolean 11182 tinsn_check_arguments (const TInsn *insn) 11183 { 11184 xtensa_isa isa = xtensa_default_isa; 11185 xtensa_opcode opcode = insn->opcode; 11186 11187 if (opcode == XTENSA_UNDEFINED) 11188 { 11189 as_bad (_("invalid opcode")); 11190 return TRUE; 11191 } 11192 11193 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) 11194 { 11195 as_bad (_("too few operands")); 11196 return TRUE; 11197 } 11198 11199 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) 11200 { 11201 as_bad (_("too many operands")); 11202 return TRUE; 11203 } 11204 return FALSE; 11205 } 11206 11207 11208 /* Load an instruction from its encoded form. */ 11209 11210 static void 11211 tinsn_from_chars (TInsn *tinsn, char *f, int slot) 11212 { 11213 vliw_insn vinsn; 11214 11215 xg_init_vinsn (&vinsn); 11216 vinsn_from_chars (&vinsn, f); 11217 11218 *tinsn = vinsn.slots[slot]; 11219 xg_free_vinsn (&vinsn); 11220 } 11221 11222 11223 static void 11224 tinsn_from_insnbuf (TInsn *tinsn, 11225 xtensa_insnbuf slotbuf, 11226 xtensa_format fmt, 11227 int slot) 11228 { 11229 int i; 11230 xtensa_isa isa = xtensa_default_isa; 11231 11232 /* Find the immed. */ 11233 tinsn_init (tinsn); 11234 tinsn->insn_type = ITYPE_INSN; 11235 tinsn->is_specific_opcode = FALSE; /* must not be specific */ 11236 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 11237 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); 11238 for (i = 0; i < tinsn->ntok; i++) 11239 { 11240 set_expr_const (&tinsn->tok[i], 11241 xtensa_insnbuf_get_operand (slotbuf, fmt, slot, 11242 tinsn->opcode, i)); 11243 } 11244 } 11245 11246 11247 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ 11248 11249 static void 11250 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) 11251 { 11252 xtensa_opcode opcode = tinsn->opcode; 11253 int opnum; 11254 11255 if (fragP->tc_frag_data.slot_symbols[slot]) 11256 { 11257 opnum = get_relaxable_immed (opcode); 11258 assert (opnum >= 0); 11259 set_expr_symbol_offset (&tinsn->tok[opnum], 11260 fragP->tc_frag_data.slot_symbols[slot], 11261 fragP->tc_frag_data.slot_offsets[slot]); 11262 } 11263 } 11264 11265 11266 static int 11267 get_num_stack_text_bytes (IStack *istack) 11268 { 11269 int i; 11270 int text_bytes = 0; 11271 11272 for (i = 0; i < istack->ninsn; i++) 11273 { 11274 TInsn *tinsn = &istack->insn[i]; 11275 if (tinsn->insn_type == ITYPE_INSN) 11276 text_bytes += xg_get_single_size (tinsn->opcode); 11277 } 11278 return text_bytes; 11279 } 11280 11281 11282 static int 11283 get_num_stack_literal_bytes (IStack *istack) 11284 { 11285 int i; 11286 int lit_bytes = 0; 11287 11288 for (i = 0; i < istack->ninsn; i++) 11289 { 11290 TInsn *tinsn = &istack->insn[i]; 11291 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) 11292 lit_bytes += 4; 11293 } 11294 return lit_bytes; 11295 } 11296 11297 11298 /* vliw_insn functions. */ 11299 11300 static void 11301 xg_init_vinsn (vliw_insn *v) 11302 { 11303 int i; 11304 xtensa_isa isa = xtensa_default_isa; 11305 11306 xg_clear_vinsn (v); 11307 11308 v->insnbuf = xtensa_insnbuf_alloc (isa); 11309 if (v->insnbuf == NULL) 11310 as_fatal (_("out of memory")); 11311 11312 for (i = 0; i < MAX_SLOTS; i++) 11313 { 11314 v->slotbuf[i] = xtensa_insnbuf_alloc (isa); 11315 if (v->slotbuf[i] == NULL) 11316 as_fatal (_("out of memory")); 11317 } 11318 } 11319 11320 11321 static void 11322 xg_clear_vinsn (vliw_insn *v) 11323 { 11324 int i; 11325 11326 memset (v, 0, offsetof (vliw_insn, insnbuf)); 11327 11328 v->format = XTENSA_UNDEFINED; 11329 v->num_slots = 0; 11330 v->inside_bundle = FALSE; 11331 11332 if (xt_saved_debug_type != DEBUG_NONE) 11333 debug_type = xt_saved_debug_type; 11334 11335 for (i = 0; i < MAX_SLOTS; i++) 11336 v->slots[i].opcode = XTENSA_UNDEFINED; 11337 } 11338 11339 11340 static bfd_boolean 11341 vinsn_has_specific_opcodes (vliw_insn *v) 11342 { 11343 int i; 11344 11345 for (i = 0; i < v->num_slots; i++) 11346 { 11347 if (v->slots[i].is_specific_opcode) 11348 return TRUE; 11349 } 11350 return FALSE; 11351 } 11352 11353 11354 static void 11355 xg_free_vinsn (vliw_insn *v) 11356 { 11357 int i; 11358 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); 11359 for (i = 0; i < MAX_SLOTS; i++) 11360 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); 11361 } 11362 11363 11364 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic 11365 operands. See also the assumptions listed for tinsn_to_slotbuf. */ 11366 11367 static bfd_boolean 11368 vinsn_to_insnbuf (vliw_insn *vinsn, 11369 char *frag_offset, 11370 fragS *fragP, 11371 bfd_boolean record_fixup) 11372 { 11373 xtensa_isa isa = xtensa_default_isa; 11374 xtensa_format fmt = vinsn->format; 11375 xtensa_insnbuf insnbuf = vinsn->insnbuf; 11376 int slot; 11377 bfd_boolean has_fixup = FALSE; 11378 11379 xtensa_format_encode (isa, fmt, insnbuf); 11380 11381 for (slot = 0; slot < vinsn->num_slots; slot++) 11382 { 11383 TInsn *tinsn = &vinsn->slots[slot]; 11384 bfd_boolean tinsn_has_fixup = 11385 tinsn_to_slotbuf (vinsn->format, slot, tinsn, 11386 vinsn->slotbuf[slot]); 11387 11388 xtensa_format_set_slot (isa, fmt, slot, 11389 insnbuf, vinsn->slotbuf[slot]); 11390 if (tinsn_has_fixup) 11391 { 11392 int i; 11393 xtensa_opcode opcode = tinsn->opcode; 11394 int noperands = xtensa_opcode_num_operands (isa, opcode); 11395 has_fixup = TRUE; 11396 11397 for (i = 0; i < noperands; i++) 11398 { 11399 expressionS* expr = &tinsn->tok[i]; 11400 switch (expr->X_op) 11401 { 11402 case O_symbol: 11403 case O_lo16: 11404 case O_hi16: 11405 if (get_relaxable_immed (opcode) == i) 11406 { 11407 /* Add a fix record for the instruction, except if this 11408 function is being called prior to relaxation, i.e., 11409 if record_fixup is false, and the instruction might 11410 be relaxed later. */ 11411 if (record_fixup 11412 || tinsn->is_specific_opcode 11413 || !xg_is_relaxable_insn (tinsn, 0)) 11414 { 11415 xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, 11416 frag_offset - fragP->fr_literal); 11417 } 11418 else 11419 { 11420 if (expr->X_op != O_symbol) 11421 as_bad (_("invalid operand")); 11422 tinsn->symbol = expr->X_add_symbol; 11423 tinsn->offset = expr->X_add_number; 11424 } 11425 } 11426 else 11427 as_bad (_("symbolic operand not allowed")); 11428 break; 11429 11430 case O_constant: 11431 case O_register: 11432 break; 11433 11434 default: 11435 as_bad (_("expression too complex")); 11436 break; 11437 } 11438 } 11439 } 11440 } 11441 11442 return has_fixup; 11443 } 11444 11445 11446 static void 11447 vinsn_from_chars (vliw_insn *vinsn, char *f) 11448 { 11449 static xtensa_insnbuf insnbuf = NULL; 11450 static xtensa_insnbuf slotbuf = NULL; 11451 int i; 11452 xtensa_format fmt; 11453 xtensa_isa isa = xtensa_default_isa; 11454 11455 if (!insnbuf) 11456 { 11457 insnbuf = xtensa_insnbuf_alloc (isa); 11458 slotbuf = xtensa_insnbuf_alloc (isa); 11459 } 11460 11461 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); 11462 fmt = xtensa_format_decode (isa, insnbuf); 11463 if (fmt == XTENSA_UNDEFINED) 11464 as_fatal (_("cannot decode instruction format")); 11465 vinsn->format = fmt; 11466 vinsn->num_slots = xtensa_format_num_slots (isa, fmt); 11467 11468 for (i = 0; i < vinsn->num_slots; i++) 11469 { 11470 TInsn *tinsn = &vinsn->slots[i]; 11471 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); 11472 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); 11473 } 11474 } 11475 11476 11477 /* Expression utilities. */ 11478 11479 /* Return TRUE if the expression is an integer constant. */ 11480 11481 bfd_boolean 11482 expr_is_const (const expressionS *s) 11483 { 11484 return (s->X_op == O_constant); 11485 } 11486 11487 11488 /* Get the expression constant. 11489 Calling this is illegal if expr_is_const () returns TRUE. */ 11490 11491 offsetT 11492 get_expr_const (const expressionS *s) 11493 { 11494 assert (expr_is_const (s)); 11495 return s->X_add_number; 11496 } 11497 11498 11499 /* Set the expression to a constant value. */ 11500 11501 void 11502 set_expr_const (expressionS *s, offsetT val) 11503 { 11504 s->X_op = O_constant; 11505 s->X_add_number = val; 11506 s->X_add_symbol = NULL; 11507 s->X_op_symbol = NULL; 11508 } 11509 11510 11511 bfd_boolean 11512 expr_is_register (const expressionS *s) 11513 { 11514 return (s->X_op == O_register); 11515 } 11516 11517 11518 /* Get the expression constant. 11519 Calling this is illegal if expr_is_const () returns TRUE. */ 11520 11521 offsetT 11522 get_expr_register (const expressionS *s) 11523 { 11524 assert (expr_is_register (s)); 11525 return s->X_add_number; 11526 } 11527 11528 11529 /* Set the expression to a symbol + constant offset. */ 11530 11531 void 11532 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) 11533 { 11534 s->X_op = O_symbol; 11535 s->X_add_symbol = sym; 11536 s->X_op_symbol = NULL; /* unused */ 11537 s->X_add_number = offset; 11538 } 11539 11540 11541 /* Return TRUE if the two expressions are equal. */ 11542 11543 bfd_boolean 11544 expr_is_equal (expressionS *s1, expressionS *s2) 11545 { 11546 if (s1->X_op != s2->X_op) 11547 return FALSE; 11548 if (s1->X_add_symbol != s2->X_add_symbol) 11549 return FALSE; 11550 if (s1->X_op_symbol != s2->X_op_symbol) 11551 return FALSE; 11552 if (s1->X_add_number != s2->X_add_number) 11553 return FALSE; 11554 return TRUE; 11555 } 11556 11557 11558 static void 11559 copy_expr (expressionS *dst, const expressionS *src) 11560 { 11561 memcpy (dst, src, sizeof (expressionS)); 11562 } 11563 11564 11565 /* Support for the "--rename-section" option. */ 11566 11567 struct rename_section_struct 11568 { 11569 char *old_name; 11570 char *new_name; 11571 struct rename_section_struct *next; 11572 }; 11573 11574 static struct rename_section_struct *section_rename; 11575 11576 11577 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add 11578 entries to the section_rename list. Note: Specifying multiple 11579 renamings separated by colons is not documented and is retained only 11580 for backward compatibility. */ 11581 11582 static void 11583 build_section_rename (const char *arg) 11584 { 11585 struct rename_section_struct *r; 11586 char *this_arg = NULL; 11587 char *next_arg = NULL; 11588 11589 for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) 11590 { 11591 char *old_name, *new_name; 11592 11593 if (this_arg) 11594 { 11595 next_arg = strchr (this_arg, ':'); 11596 if (next_arg) 11597 { 11598 *next_arg = '\0'; 11599 next_arg++; 11600 } 11601 } 11602 11603 old_name = this_arg; 11604 new_name = strchr (this_arg, '='); 11605 11606 if (*old_name == '\0') 11607 { 11608 as_warn (_("ignoring extra '-rename-section' delimiter ':'")); 11609 continue; 11610 } 11611 if (!new_name || new_name[1] == '\0') 11612 { 11613 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), 11614 old_name); 11615 continue; 11616 } 11617 *new_name = '\0'; 11618 new_name++; 11619 11620 /* Check for invalid section renaming. */ 11621 for (r = section_rename; r != NULL; r = r->next) 11622 { 11623 if (strcmp (r->old_name, old_name) == 0) 11624 as_bad (_("section %s renamed multiple times"), old_name); 11625 if (strcmp (r->new_name, new_name) == 0) 11626 as_bad (_("multiple sections remapped to output section %s"), 11627 new_name); 11628 } 11629 11630 /* Now add it. */ 11631 r = (struct rename_section_struct *) 11632 xmalloc (sizeof (struct rename_section_struct)); 11633 r->old_name = xstrdup (old_name); 11634 r->new_name = xstrdup (new_name); 11635 r->next = section_rename; 11636 section_rename = r; 11637 } 11638 } 11639 11640 11641 char * 11642 xtensa_section_rename (char *name) 11643 { 11644 struct rename_section_struct *r = section_rename; 11645 11646 for (r = section_rename; r != NULL; r = r->next) 11647 { 11648 if (strcmp (r->old_name, name) == 0) 11649 return r->new_name; 11650 } 11651 11652 return name; 11653 } 11654