13d8817e4Smiod /* opcode/i386.h -- Intel 80386 opcode table 23d8817e4Smiod Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 33d8817e4Smiod 2000, 2001, 2002, 2003, 2004, 2005 43d8817e4Smiod Free Software Foundation, Inc. 53d8817e4Smiod 63d8817e4Smiod This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. 73d8817e4Smiod 83d8817e4Smiod This program is free software; you can redistribute it and/or modify 93d8817e4Smiod it under the terms of the GNU General Public License as published by 103d8817e4Smiod the Free Software Foundation; either version 2 of the License, or 113d8817e4Smiod (at your option) any later version. 123d8817e4Smiod 133d8817e4Smiod This program is distributed in the hope that it will be useful, 143d8817e4Smiod but WITHOUT ANY WARRANTY; without even the implied warranty of 153d8817e4Smiod MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 163d8817e4Smiod GNU General Public License for more details. 173d8817e4Smiod 183d8817e4Smiod You should have received a copy of the GNU General Public License 193d8817e4Smiod along with this program; if not, write to the Free Software 203d8817e4Smiod Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 213d8817e4Smiod 223d8817e4Smiod /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived 233d8817e4Smiod ix86 Unix assemblers, generate floating point instructions with 243d8817e4Smiod reversed source and destination registers in certain cases. 253d8817e4Smiod Unfortunately, gcc and possibly many other programs use this 263d8817e4Smiod reversed syntax, so we're stuck with it. 273d8817e4Smiod 283d8817e4Smiod eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but 293d8817e4Smiod `fsub %st,%st(3)' results in st(3) = st - st(3), rather than 303d8817e4Smiod the expected st(3) = st(3) - st 313d8817e4Smiod 323d8817e4Smiod This happens with all the non-commutative arithmetic floating point 333d8817e4Smiod operations with two register operands, where the source register is 343d8817e4Smiod %st, and destination register is %st(i). See FloatDR below. 353d8817e4Smiod 363d8817e4Smiod The affected opcode map is dceX, dcfX, deeX, defX. */ 373d8817e4Smiod 383d8817e4Smiod #ifndef SYSV386_COMPAT 393d8817e4Smiod /* Set non-zero for broken, compatible instructions. Set to zero for 403d8817e4Smiod non-broken opcodes at your peril. gcc generates SystemV/386 413d8817e4Smiod compatible instructions. */ 423d8817e4Smiod #define SYSV386_COMPAT 1 433d8817e4Smiod #endif 443d8817e4Smiod #ifndef OLDGCC_COMPAT 453d8817e4Smiod /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could 463d8817e4Smiod generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands 473d8817e4Smiod reversed. */ 483d8817e4Smiod #define OLDGCC_COMPAT SYSV386_COMPAT 493d8817e4Smiod #endif 503d8817e4Smiod 513d8817e4Smiod static const template i386_optab[] = 523d8817e4Smiod { 533d8817e4Smiod 543d8817e4Smiod #define X None 553d8817e4Smiod #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) 563d8817e4Smiod #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) 573d8817e4Smiod #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) 583d8817e4Smiod #define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf) 593d8817e4Smiod #define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) 603d8817e4Smiod #define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf) 613d8817e4Smiod #define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf) 623d8817e4Smiod #define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf) 633d8817e4Smiod #define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf) 643d8817e4Smiod #define wlq_Suf (No_bSuf|No_sSuf|No_xSuf) 653d8817e4Smiod #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf) 663d8817e4Smiod #define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf) 673d8817e4Smiod #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf) 683d8817e4Smiod #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf) 693d8817e4Smiod #define bwlq_Suf (No_sSuf|No_xSuf) 703d8817e4Smiod #define FP (NoSuf) 713d8817e4Smiod #define l_FP (l_Suf) 723d8817e4Smiod #define q_FP (q_Suf|NoRex64) 733d8817e4Smiod #define x_FP (x_Suf|FloatMF) 743d8817e4Smiod #define sl_FP (sl_Suf|FloatMF) 753d8817e4Smiod #if SYSV386_COMPAT 763d8817e4Smiod /* Someone forgot that the FloatR bit reverses the operation when not 773d8817e4Smiod equal to the FloatD bit. ie. Changing only FloatD results in the 783d8817e4Smiod destination being swapped *and* the direction being reversed. */ 793d8817e4Smiod #define FloatDR FloatD 803d8817e4Smiod #else 813d8817e4Smiod #define FloatDR (FloatD|FloatR) 823d8817e4Smiod #endif 833d8817e4Smiod 843d8817e4Smiod /* Move instructions. */ 853d8817e4Smiod #define MOV_AX_DISP32 0xa0 863d8817e4Smiod /* We put the 64bit displacement first and we only mark constants 873d8817e4Smiod larger than 32bit as Disp64. */ 883d8817e4Smiod { "mov", 2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, 893d8817e4Smiod { "mov", 2, 0xa0, X, CpuNo64,bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, 903d8817e4Smiod { "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 913d8817e4Smiod /* In the 64bit mode the short form mov immediate is redefined to have 923d8817e4Smiod 64bit value. */ 933d8817e4Smiod { "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } }, 943d8817e4Smiod { "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } }, 953d8817e4Smiod { "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, 963d8817e4Smiod /* The segment register moves accept WordReg so that a segment register 973d8817e4Smiod can be copied to a 32 bit register, and vice versa, without using a 983d8817e4Smiod size prefix. When moving to a 32 bit register, the upper 16 bits 993d8817e4Smiod are set to an implementation defined value (on the Pentium Pro, 1003d8817e4Smiod the implementation defined value is zero). */ 1013d8817e4Smiod { "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|InvMem, 0 } }, 1023d8817e4Smiod { "mov", 2, 0x8c, X, 0, w_Suf|Modrm|IgnoreSize, { SReg2, WordMem, 0 } }, 1033d8817e4Smiod { "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|InvMem, 0 } }, 1043d8817e4Smiod { "mov", 2, 0x8c, X, Cpu386, w_Suf|Modrm|IgnoreSize, { SReg3, WordMem, 0 } }, 1053d8817e4Smiod { "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg2, 0 } }, 1063d8817e4Smiod { "mov", 2, 0x8e, X, 0, w_Suf|Modrm|IgnoreSize, { WordMem, SReg2, 0 } }, 1073d8817e4Smiod { "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg3, 0 } }, 1083d8817e4Smiod { "mov", 2, 0x8e, X, Cpu386, w_Suf|Modrm|IgnoreSize, { WordMem, SReg3, 0 } }, 1093d8817e4Smiod /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit 1103d8817e4Smiod mode they are 64bit.*/ 1113d8817e4Smiod { "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} }, 1123d8817e4Smiod { "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, 1133d8817e4Smiod { "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, 1143d8817e4Smiod { "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, 1153d8817e4Smiod { "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, 1163d8817e4Smiod { "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, 1173d8817e4Smiod { "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, 1183d8817e4Smiod 1193d8817e4Smiod /* Move with sign extend. */ 1203d8817e4Smiod /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid 1213d8817e4Smiod conflict with the "movs" string move instruction. */ 1223d8817e4Smiod {"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, 1233d8817e4Smiod {"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, 1243d8817e4Smiod {"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} }, 1253d8817e4Smiod {"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, 1263d8817e4Smiod {"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} }, 1273d8817e4Smiod {"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, 1283d8817e4Smiod /* Intel Syntax next 3 insns */ 1293d8817e4Smiod {"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, 1303d8817e4Smiod {"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} }, 1313d8817e4Smiod {"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, 1323d8817e4Smiod 1333d8817e4Smiod /* Move with zero extend. We can't remove "movzb" since existing 1343d8817e4Smiod assembly codes may use it. */ 1353d8817e4Smiod {"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, 1363d8817e4Smiod /* "movzbl" & "movzbw" should not be unified into "movzb" for 1373d8817e4Smiod consistency with the sign extending moves above. */ 1383d8817e4Smiod {"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, 1393d8817e4Smiod {"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, 1403d8817e4Smiod {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, 1413d8817e4Smiod /* These instructions are not particulary useful, since the zero extend 1423d8817e4Smiod 32->64 is implicit, but we can encode them. */ 1433d8817e4Smiod {"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, 1443d8817e4Smiod {"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, 1453d8817e4Smiod /* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful, 1463d8817e4Smiod since the zero extend 32->64 is implicit, but we can encode them). */ 1473d8817e4Smiod {"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, 1483d8817e4Smiod {"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} }, 1493d8817e4Smiod 1503d8817e4Smiod /* Push instructions. */ 1513d8817e4Smiod {"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, 1523d8817e4Smiod {"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, 1533d8817e4Smiod {"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, 1543d8817e4Smiod {"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, 1553d8817e4Smiod {"push", 1, 0x06, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, 1563d8817e4Smiod {"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, 1573d8817e4Smiod /* In 64bit mode, the operand size is implicitly 64bit. */ 1583d8817e4Smiod {"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, 1593d8817e4Smiod {"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, 1603d8817e4Smiod {"push", 1, 0x6a, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, 1613d8817e4Smiod {"push", 1, 0x68, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} }, 1623d8817e4Smiod {"push", 1, 0x0fa0, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, 1633d8817e4Smiod 1643d8817e4Smiod {"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, 1653d8817e4Smiod 1663d8817e4Smiod /* Pop instructions. */ 1673d8817e4Smiod {"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, 1683d8817e4Smiod {"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, 1693d8817e4Smiod #define POP_SEG_SHORT 0x07 1703d8817e4Smiod {"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, 1713d8817e4Smiod {"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, 1723d8817e4Smiod /* In 64bit mode, the operand size is implicitly 64bit. */ 1733d8817e4Smiod {"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, 1743d8817e4Smiod {"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, 1753d8817e4Smiod {"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, 1763d8817e4Smiod 1773d8817e4Smiod {"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, 1783d8817e4Smiod 1793d8817e4Smiod /* Exchange instructions. 1803d8817e4Smiod xchg commutes: we allow both operand orders. 1813d8817e4Smiod 1823d8817e4Smiod In the 64bit code, xchg eax, eax is reused for new nop instruction. */ 1833d8817e4Smiod #if 0 /* While the two entries that are disabled generate shorter code 1843d8817e4Smiod for xchg eax, reg (on x86_64), the special case xchg eax, eax 1853d8817e4Smiod does not get handled correctly - it degenerates into nop, but 1863d8817e4Smiod that way the side effect of zero-extending eax to rax is lost. */ 1873d8817e4Smiod {"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } }, 1883d8817e4Smiod {"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } }, 1893d8817e4Smiod #else 1903d8817e4Smiod {"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, 1913d8817e4Smiod {"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, 1923d8817e4Smiod {"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Reg16|Reg64, Acc, 0 } }, 1933d8817e4Smiod {"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Acc, Reg16|Reg64, 0 } }, 1943d8817e4Smiod #endif 1953d8817e4Smiod {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, 1963d8817e4Smiod {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, 1973d8817e4Smiod 1983d8817e4Smiod /* In/out from ports. */ 1993d8817e4Smiod /* XXX should reject %rax */ 2003d8817e4Smiod {"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } }, 2013d8817e4Smiod {"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, 2023d8817e4Smiod {"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, 2033d8817e4Smiod {"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, 2043d8817e4Smiod {"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } }, 2053d8817e4Smiod {"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, 2063d8817e4Smiod {"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, 2073d8817e4Smiod {"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, 2083d8817e4Smiod 2093d8817e4Smiod /* Load effective address. */ 2103d8817e4Smiod {"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } }, 2113d8817e4Smiod 2123d8817e4Smiod /* Load segment registers from memory. */ 2133d8817e4Smiod {"lds", 2, 0xc5, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, 2143d8817e4Smiod {"les", 2, 0xc4, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, 2153d8817e4Smiod {"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, 2163d8817e4Smiod {"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, 2173d8817e4Smiod {"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, 2183d8817e4Smiod 2193d8817e4Smiod /* Flags register instructions. */ 2203d8817e4Smiod {"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} }, 2213d8817e4Smiod {"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} }, 2223d8817e4Smiod {"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} }, 2233d8817e4Smiod {"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} }, 2243d8817e4Smiod {"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} }, 2253d8817e4Smiod {"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} }, 2263d8817e4Smiod {"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} }, 2273d8817e4Smiod {"pushf", 0, 0x9c, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, 2283d8817e4Smiod {"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, 2293d8817e4Smiod {"popf", 0, 0x9d, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, 2303d8817e4Smiod {"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, 2313d8817e4Smiod {"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, 2323d8817e4Smiod {"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, 2333d8817e4Smiod {"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} }, 2343d8817e4Smiod 2353d8817e4Smiod /* Arithmetic. */ 2363d8817e4Smiod {"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 2373d8817e4Smiod {"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 2383d8817e4Smiod {"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 2393d8817e4Smiod {"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 2403d8817e4Smiod 2413d8817e4Smiod {"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} }, 2423d8817e4Smiod {"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 2433d8817e4Smiod 2443d8817e4Smiod {"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 2453d8817e4Smiod {"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 2463d8817e4Smiod {"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 2473d8817e4Smiod {"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 2483d8817e4Smiod 2493d8817e4Smiod {"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} }, 2503d8817e4Smiod {"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 2513d8817e4Smiod 2523d8817e4Smiod {"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 2533d8817e4Smiod {"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 2543d8817e4Smiod {"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 2553d8817e4Smiod {"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 2563d8817e4Smiod 2573d8817e4Smiod {"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 2583d8817e4Smiod {"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 2593d8817e4Smiod {"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 2603d8817e4Smiod {"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 2613d8817e4Smiod 2623d8817e4Smiod {"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, 2633d8817e4Smiod {"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, 2643d8817e4Smiod {"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 2653d8817e4Smiod {"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 2663d8817e4Smiod 2673d8817e4Smiod {"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 2683d8817e4Smiod {"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 2693d8817e4Smiod {"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 2703d8817e4Smiod {"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 2713d8817e4Smiod 2723d8817e4Smiod {"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 2733d8817e4Smiod {"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 2743d8817e4Smiod {"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 2753d8817e4Smiod {"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 2763d8817e4Smiod 2773d8817e4Smiod {"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 2783d8817e4Smiod {"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 2793d8817e4Smiod {"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 2803d8817e4Smiod {"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 2813d8817e4Smiod 2823d8817e4Smiod /* clr with 1 operand is really xor with 2 operands. */ 2833d8817e4Smiod {"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, 2843d8817e4Smiod 2853d8817e4Smiod {"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 2863d8817e4Smiod {"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 2873d8817e4Smiod {"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 2883d8817e4Smiod {"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 2893d8817e4Smiod 2903d8817e4Smiod {"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 2913d8817e4Smiod {"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 2923d8817e4Smiod 2933d8817e4Smiod {"aaa", 0, 0x37, X, CpuNo64, NoSuf, { 0, 0, 0} }, 2943d8817e4Smiod {"aas", 0, 0x3f, X, CpuNo64, NoSuf, { 0, 0, 0} }, 2953d8817e4Smiod {"daa", 0, 0x27, X, CpuNo64, NoSuf, { 0, 0, 0} }, 2963d8817e4Smiod {"das", 0, 0x2f, X, CpuNo64, NoSuf, { 0, 0, 0} }, 2973d8817e4Smiod {"aad", 0, 0xd50a, X, CpuNo64, NoSuf, { 0, 0, 0} }, 2983d8817e4Smiod {"aad", 1, 0xd5, X, CpuNo64, NoSuf, { Imm8, 0, 0} }, 2993d8817e4Smiod {"aam", 0, 0xd40a, X, CpuNo64, NoSuf, { 0, 0, 0} }, 3003d8817e4Smiod {"aam", 1, 0xd4, X, CpuNo64, NoSuf, { Imm8, 0, 0} }, 3013d8817e4Smiod 3023d8817e4Smiod /* Conversion insns. */ 3033d8817e4Smiod /* Intel naming */ 3043d8817e4Smiod {"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, 3053d8817e4Smiod {"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, 3063d8817e4Smiod {"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, 3073d8817e4Smiod {"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, 3083d8817e4Smiod {"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, 3093d8817e4Smiod {"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, 3103d8817e4Smiod /* AT&T naming */ 3113d8817e4Smiod {"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, 3123d8817e4Smiod {"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, 3133d8817e4Smiod {"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, 3143d8817e4Smiod {"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, 3153d8817e4Smiod {"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, 3163d8817e4Smiod {"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, 3173d8817e4Smiod 3183d8817e4Smiod /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are 3193d8817e4Smiod expanding 64-bit multiplies, and *cannot* be selected to accomplish 3203d8817e4Smiod 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) 3213d8817e4Smiod These multiplies can only be selected with single operand forms. */ 3223d8817e4Smiod {"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3233d8817e4Smiod {"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3243d8817e4Smiod {"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 3253d8817e4Smiod {"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, 3263d8817e4Smiod {"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} }, 3273d8817e4Smiod /* imul with 2 operands mimics imul with 3 by putting the register in 3283d8817e4Smiod both i.rm.reg & i.rm.regmem fields. regKludge enables this 3293d8817e4Smiod transformation. */ 3303d8817e4Smiod {"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, 3313d8817e4Smiod {"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} }, 3323d8817e4Smiod 3333d8817e4Smiod {"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3343d8817e4Smiod {"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, 3353d8817e4Smiod {"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3363d8817e4Smiod {"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, 3373d8817e4Smiod 3383d8817e4Smiod {"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 3393d8817e4Smiod {"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 3403d8817e4Smiod {"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 3413d8817e4Smiod {"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3423d8817e4Smiod 3433d8817e4Smiod {"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 3443d8817e4Smiod {"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 3453d8817e4Smiod {"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 3463d8817e4Smiod {"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3473d8817e4Smiod 3483d8817e4Smiod {"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 3493d8817e4Smiod {"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 3503d8817e4Smiod {"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 3513d8817e4Smiod {"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3523d8817e4Smiod 3533d8817e4Smiod {"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 3543d8817e4Smiod {"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 3553d8817e4Smiod {"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 3563d8817e4Smiod {"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3573d8817e4Smiod 3583d8817e4Smiod {"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 3593d8817e4Smiod {"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 3603d8817e4Smiod {"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 3613d8817e4Smiod {"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3623d8817e4Smiod 3633d8817e4Smiod {"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 3643d8817e4Smiod {"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 3653d8817e4Smiod {"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 3663d8817e4Smiod {"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3673d8817e4Smiod 3683d8817e4Smiod {"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 3693d8817e4Smiod {"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 3703d8817e4Smiod {"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 3713d8817e4Smiod {"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3723d8817e4Smiod 3733d8817e4Smiod {"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 3743d8817e4Smiod {"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 3753d8817e4Smiod {"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 3763d8817e4Smiod {"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 3773d8817e4Smiod 3783d8817e4Smiod {"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, 3793d8817e4Smiod {"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, 3803d8817e4Smiod {"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 3813d8817e4Smiod 3823d8817e4Smiod {"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, 3833d8817e4Smiod {"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, 3843d8817e4Smiod {"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 3853d8817e4Smiod 3863d8817e4Smiod /* Control transfer instructions. */ 3873d8817e4Smiod {"call", 1, 0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, 3883d8817e4Smiod {"call", 1, 0xe8, X, Cpu64, wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} }, 3893d8817e4Smiod {"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, 3903d8817e4Smiod {"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} }, 3913d8817e4Smiod /* Intel Syntax */ 3923d8817e4Smiod {"call", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, 3933d8817e4Smiod /* Intel Syntax */ 3943d8817e4Smiod {"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, 3953d8817e4Smiod {"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} }, 3963d8817e4Smiod {"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, 3973d8817e4Smiod 3983d8817e4Smiod #define JUMP_PC_RELATIVE 0xeb 3993d8817e4Smiod {"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp,0, 0} }, 4003d8817e4Smiod {"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, 4013d8817e4Smiod {"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} }, 4023d8817e4Smiod /* Intel Syntax. */ 4033d8817e4Smiod {"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, 4043d8817e4Smiod /* Intel Syntax. */ 4053d8817e4Smiod {"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, 4063d8817e4Smiod {"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, 4073d8817e4Smiod {"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, 4083d8817e4Smiod 4093d8817e4Smiod {"ret", 0, 0xc3, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, 4103d8817e4Smiod {"ret", 1, 0xc2, X, CpuNo64,wl_Suf|DefaultSize, { Imm16, 0, 0} }, 4113d8817e4Smiod {"ret", 0, 0xc3, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, 4123d8817e4Smiod {"ret", 1, 0xc2, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} }, 4133d8817e4Smiod {"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, 4143d8817e4Smiod {"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} }, 4153d8817e4Smiod {"enter", 2, 0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, 4163d8817e4Smiod {"enter", 2, 0xc8, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm16, Imm8, 0} }, 4173d8817e4Smiod {"leave", 0, 0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0} }, 4183d8817e4Smiod {"leave", 0, 0xc9, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { 0, 0, 0} }, 4193d8817e4Smiod 4203d8817e4Smiod /* Conditional jumps. */ 4213d8817e4Smiod {"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4223d8817e4Smiod {"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4233d8817e4Smiod {"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4243d8817e4Smiod {"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4253d8817e4Smiod {"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4263d8817e4Smiod {"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4273d8817e4Smiod {"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4283d8817e4Smiod {"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4293d8817e4Smiod {"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4303d8817e4Smiod {"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4313d8817e4Smiod {"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4323d8817e4Smiod {"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4333d8817e4Smiod {"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4343d8817e4Smiod {"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4353d8817e4Smiod {"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4363d8817e4Smiod {"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4373d8817e4Smiod {"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4383d8817e4Smiod {"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4393d8817e4Smiod {"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4403d8817e4Smiod {"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4413d8817e4Smiod {"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4423d8817e4Smiod {"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4433d8817e4Smiod {"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4443d8817e4Smiod {"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4453d8817e4Smiod {"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4463d8817e4Smiod {"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4473d8817e4Smiod {"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4483d8817e4Smiod {"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4493d8817e4Smiod {"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4503d8817e4Smiod {"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 4513d8817e4Smiod 4523d8817e4Smiod /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ 4533d8817e4Smiod {"jcxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} }, 4543d8817e4Smiod {"jecxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, 4553d8817e4Smiod {"jecxz", 1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, 4563d8817e4Smiod {"jrcxz", 1, 0xe3, X, Cpu64, NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} }, 4573d8817e4Smiod 4583d8817e4Smiod /* The loop instructions also use the address size prefix to select 4593d8817e4Smiod %cx rather than %ecx for the loop count, so the `w' form of these 4603d8817e4Smiod instructions emit an address size prefix rather than a data size 4613d8817e4Smiod prefix. */ 4623d8817e4Smiod {"loop", 1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, 4633d8817e4Smiod {"loop", 1, 0xe2, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, 4643d8817e4Smiod {"loopz", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, 4653d8817e4Smiod {"loopz", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, 4663d8817e4Smiod {"loope", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, 4673d8817e4Smiod {"loope", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, 4683d8817e4Smiod {"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, 4693d8817e4Smiod {"loopnz", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, 4703d8817e4Smiod {"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, 4713d8817e4Smiod {"loopne", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, 4723d8817e4Smiod 4733d8817e4Smiod /* Set byte on flag instructions. */ 4743d8817e4Smiod {"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4753d8817e4Smiod {"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4763d8817e4Smiod {"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4773d8817e4Smiod {"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4783d8817e4Smiod {"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4793d8817e4Smiod {"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4803d8817e4Smiod {"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4813d8817e4Smiod {"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4823d8817e4Smiod {"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4833d8817e4Smiod {"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4843d8817e4Smiod {"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4853d8817e4Smiod {"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4863d8817e4Smiod {"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4873d8817e4Smiod {"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4883d8817e4Smiod {"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4893d8817e4Smiod {"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4903d8817e4Smiod {"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4913d8817e4Smiod {"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4923d8817e4Smiod {"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4933d8817e4Smiod {"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4943d8817e4Smiod {"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4953d8817e4Smiod {"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4963d8817e4Smiod {"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4973d8817e4Smiod {"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4983d8817e4Smiod {"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 4993d8817e4Smiod {"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 5003d8817e4Smiod {"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 5013d8817e4Smiod {"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 5023d8817e4Smiod {"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 5033d8817e4Smiod {"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 5043d8817e4Smiod 5053d8817e4Smiod /* String manipulation. */ 5063d8817e4Smiod {"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 5073d8817e4Smiod {"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, 5083d8817e4Smiod {"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 5093d8817e4Smiod {"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, 5103d8817e4Smiod {"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, 5113d8817e4Smiod {"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, 5123d8817e4Smiod {"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, 5133d8817e4Smiod {"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, 5143d8817e4Smiod {"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 5153d8817e4Smiod {"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, 5163d8817e4Smiod {"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, 5173d8817e4Smiod {"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 5183d8817e4Smiod {"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, 5193d8817e4Smiod {"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, 5203d8817e4Smiod {"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 5213d8817e4Smiod {"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, 5223d8817e4Smiod {"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 5233d8817e4Smiod {"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, 5243d8817e4Smiod {"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 5253d8817e4Smiod {"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 5263d8817e4Smiod {"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, 5273d8817e4Smiod {"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 5283d8817e4Smiod {"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 5293d8817e4Smiod {"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, 5303d8817e4Smiod {"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 5313d8817e4Smiod {"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 5323d8817e4Smiod {"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, 5333d8817e4Smiod {"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 5343d8817e4Smiod {"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 5353d8817e4Smiod {"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, 5363d8817e4Smiod {"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} }, 5373d8817e4Smiod {"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} }, 5383d8817e4Smiod 5393d8817e4Smiod /* Bit manipulation. */ 5403d8817e4Smiod {"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 5413d8817e4Smiod {"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 5423d8817e4Smiod {"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 5433d8817e4Smiod {"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 5443d8817e4Smiod {"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 5453d8817e4Smiod {"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 5463d8817e4Smiod {"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 5473d8817e4Smiod {"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 5483d8817e4Smiod {"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 5493d8817e4Smiod {"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 5503d8817e4Smiod 5513d8817e4Smiod /* Interrupts & op. sys insns. */ 5523d8817e4Smiod /* See gas/config/tc-i386.c for conversion of 'int $3' into the special 5533d8817e4Smiod int 3 insn. */ 5543d8817e4Smiod #define INT_OPCODE 0xcd 5553d8817e4Smiod #define INT3_OPCODE 0xcc 5563d8817e4Smiod {"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} }, 5573d8817e4Smiod {"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} }, 5583d8817e4Smiod {"into", 0, 0xce, X, CpuNo64, NoSuf, { 0, 0, 0} }, 5593d8817e4Smiod {"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, 5603d8817e4Smiod /* i386sl, i486sl, later 486, and Pentium. */ 5613d8817e4Smiod {"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} }, 5623d8817e4Smiod 5633d8817e4Smiod {"bound", 2, 0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm, { WordReg, WordMem, 0} }, 5643d8817e4Smiod 5653d8817e4Smiod {"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} }, 5663d8817e4Smiod /* nop is actually 'xchgl %eax, %eax'. */ 5673d8817e4Smiod {"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} }, 5683d8817e4Smiod 5693d8817e4Smiod /* Protection control. */ 5703d8817e4Smiod {"arpl", 2, 0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, 5713d8817e4Smiod {"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 5723d8817e4Smiod {"lgdt", 1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, 5733d8817e4Smiod {"lgdt", 1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, 5743d8817e4Smiod {"lidt", 1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, 5753d8817e4Smiod {"lidt", 1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, 5763d8817e4Smiod {"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 5773d8817e4Smiod {"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 5783d8817e4Smiod {"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 5793d8817e4Smiod {"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 5803d8817e4Smiod 5813d8817e4Smiod {"sgdt", 1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, 5823d8817e4Smiod {"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, 5833d8817e4Smiod {"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, 5843d8817e4Smiod {"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, 5853d8817e4Smiod {"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, 5863d8817e4Smiod {"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, 5873d8817e4Smiod {"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, 5883d8817e4Smiod {"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, 5893d8817e4Smiod {"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, 5903d8817e4Smiod {"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, 5913d8817e4Smiod 5923d8817e4Smiod {"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 5933d8817e4Smiod {"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 5943d8817e4Smiod 5953d8817e4Smiod /* Floating point instructions. */ 5963d8817e4Smiod 5973d8817e4Smiod /* load */ 5983d8817e4Smiod {"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 5993d8817e4Smiod {"fld", 1, 0xd9, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 6003d8817e4Smiod {"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, 6013d8817e4Smiod /* Intel Syntax */ 6023d8817e4Smiod {"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} }, 6033d8817e4Smiod {"fild", 1, 0xdf, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 6043d8817e4Smiod {"fild", 1, 0xdf, 5, 0, q_FP|Modrm, { LLongMem, 0, 0} }, 6053d8817e4Smiod {"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, 6063d8817e4Smiod {"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, 6073d8817e4Smiod {"fbld", 1, 0xdf, 4, 0, x_Suf|Modrm, { LLongMem, 0, 0} }, 6083d8817e4Smiod 6093d8817e4Smiod /* store (no pop) */ 6103d8817e4Smiod {"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 6113d8817e4Smiod {"fst", 1, 0xd9, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 6123d8817e4Smiod {"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, 6133d8817e4Smiod {"fist", 1, 0xdf, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 6143d8817e4Smiod 6153d8817e4Smiod /* store (with pop) */ 6163d8817e4Smiod {"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 6173d8817e4Smiod {"fstp", 1, 0xd9, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 6183d8817e4Smiod {"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, 6193d8817e4Smiod /* Intel Syntax */ 6203d8817e4Smiod {"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} }, 6213d8817e4Smiod {"fistp", 1, 0xdf, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 6223d8817e4Smiod {"fistp", 1, 0xdf, 7, 0, q_FP|Modrm, { LLongMem, 0, 0} }, 6233d8817e4Smiod {"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, 6243d8817e4Smiod {"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, 6253d8817e4Smiod {"fbstp", 1, 0xdf, 6, 0, x_Suf|Modrm, { LLongMem, 0, 0} }, 6263d8817e4Smiod 6273d8817e4Smiod /* exchange %st<n> with %st0 */ 6283d8817e4Smiod {"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 6293d8817e4Smiod /* alias for fxch %st(1) */ 6303d8817e4Smiod {"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} }, 6313d8817e4Smiod 6323d8817e4Smiod /* comparison (without pop) */ 6333d8817e4Smiod {"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 6343d8817e4Smiod /* alias for fcom %st(1) */ 6353d8817e4Smiod {"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} }, 6363d8817e4Smiod {"fcom", 1, 0xd8, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 6373d8817e4Smiod {"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, 6383d8817e4Smiod {"ficom", 1, 0xde, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 6393d8817e4Smiod 6403d8817e4Smiod /* comparison (with pop) */ 6413d8817e4Smiod {"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 6423d8817e4Smiod /* alias for fcomp %st(1) */ 6433d8817e4Smiod {"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} }, 6443d8817e4Smiod {"fcomp", 1, 0xd8, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 6453d8817e4Smiod {"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, 6463d8817e4Smiod {"ficomp", 1, 0xde, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 6473d8817e4Smiod {"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} }, 6483d8817e4Smiod 6493d8817e4Smiod /* unordered comparison (with pop) */ 6503d8817e4Smiod {"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, 6513d8817e4Smiod /* alias for fucom %st(1) */ 6523d8817e4Smiod {"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} }, 6533d8817e4Smiod {"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, 6543d8817e4Smiod /* alias for fucomp %st(1) */ 6553d8817e4Smiod {"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} }, 6563d8817e4Smiod {"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} }, 6573d8817e4Smiod 6583d8817e4Smiod {"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} }, 6593d8817e4Smiod {"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} }, 6603d8817e4Smiod 6613d8817e4Smiod /* load constants into %st0 */ 6623d8817e4Smiod {"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} }, 6633d8817e4Smiod {"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} }, 6643d8817e4Smiod {"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} }, 6653d8817e4Smiod {"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} }, 6663d8817e4Smiod {"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} }, 6673d8817e4Smiod {"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} }, 6683d8817e4Smiod {"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} }, 6693d8817e4Smiod 6703d8817e4Smiod /* Arithmetic. */ 6713d8817e4Smiod 6723d8817e4Smiod /* add */ 6733d8817e4Smiod {"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 6743d8817e4Smiod /* alias for fadd %st(i), %st */ 6753d8817e4Smiod {"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 6763d8817e4Smiod #if SYSV386_COMPAT 6773d8817e4Smiod /* alias for faddp */ 6783d8817e4Smiod {"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} }, 6793d8817e4Smiod #endif 6803d8817e4Smiod {"fadd", 1, 0xd8, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 6813d8817e4Smiod {"fiadd", 1, 0xde, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 6823d8817e4Smiod 6833d8817e4Smiod {"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 6843d8817e4Smiod {"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 6853d8817e4Smiod /* alias for faddp %st, %st(1) */ 6863d8817e4Smiod {"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} }, 6873d8817e4Smiod {"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 6883d8817e4Smiod 6893d8817e4Smiod /* subtract */ 6903d8817e4Smiod {"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 6913d8817e4Smiod {"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 6923d8817e4Smiod #if SYSV386_COMPAT 6933d8817e4Smiod /* alias for fsubp */ 6943d8817e4Smiod {"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} }, 6953d8817e4Smiod #endif 6963d8817e4Smiod {"fsub", 1, 0xd8, 4, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 6973d8817e4Smiod {"fisub", 1, 0xde, 4, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 6983d8817e4Smiod 6993d8817e4Smiod #if SYSV386_COMPAT 7003d8817e4Smiod {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 7013d8817e4Smiod {"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7023d8817e4Smiod {"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, 7033d8817e4Smiod #if OLDGCC_COMPAT 7043d8817e4Smiod {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 7053d8817e4Smiod #endif 7063d8817e4Smiod #else 7073d8817e4Smiod {"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 7083d8817e4Smiod {"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7093d8817e4Smiod {"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, 7103d8817e4Smiod #endif 7113d8817e4Smiod 7123d8817e4Smiod /* subtract reverse */ 7133d8817e4Smiod {"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 7143d8817e4Smiod {"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7153d8817e4Smiod #if SYSV386_COMPAT 7163d8817e4Smiod /* alias for fsubrp */ 7173d8817e4Smiod {"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} }, 7183d8817e4Smiod #endif 7193d8817e4Smiod {"fsubr", 1, 0xd8, 5, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 7203d8817e4Smiod {"fisubr", 1, 0xde, 5, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 7213d8817e4Smiod 7223d8817e4Smiod #if SYSV386_COMPAT 7233d8817e4Smiod {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 7243d8817e4Smiod {"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7253d8817e4Smiod {"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, 7263d8817e4Smiod #if OLDGCC_COMPAT 7273d8817e4Smiod {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 7283d8817e4Smiod #endif 7293d8817e4Smiod #else 7303d8817e4Smiod {"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 7313d8817e4Smiod {"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7323d8817e4Smiod {"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, 7333d8817e4Smiod #endif 7343d8817e4Smiod 7353d8817e4Smiod /* multiply */ 7363d8817e4Smiod {"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 7373d8817e4Smiod {"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7383d8817e4Smiod #if SYSV386_COMPAT 7393d8817e4Smiod /* alias for fmulp */ 7403d8817e4Smiod {"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} }, 7413d8817e4Smiod #endif 7423d8817e4Smiod {"fmul", 1, 0xd8, 1, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 7433d8817e4Smiod {"fimul", 1, 0xde, 1, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 7443d8817e4Smiod 7453d8817e4Smiod {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 7463d8817e4Smiod {"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7473d8817e4Smiod {"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} }, 7483d8817e4Smiod {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 7493d8817e4Smiod 7503d8817e4Smiod /* divide */ 7513d8817e4Smiod {"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 7523d8817e4Smiod {"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7533d8817e4Smiod #if SYSV386_COMPAT 7543d8817e4Smiod /* alias for fdivp */ 7553d8817e4Smiod {"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} }, 7563d8817e4Smiod #endif 7573d8817e4Smiod {"fdiv", 1, 0xd8, 6, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 7583d8817e4Smiod {"fidiv", 1, 0xde, 6, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 7593d8817e4Smiod 7603d8817e4Smiod #if SYSV386_COMPAT 7613d8817e4Smiod {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 7623d8817e4Smiod {"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7633d8817e4Smiod {"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, 7643d8817e4Smiod #if OLDGCC_COMPAT 7653d8817e4Smiod {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 7663d8817e4Smiod #endif 7673d8817e4Smiod #else 7683d8817e4Smiod {"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 7693d8817e4Smiod {"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7703d8817e4Smiod {"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, 7713d8817e4Smiod #endif 7723d8817e4Smiod 7733d8817e4Smiod /* divide reverse */ 7743d8817e4Smiod {"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 7753d8817e4Smiod {"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7763d8817e4Smiod #if SYSV386_COMPAT 7773d8817e4Smiod /* alias for fdivrp */ 7783d8817e4Smiod {"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} }, 7793d8817e4Smiod #endif 7803d8817e4Smiod {"fdivr", 1, 0xd8, 7, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, 7813d8817e4Smiod {"fidivr", 1, 0xde, 7, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 7823d8817e4Smiod 7833d8817e4Smiod #if SYSV386_COMPAT 7843d8817e4Smiod {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 7853d8817e4Smiod {"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7863d8817e4Smiod {"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, 7873d8817e4Smiod #if OLDGCC_COMPAT 7883d8817e4Smiod {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 7893d8817e4Smiod #endif 7903d8817e4Smiod #else 7913d8817e4Smiod {"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 7923d8817e4Smiod {"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 7933d8817e4Smiod {"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, 7943d8817e4Smiod #endif 7953d8817e4Smiod 7963d8817e4Smiod {"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} }, 7973d8817e4Smiod {"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} }, 7983d8817e4Smiod {"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} }, 7993d8817e4Smiod {"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} }, 8003d8817e4Smiod {"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} }, 8013d8817e4Smiod {"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} }, 8023d8817e4Smiod {"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} }, 8033d8817e4Smiod {"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} }, 8043d8817e4Smiod {"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} }, 8053d8817e4Smiod {"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} }, 8063d8817e4Smiod {"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} }, 8073d8817e4Smiod {"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} }, 8083d8817e4Smiod {"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} }, 8093d8817e4Smiod {"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} }, 8103d8817e4Smiod {"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} }, 8113d8817e4Smiod {"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} }, 8123d8817e4Smiod {"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} }, 8133d8817e4Smiod {"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} }, 8143d8817e4Smiod 8153d8817e4Smiod /* processor control */ 8163d8817e4Smiod {"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} }, 8173d8817e4Smiod {"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} }, 8183d8817e4Smiod {"fldcw", 1, 0xd9, 5, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, 8193d8817e4Smiod {"fnstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, 8203d8817e4Smiod {"fstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} }, 8213d8817e4Smiod /* XXX should reject %al, %eax, and %rax */ 8223d8817e4Smiod {"fnstsw", 1, 0xdfe0, X, 0, FP|IgnoreSize, { Acc, 0, 0} }, 8233d8817e4Smiod {"fnstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, 8243d8817e4Smiod {"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} }, 8253d8817e4Smiod /* XXX should reject %al, %eax, and %rax */ 8263d8817e4Smiod {"fstsw", 1, 0xdfe0, X, 0, FP|FWait|IgnoreSize, { Acc, 0, 0} }, 8273d8817e4Smiod {"fstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} }, 8283d8817e4Smiod {"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} }, 8293d8817e4Smiod {"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} }, 8303d8817e4Smiod {"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} }, 8313d8817e4Smiod /* Short forms of fldenv, fstenv use data size prefix. */ 8323d8817e4Smiod {"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, 8333d8817e4Smiod {"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} }, 8343d8817e4Smiod {"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, 8353d8817e4Smiod {"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, 8363d8817e4Smiod {"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} }, 8373d8817e4Smiod {"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, 8383d8817e4Smiod 8393d8817e4Smiod {"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 8403d8817e4Smiod /* P6:free st(i), pop st */ 8413d8817e4Smiod {"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 8423d8817e4Smiod {"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} }, 8433d8817e4Smiod #define FWAIT_OPCODE 0x9b 8443d8817e4Smiod {"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} }, 8453d8817e4Smiod 8463d8817e4Smiod /* Opcode prefixes; we allow them as separate insns too. */ 8473d8817e4Smiod 8483d8817e4Smiod #define ADDR_PREFIX_OPCODE 0x67 8493d8817e4Smiod {"addr16", 0, 0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 8503d8817e4Smiod {"addr32", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 8513d8817e4Smiod {"aword", 0, 0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 8523d8817e4Smiod {"adword", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 8533d8817e4Smiod #define DATA_PREFIX_OPCODE 0x66 8543d8817e4Smiod {"data16", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 8553d8817e4Smiod {"data32", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 8563d8817e4Smiod {"word", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 8573d8817e4Smiod {"dword", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 8583d8817e4Smiod #define LOCK_PREFIX_OPCODE 0xf0 8593d8817e4Smiod {"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8603d8817e4Smiod {"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8613d8817e4Smiod #define CS_PREFIX_OPCODE 0x2e 8623d8817e4Smiod {"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8633d8817e4Smiod #define DS_PREFIX_OPCODE 0x3e 8643d8817e4Smiod {"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8653d8817e4Smiod #define ES_PREFIX_OPCODE 0x26 8663d8817e4Smiod {"es", 0, 0x26, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, 8673d8817e4Smiod #define FS_PREFIX_OPCODE 0x64 8683d8817e4Smiod {"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, 8693d8817e4Smiod #define GS_PREFIX_OPCODE 0x65 8703d8817e4Smiod {"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, 8713d8817e4Smiod #define SS_PREFIX_OPCODE 0x36 8723d8817e4Smiod {"ss", 0, 0x36, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, 8733d8817e4Smiod #define REPNE_PREFIX_OPCODE 0xf2 8743d8817e4Smiod #define REPE_PREFIX_OPCODE 0xf3 8753d8817e4Smiod {"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8763d8817e4Smiod {"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8773d8817e4Smiod {"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8783d8817e4Smiod {"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8793d8817e4Smiod {"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8803d8817e4Smiod {"ht", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8813d8817e4Smiod {"hnt", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 8823d8817e4Smiod {"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8833d8817e4Smiod {"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8843d8817e4Smiod {"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8853d8817e4Smiod {"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8863d8817e4Smiod {"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8873d8817e4Smiod {"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8883d8817e4Smiod {"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8893d8817e4Smiod {"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8903d8817e4Smiod {"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8913d8817e4Smiod {"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8923d8817e4Smiod {"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8933d8817e4Smiod {"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8943d8817e4Smiod {"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8953d8817e4Smiod {"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8963d8817e4Smiod {"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8973d8817e4Smiod {"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 8983d8817e4Smiod 8993d8817e4Smiod /* 486 extensions. */ 9003d8817e4Smiod 9013d8817e4Smiod {"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } }, 9023d8817e4Smiod {"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, 9033d8817e4Smiod {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, 9043d8817e4Smiod {"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} }, 9053d8817e4Smiod {"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} }, 9063d8817e4Smiod {"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} }, 9073d8817e4Smiod 9083d8817e4Smiod /* 586 and late 486 extensions. */ 9093d8817e4Smiod {"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} }, 9103d8817e4Smiod 9113d8817e4Smiod /* Pentium extensions. */ 9123d8817e4Smiod {"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} }, 9133d8817e4Smiod {"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} }, 9143d8817e4Smiod {"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} }, 9153d8817e4Smiod {"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm, { LLongMem, 0, 0} }, 9163d8817e4Smiod 9173d8817e4Smiod /* Pentium II/Pentium Pro extensions. */ 9183d8817e4Smiod {"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} }, 9193d8817e4Smiod {"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} }, 9203d8817e4Smiod {"fxsave", 1, 0x0fae, 0, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, 9213d8817e4Smiod {"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, 9223d8817e4Smiod {"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, 9233d8817e4Smiod /* official undefined instr. */ 9243d8817e4Smiod {"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, 9253d8817e4Smiod /* alias for ud2 */ 9263d8817e4Smiod {"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, 9273d8817e4Smiod /* 2nd. official undefined instr. */ 9283d8817e4Smiod {"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} }, 9293d8817e4Smiod 9303d8817e4Smiod {"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9313d8817e4Smiod {"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9323d8817e4Smiod {"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9333d8817e4Smiod {"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9343d8817e4Smiod {"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9353d8817e4Smiod {"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9363d8817e4Smiod {"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9373d8817e4Smiod {"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9383d8817e4Smiod {"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9393d8817e4Smiod {"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9403d8817e4Smiod {"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9413d8817e4Smiod {"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9423d8817e4Smiod {"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9433d8817e4Smiod {"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9443d8817e4Smiod {"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9453d8817e4Smiod {"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9463d8817e4Smiod {"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9473d8817e4Smiod {"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9483d8817e4Smiod {"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9493d8817e4Smiod {"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9503d8817e4Smiod {"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9513d8817e4Smiod {"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9523d8817e4Smiod {"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9533d8817e4Smiod {"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9543d8817e4Smiod {"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9553d8817e4Smiod {"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9563d8817e4Smiod {"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9573d8817e4Smiod {"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 9583d8817e4Smiod 9593d8817e4Smiod {"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9603d8817e4Smiod {"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9613d8817e4Smiod {"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9623d8817e4Smiod {"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9633d8817e4Smiod {"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9643d8817e4Smiod {"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9653d8817e4Smiod {"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9663d8817e4Smiod {"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9673d8817e4Smiod {"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9683d8817e4Smiod {"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9693d8817e4Smiod {"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9703d8817e4Smiod {"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9713d8817e4Smiod 9723d8817e4Smiod {"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9733d8817e4Smiod {"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, 9743d8817e4Smiod {"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 9753d8817e4Smiod {"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9763d8817e4Smiod {"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, 9773d8817e4Smiod {"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 9783d8817e4Smiod {"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9793d8817e4Smiod {"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9803d8817e4Smiod {"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, 9813d8817e4Smiod {"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 9823d8817e4Smiod {"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 983dab0f388Smiod {"fucomip", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, 984dab0f388Smiod {"fucomip", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 9853d8817e4Smiod {"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 9863d8817e4Smiod {"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, 9873d8817e4Smiod {"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 9883d8817e4Smiod 9893d8817e4Smiod /* Pentium4 extensions. */ 9903d8817e4Smiod 9913d8817e4Smiod {"movnti", 2, 0x0fc3, X, CpuP4, wlq_Suf|Modrm, { WordReg, WordMem, 0 } }, 9923d8817e4Smiod {"clflush", 1, 0x0fae, 7, CpuP4, NoSuf|Modrm|IgnoreSize, { ByteMem, 0, 0 } }, 9933d8817e4Smiod {"lfence", 0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } }, 9943d8817e4Smiod {"mfence", 0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } }, 995e8ef1766Sguenther {"rdfsbase", 1, 0xf30fae, 0, CpuNEW, FP|Modrm, { Reg32|Reg64, 0, 0 } }, 996e8ef1766Sguenther {"rdgsbase", 1, 0xf30fae, 1, CpuNEW, FP|Modrm, { Reg32|Reg64, 0, 0 } }, 997e8ef1766Sguenther {"wrfsbase", 1, 0xf30fae, 2, CpuNEW, FP|Modrm, { Reg32|Reg64, 0, 0 } }, 998e8ef1766Sguenther {"wrgsbase", 1, 0xf30fae, 3, CpuNEW, FP|Modrm, { Reg32|Reg64, 0, 0 } }, 9993d8817e4Smiod {"pause", 0, 0xf390, X, CpuP4, NoSuf, { 0, 0, 0 } }, 10003d8817e4Smiod 10013d8817e4Smiod /* MMX/SSE2 instructions. */ 10023d8817e4Smiod 10033d8817e4Smiod {"emms", 0, 0x0f77, X, CpuMMX, NoSuf, { 0, 0, 0 } }, 10043d8817e4Smiod /* These really shouldn't allow for Reg64 (movq is the right mnemonic for 10053d8817e4Smiod copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's 10063d8817e4Smiod spec). AMD's spec, having been in existence for much longer, failed to 10073d8817e4Smiod recognize that and specified movd for 32- and 64-bit operations. */ 10083d8817e4Smiod {"movd", 2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } }, 10093d8817e4Smiod {"movd", 2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } }, 10103d8817e4Smiod {"movd", 2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegXMM, 0 } }, 10113d8817e4Smiod {"movd", 2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LongMem, 0 } }, 10123d8817e4Smiod /* In the 64bit mode the short form mov immediate is redefined to have 10133d8817e4Smiod 64bit displacement value. */ 10143d8817e4Smiod {"movq", 2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX|LLongMem, RegMMX, 0 } }, 10153d8817e4Smiod {"movq", 2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX, RegMMX|LLongMem, 0 } }, 10163d8817e4Smiod {"movq", 2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM|LLongMem, RegXMM, 0 } }, 10173d8817e4Smiod {"movq", 2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM, RegXMM|LLongMem, 0 } }, 10183d8817e4Smiod {"movq", 2, 0x0f6e, X, Cpu64, NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegMMX, 0 } }, 10193d8817e4Smiod {"movq", 2, 0x0f7e, X, Cpu64, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg64|LLongMem, 0 } }, 10203d8817e4Smiod {"movq", 2, 0x660f6e,X,Cpu64, NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegXMM, 0 } }, 10213d8817e4Smiod {"movq", 2, 0x660f7e,X,Cpu64, NoSuf|IgnoreSize|Modrm, { RegXMM, Reg64|LLongMem, 0 } }, 10223d8817e4Smiod /* We put the 64bit displacement first and we only mark constants 10233d8817e4Smiod larger than 32bit as Disp64. */ 10243d8817e4Smiod {"movq", 2, 0xa0, X, Cpu64, NoSuf|D|W|Size64, { Disp64, Acc, 0 } }, 10253d8817e4Smiod {"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } }, 10263d8817e4Smiod {"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } }, 10273d8817e4Smiod {"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, 10283d8817e4Smiod /* The segment register moves accept Reg64 so that a segment register 10293d8817e4Smiod can be copied to a 64 bit register, and vice versa. */ 10303d8817e4Smiod {"movq", 2, 0x8c, X, Cpu64, NoSuf|Modrm|Size64, { SReg2|SReg3, Reg64|InvMem, 0 } }, 10313d8817e4Smiod {"movq", 2, 0x8e, X, Cpu64, NoSuf|Modrm|Size64, { Reg64, SReg2|SReg3, 0 } }, 10323d8817e4Smiod /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit 10333d8817e4Smiod mode they are 64bit.*/ 10343d8817e4Smiod {"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} }, 10353d8817e4Smiod {"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} }, 10363d8817e4Smiod /* Real MMX instructions. */ 10373d8817e4Smiod {"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10383d8817e4Smiod {"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10393d8817e4Smiod {"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10403d8817e4Smiod {"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10413d8817e4Smiod {"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10423d8817e4Smiod {"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10433d8817e4Smiod {"paddb", 2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10443d8817e4Smiod {"paddb", 2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10453d8817e4Smiod {"paddw", 2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10463d8817e4Smiod {"paddw", 2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10473d8817e4Smiod {"paddd", 2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10483d8817e4Smiod {"paddd", 2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10493d8817e4Smiod {"paddq", 2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 10503d8817e4Smiod {"paddq", 2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10513d8817e4Smiod {"paddsb", 2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10523d8817e4Smiod {"paddsb", 2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10533d8817e4Smiod {"paddsw", 2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10543d8817e4Smiod {"paddsw", 2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10553d8817e4Smiod {"paddusb", 2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10563d8817e4Smiod {"paddusb", 2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10573d8817e4Smiod {"paddusw", 2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10583d8817e4Smiod {"paddusw", 2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10593d8817e4Smiod {"pand", 2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10603d8817e4Smiod {"pand", 2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10613d8817e4Smiod {"pandn", 2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10623d8817e4Smiod {"pandn", 2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10633d8817e4Smiod {"pcmpeqb", 2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10643d8817e4Smiod {"pcmpeqb", 2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10653d8817e4Smiod {"pcmpeqw", 2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10663d8817e4Smiod {"pcmpeqw", 2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10673d8817e4Smiod {"pcmpeqd", 2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10683d8817e4Smiod {"pcmpeqd", 2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10693d8817e4Smiod {"pcmpgtb", 2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10703d8817e4Smiod {"pcmpgtb", 2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10713d8817e4Smiod {"pcmpgtw", 2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10723d8817e4Smiod {"pcmpgtw", 2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10733d8817e4Smiod {"pcmpgtd", 2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10743d8817e4Smiod {"pcmpgtd", 2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10753d8817e4Smiod {"pmaddwd", 2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10763d8817e4Smiod {"pmaddwd", 2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10773d8817e4Smiod {"pmulhw", 2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10783d8817e4Smiod {"pmulhw", 2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10793d8817e4Smiod {"pmullw", 2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10803d8817e4Smiod {"pmullw", 2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10813d8817e4Smiod {"por", 2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10823d8817e4Smiod {"por", 2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10833d8817e4Smiod {"psllw", 2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10843d8817e4Smiod {"psllw", 2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10853d8817e4Smiod {"psllw", 2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, 10863d8817e4Smiod {"psllw", 2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, 10873d8817e4Smiod {"pslld", 2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10883d8817e4Smiod {"pslld", 2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10893d8817e4Smiod {"pslld", 2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, 10903d8817e4Smiod {"pslld", 2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, 10913d8817e4Smiod {"psllq", 2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10923d8817e4Smiod {"psllq", 2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10933d8817e4Smiod {"psllq", 2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, 10943d8817e4Smiod {"psllq", 2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, 10953d8817e4Smiod {"psraw", 2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 10963d8817e4Smiod {"psraw", 2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 10973d8817e4Smiod {"psraw", 2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, 10983d8817e4Smiod {"psraw", 2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, 10993d8817e4Smiod {"psrad", 2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11003d8817e4Smiod {"psrad", 2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11013d8817e4Smiod {"psrad", 2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, 11023d8817e4Smiod {"psrad", 2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, 11033d8817e4Smiod {"psrlw", 2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11043d8817e4Smiod {"psrlw", 2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11053d8817e4Smiod {"psrlw", 2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, 11063d8817e4Smiod {"psrlw", 2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, 11073d8817e4Smiod {"psrld", 2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11083d8817e4Smiod {"psrld", 2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11093d8817e4Smiod {"psrld", 2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, 11103d8817e4Smiod {"psrld", 2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, 11113d8817e4Smiod {"psrlq", 2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11123d8817e4Smiod {"psrlq", 2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11133d8817e4Smiod {"psrlq", 2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, 11143d8817e4Smiod {"psrlq", 2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, 11153d8817e4Smiod {"psubb", 2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11163d8817e4Smiod {"psubb", 2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11173d8817e4Smiod {"psubw", 2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11183d8817e4Smiod {"psubw", 2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11193d8817e4Smiod {"psubd", 2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11203d8817e4Smiod {"psubd", 2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11213d8817e4Smiod {"psubq", 2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 11223d8817e4Smiod {"psubq", 2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11233d8817e4Smiod {"psubsb", 2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11243d8817e4Smiod {"psubsb", 2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11253d8817e4Smiod {"psubsw", 2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11263d8817e4Smiod {"psubsw", 2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11273d8817e4Smiod {"psubusb", 2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11283d8817e4Smiod {"psubusb", 2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11293d8817e4Smiod {"psubusw", 2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11303d8817e4Smiod {"psubusw", 2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11313d8817e4Smiod {"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11323d8817e4Smiod {"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11333d8817e4Smiod {"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11343d8817e4Smiod {"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11353d8817e4Smiod {"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11363d8817e4Smiod {"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11373d8817e4Smiod {"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11383d8817e4Smiod {"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11393d8817e4Smiod {"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11403d8817e4Smiod {"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11413d8817e4Smiod {"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11423d8817e4Smiod {"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11433d8817e4Smiod {"pxor", 2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 11443d8817e4Smiod {"pxor", 2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11453d8817e4Smiod 11463d8817e4Smiod /* PIII Katmai New Instructions / SIMD instructions. */ 11473d8817e4Smiod 11483d8817e4Smiod {"addps", 2, 0x0f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11493d8817e4Smiod {"addss", 2, 0xf30f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 11503d8817e4Smiod {"andnps", 2, 0x0f55, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11513d8817e4Smiod {"andps", 2, 0x0f54, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 11523d8817e4Smiod {"cmpeqps", 2, 0x0fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 11533d8817e4Smiod {"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 11543d8817e4Smiod {"cmpleps", 2, 0x0fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 11553d8817e4Smiod {"cmpless", 2, 0xf30fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 11563d8817e4Smiod {"cmpltps", 2, 0x0fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 11573d8817e4Smiod {"cmpltss", 2, 0xf30fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 11583d8817e4Smiod {"cmpneqps", 2, 0x0fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 11593d8817e4Smiod {"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 11603d8817e4Smiod {"cmpnleps", 2, 0x0fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 11613d8817e4Smiod {"cmpnless", 2, 0xf30fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 11623d8817e4Smiod {"cmpnltps", 2, 0x0fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 11633d8817e4Smiod {"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 11643d8817e4Smiod {"cmpordps", 2, 0x0fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 11653d8817e4Smiod {"cmpordss", 2, 0xf30fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 11663d8817e4Smiod {"cmpunordps",2, 0x0fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 11673d8817e4Smiod {"cmpunordss",2, 0xf30fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 11683d8817e4Smiod {"cmpps", 3, 0x0fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 11693d8817e4Smiod {"cmpss", 3, 0xf30fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, 11703d8817e4Smiod {"comiss", 2, 0x0f2f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 11713d8817e4Smiod {"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, 11723d8817e4Smiod {"cvtps2pi", 2, 0x0f2d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, 11733d8817e4Smiod {"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, 11743d8817e4Smiod {"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, 11753d8817e4Smiod {"cvttps2pi", 2, 0x0f2c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, 11763d8817e4Smiod {"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } }, 11773d8817e4Smiod {"divps", 2, 0x0f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11783d8817e4Smiod {"divss", 2, 0xf30f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 11793d8817e4Smiod {"ldmxcsr", 1, 0x0fae, 2, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } }, 11803d8817e4Smiod {"maskmovq", 2, 0x0ff7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, 11813d8817e4Smiod {"maxps", 2, 0x0f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11823d8817e4Smiod {"maxss", 2, 0xf30f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 11833d8817e4Smiod {"minps", 2, 0x0f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11843d8817e4Smiod {"minss", 2, 0xf30f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 11853d8817e4Smiod {"movaps", 2, 0x0f28, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 11863d8817e4Smiod {"movaps", 2, 0x0f29, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 11873d8817e4Smiod {"movhlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, 11883d8817e4Smiod {"movhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, 11893d8817e4Smiod {"movhps", 2, 0x0f17, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, 11903d8817e4Smiod {"movlhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, 11913d8817e4Smiod {"movlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, 11923d8817e4Smiod {"movlps", 2, 0x0f13, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, 11933d8817e4Smiod {"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, 11943d8817e4Smiod {"movntps", 2, 0x0f2b, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, 11953d8817e4Smiod {"movntq", 2, 0x0fe7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, LLongMem, 0 } }, 11963d8817e4Smiod {"movntdq", 2, 0x660fe7, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, 11973d8817e4Smiod {"movss", 2, 0xf30f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 11983d8817e4Smiod {"movss", 2, 0xf30f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, 11993d8817e4Smiod {"movups", 2, 0x0f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12003d8817e4Smiod {"movups", 2, 0x0f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 12013d8817e4Smiod {"mulps", 2, 0x0f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12023d8817e4Smiod {"mulss", 2, 0xf30f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 12033d8817e4Smiod {"orps", 2, 0x0f56, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12043d8817e4Smiod {"pavgb", 2, 0x0fe0, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 12053d8817e4Smiod {"pavgb", 2, 0x660fe0, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12063d8817e4Smiod {"pavgw", 2, 0x0fe3, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 12073d8817e4Smiod {"pavgw", 2, 0x660fe3, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12083d8817e4Smiod {"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } }, 12093d8817e4Smiod {"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } }, 12103d8817e4Smiod {"pinsrw", 3, 0x0fc4, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } }, 12113d8817e4Smiod {"pinsrw", 3, 0x660fc4, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } }, 12123d8817e4Smiod {"pmaxsw", 2, 0x0fee, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 12133d8817e4Smiod {"pmaxsw", 2, 0x660fee, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12143d8817e4Smiod {"pmaxub", 2, 0x0fde, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 12153d8817e4Smiod {"pmaxub", 2, 0x660fde, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12163d8817e4Smiod {"pminsw", 2, 0x0fea, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 12173d8817e4Smiod {"pminsw", 2, 0x660fea, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12183d8817e4Smiod {"pminub", 2, 0x0fda, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 12193d8817e4Smiod {"pminub", 2, 0x660fda, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12203d8817e4Smiod {"pmovmskb", 2, 0x0fd7, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } }, 12213d8817e4Smiod {"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, 12223d8817e4Smiod {"pmulhuw", 2, 0x0fe4, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 12233d8817e4Smiod {"pmulhuw", 2, 0x660fe4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12243d8817e4Smiod {"prefetchnta", 1, 0x0f18, 0, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, 12253d8817e4Smiod {"prefetcht0", 1, 0x0f18, 1, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, 12263d8817e4Smiod {"prefetcht1", 1, 0x0f18, 2, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, 12273d8817e4Smiod {"prefetcht2", 1, 0x0f18, 3, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, 12283d8817e4Smiod {"psadbw", 2, 0x0ff6, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 12293d8817e4Smiod {"psadbw", 2, 0x660ff6, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12303d8817e4Smiod {"pshufw", 3, 0x0f70, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, 12313d8817e4Smiod {"rcpps", 2, 0x0f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12323d8817e4Smiod {"rcpss", 2, 0xf30f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 12333d8817e4Smiod {"rsqrtps", 2, 0x0f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12343d8817e4Smiod {"rsqrtss", 2, 0xf30f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 12353d8817e4Smiod {"sfence", 0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } }, 12363d8817e4Smiod {"shufps", 3, 0x0fc6, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 12373d8817e4Smiod {"sqrtps", 2, 0x0f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12383d8817e4Smiod {"sqrtss", 2, 0xf30f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 12393d8817e4Smiod {"stmxcsr", 1, 0x0fae, 3, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } }, 12403d8817e4Smiod {"subps", 2, 0x0f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12413d8817e4Smiod {"subss", 2, 0xf30f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 12423d8817e4Smiod {"ucomiss", 2, 0x0f2e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 12433d8817e4Smiod {"unpckhps", 2, 0x0f15, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12443d8817e4Smiod {"unpcklps", 2, 0x0f14, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12453d8817e4Smiod {"xorps", 2, 0x0f57, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12463d8817e4Smiod 12473d8817e4Smiod /* SSE-2 instructions. */ 12483d8817e4Smiod 12493d8817e4Smiod {"addpd", 2, 0x660f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12503d8817e4Smiod {"addsd", 2, 0xf20f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 12513d8817e4Smiod {"andnpd", 2, 0x660f55, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12523d8817e4Smiod {"andpd", 2, 0x660f54, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 12533d8817e4Smiod {"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 12543d8817e4Smiod {"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 12553d8817e4Smiod {"cmplepd", 2, 0x660fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 12563d8817e4Smiod {"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 12573d8817e4Smiod {"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 12583d8817e4Smiod {"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 12593d8817e4Smiod {"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 12603d8817e4Smiod {"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 12613d8817e4Smiod {"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 12623d8817e4Smiod {"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 12633d8817e4Smiod {"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 12643d8817e4Smiod {"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 12653d8817e4Smiod {"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 12663d8817e4Smiod {"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 12673d8817e4Smiod {"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 12683d8817e4Smiod {"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 12693d8817e4Smiod {"cmppd", 3, 0x660fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 12703d8817e4Smiod /* Intel mode string compare. */ 12713d8817e4Smiod {"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, 12723d8817e4Smiod {"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, 12733d8817e4Smiod {"cmpsd", 3, 0xf20fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, 12743d8817e4Smiod {"comisd", 2, 0x660f2f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 12753d8817e4Smiod {"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, 12763d8817e4Smiod {"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, 12773d8817e4Smiod {"divpd", 2, 0x660f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12783d8817e4Smiod {"divsd", 2, 0xf20f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 12793d8817e4Smiod {"maxpd", 2, 0x660f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12803d8817e4Smiod {"maxsd", 2, 0xf20f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 12813d8817e4Smiod {"minpd", 2, 0x660f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12823d8817e4Smiod {"minsd", 2, 0xf20f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 12833d8817e4Smiod {"movapd", 2, 0x660f28, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12843d8817e4Smiod {"movapd", 2, 0x660f29, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 12853d8817e4Smiod {"movhpd", 2, 0x660f16, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, 12863d8817e4Smiod {"movhpd", 2, 0x660f17, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, 12873d8817e4Smiod {"movlpd", 2, 0x660f12, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, 12883d8817e4Smiod {"movlpd", 2, 0x660f13, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, 12893d8817e4Smiod {"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, 12903d8817e4Smiod {"movntpd", 2, 0x660f2b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, 12913d8817e4Smiod /* Intel mode string move. */ 12923d8817e4Smiod {"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, 12933d8817e4Smiod {"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, 12943d8817e4Smiod {"movsd", 2, 0xf20f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 12953d8817e4Smiod {"movsd", 2, 0xf20f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, 12963d8817e4Smiod {"movupd", 2, 0x660f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12973d8817e4Smiod {"movupd", 2, 0x660f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 12983d8817e4Smiod {"mulpd", 2, 0x660f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 12993d8817e4Smiod {"mulsd", 2, 0xf20f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 13003d8817e4Smiod {"orpd", 2, 0x660f56, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13013d8817e4Smiod {"shufpd", 3, 0x660fc6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 13023d8817e4Smiod {"sqrtpd", 2, 0x660f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13033d8817e4Smiod {"sqrtsd", 2, 0xf20f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 13043d8817e4Smiod {"subpd", 2, 0x660f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13053d8817e4Smiod {"subsd", 2, 0xf20f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 13063d8817e4Smiod {"ucomisd", 2, 0x660f2e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 13073d8817e4Smiod {"unpckhpd", 2, 0x660f15, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13083d8817e4Smiod {"unpcklpd", 2, 0x660f14, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13093d8817e4Smiod {"xorpd", 2, 0x660f57, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13103d8817e4Smiod {"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13113d8817e4Smiod {"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13123d8817e4Smiod {"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13133d8817e4Smiod {"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, 13143d8817e4Smiod {"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13153d8817e4Smiod {"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13163d8817e4Smiod {"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13173d8817e4Smiod {"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } }, 13183d8817e4Smiod {"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13193d8817e4Smiod {"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13203d8817e4Smiod {"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, 13213d8817e4Smiod {"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, 13223d8817e4Smiod {"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13233d8817e4Smiod {"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13243d8817e4Smiod {"maskmovdqu",2, 0x660ff7, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, 13253d8817e4Smiod {"movdqa", 2, 0x660f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13263d8817e4Smiod {"movdqa", 2, 0x660f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 13273d8817e4Smiod {"movdqu", 2, 0xf30f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13283d8817e4Smiod {"movdqu", 2, 0xf30f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 13293d8817e4Smiod {"movdq2q", 2, 0xf20fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegMMX, 0 } }, 13303d8817e4Smiod {"movq2dq", 2, 0xf30fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegXMM, 0 } }, 13313d8817e4Smiod {"pmuludq", 2, 0x0ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 13323d8817e4Smiod {"pmuludq", 2, 0x660ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 13333d8817e4Smiod {"pshufd", 3, 0x660f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 13343d8817e4Smiod {"pshufhw", 3, 0xf30f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 13353d8817e4Smiod {"pshuflw", 3, 0xf20f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 13363d8817e4Smiod {"pslldq", 2, 0x660f73, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, 13373d8817e4Smiod {"psrldq", 2, 0x660f73, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, 13383d8817e4Smiod {"punpckhqdq",2, 0x660f6d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13393d8817e4Smiod {"punpcklqdq",2, 0x660f6c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13403d8817e4Smiod 13413d8817e4Smiod /* Prescott New Instructions. */ 13423d8817e4Smiod 13433d8817e4Smiod {"addsubpd", 2, 0x660fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13443d8817e4Smiod {"addsubps", 2, 0xf20fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13453d8817e4Smiod {"cmpxchg16b",1, 0x0fc7, 1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} }, 13463d8817e4Smiod {"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, 13473d8817e4Smiod {"fisttp", 1, 0xdd, 1, CpuPNI, q_FP|Modrm, { LLongMem, 0, 0} }, 13483d8817e4Smiod {"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, 13493d8817e4Smiod {"haddpd", 2, 0x660f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13503d8817e4Smiod {"haddps", 2, 0xf20f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13513d8817e4Smiod {"hsubpd", 2, 0x660f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13523d8817e4Smiod {"hsubps", 2, 0xf20f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13533d8817e4Smiod {"lddqu", 2, 0xf20ff0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, 13543d8817e4Smiod {"monitor", 0, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} }, 13553d8817e4Smiod /* monitor is very special. CX and DX are always 64bits with zero upper 13563d8817e4Smiod 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. The 13573d8817e4Smiod address size override prefix can be used to overrride the AX size in 13583d8817e4Smiod all modes. */ 13593d8817e4Smiod /* Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. */ 13603d8817e4Smiod {"monitor", 3, 0x0f01, 0xc8, CpuPNI|CpuNo64, NoSuf|ImmExt, { Reg16|Reg32, Reg32, Reg32 } }, 13613d8817e4Smiod /* Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. */ 13623d8817e4Smiod {"monitor", 3, 0x0f01, 0xc8, CpuPNI|Cpu64, NoSuf|ImmExt|NoRex64, { Reg32|Reg64, Reg64, Reg64 } }, 13633d8817e4Smiod {"movddup", 2, 0xf20f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13643d8817e4Smiod {"movshdup", 2, 0xf30f16, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13653d8817e4Smiod {"movsldup", 2, 0xf30f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13663d8817e4Smiod {"mwait", 0, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} }, 13673d8817e4Smiod /* mwait is very special. AX and CX are always 64bits with zero upper 13683d8817e4Smiod 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. */ 13693d8817e4Smiod /* Need to ensure only "mwait %eax,%ecx" is accepted. */ 13703d8817e4Smiod {"mwait", 2, 0x0f01, 0xc9, CpuPNI|CpuNo64, NoSuf|ImmExt, { Reg32, Reg32, 0} }, 13713d8817e4Smiod /* Need to ensure only "mwait %rax,%rcx" is accepted. */ 13723d8817e4Smiod {"mwait", 2, 0x0f01, 0xc9, CpuPNI|Cpu64, NoSuf|ImmExt|NoRex64, { Reg64, Reg64, 0} }, 13733d8817e4Smiod 13743d8817e4Smiod /* VMX instructions. */ 1375c035e489Smlarkin {"invept", 2, 0x660f3880, X, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, 1376c035e489Smlarkin {"invept", 2, 0x660f3880, X, CpuVMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, 1377c035e489Smlarkin {"invvpid", 2, 0x660f3881, X, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, 1378c035e489Smlarkin {"invvpid", 2, 0x660f3881, X, CpuVMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, 13793d8817e4Smiod {"vmcall", 0, 0x0f01, 0xc1, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, 13803d8817e4Smiod {"vmclear", 1, 0x660fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, 13813d8817e4Smiod {"vmlaunch", 0, 0x0f01, 0xc2, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, 13823d8817e4Smiod {"vmresume", 0, 0x0f01, 0xc3, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, 13833d8817e4Smiod {"vmptrld", 1, 0x0fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, 13843d8817e4Smiod {"vmptrst", 1, 0x0fc7, 7, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, 13853d8817e4Smiod {"vmread", 2, 0x0f78, X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32, Reg32|LongMem, 0} }, 13863d8817e4Smiod {"vmread", 2, 0x0f78, X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64, Reg64|LLongMem, 0} }, 13873d8817e4Smiod {"vmwrite", 2, 0x0f79, X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32|LongMem, Reg32, 0} }, 13883d8817e4Smiod {"vmwrite", 2, 0x0f79, X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64|LLongMem, Reg64, 0} }, 13893d8817e4Smiod {"vmxoff", 0, 0x0f01, 0xc4, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, 13903d8817e4Smiod {"vmxon", 1, 0xf30fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, 13913d8817e4Smiod 13923d8817e4Smiod /* Merom New Instructions. */ 13933d8817e4Smiod 13943d8817e4Smiod {"phaddw", 2, 0x0f3801,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 13953d8817e4Smiod {"phaddw", 2, 0x660f3801,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13963d8817e4Smiod {"phaddd", 2, 0x0f3802,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 13973d8817e4Smiod {"phaddd", 2, 0x660f3802,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 13983d8817e4Smiod {"phaddsw", 2, 0x0f3803,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 13993d8817e4Smiod {"phaddsw", 2, 0x660f3803,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14003d8817e4Smiod {"phsubw", 2, 0x0f3805,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14013d8817e4Smiod {"phsubw", 2, 0x660f3805,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14023d8817e4Smiod {"phsubd", 2, 0x0f3806,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14033d8817e4Smiod {"phsubd", 2, 0x660f3806,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14043d8817e4Smiod {"phsubsw", 2, 0x0f3807,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14053d8817e4Smiod {"phsubsw", 2, 0x660f3807,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14063d8817e4Smiod {"pmaddubsw", 2, 0x0f3804,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14073d8817e4Smiod {"pmaddubsw", 2, 0x660f3804,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14083d8817e4Smiod {"pmulhrsw", 2, 0x0f380b,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14093d8817e4Smiod {"pmulhrsw", 2, 0x660f380b,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14103d8817e4Smiod {"pshufb", 2, 0x0f3800,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14113d8817e4Smiod {"pshufb", 2, 0x660f3800,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14123d8817e4Smiod {"psignb", 2, 0x0f3808,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14133d8817e4Smiod {"psignb", 2, 0x660f3808,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14143d8817e4Smiod {"psignw", 2, 0x0f3809,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14153d8817e4Smiod {"psignw", 2, 0x660f3809,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14163d8817e4Smiod {"psignd", 2, 0x0f380a,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14173d8817e4Smiod {"psignd", 2, 0x660f380a,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14183d8817e4Smiod {"palignr", 3, 0x0f3a0f,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LongMem, RegMMX } }, 14193d8817e4Smiod {"palignr", 3, 0x660f3a0f,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 14203d8817e4Smiod {"pabsb", 2, 0x0f381c,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14213d8817e4Smiod {"pabsb", 2, 0x660f381c,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14223d8817e4Smiod {"pabsw", 2, 0x0f381d,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14233d8817e4Smiod {"pabsw", 2, 0x660f381d,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14243d8817e4Smiod {"pabsd", 2, 0x0f381e,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 14253d8817e4Smiod {"pabsd", 2, 0x660f381e,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 14263d8817e4Smiod 14273d8817e4Smiod /* AMD 3DNow! instructions. */ 14283d8817e4Smiod 14293d8817e4Smiod {"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, 14303d8817e4Smiod {"prefetchw",1, 0x0f0d, 1, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, 14313d8817e4Smiod {"femms", 0, 0x0f0e, X, Cpu3dnow, NoSuf, { 0, 0, 0 } }, 14323d8817e4Smiod {"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14333d8817e4Smiod {"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14343d8817e4Smiod {"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14353d8817e4Smiod {"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14363d8817e4Smiod {"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14373d8817e4Smiod {"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14383d8817e4Smiod {"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14393d8817e4Smiod {"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14403d8817e4Smiod {"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14413d8817e4Smiod {"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14423d8817e4Smiod {"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14433d8817e4Smiod {"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14443d8817e4Smiod {"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14453d8817e4Smiod {"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14463d8817e4Smiod {"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14473d8817e4Smiod {"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14483d8817e4Smiod {"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14493d8817e4Smiod {"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14503d8817e4Smiod {"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14513d8817e4Smiod {"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14523d8817e4Smiod {"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14533d8817e4Smiod {"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14543d8817e4Smiod {"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14553d8817e4Smiod {"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 14563d8817e4Smiod 14573d8817e4Smiod /* AMD extensions. */ 14583d8817e4Smiod {"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} }, 14593d8817e4Smiod {"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} }, 14603d8817e4Smiod {"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} }, 14613d8817e4Smiod {"rdtscp", 0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt, { 0, 0, 0} }, 14623d8817e4Smiod 14633d8817e4Smiod /* AMD Pacifica additions. */ 14643d8817e4Smiod {"clgi", 0, 0x0f01, 0xdd, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, 14653d8817e4Smiod {"invlpga", 0, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, 14663d8817e4Smiod /* Need to ensure only "invlpga ...,%ecx" is accepted. */ 14671b7f1d49Skettenis {"invlpga", 2, 0x0f01, 0xdf, CpuSVME|CpuNo64, NoSuf|ImmExt, { Reg32, Reg32, 0 } }, 14681b7f1d49Skettenis {"invlpga", 2, 0x0f01, 0xdf, CpuSVME|Cpu64, NoSuf|ImmExt|NoRex64, { Reg64, Reg32, 0 } }, 14693d8817e4Smiod {"skinit", 0, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, 14701b7f1d49Skettenis {"skinit", 1, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { Reg32, 0, 0 } }, 14713d8817e4Smiod {"stgi", 0, 0x0f01, 0xdc, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, 14723d8817e4Smiod {"vmload", 0, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, 14731b7f1d49Skettenis {"vmload", 1, 0x0f01, 0xda, CpuSVME|CpuNo64, NoSuf|ImmExt, { Reg32, 0, 0 } }, 14741b7f1d49Skettenis {"vmload", 1, 0x0f01, 0xda, CpuSVME|Cpu64, NoSuf|ImmExt|NoRex64, { Reg64, 0, 0 } }, 14753d8817e4Smiod {"vmmcall", 0, 0x0f01, 0xd9, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, 14763d8817e4Smiod {"vmrun", 0, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, 14771b7f1d49Skettenis {"vmrun", 1, 0x0f01, 0xd8, CpuSVME|CpuNo64, NoSuf|ImmExt, { Reg32, 0, 0 } }, 14781b7f1d49Skettenis {"vmrun", 1, 0x0f01, 0xd8, CpuSVME|Cpu64, NoSuf|ImmExt|NoRex64, { Reg64, 0, 0 } }, 14793d8817e4Smiod {"vmsave", 0, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, 14801b7f1d49Skettenis {"vmsave", 1, 0x0f01, 0xdb, CpuSVME|CpuNo64, NoSuf|ImmExt, { Reg32, 0, 0 } }, 14811b7f1d49Skettenis {"vmsave", 1, 0x0f01, 0xdb, CpuSVME|Cpu64, NoSuf|ImmExt|NoRex64, { Reg64, 0, 0 } }, 14823d8817e4Smiod 14833d8817e4Smiod /* VIA PadLock extensions. */ 14843d8817e4Smiod {"xstore-rng",0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14853d8817e4Smiod {"xcrypt-ecb",0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14863d8817e4Smiod {"xcrypt-cbc",0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14873d8817e4Smiod {"xcrypt-ctr",0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14883d8817e4Smiod {"xcrypt-cfb",0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14893d8817e4Smiod {"xcrypt-ofb",0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14903d8817e4Smiod {"montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14913d8817e4Smiod {"xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14923d8817e4Smiod {"xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14933d8817e4Smiod /* Aliases without hyphens. */ 14943d8817e4Smiod {"xstorerng", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14953d8817e4Smiod {"xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14963d8817e4Smiod {"xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14973d8817e4Smiod {"xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14983d8817e4Smiod {"xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 14993d8817e4Smiod {"xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 15003d8817e4Smiod /* Alias for xstore-rng. */ 15013d8817e4Smiod {"xstore", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, 15023d8817e4Smiod 1503d2386abeSmiod /* Intel AES extensions */ 1504d2386abeSmiod {"aesdec", 2, 0x660f38de, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1505d2386abeSmiod {"aesdeclast", 2, 0x660f38df, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1506d2386abeSmiod {"aesenc", 2, 0x660f38dc, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1507d2386abeSmiod {"aesenclast", 2, 0x660f38dd, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1508d2386abeSmiod {"aesimc", 2, 0x660f38db, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1509d2386abeSmiod {"aeskeygenassist", 3, 0x660f3adf, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM|LLongMem, RegXMM } }, 1510d2386abeSmiod 1511d2386abeSmiod /* Intel Carry-less Multiplication extensions */ 1512d2386abeSmiod {"pclmulqdq", 3, 0x660f3a44, X, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM|LLongMem, RegXMM } }, 1513d2386abeSmiod {"pclmullqlqdq", 2, 0x660f3a44, 0x0, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem, RegXMM } }, 1514d2386abeSmiod {"pclmulhqlqdq", 2, 0x660f3a44, 0x1, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem, RegXMM } }, 1515d2386abeSmiod {"pclmullqhqdq", 2, 0x660f3a44, 0x10, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem, RegXMM } }, 1516d2386abeSmiod {"pclmulhqhqdq", 2, 0x660f3a44, 0x11, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem, RegXMM } }, 1517d2386abeSmiod 15187e0148a2Skettenis /* Intel Random Number Generator extensions */ 1519e8ef1766Sguenther {"rdrand", 1, 0x0fc7, 0x6, CpuNEW, Modrm|NoSuf, { Reg16|Reg32|Reg64 } }, 1520e64e014eSjsg {"rdseed", 1, 0x0fc7, 0x7, CpuNEW, Modrm|NoSuf, { Reg16|Reg32|Reg64 } }, 15217e0148a2Skettenis 15225ef8804eSjsg /* Intel Supervisor Mode Access Prevention extensions */ 15235ef8804eSjsg {"clac", 0, 0x0f01, 0xca, CpuSMAP, NoSuf|ImmExt, { 0, 0, 0 } }, 15245ef8804eSjsg {"stac", 0, 0x0f01, 0xcb, CpuSMAP, NoSuf|ImmExt, { 0, 0, 0 } }, 15255ef8804eSjsg 15263d8cda5cSguenther /* Intel XSAVE extensions */ 15273d8cda5cSguenther {"xgetbv", 0, 0x0f01, 0xd0, CpuXSAVE, NoSuf|ImmExt, { 0, 0, 0 } }, 15283d8cda5cSguenther {"xsetbv", 0, 0x0f01, 0xd1, CpuXSAVE, NoSuf|ImmExt, { 0, 0, 0 } }, 15293d8cda5cSguenther {"xsave", 1, 0x0fae, 4, CpuXSAVE, q_Suf|Modrm, { LLongMem, 0, 0 } }, 15303d8cda5cSguenther {"xrstor", 1, 0x0fae, 5, CpuXSAVE, q_Suf|Modrm, { LLongMem, 0, 0 } }, 15313d8cda5cSguenther {"xsaveopt", 1, 0x0fae, 6, CpuXSAVE, q_Suf|Modrm, { LLongMem, 0, 0 } }, 15323d8cda5cSguenther 1533998c1271Sguenther /* Intel PCID extension */ 1534998c1271Sguenther {"invpcid", 2, 0x660f3882, X, CpuNEW|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, 1535998c1271Sguenther {"invpcid", 2, 0x660f3882, X, CpuNEW|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, 1536998c1271Sguenther 1537*aa7b6e9dSguenther /* Intel Indirect Branch Tracking extensions */ 1538*aa7b6e9dSguenther {"endbr64", 0, 0xF30F1E, 0xFA, Cpu64, NoSuf|ImmExt, { 0, 0, 0 } }, 1539*aa7b6e9dSguenther {"endbr32", 0, 0xF30F1E, 0xFB, CpuNo64, NoSuf|ImmExt, { 0, 0, 0 } }, 1540*aa7b6e9dSguenther 15413d8817e4Smiod /* sentinel */ 15423d8817e4Smiod {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } 15433d8817e4Smiod }; 15443d8817e4Smiod #undef X 15453d8817e4Smiod #undef NoSuf 15463d8817e4Smiod #undef b_Suf 15473d8817e4Smiod #undef w_Suf 15483d8817e4Smiod #undef l_Suf 15493d8817e4Smiod #undef q_Suf 15503d8817e4Smiod #undef x_Suf 15513d8817e4Smiod #undef bw_Suf 15523d8817e4Smiod #undef bl_Suf 15533d8817e4Smiod #undef wl_Suf 15543d8817e4Smiod #undef wlq_Suf 15553d8817e4Smiod #undef sl_Suf 15563d8817e4Smiod #undef bwl_Suf 15573d8817e4Smiod #undef bwlq_Suf 15583d8817e4Smiod #undef FP 15593d8817e4Smiod #undef l_FP 15603d8817e4Smiod #undef q_FP 15613d8817e4Smiod #undef x_FP 15623d8817e4Smiod #undef sl_FP 15633d8817e4Smiod 15643d8817e4Smiod #define MAX_MNEM_SIZE 16 /* For parsing insn mnemonics from input. */ 15653d8817e4Smiod 15663d8817e4Smiod /* 386 register table. */ 15673d8817e4Smiod 15683d8817e4Smiod static const reg_entry i386_regtab[] = 15693d8817e4Smiod { 15703d8817e4Smiod /* Make %st first as we test for it. */ 15713d8817e4Smiod {"st", FloatReg|FloatAcc, 0, 0}, 15723d8817e4Smiod /* 8 bit regs */ 15733d8817e4Smiod #define REGNAM_AL 1 /* Entry in i386_regtab. */ 15743d8817e4Smiod {"al", Reg8|Acc, 0, 0}, 15753d8817e4Smiod {"cl", Reg8|ShiftCount, 0, 1}, 15763d8817e4Smiod {"dl", Reg8, 0, 2}, 15773d8817e4Smiod {"bl", Reg8, 0, 3}, 15783d8817e4Smiod {"ah", Reg8, 0, 4}, 15793d8817e4Smiod {"ch", Reg8, 0, 5}, 15803d8817e4Smiod {"dh", Reg8, 0, 6}, 15813d8817e4Smiod {"bh", Reg8, 0, 7}, 15823d8817e4Smiod {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */ 15833d8817e4Smiod {"cxl", Reg8, RegRex64, 1}, 15843d8817e4Smiod {"dxl", Reg8, RegRex64, 2}, 15853d8817e4Smiod {"bxl", Reg8, RegRex64, 3}, 15863d8817e4Smiod {"spl", Reg8, RegRex64, 4}, 15873d8817e4Smiod {"bpl", Reg8, RegRex64, 5}, 15883d8817e4Smiod {"sil", Reg8, RegRex64, 6}, 15893d8817e4Smiod {"dil", Reg8, RegRex64, 7}, 15903d8817e4Smiod {"r8b", Reg8, RegRex64|RegRex, 0}, 15913d8817e4Smiod {"r9b", Reg8, RegRex64|RegRex, 1}, 15923d8817e4Smiod {"r10b", Reg8, RegRex64|RegRex, 2}, 15933d8817e4Smiod {"r11b", Reg8, RegRex64|RegRex, 3}, 15943d8817e4Smiod {"r12b", Reg8, RegRex64|RegRex, 4}, 15953d8817e4Smiod {"r13b", Reg8, RegRex64|RegRex, 5}, 15963d8817e4Smiod {"r14b", Reg8, RegRex64|RegRex, 6}, 15973d8817e4Smiod {"r15b", Reg8, RegRex64|RegRex, 7}, 15983d8817e4Smiod /* 16 bit regs */ 15993d8817e4Smiod #define REGNAM_AX 25 16003d8817e4Smiod {"ax", Reg16|Acc, 0, 0}, 16013d8817e4Smiod {"cx", Reg16, 0, 1}, 16023d8817e4Smiod {"dx", Reg16|InOutPortReg, 0, 2}, 16033d8817e4Smiod {"bx", Reg16|BaseIndex, 0, 3}, 16043d8817e4Smiod {"sp", Reg16, 0, 4}, 16053d8817e4Smiod {"bp", Reg16|BaseIndex, 0, 5}, 16063d8817e4Smiod {"si", Reg16|BaseIndex, 0, 6}, 16073d8817e4Smiod {"di", Reg16|BaseIndex, 0, 7}, 16083d8817e4Smiod {"r8w", Reg16, RegRex, 0}, 16093d8817e4Smiod {"r9w", Reg16, RegRex, 1}, 16103d8817e4Smiod {"r10w", Reg16, RegRex, 2}, 16113d8817e4Smiod {"r11w", Reg16, RegRex, 3}, 16123d8817e4Smiod {"r12w", Reg16, RegRex, 4}, 16133d8817e4Smiod {"r13w", Reg16, RegRex, 5}, 16143d8817e4Smiod {"r14w", Reg16, RegRex, 6}, 16153d8817e4Smiod {"r15w", Reg16, RegRex, 7}, 16163d8817e4Smiod /* 32 bit regs */ 16173d8817e4Smiod #define REGNAM_EAX 41 16183d8817e4Smiod {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot. */ 16193d8817e4Smiod {"ecx", Reg32|BaseIndex, 0, 1}, 16203d8817e4Smiod {"edx", Reg32|BaseIndex, 0, 2}, 16213d8817e4Smiod {"ebx", Reg32|BaseIndex, 0, 3}, 16223d8817e4Smiod {"esp", Reg32, 0, 4}, 16233d8817e4Smiod {"ebp", Reg32|BaseIndex, 0, 5}, 16243d8817e4Smiod {"esi", Reg32|BaseIndex, 0, 6}, 16253d8817e4Smiod {"edi", Reg32|BaseIndex, 0, 7}, 16263d8817e4Smiod {"r8d", Reg32|BaseIndex, RegRex, 0}, 16273d8817e4Smiod {"r9d", Reg32|BaseIndex, RegRex, 1}, 16283d8817e4Smiod {"r10d", Reg32|BaseIndex, RegRex, 2}, 16293d8817e4Smiod {"r11d", Reg32|BaseIndex, RegRex, 3}, 16303d8817e4Smiod {"r12d", Reg32|BaseIndex, RegRex, 4}, 16313d8817e4Smiod {"r13d", Reg32|BaseIndex, RegRex, 5}, 16323d8817e4Smiod {"r14d", Reg32|BaseIndex, RegRex, 6}, 16333d8817e4Smiod {"r15d", Reg32|BaseIndex, RegRex, 7}, 16343d8817e4Smiod {"rax", Reg64|BaseIndex|Acc, 0, 0}, 16353d8817e4Smiod {"rcx", Reg64|BaseIndex, 0, 1}, 16363d8817e4Smiod {"rdx", Reg64|BaseIndex, 0, 2}, 16373d8817e4Smiod {"rbx", Reg64|BaseIndex, 0, 3}, 16383d8817e4Smiod {"rsp", Reg64, 0, 4}, 16393d8817e4Smiod {"rbp", Reg64|BaseIndex, 0, 5}, 16403d8817e4Smiod {"rsi", Reg64|BaseIndex, 0, 6}, 16413d8817e4Smiod {"rdi", Reg64|BaseIndex, 0, 7}, 16423d8817e4Smiod {"r8", Reg64|BaseIndex, RegRex, 0}, 16433d8817e4Smiod {"r9", Reg64|BaseIndex, RegRex, 1}, 16443d8817e4Smiod {"r10", Reg64|BaseIndex, RegRex, 2}, 16453d8817e4Smiod {"r11", Reg64|BaseIndex, RegRex, 3}, 16463d8817e4Smiod {"r12", Reg64|BaseIndex, RegRex, 4}, 16473d8817e4Smiod {"r13", Reg64|BaseIndex, RegRex, 5}, 16483d8817e4Smiod {"r14", Reg64|BaseIndex, RegRex, 6}, 16493d8817e4Smiod {"r15", Reg64|BaseIndex, RegRex, 7}, 16503d8817e4Smiod /* Segment registers. */ 16513d8817e4Smiod {"es", SReg2, 0, 0}, 16523d8817e4Smiod {"cs", SReg2, 0, 1}, 16533d8817e4Smiod {"ss", SReg2, 0, 2}, 16543d8817e4Smiod {"ds", SReg2, 0, 3}, 16553d8817e4Smiod {"fs", SReg3, 0, 4}, 16563d8817e4Smiod {"gs", SReg3, 0, 5}, 16573d8817e4Smiod /* Control registers. */ 16583d8817e4Smiod {"cr0", Control, 0, 0}, 16593d8817e4Smiod {"cr1", Control, 0, 1}, 16603d8817e4Smiod {"cr2", Control, 0, 2}, 16613d8817e4Smiod {"cr3", Control, 0, 3}, 16623d8817e4Smiod {"cr4", Control, 0, 4}, 16633d8817e4Smiod {"cr5", Control, 0, 5}, 16643d8817e4Smiod {"cr6", Control, 0, 6}, 16653d8817e4Smiod {"cr7", Control, 0, 7}, 16663d8817e4Smiod {"cr8", Control, RegRex, 0}, 16673d8817e4Smiod {"cr9", Control, RegRex, 1}, 16683d8817e4Smiod {"cr10", Control, RegRex, 2}, 16693d8817e4Smiod {"cr11", Control, RegRex, 3}, 16703d8817e4Smiod {"cr12", Control, RegRex, 4}, 16713d8817e4Smiod {"cr13", Control, RegRex, 5}, 16723d8817e4Smiod {"cr14", Control, RegRex, 6}, 16733d8817e4Smiod {"cr15", Control, RegRex, 7}, 16743d8817e4Smiod /* Debug registers. */ 16753d8817e4Smiod {"db0", Debug, 0, 0}, 16763d8817e4Smiod {"db1", Debug, 0, 1}, 16773d8817e4Smiod {"db2", Debug, 0, 2}, 16783d8817e4Smiod {"db3", Debug, 0, 3}, 16793d8817e4Smiod {"db4", Debug, 0, 4}, 16803d8817e4Smiod {"db5", Debug, 0, 5}, 16813d8817e4Smiod {"db6", Debug, 0, 6}, 16823d8817e4Smiod {"db7", Debug, 0, 7}, 16833d8817e4Smiod {"db8", Debug, RegRex, 0}, 16843d8817e4Smiod {"db9", Debug, RegRex, 1}, 16853d8817e4Smiod {"db10", Debug, RegRex, 2}, 16863d8817e4Smiod {"db11", Debug, RegRex, 3}, 16873d8817e4Smiod {"db12", Debug, RegRex, 4}, 16883d8817e4Smiod {"db13", Debug, RegRex, 5}, 16893d8817e4Smiod {"db14", Debug, RegRex, 6}, 16903d8817e4Smiod {"db15", Debug, RegRex, 7}, 16913d8817e4Smiod {"dr0", Debug, 0, 0}, 16923d8817e4Smiod {"dr1", Debug, 0, 1}, 16933d8817e4Smiod {"dr2", Debug, 0, 2}, 16943d8817e4Smiod {"dr3", Debug, 0, 3}, 16953d8817e4Smiod {"dr4", Debug, 0, 4}, 16963d8817e4Smiod {"dr5", Debug, 0, 5}, 16973d8817e4Smiod {"dr6", Debug, 0, 6}, 16983d8817e4Smiod {"dr7", Debug, 0, 7}, 16993d8817e4Smiod {"dr8", Debug, RegRex, 0}, 17003d8817e4Smiod {"dr9", Debug, RegRex, 1}, 17013d8817e4Smiod {"dr10", Debug, RegRex, 2}, 17023d8817e4Smiod {"dr11", Debug, RegRex, 3}, 17033d8817e4Smiod {"dr12", Debug, RegRex, 4}, 17043d8817e4Smiod {"dr13", Debug, RegRex, 5}, 17053d8817e4Smiod {"dr14", Debug, RegRex, 6}, 17063d8817e4Smiod {"dr15", Debug, RegRex, 7}, 17073d8817e4Smiod /* Test registers. */ 17083d8817e4Smiod {"tr0", Test, 0, 0}, 17093d8817e4Smiod {"tr1", Test, 0, 1}, 17103d8817e4Smiod {"tr2", Test, 0, 2}, 17113d8817e4Smiod {"tr3", Test, 0, 3}, 17123d8817e4Smiod {"tr4", Test, 0, 4}, 17133d8817e4Smiod {"tr5", Test, 0, 5}, 17143d8817e4Smiod {"tr6", Test, 0, 6}, 17153d8817e4Smiod {"tr7", Test, 0, 7}, 17163d8817e4Smiod /* MMX and simd registers. */ 17173d8817e4Smiod {"mm0", RegMMX, 0, 0}, 17183d8817e4Smiod {"mm1", RegMMX, 0, 1}, 17193d8817e4Smiod {"mm2", RegMMX, 0, 2}, 17203d8817e4Smiod {"mm3", RegMMX, 0, 3}, 17213d8817e4Smiod {"mm4", RegMMX, 0, 4}, 17223d8817e4Smiod {"mm5", RegMMX, 0, 5}, 17233d8817e4Smiod {"mm6", RegMMX, 0, 6}, 17243d8817e4Smiod {"mm7", RegMMX, 0, 7}, 17253d8817e4Smiod {"xmm0", RegXMM, 0, 0}, 17263d8817e4Smiod {"xmm1", RegXMM, 0, 1}, 17273d8817e4Smiod {"xmm2", RegXMM, 0, 2}, 17283d8817e4Smiod {"xmm3", RegXMM, 0, 3}, 17293d8817e4Smiod {"xmm4", RegXMM, 0, 4}, 17303d8817e4Smiod {"xmm5", RegXMM, 0, 5}, 17313d8817e4Smiod {"xmm6", RegXMM, 0, 6}, 17323d8817e4Smiod {"xmm7", RegXMM, 0, 7}, 17333d8817e4Smiod {"xmm8", RegXMM, RegRex, 0}, 17343d8817e4Smiod {"xmm9", RegXMM, RegRex, 1}, 17353d8817e4Smiod {"xmm10", RegXMM, RegRex, 2}, 17363d8817e4Smiod {"xmm11", RegXMM, RegRex, 3}, 17373d8817e4Smiod {"xmm12", RegXMM, RegRex, 4}, 17383d8817e4Smiod {"xmm13", RegXMM, RegRex, 5}, 17393d8817e4Smiod {"xmm14", RegXMM, RegRex, 6}, 17403d8817e4Smiod {"xmm15", RegXMM, RegRex, 7}, 17413d8817e4Smiod /* No type will make this register rejected for all purposes except 17423d8817e4Smiod for addressing. This saves creating one extra type for RIP. */ 17433d8817e4Smiod {"rip", BaseIndex, 0, 0} 17443d8817e4Smiod }; 17453d8817e4Smiod 17463d8817e4Smiod static const reg_entry i386_float_regtab[] = 17473d8817e4Smiod { 17483d8817e4Smiod {"st(0)", FloatReg|FloatAcc, 0, 0}, 17493d8817e4Smiod {"st(1)", FloatReg, 0, 1}, 17503d8817e4Smiod {"st(2)", FloatReg, 0, 2}, 17513d8817e4Smiod {"st(3)", FloatReg, 0, 3}, 17523d8817e4Smiod {"st(4)", FloatReg, 0, 4}, 17533d8817e4Smiod {"st(5)", FloatReg, 0, 5}, 17543d8817e4Smiod {"st(6)", FloatReg, 0, 6}, 17553d8817e4Smiod {"st(7)", FloatReg, 0, 7} 17563d8817e4Smiod }; 17573d8817e4Smiod 17583d8817e4Smiod #define MAX_REG_NAME_SIZE 8 /* For parsing register names from input. */ 17593d8817e4Smiod 17603d8817e4Smiod /* Segment stuff. */ 17613d8817e4Smiod static const seg_entry cs = { "cs", 0x2e }; 17623d8817e4Smiod static const seg_entry ds = { "ds", 0x3e }; 17633d8817e4Smiod static const seg_entry ss = { "ss", 0x36 }; 17643d8817e4Smiod static const seg_entry es = { "es", 0x26 }; 17653d8817e4Smiod static const seg_entry fs = { "fs", 0x64 }; 17663d8817e4Smiod static const seg_entry gs = { "gs", 0x65 }; 17673d8817e4Smiod 1768