1 /* Opcode table for the TI MSP430 microcontrollers 2 3 Copyright 2002, 2004 Free Software Foundation, Inc. 4 Contributed by Dmitry Diky <diwil@mail.ru> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 19 20 #ifndef __MSP430_H_ 21 #define __MSP430_H_ 22 23 struct msp430_operand_s 24 { 25 int ol; /* Operand length words. */ 26 int am; /* Addr mode. */ 27 int reg; /* Register. */ 28 int mode; /* Pperand mode. */ 29 #define OP_REG 0 30 #define OP_EXP 1 31 #ifndef DASM_SECTION 32 expressionS exp; 33 #endif 34 }; 35 36 #define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */ 37 38 struct msp430_opcode_s 39 { 40 char *name; 41 int fmt; 42 int insn_opnumb; 43 int bin_opcode; 44 int bin_mask; 45 }; 46 47 #define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask } 48 49 static struct msp430_opcode_s msp430_opcodes[] = 50 { 51 MSP_INSN (and, 1, 2, 0xf000, 0xf000), 52 MSP_INSN (inv, 0, 1, 0xe330, 0xfff0), 53 MSP_INSN (xor, 1, 2, 0xe000, 0xf000), 54 MSP_INSN (setz, 0, 0, 0xd322, 0xffff), 55 MSP_INSN (setc, 0, 0, 0xd312, 0xffff), 56 MSP_INSN (eint, 0, 0, 0xd232, 0xffff), 57 MSP_INSN (setn, 0, 0, 0xd222, 0xffff), 58 MSP_INSN (bis, 1, 2, 0xd000, 0xf000), 59 MSP_INSN (clrz, 0, 0, 0xc322, 0xffff), 60 MSP_INSN (clrc, 0, 0, 0xc312, 0xffff), 61 MSP_INSN (dint, 0, 0, 0xc232, 0xffff), 62 MSP_INSN (clrn, 0, 0, 0xc222, 0xffff), 63 MSP_INSN (bic, 1, 2, 0xc000, 0xf000), 64 MSP_INSN (bit, 1, 2, 0xb000, 0xf000), 65 MSP_INSN (dadc, 0, 1, 0xa300, 0xff30), 66 MSP_INSN (dadd, 1, 2, 0xa000, 0xf000), 67 MSP_INSN (tst, 0, 1, 0x9300, 0xff30), 68 MSP_INSN (cmp, 1, 2, 0x9000, 0xf000), 69 MSP_INSN (decd, 0, 1, 0x8320, 0xff30), 70 MSP_INSN (dec, 0, 1, 0x8310, 0xff30), 71 MSP_INSN (sub, 1, 2, 0x8000, 0xf000), 72 MSP_INSN (sbc, 0, 1, 0x7300, 0xff30), 73 MSP_INSN (subc, 1, 2, 0x7000, 0xf000), 74 MSP_INSN (adc, 0, 1, 0x6300, 0xff30), 75 MSP_INSN (rlc, 0, 2, 0x6000, 0xf000), 76 MSP_INSN (addc, 1, 2, 0x6000, 0xf000), 77 MSP_INSN (incd, 0, 1, 0x5320, 0xff30), 78 MSP_INSN (inc, 0, 1, 0x5310, 0xff30), 79 MSP_INSN (rla, 0, 2, 0x5000, 0xf000), 80 MSP_INSN (add, 1, 2, 0x5000, 0xf000), 81 MSP_INSN (nop, 0, 0, 0x4303, 0xffff), 82 MSP_INSN (clr, 0, 1, 0x4300, 0xff30), 83 MSP_INSN (ret, 0, 0, 0x4130, 0xff30), 84 MSP_INSN (pop, 0, 1, 0x4130, 0xff30), 85 MSP_INSN (br, 0, 3, 0x4000, 0xf000), 86 MSP_INSN (mov, 1, 2, 0x4000, 0xf000), 87 MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00), 88 MSP_INSN (jl, 3, 1, 0x3800, 0xfc00), 89 MSP_INSN (jge, 3, 1, 0x3400, 0xfc00), 90 MSP_INSN (jn, 3, 1, 0x3000, 0xfc00), 91 MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00), 92 MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00), 93 MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00), 94 MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00), 95 MSP_INSN (jz, 3, 1, 0x2400, 0xfc00), 96 MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00), 97 MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00), 98 MSP_INSN (jne, 3, 1, 0x2000, 0xfc00), 99 MSP_INSN (reti, 2, 0, 0x1300, 0xffc0), 100 MSP_INSN (call, 2, 1, 0x1280, 0xffc0), 101 MSP_INSN (push, 2, 1, 0x1200, 0xff80), 102 MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0), 103 MSP_INSN (rra, 2, 1, 0x1100, 0xff80), 104 MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0), 105 MSP_INSN (rrc, 2, 1, 0x1000, 0xff80), 106 /* Simple polymorphs. */ 107 MSP_INSN (beq, 4, 0, 0, 0xffff), 108 MSP_INSN (bne, 4, 1, 0, 0xffff), 109 MSP_INSN (blt, 4, 2, 0, 0xffff), 110 MSP_INSN (bltu, 4, 3, 0, 0xffff), 111 MSP_INSN (bge, 4, 4, 0, 0xffff), 112 MSP_INSN (bgeu, 4, 5, 0, 0xffff), 113 MSP_INSN (bltn, 4, 6, 0, 0xffff), 114 MSP_INSN (jump, 4, 7, 0, 0xffff), 115 /* Long polymorphs. */ 116 MSP_INSN (bgt, 5, 0, 0, 0xffff), 117 MSP_INSN (bgtu, 5, 1, 0, 0xffff), 118 MSP_INSN (bleu, 5, 2, 0, 0xffff), 119 MSP_INSN (ble, 5, 3, 0, 0xffff), 120 121 /* End of instruction set. */ 122 { NULL, 0, 0, 0, 0 } 123 }; 124 125 #endif 126