1*3d8817e4Smiod /* Assemble Matsushita MN10200 instructions. 2*3d8817e4Smiod Copyright 1996, 1997, 2000 Free Software Foundation, Inc. 3*3d8817e4Smiod 4*3d8817e4Smiod This program is free software; you can redistribute it and/or modify 5*3d8817e4Smiod it under the terms of the GNU General Public License as published by 6*3d8817e4Smiod the Free Software Foundation; either version 2 of the License, or 7*3d8817e4Smiod (at your option) any later version. 8*3d8817e4Smiod 9*3d8817e4Smiod This program is distributed in the hope that it will be useful, 10*3d8817e4Smiod but WITHOUT ANY WARRANTY; without even the implied warranty of 11*3d8817e4Smiod MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*3d8817e4Smiod GNU General Public License for more details. 13*3d8817e4Smiod 14*3d8817e4Smiod You should have received a copy of the GNU General Public License 15*3d8817e4Smiod along with this program; if not, write to the Free Software 16*3d8817e4Smiod Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 17*3d8817e4Smiod 18*3d8817e4Smiod #include "sysdep.h" 19*3d8817e4Smiod #include "opcode/mn10200.h" 20*3d8817e4Smiod 21*3d8817e4Smiod 22*3d8817e4Smiod const struct mn10200_operand mn10200_operands[] = { 23*3d8817e4Smiod #define UNUSED 0 24*3d8817e4Smiod {0, 0, 0}, 25*3d8817e4Smiod 26*3d8817e4Smiod /* dn register in the first register operand position. */ 27*3d8817e4Smiod #define DN0 (UNUSED+1) 28*3d8817e4Smiod {2, 0, MN10200_OPERAND_DREG}, 29*3d8817e4Smiod 30*3d8817e4Smiod /* dn register in the second register operand position. */ 31*3d8817e4Smiod #define DN1 (DN0+1) 32*3d8817e4Smiod {2, 2, MN10200_OPERAND_DREG}, 33*3d8817e4Smiod 34*3d8817e4Smiod /* dm register in the first register operand position. */ 35*3d8817e4Smiod #define DM0 (DN1+1) 36*3d8817e4Smiod {2, 0, MN10200_OPERAND_DREG}, 37*3d8817e4Smiod 38*3d8817e4Smiod /* dm register in the second register operand position. */ 39*3d8817e4Smiod #define DM1 (DM0+1) 40*3d8817e4Smiod {2, 2, MN10200_OPERAND_DREG}, 41*3d8817e4Smiod 42*3d8817e4Smiod /* an register in the first register operand position. */ 43*3d8817e4Smiod #define AN0 (DM1+1) 44*3d8817e4Smiod {2, 0, MN10200_OPERAND_AREG}, 45*3d8817e4Smiod 46*3d8817e4Smiod /* an register in the second register operand position. */ 47*3d8817e4Smiod #define AN1 (AN0+1) 48*3d8817e4Smiod {2, 2, MN10200_OPERAND_AREG}, 49*3d8817e4Smiod 50*3d8817e4Smiod /* am register in the first register operand position. */ 51*3d8817e4Smiod #define AM0 (AN1+1) 52*3d8817e4Smiod {2, 0, MN10200_OPERAND_AREG}, 53*3d8817e4Smiod 54*3d8817e4Smiod /* am register in the second register operand position. */ 55*3d8817e4Smiod #define AM1 (AM0+1) 56*3d8817e4Smiod {2, 2, MN10200_OPERAND_AREG}, 57*3d8817e4Smiod 58*3d8817e4Smiod /* 8 bit unsigned immediate which may promote to a 16bit 59*3d8817e4Smiod unsigned immediate. */ 60*3d8817e4Smiod #define IMM8 (AM1+1) 61*3d8817e4Smiod {8, 0, MN10200_OPERAND_PROMOTE}, 62*3d8817e4Smiod 63*3d8817e4Smiod /* 16 bit unsigned immediate which may promote to a 32bit 64*3d8817e4Smiod unsigned immediate. */ 65*3d8817e4Smiod #define IMM16 (IMM8+1) 66*3d8817e4Smiod {16, 0, MN10200_OPERAND_PROMOTE}, 67*3d8817e4Smiod 68*3d8817e4Smiod /* 16 bit pc-relative immediate which may promote to a 16bit 69*3d8817e4Smiod pc-relative immediate. */ 70*3d8817e4Smiod #define IMM16_PCREL (IMM16+1) 71*3d8817e4Smiod {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED}, 72*3d8817e4Smiod 73*3d8817e4Smiod /* 16bit unsigned dispacement in a memory operation which 74*3d8817e4Smiod may promote to a 32bit displacement. */ 75*3d8817e4Smiod #define IMM16_MEM (IMM16_PCREL+1) 76*3d8817e4Smiod {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR}, 77*3d8817e4Smiod 78*3d8817e4Smiod /* 24 immediate, low 16 bits in the main instruction 79*3d8817e4Smiod word, 8 in the extension word. */ 80*3d8817e4Smiod 81*3d8817e4Smiod #define IMM24 (IMM16_MEM+1) 82*3d8817e4Smiod {24, 0, MN10200_OPERAND_EXTENDED}, 83*3d8817e4Smiod 84*3d8817e4Smiod /* 32bit pc-relative offset. */ 85*3d8817e4Smiod #define IMM24_PCREL (IMM24+1) 86*3d8817e4Smiod {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED}, 87*3d8817e4Smiod 88*3d8817e4Smiod /* 32bit memory offset. */ 89*3d8817e4Smiod #define IMM24_MEM (IMM24_PCREL+1) 90*3d8817e4Smiod {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR}, 91*3d8817e4Smiod 92*3d8817e4Smiod /* Processor status word. */ 93*3d8817e4Smiod #define PSW (IMM24_MEM+1) 94*3d8817e4Smiod {0, 0, MN10200_OPERAND_PSW}, 95*3d8817e4Smiod 96*3d8817e4Smiod /* MDR register. */ 97*3d8817e4Smiod #define MDR (PSW+1) 98*3d8817e4Smiod {0, 0, MN10200_OPERAND_MDR}, 99*3d8817e4Smiod 100*3d8817e4Smiod /* Index register. */ 101*3d8817e4Smiod #define DI (MDR+1) 102*3d8817e4Smiod {2, 4, MN10200_OPERAND_DREG}, 103*3d8817e4Smiod 104*3d8817e4Smiod /* 8 bit signed displacement, may promote to 16bit signed dispacement. */ 105*3d8817e4Smiod #define SD8 (DI+1) 106*3d8817e4Smiod {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 107*3d8817e4Smiod 108*3d8817e4Smiod /* 16 bit signed displacement, may promote to 32bit dispacement. */ 109*3d8817e4Smiod #define SD16 (SD8+1) 110*3d8817e4Smiod {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 111*3d8817e4Smiod 112*3d8817e4Smiod /* 8 bit pc-relative displacement. */ 113*3d8817e4Smiod #define SD8N_PCREL (SD16+1) 114*3d8817e4Smiod {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX}, 115*3d8817e4Smiod 116*3d8817e4Smiod /* 8 bit signed immediate which may promote to 16bit signed immediate. */ 117*3d8817e4Smiod #define SIMM8 (SD8N_PCREL+1) 118*3d8817e4Smiod {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 119*3d8817e4Smiod 120*3d8817e4Smiod /* 16 bit signed immediate which may promote to 32bit immediate. */ 121*3d8817e4Smiod #define SIMM16 (SIMM8+1) 122*3d8817e4Smiod {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 123*3d8817e4Smiod 124*3d8817e4Smiod /* 16 bit signed immediate which may not promote. */ 125*3d8817e4Smiod #define SIMM16N (SIMM16+1) 126*3d8817e4Smiod {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK}, 127*3d8817e4Smiod 128*3d8817e4Smiod /* Either an open paren or close paren. */ 129*3d8817e4Smiod #define PAREN (SIMM16N+1) 130*3d8817e4Smiod {0, 0, MN10200_OPERAND_PAREN}, 131*3d8817e4Smiod 132*3d8817e4Smiod /* dn register that appears in the first and second register positions. */ 133*3d8817e4Smiod #define DN01 (PAREN+1) 134*3d8817e4Smiod {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED}, 135*3d8817e4Smiod 136*3d8817e4Smiod /* an register that appears in the first and second register positions. */ 137*3d8817e4Smiod #define AN01 (DN01+1) 138*3d8817e4Smiod {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED}, 139*3d8817e4Smiod } ; 140*3d8817e4Smiod 141*3d8817e4Smiod #define MEM(ADDR) PAREN, ADDR, PAREN 142*3d8817e4Smiod #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 143*3d8817e4Smiod 144*3d8817e4Smiod /* The opcode table. 145*3d8817e4Smiod 146*3d8817e4Smiod The format of the opcode table is: 147*3d8817e4Smiod 148*3d8817e4Smiod NAME OPCODE MASK { OPERANDS } 149*3d8817e4Smiod 150*3d8817e4Smiod NAME is the name of the instruction. 151*3d8817e4Smiod OPCODE is the instruction opcode. 152*3d8817e4Smiod MASK is the opcode mask; this is used to tell the disassembler 153*3d8817e4Smiod which bits in the actual opcode must match OPCODE. 154*3d8817e4Smiod OPERANDS is the list of operands. 155*3d8817e4Smiod 156*3d8817e4Smiod The disassembler reads the table in order and prints the first 157*3d8817e4Smiod instruction which matches, so this table is sorted to put more 158*3d8817e4Smiod specific instructions before more general instructions. It is also 159*3d8817e4Smiod sorted by major opcode. */ 160*3d8817e4Smiod 161*3d8817e4Smiod const struct mn10200_opcode mn10200_opcodes[] = { 162*3d8817e4Smiod { "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}}, 163*3d8817e4Smiod { "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}}, 164*3d8817e4Smiod { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}}, 165*3d8817e4Smiod { "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}}, 166*3d8817e4Smiod { "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}}, 167*3d8817e4Smiod { "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}}, 168*3d8817e4Smiod { "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}}, 169*3d8817e4Smiod { "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}}, 170*3d8817e4Smiod { "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}}, 171*3d8817e4Smiod { "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}}, 172*3d8817e4Smiod { "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}}, 173*3d8817e4Smiod { "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 174*3d8817e4Smiod { "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 175*3d8817e4Smiod { "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, 176*3d8817e4Smiod { "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, 177*3d8817e4Smiod { "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, 178*3d8817e4Smiod { "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}}, 179*3d8817e4Smiod { "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}}, 180*3d8817e4Smiod { "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}}, 181*3d8817e4Smiod { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}}, 182*3d8817e4Smiod { "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}}, 183*3d8817e4Smiod { "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}}, 184*3d8817e4Smiod { "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}}, 185*3d8817e4Smiod { "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}}, 186*3d8817e4Smiod { "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}}, 187*3d8817e4Smiod { "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, 188*3d8817e4Smiod { "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, 189*3d8817e4Smiod { "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, 190*3d8817e4Smiod { "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, 191*3d8817e4Smiod { "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, 192*3d8817e4Smiod { "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}}, 193*3d8817e4Smiod { "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM(AN1)}}, 194*3d8817e4Smiod { "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}}, 195*3d8817e4Smiod { "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}}, 196*3d8817e4Smiod { "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}}, 197*3d8817e4Smiod { "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}}, 198*3d8817e4Smiod { "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}}, 199*3d8817e4Smiod { "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}}, 200*3d8817e4Smiod { "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 201*3d8817e4Smiod { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}}, 202*3d8817e4Smiod { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 203*3d8817e4Smiod 204*3d8817e4Smiod { "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, 205*3d8817e4Smiod { "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 206*3d8817e4Smiod { "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 207*3d8817e4Smiod { "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, 208*3d8817e4Smiod { "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, 209*3d8817e4Smiod { "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, 210*3d8817e4Smiod 211*3d8817e4Smiod { "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, 212*3d8817e4Smiod { "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 213*3d8817e4Smiod { "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 214*3d8817e4Smiod { "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, 215*3d8817e4Smiod { "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, 216*3d8817e4Smiod { "movb", 0x10, 0xf0, FMT_1, {DM0, MEM(AN1)}}, 217*3d8817e4Smiod { "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, 218*3d8817e4Smiod { "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, 219*3d8817e4Smiod { "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, 220*3d8817e4Smiod { "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, 221*3d8817e4Smiod { "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, 222*3d8817e4Smiod { "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, 223*3d8817e4Smiod 224*3d8817e4Smiod { "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}}, 225*3d8817e4Smiod { "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, 226*3d8817e4Smiod { "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 227*3d8817e4Smiod { "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 228*3d8817e4Smiod { "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, 229*3d8817e4Smiod { "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, 230*3d8817e4Smiod { "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, 231*3d8817e4Smiod 232*3d8817e4Smiod { "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}}, 233*3d8817e4Smiod { "extx", 0xb0, 0xfc, FMT_1, {DN0}}, 234*3d8817e4Smiod { "extxu", 0xb4, 0xfc, FMT_1, {DN0}}, 235*3d8817e4Smiod { "extxb", 0xb8, 0xfc, FMT_1, {DN0}}, 236*3d8817e4Smiod { "extxbu", 0xbc, 0xfc, FMT_1, {DN0}}, 237*3d8817e4Smiod 238*3d8817e4Smiod { "add", 0x90, 0xf0, FMT_1, {DN1, DM0}}, 239*3d8817e4Smiod { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}}, 240*3d8817e4Smiod { "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}}, 241*3d8817e4Smiod { "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}}, 242*3d8817e4Smiod { "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}}, 243*3d8817e4Smiod { "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, 244*3d8817e4Smiod { "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 245*3d8817e4Smiod { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}}, 246*3d8817e4Smiod { "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}}, 247*3d8817e4Smiod { "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 248*3d8817e4Smiod { "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}}, 249*3d8817e4Smiod { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}}, 250*3d8817e4Smiod 251*3d8817e4Smiod { "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}}, 252*3d8817e4Smiod { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}}, 253*3d8817e4Smiod { "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}}, 254*3d8817e4Smiod { "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}}, 255*3d8817e4Smiod { "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}}, 256*3d8817e4Smiod { "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 257*3d8817e4Smiod { "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}}, 258*3d8817e4Smiod { "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 259*3d8817e4Smiod { "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}}, 260*3d8817e4Smiod 261*3d8817e4Smiod { "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}}, 262*3d8817e4Smiod { "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}}, 263*3d8817e4Smiod 264*3d8817e4Smiod { "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}}, 265*3d8817e4Smiod 266*3d8817e4Smiod { "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}}, 267*3d8817e4Smiod { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}}, 268*3d8817e4Smiod { "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}}, 269*3d8817e4Smiod { "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}}, 270*3d8817e4Smiod { "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}}, 271*3d8817e4Smiod { "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, 272*3d8817e4Smiod { "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 273*3d8817e4Smiod { "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}}, 274*3d8817e4Smiod { "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 275*3d8817e4Smiod 276*3d8817e4Smiod { "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}}, 277*3d8817e4Smiod { "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}}, 278*3d8817e4Smiod { "and", 0xf7000000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 279*3d8817e4Smiod { "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, 280*3d8817e4Smiod { "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}}, 281*3d8817e4Smiod { "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}}, 282*3d8817e4Smiod { "or", 0xf7400000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 283*3d8817e4Smiod { "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, 284*3d8817e4Smiod { "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}}, 285*3d8817e4Smiod { "xor", 0xf74c0000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 286*3d8817e4Smiod { "not", 0xf3e4, 0xfffc, FMT_4, {DN0}}, 287*3d8817e4Smiod 288*3d8817e4Smiod { "asr", 0xf338, 0xfffc, FMT_4, {DN0}}, 289*3d8817e4Smiod { "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}}, 290*3d8817e4Smiod { "ror", 0xf334, 0xfffc, FMT_4, {DN0}}, 291*3d8817e4Smiod { "rol", 0xf330, 0xfffc, FMT_4, {DN0}}, 292*3d8817e4Smiod 293*3d8817e4Smiod { "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}}, 294*3d8817e4Smiod { "btst", 0xf7040000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 295*3d8817e4Smiod { "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, 296*3d8817e4Smiod { "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, 297*3d8817e4Smiod 298*3d8817e4Smiod { "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}}, 299*3d8817e4Smiod { "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}}, 300*3d8817e4Smiod { "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}}, 301*3d8817e4Smiod { "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}}, 302*3d8817e4Smiod { "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}}, 303*3d8817e4Smiod { "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}}, 304*3d8817e4Smiod { "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}}, 305*3d8817e4Smiod { "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}}, 306*3d8817e4Smiod { "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}}, 307*3d8817e4Smiod { "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}}, 308*3d8817e4Smiod { "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}}, 309*3d8817e4Smiod { "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}}, 310*3d8817e4Smiod { "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}}, 311*3d8817e4Smiod { "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}}, 312*3d8817e4Smiod { "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}}, 313*3d8817e4Smiod 314*3d8817e4Smiod { "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}}, 315*3d8817e4Smiod { "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}}, 316*3d8817e4Smiod { "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}}, 317*3d8817e4Smiod { "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}}, 318*3d8817e4Smiod { "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}}, 319*3d8817e4Smiod { "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}}, 320*3d8817e4Smiod { "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}}, 321*3d8817e4Smiod { "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}}, 322*3d8817e4Smiod { "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}}, 323*3d8817e4Smiod { "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}}, 324*3d8817e4Smiod { "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}}, 325*3d8817e4Smiod { "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}}, 326*3d8817e4Smiod { "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}}, 327*3d8817e4Smiod { "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}}, 328*3d8817e4Smiod 329*3d8817e4Smiod { "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}}, 330*3d8817e4Smiod { "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}}, 331*3d8817e4Smiod { "jmp", 0xf000, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, 332*3d8817e4Smiod { "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}}, 333*3d8817e4Smiod { "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}}, 334*3d8817e4Smiod { "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, 335*3d8817e4Smiod 336*3d8817e4Smiod { "nop", 0xf6, 0xff, FMT_1, {UNUSED}}, 337*3d8817e4Smiod 338*3d8817e4Smiod { "rts", 0xfe, 0xff, FMT_1, {UNUSED}}, 339*3d8817e4Smiod { "rti", 0xeb, 0xff, FMT_1, {UNUSED}}, 340*3d8817e4Smiod 341*3d8817e4Smiod /* Extension. We need some instruction to trigger "emulated syscalls" 342*3d8817e4Smiod for our simulator. */ 343*3d8817e4Smiod { "syscall", 0xf010, 0xffff, FMT_4, {UNUSED}}, 344*3d8817e4Smiod 345*3d8817e4Smiod /* Extension. When talking to the simulator, gdb requires some instruction 346*3d8817e4Smiod that will trigger a "breakpoint" (really just an instruction that isn't 347*3d8817e4Smiod otherwise used by the tools. This instruction must be the same size 348*3d8817e4Smiod as the smallest instruction on the target machine. In the case of the 349*3d8817e4Smiod mn10x00 the "break" instruction must be one byte. 0xff is available on 350*3d8817e4Smiod both mn10x00 architectures. */ 351*3d8817e4Smiod { "break", 0xff, 0xff, FMT_1, {UNUSED}}, 352*3d8817e4Smiod 353*3d8817e4Smiod { 0, 0, 0, 0, {0}}, 354*3d8817e4Smiod 355*3d8817e4Smiod } ; 356*3d8817e4Smiod 357*3d8817e4Smiod const int mn10200_num_opcodes = 358*3d8817e4Smiod sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]); 359*3d8817e4Smiod 360*3d8817e4Smiod 361