1*3d8817e4Smiod /* Assemble Matsushita MN10300 instructions. 2*3d8817e4Smiod Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004 3*3d8817e4Smiod Free Software Foundation, Inc. 4*3d8817e4Smiod 5*3d8817e4Smiod This program is free software; you can redistribute it and/or modify 6*3d8817e4Smiod it under the terms of the GNU General Public License as published by 7*3d8817e4Smiod the Free Software Foundation; either version 2 of the License, or 8*3d8817e4Smiod (at your option) any later version. 9*3d8817e4Smiod 10*3d8817e4Smiod This program is distributed in the hope that it will be useful, 11*3d8817e4Smiod but WITHOUT ANY WARRANTY; without even the implied warranty of 12*3d8817e4Smiod MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*3d8817e4Smiod GNU General Public License for more details. 14*3d8817e4Smiod 15*3d8817e4Smiod You should have received a copy of the GNU General Public License 16*3d8817e4Smiod along with this program; if not, write to the Free Software 17*3d8817e4Smiod Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 18*3d8817e4Smiod 19*3d8817e4Smiod /* This file is formatted at > 80 columns. Attempting to read it on a 20*3d8817e4Smiod screeen with less than 80 columns will be difficult. */ 21*3d8817e4Smiod #include "sysdep.h" 22*3d8817e4Smiod #include "opcode/mn10300.h" 23*3d8817e4Smiod 24*3d8817e4Smiod 25*3d8817e4Smiod const struct mn10300_operand mn10300_operands[] = { 26*3d8817e4Smiod #define UNUSED 0 27*3d8817e4Smiod {0, 0, 0}, 28*3d8817e4Smiod 29*3d8817e4Smiod /* dn register in the first register operand position. */ 30*3d8817e4Smiod #define DN0 (UNUSED+1) 31*3d8817e4Smiod {2, 0, MN10300_OPERAND_DREG}, 32*3d8817e4Smiod 33*3d8817e4Smiod /* dn register in the second register operand position. */ 34*3d8817e4Smiod #define DN1 (DN0+1) 35*3d8817e4Smiod {2, 2, MN10300_OPERAND_DREG}, 36*3d8817e4Smiod 37*3d8817e4Smiod /* dn register in the third register operand position. */ 38*3d8817e4Smiod #define DN2 (DN1+1) 39*3d8817e4Smiod {2, 4, MN10300_OPERAND_DREG}, 40*3d8817e4Smiod 41*3d8817e4Smiod /* dm register in the first register operand position. */ 42*3d8817e4Smiod #define DM0 (DN2+1) 43*3d8817e4Smiod {2, 0, MN10300_OPERAND_DREG}, 44*3d8817e4Smiod 45*3d8817e4Smiod /* dm register in the second register operand position. */ 46*3d8817e4Smiod #define DM1 (DM0+1) 47*3d8817e4Smiod {2, 2, MN10300_OPERAND_DREG}, 48*3d8817e4Smiod 49*3d8817e4Smiod /* dm register in the third register operand position. */ 50*3d8817e4Smiod #define DM2 (DM1+1) 51*3d8817e4Smiod {2, 4, MN10300_OPERAND_DREG}, 52*3d8817e4Smiod 53*3d8817e4Smiod /* an register in the first register operand position. */ 54*3d8817e4Smiod #define AN0 (DM2+1) 55*3d8817e4Smiod {2, 0, MN10300_OPERAND_AREG}, 56*3d8817e4Smiod 57*3d8817e4Smiod /* an register in the second register operand position. */ 58*3d8817e4Smiod #define AN1 (AN0+1) 59*3d8817e4Smiod {2, 2, MN10300_OPERAND_AREG}, 60*3d8817e4Smiod 61*3d8817e4Smiod /* an register in the third register operand position. */ 62*3d8817e4Smiod #define AN2 (AN1+1) 63*3d8817e4Smiod {2, 4, MN10300_OPERAND_AREG}, 64*3d8817e4Smiod 65*3d8817e4Smiod /* am register in the first register operand position. */ 66*3d8817e4Smiod #define AM0 (AN2+1) 67*3d8817e4Smiod {2, 0, MN10300_OPERAND_AREG}, 68*3d8817e4Smiod 69*3d8817e4Smiod /* am register in the second register operand position. */ 70*3d8817e4Smiod #define AM1 (AM0+1) 71*3d8817e4Smiod {2, 2, MN10300_OPERAND_AREG}, 72*3d8817e4Smiod 73*3d8817e4Smiod /* am register in the third register operand position. */ 74*3d8817e4Smiod #define AM2 (AM1+1) 75*3d8817e4Smiod {2, 4, MN10300_OPERAND_AREG}, 76*3d8817e4Smiod 77*3d8817e4Smiod /* 8 bit unsigned immediate which may promote to a 16bit 78*3d8817e4Smiod unsigned immediate. */ 79*3d8817e4Smiod #define IMM8 (AM2+1) 80*3d8817e4Smiod {8, 0, MN10300_OPERAND_PROMOTE}, 81*3d8817e4Smiod 82*3d8817e4Smiod /* 16 bit unsigned immediate which may promote to a 32bit 83*3d8817e4Smiod unsigned immediate. */ 84*3d8817e4Smiod #define IMM16 (IMM8+1) 85*3d8817e4Smiod {16, 0, MN10300_OPERAND_PROMOTE}, 86*3d8817e4Smiod 87*3d8817e4Smiod /* 16 bit pc-relative immediate which may promote to a 16bit 88*3d8817e4Smiod pc-relative immediate. */ 89*3d8817e4Smiod #define IMM16_PCREL (IMM16+1) 90*3d8817e4Smiod {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, 91*3d8817e4Smiod 92*3d8817e4Smiod /* 16bit unsigned displacement in a memory operation which 93*3d8817e4Smiod may promote to a 32bit displacement. */ 94*3d8817e4Smiod #define IMM16_MEM (IMM16_PCREL+1) 95*3d8817e4Smiod {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, 96*3d8817e4Smiod 97*3d8817e4Smiod /* 32bit immediate, high 16 bits in the main instruction 98*3d8817e4Smiod word, 16bits in the extension word. 99*3d8817e4Smiod 100*3d8817e4Smiod The "bits" field indicates how many bits are in the 101*3d8817e4Smiod main instruction word for MN10300_OPERAND_SPLIT! */ 102*3d8817e4Smiod #define IMM32 (IMM16_MEM+1) 103*3d8817e4Smiod {16, 0, MN10300_OPERAND_SPLIT}, 104*3d8817e4Smiod 105*3d8817e4Smiod /* 32bit pc-relative offset. */ 106*3d8817e4Smiod #define IMM32_PCREL (IMM32+1) 107*3d8817e4Smiod {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, 108*3d8817e4Smiod 109*3d8817e4Smiod /* 32bit memory offset. */ 110*3d8817e4Smiod #define IMM32_MEM (IMM32_PCREL+1) 111*3d8817e4Smiod {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, 112*3d8817e4Smiod 113*3d8817e4Smiod /* 32bit immediate, high 16 bits in the main instruction 114*3d8817e4Smiod word, 16bits in the extension word, low 16bits are left 115*3d8817e4Smiod shifted 8 places. 116*3d8817e4Smiod 117*3d8817e4Smiod The "bits" field indicates how many bits are in the 118*3d8817e4Smiod main instruction word for MN10300_OPERAND_SPLIT! */ 119*3d8817e4Smiod #define IMM32_LOWSHIFT8 (IMM32_MEM+1) 120*3d8817e4Smiod {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, 121*3d8817e4Smiod 122*3d8817e4Smiod /* 32bit immediate, high 24 bits in the main instruction 123*3d8817e4Smiod word, 8 in the extension word. 124*3d8817e4Smiod 125*3d8817e4Smiod The "bits" field indicates how many bits are in the 126*3d8817e4Smiod main instruction word for MN10300_OPERAND_SPLIT! */ 127*3d8817e4Smiod #define IMM32_HIGH24 (IMM32_LOWSHIFT8+1) 128*3d8817e4Smiod {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, 129*3d8817e4Smiod 130*3d8817e4Smiod /* 32bit immediate, high 24 bits in the main instruction 131*3d8817e4Smiod word, 8 in the extension word, low 8 bits are left 132*3d8817e4Smiod shifted 16 places. 133*3d8817e4Smiod 134*3d8817e4Smiod The "bits" field indicates how many bits are in the 135*3d8817e4Smiod main instruction word for MN10300_OPERAND_SPLIT! */ 136*3d8817e4Smiod #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) 137*3d8817e4Smiod {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, 138*3d8817e4Smiod 139*3d8817e4Smiod /* Stack pointer. */ 140*3d8817e4Smiod #define SP (IMM32_HIGH24_LOWSHIFT16+1) 141*3d8817e4Smiod {8, 0, MN10300_OPERAND_SP}, 142*3d8817e4Smiod 143*3d8817e4Smiod /* Processor status word. */ 144*3d8817e4Smiod #define PSW (SP+1) 145*3d8817e4Smiod {0, 0, MN10300_OPERAND_PSW}, 146*3d8817e4Smiod 147*3d8817e4Smiod /* MDR register. */ 148*3d8817e4Smiod #define MDR (PSW+1) 149*3d8817e4Smiod {0, 0, MN10300_OPERAND_MDR}, 150*3d8817e4Smiod 151*3d8817e4Smiod /* Index register. */ 152*3d8817e4Smiod #define DI (MDR+1) 153*3d8817e4Smiod {2, 2, MN10300_OPERAND_DREG}, 154*3d8817e4Smiod 155*3d8817e4Smiod /* 8 bit signed displacement, may promote to 16bit signed displacement. */ 156*3d8817e4Smiod #define SD8 (DI+1) 157*3d8817e4Smiod {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, 158*3d8817e4Smiod 159*3d8817e4Smiod /* 16 bit signed displacement, may promote to 32bit displacement. */ 160*3d8817e4Smiod #define SD16 (SD8+1) 161*3d8817e4Smiod {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, 162*3d8817e4Smiod 163*3d8817e4Smiod /* 8 bit signed displacement that can not promote. */ 164*3d8817e4Smiod #define SD8N (SD16+1) 165*3d8817e4Smiod {8, 0, MN10300_OPERAND_SIGNED}, 166*3d8817e4Smiod 167*3d8817e4Smiod /* 8 bit pc-relative displacement. */ 168*3d8817e4Smiod #define SD8N_PCREL (SD8N+1) 169*3d8817e4Smiod {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX}, 170*3d8817e4Smiod 171*3d8817e4Smiod /* 8 bit signed displacement shifted left 8 bits in the instruction. */ 172*3d8817e4Smiod #define SD8N_SHIFT8 (SD8N_PCREL+1) 173*3d8817e4Smiod {8, 8, MN10300_OPERAND_SIGNED}, 174*3d8817e4Smiod 175*3d8817e4Smiod /* 8 bit signed immediate which may promote to 16bit signed immediate. */ 176*3d8817e4Smiod #define SIMM8 (SD8N_SHIFT8+1) 177*3d8817e4Smiod {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, 178*3d8817e4Smiod 179*3d8817e4Smiod /* 16 bit signed immediate which may promote to 32bit immediate. */ 180*3d8817e4Smiod #define SIMM16 (SIMM8+1) 181*3d8817e4Smiod {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, 182*3d8817e4Smiod 183*3d8817e4Smiod /* Either an open paren or close paren. */ 184*3d8817e4Smiod #define PAREN (SIMM16+1) 185*3d8817e4Smiod {0, 0, MN10300_OPERAND_PAREN}, 186*3d8817e4Smiod 187*3d8817e4Smiod /* dn register that appears in the first and second register positions. */ 188*3d8817e4Smiod #define DN01 (PAREN+1) 189*3d8817e4Smiod {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED}, 190*3d8817e4Smiod 191*3d8817e4Smiod /* an register that appears in the first and second register positions. */ 192*3d8817e4Smiod #define AN01 (DN01+1) 193*3d8817e4Smiod {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED}, 194*3d8817e4Smiod 195*3d8817e4Smiod /* 16bit pc-relative displacement which may promote to 32bit pc-relative 196*3d8817e4Smiod displacement. */ 197*3d8817e4Smiod #define D16_SHIFT (AN01+1) 198*3d8817e4Smiod {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, 199*3d8817e4Smiod 200*3d8817e4Smiod /* 8 bit immediate found in the extension word. */ 201*3d8817e4Smiod #define IMM8E (D16_SHIFT+1) 202*3d8817e4Smiod {8, 0, MN10300_OPERAND_EXTENDED}, 203*3d8817e4Smiod 204*3d8817e4Smiod /* Register list found in the extension word shifted 8 bits left. */ 205*3d8817e4Smiod #define REGSE_SHIFT8 (IMM8E+1) 206*3d8817e4Smiod {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST}, 207*3d8817e4Smiod 208*3d8817e4Smiod /* Register list shifted 8 bits left. */ 209*3d8817e4Smiod #define REGS_SHIFT8 (REGSE_SHIFT8 + 1) 210*3d8817e4Smiod {8, 8, MN10300_OPERAND_REG_LIST}, 211*3d8817e4Smiod 212*3d8817e4Smiod /* Reigster list. */ 213*3d8817e4Smiod #define REGS (REGS_SHIFT8+1) 214*3d8817e4Smiod {8, 0, MN10300_OPERAND_REG_LIST}, 215*3d8817e4Smiod 216*3d8817e4Smiod /* UStack pointer. */ 217*3d8817e4Smiod #define USP (REGS+1) 218*3d8817e4Smiod {0, 0, MN10300_OPERAND_USP}, 219*3d8817e4Smiod 220*3d8817e4Smiod /* SStack pointer. */ 221*3d8817e4Smiod #define SSP (USP+1) 222*3d8817e4Smiod {0, 0, MN10300_OPERAND_SSP}, 223*3d8817e4Smiod 224*3d8817e4Smiod /* MStack pointer. */ 225*3d8817e4Smiod #define MSP (SSP+1) 226*3d8817e4Smiod {0, 0, MN10300_OPERAND_MSP}, 227*3d8817e4Smiod 228*3d8817e4Smiod /* PC . */ 229*3d8817e4Smiod #define PC (MSP+1) 230*3d8817e4Smiod {0, 0, MN10300_OPERAND_PC}, 231*3d8817e4Smiod 232*3d8817e4Smiod /* 4 bit immediate for syscall. */ 233*3d8817e4Smiod #define IMM4 (PC+1) 234*3d8817e4Smiod {4, 0, 0}, 235*3d8817e4Smiod 236*3d8817e4Smiod /* Processor status word. */ 237*3d8817e4Smiod #define EPSW (IMM4+1) 238*3d8817e4Smiod {0, 0, MN10300_OPERAND_EPSW}, 239*3d8817e4Smiod 240*3d8817e4Smiod /* rn register in the first register operand position. */ 241*3d8817e4Smiod #define RN0 (EPSW+1) 242*3d8817e4Smiod {4, 0, MN10300_OPERAND_RREG}, 243*3d8817e4Smiod 244*3d8817e4Smiod /* rn register in the fourth register operand position. */ 245*3d8817e4Smiod #define RN2 (RN0+1) 246*3d8817e4Smiod {4, 4, MN10300_OPERAND_RREG}, 247*3d8817e4Smiod 248*3d8817e4Smiod /* rm register in the first register operand position. */ 249*3d8817e4Smiod #define RM0 (RN2+1) 250*3d8817e4Smiod {4, 0, MN10300_OPERAND_RREG}, 251*3d8817e4Smiod 252*3d8817e4Smiod /* rm register in the second register operand position. */ 253*3d8817e4Smiod #define RM1 (RM0+1) 254*3d8817e4Smiod {4, 2, MN10300_OPERAND_RREG}, 255*3d8817e4Smiod 256*3d8817e4Smiod /* rm register in the third register operand position. */ 257*3d8817e4Smiod #define RM2 (RM1+1) 258*3d8817e4Smiod {4, 4, MN10300_OPERAND_RREG}, 259*3d8817e4Smiod 260*3d8817e4Smiod #define RN02 (RM2+1) 261*3d8817e4Smiod {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED}, 262*3d8817e4Smiod 263*3d8817e4Smiod #define XRN0 (RN02+1) 264*3d8817e4Smiod {4, 0, MN10300_OPERAND_XRREG}, 265*3d8817e4Smiod 266*3d8817e4Smiod #define XRM2 (XRN0+1) 267*3d8817e4Smiod {4, 4, MN10300_OPERAND_XRREG}, 268*3d8817e4Smiod 269*3d8817e4Smiod /* + for autoincrement */ 270*3d8817e4Smiod #define PLUS (XRM2+1) 271*3d8817e4Smiod {0, 0, MN10300_OPERAND_PLUS}, 272*3d8817e4Smiod 273*3d8817e4Smiod #define XRN02 (PLUS+1) 274*3d8817e4Smiod {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED}, 275*3d8817e4Smiod 276*3d8817e4Smiod /* Ick */ 277*3d8817e4Smiod #define RD0 (XRN02+1) 278*3d8817e4Smiod {4, -8, MN10300_OPERAND_RREG}, 279*3d8817e4Smiod 280*3d8817e4Smiod #define RD2 (RD0+1) 281*3d8817e4Smiod {4, -4, MN10300_OPERAND_RREG}, 282*3d8817e4Smiod 283*3d8817e4Smiod /* 8 unsigned displacement in a memory operation which 284*3d8817e4Smiod may promote to a 32bit displacement. */ 285*3d8817e4Smiod #define IMM8_MEM (RD2+1) 286*3d8817e4Smiod {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, 287*3d8817e4Smiod 288*3d8817e4Smiod /* Index register. */ 289*3d8817e4Smiod #define RI (IMM8_MEM+1) 290*3d8817e4Smiod {4, 4, MN10300_OPERAND_RREG}, 291*3d8817e4Smiod 292*3d8817e4Smiod /* 24 bit signed displacement, may promote to 32bit displacement. */ 293*3d8817e4Smiod #define SD24 (RI+1) 294*3d8817e4Smiod {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, 295*3d8817e4Smiod 296*3d8817e4Smiod /* 24 bit unsigned immediate which may promote to a 32bit 297*3d8817e4Smiod unsigned immediate. */ 298*3d8817e4Smiod #define IMM24 (SD24+1) 299*3d8817e4Smiod {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE}, 300*3d8817e4Smiod 301*3d8817e4Smiod /* 24 bit signed immediate which may promote to a 32bit 302*3d8817e4Smiod signed immediate. */ 303*3d8817e4Smiod #define SIMM24 (IMM24+1) 304*3d8817e4Smiod {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED}, 305*3d8817e4Smiod 306*3d8817e4Smiod /* 24bit unsigned displacement in a memory operation which 307*3d8817e4Smiod may promote to a 32bit displacement. */ 308*3d8817e4Smiod #define IMM24_MEM (SIMM24+1) 309*3d8817e4Smiod {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, 310*3d8817e4Smiod /* 32bit immediate, high 8 bits in the main instruction 311*3d8817e4Smiod word, 24 in the extension word. 312*3d8817e4Smiod 313*3d8817e4Smiod The "bits" field indicates how many bits are in the 314*3d8817e4Smiod main instruction word for MN10300_OPERAND_SPLIT! */ 315*3d8817e4Smiod #define IMM32_HIGH8 (IMM24_MEM+1) 316*3d8817e4Smiod {8, 0, MN10300_OPERAND_SPLIT}, 317*3d8817e4Smiod 318*3d8817e4Smiod /* Similarly, but a memory address. */ 319*3d8817e4Smiod #define IMM32_HIGH8_MEM (IMM32_HIGH8+1) 320*3d8817e4Smiod {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, 321*3d8817e4Smiod 322*3d8817e4Smiod /* rm register in the seventh register operand position. */ 323*3d8817e4Smiod #define RM6 (IMM32_HIGH8_MEM+1) 324*3d8817e4Smiod {4, 12, MN10300_OPERAND_RREG}, 325*3d8817e4Smiod 326*3d8817e4Smiod /* rm register in the fifth register operand position. */ 327*3d8817e4Smiod #define RN4 (RM6+1) 328*3d8817e4Smiod {4, 8, MN10300_OPERAND_RREG}, 329*3d8817e4Smiod 330*3d8817e4Smiod /* 4 bit immediate for dsp instructions. */ 331*3d8817e4Smiod #define IMM4_2 (RN4+1) 332*3d8817e4Smiod {4, 4, 0}, 333*3d8817e4Smiod 334*3d8817e4Smiod /* 4 bit immediate for dsp instructions. */ 335*3d8817e4Smiod #define SIMM4_2 (IMM4_2+1) 336*3d8817e4Smiod {4, 4, MN10300_OPERAND_SIGNED}, 337*3d8817e4Smiod 338*3d8817e4Smiod /* 4 bit immediate for dsp instructions. */ 339*3d8817e4Smiod #define SIMM4_6 (SIMM4_2+1) 340*3d8817e4Smiod {4, 12, MN10300_OPERAND_SIGNED}, 341*3d8817e4Smiod 342*3d8817e4Smiod #define FPCR (SIMM4_6+1) 343*3d8817e4Smiod {0, 0, MN10300_OPERAND_FPCR}, 344*3d8817e4Smiod 345*3d8817e4Smiod /* We call f[sd]m registers those whose most significant bit is stored 346*3d8817e4Smiod * within the opcode half-word, i.e., in a bit on the left of the 4 347*3d8817e4Smiod * least significant bits, and f[sd]n registers those whose most 348*3d8817e4Smiod * significant bit is stored at the end of the full word, after the 4 349*3d8817e4Smiod * least significant bits. They're not numbered after their position 350*3d8817e4Smiod * in the mnemonic asm instruction, but after their position in the 351*3d8817e4Smiod * opcode word, i.e., depending on the amount of shift they need. 352*3d8817e4Smiod * 353*3d8817e4Smiod * The additional bit is shifted as follows: for `n' registers, it 354*3d8817e4Smiod * will be shifted by (|shift|/4); for `m' registers, it will be 355*3d8817e4Smiod * shifted by (8+(8&shift)+(shift&4)/4); for accumulator, whose 356*3d8817e4Smiod * specifications are only 3-bits long, the two least-significant bits 357*3d8817e4Smiod * are shifted by 16, and the most-significant bit is shifted by -2 358*3d8817e4Smiod * (i.e., it's stored in the least significant bit of the full 359*3d8817e4Smiod * word). */ 360*3d8817e4Smiod 361*3d8817e4Smiod /* fsm register in the first register operand position. */ 362*3d8817e4Smiod #define FSM0 (FPCR+1) 363*3d8817e4Smiod {5, 0, MN10300_OPERAND_FSREG }, 364*3d8817e4Smiod 365*3d8817e4Smiod /* fsm register in the second register operand position. */ 366*3d8817e4Smiod #define FSM1 (FSM0+1) 367*3d8817e4Smiod {5, 4, MN10300_OPERAND_FSREG }, 368*3d8817e4Smiod 369*3d8817e4Smiod /* fsm register in the third register operand position. */ 370*3d8817e4Smiod #define FSM2 (FSM1+1) 371*3d8817e4Smiod {5, 8, MN10300_OPERAND_FSREG }, 372*3d8817e4Smiod 373*3d8817e4Smiod /* fsm register in the fourth register operand position. */ 374*3d8817e4Smiod #define FSM3 (FSM2+1) 375*3d8817e4Smiod {5, 12, MN10300_OPERAND_FSREG }, 376*3d8817e4Smiod 377*3d8817e4Smiod /* fsn register in the first register operand position. */ 378*3d8817e4Smiod #define FSN1 (FSM3+1) 379*3d8817e4Smiod {5, -4, MN10300_OPERAND_FSREG }, 380*3d8817e4Smiod 381*3d8817e4Smiod /* fsn register in the second register operand position. */ 382*3d8817e4Smiod #define FSN2 (FSN1+1) 383*3d8817e4Smiod {5, -8, MN10300_OPERAND_FSREG }, 384*3d8817e4Smiod 385*3d8817e4Smiod /* fsm register in the third register operand position. */ 386*3d8817e4Smiod #define FSN3 (FSN2+1) 387*3d8817e4Smiod {5, -12, MN10300_OPERAND_FSREG }, 388*3d8817e4Smiod 389*3d8817e4Smiod /* fsm accumulator, in the fourth register operand position. */ 390*3d8817e4Smiod #define FSACC (FSN3+1) 391*3d8817e4Smiod {3, -16, MN10300_OPERAND_FSREG }, 392*3d8817e4Smiod 393*3d8817e4Smiod /* fdm register in the first register operand position. */ 394*3d8817e4Smiod #define FDM0 (FSACC+1) 395*3d8817e4Smiod {5, 0, MN10300_OPERAND_FDREG }, 396*3d8817e4Smiod 397*3d8817e4Smiod /* fdm register in the second register operand position. */ 398*3d8817e4Smiod #define FDM1 (FDM0+1) 399*3d8817e4Smiod {5, 4, MN10300_OPERAND_FDREG }, 400*3d8817e4Smiod 401*3d8817e4Smiod /* fdm register in the third register operand position. */ 402*3d8817e4Smiod #define FDM2 (FDM1+1) 403*3d8817e4Smiod {5, 8, MN10300_OPERAND_FDREG }, 404*3d8817e4Smiod 405*3d8817e4Smiod /* fdm register in the fourth register operand position. */ 406*3d8817e4Smiod #define FDM3 (FDM2+1) 407*3d8817e4Smiod {5, 12, MN10300_OPERAND_FDREG }, 408*3d8817e4Smiod 409*3d8817e4Smiod /* fdn register in the first register operand position. */ 410*3d8817e4Smiod #define FDN1 (FDM3+1) 411*3d8817e4Smiod {5, -4, MN10300_OPERAND_FDREG }, 412*3d8817e4Smiod 413*3d8817e4Smiod /* fdn register in the second register operand position. */ 414*3d8817e4Smiod #define FDN2 (FDN1+1) 415*3d8817e4Smiod {5, -8, MN10300_OPERAND_FDREG }, 416*3d8817e4Smiod 417*3d8817e4Smiod /* fdn register in the third register operand position. */ 418*3d8817e4Smiod #define FDN3 (FDN2+1) 419*3d8817e4Smiod {5, -12, MN10300_OPERAND_FDREG }, 420*3d8817e4Smiod 421*3d8817e4Smiod } ; 422*3d8817e4Smiod 423*3d8817e4Smiod #define MEM(ADDR) PAREN, ADDR, PAREN 424*3d8817e4Smiod #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN 425*3d8817e4Smiod #define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN 426*3d8817e4Smiod #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 427*3d8817e4Smiod 428*3d8817e4Smiod /* The opcode table. 429*3d8817e4Smiod 430*3d8817e4Smiod The format of the opcode table is: 431*3d8817e4Smiod 432*3d8817e4Smiod NAME OPCODE MASK MATCH_MASK, FORMAT, PROCESSOR { OPERANDS } 433*3d8817e4Smiod 434*3d8817e4Smiod NAME is the name of the instruction. 435*3d8817e4Smiod OPCODE is the instruction opcode. 436*3d8817e4Smiod MASK is the opcode mask; this is used to tell the disassembler 437*3d8817e4Smiod which bits in the actual opcode must match OPCODE. 438*3d8817e4Smiod OPERANDS is the list of operands. 439*3d8817e4Smiod 440*3d8817e4Smiod The disassembler reads the table in order and prints the first 441*3d8817e4Smiod instruction which matches, so this table is sorted to put more 442*3d8817e4Smiod specific instructions before more general instructions. It is also 443*3d8817e4Smiod sorted by major opcode. */ 444*3d8817e4Smiod 445*3d8817e4Smiod const struct mn10300_opcode mn10300_opcodes[] = { 446*3d8817e4Smiod { "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, 447*3d8817e4Smiod { "mov", 0x80, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}}, 448*3d8817e4Smiod { "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, 449*3d8817e4Smiod { "mov", 0xf1d0, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, 450*3d8817e4Smiod { "mov", 0x9000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}}, 451*3d8817e4Smiod { "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}}, 452*3d8817e4Smiod { "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}}, 453*3d8817e4Smiod { "mov", 0xf2f0, 0xfff3, 0, FMT_D0, 0, {AM1, SP}}, 454*3d8817e4Smiod { "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}}, 455*3d8817e4Smiod { "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}}, 456*3d8817e4Smiod { "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}}, 457*3d8817e4Smiod { "mov", 0xf2f2, 0xfff3, 0, FMT_D0, 0, {DM1, MDR}}, 458*3d8817e4Smiod { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, 459*3d8817e4Smiod { "mov", 0x5800, 0xfcff, 0, FMT_S1, 0, {MEM(SP), DN0}}, 460*3d8817e4Smiod { "mov", 0x300000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, 461*3d8817e4Smiod { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, 462*3d8817e4Smiod { "mov", 0x5c00, 0xfcff, 0, FMT_S1, 0, {MEM(SP), AN0}}, 463*3d8817e4Smiod { "mov", 0xfaa00000, 0xfffc0000, 0, FMT_D2, 0, {MEM(IMM16_MEM), AN0}}, 464*3d8817e4Smiod { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, 465*3d8817e4Smiod { "mov", 0x4200, 0xf3ff, 0, FMT_S1, 0, {DM1, MEM(SP)}}, 466*3d8817e4Smiod { "mov", 0x010000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, 467*3d8817e4Smiod { "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}}, 468*3d8817e4Smiod { "mov", 0x4300, 0xf3ff, 0, FMT_S1, 0, {AM1, MEM(SP)}}, 469*3d8817e4Smiod { "mov", 0xfa800000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM(IMM16_MEM)}}, 470*3d8817e4Smiod { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}}, 471*3d8817e4Smiod { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, 472*3d8817e4Smiod { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, 473*3d8817e4Smiod { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}}, 474*3d8817e4Smiod { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, 475*3d8817e4Smiod { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, 476*3d8817e4Smiod { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, 477*3d8817e4Smiod { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, 478*3d8817e4Smiod { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}}, 479*3d8817e4Smiod { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}}, 480*3d8817e4Smiod { "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}}, 481*3d8817e4Smiod { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, 482*3d8817e4Smiod { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, 483*3d8817e4Smiod { "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}}, 484*3d8817e4Smiod { "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, 485*3d8817e4Smiod { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, 486*3d8817e4Smiod { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, 487*3d8817e4Smiod { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, 488*3d8817e4Smiod { "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}}, 489*3d8817e4Smiod { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}}, 490*3d8817e4Smiod 491*3d8817e4Smiod { "mov", 0xf020, 0xfffc, 0, FMT_D0, AM33, {USP, AN0}}, 492*3d8817e4Smiod { "mov", 0xf024, 0xfffc, 0, FMT_D0, AM33, {SSP, AN0}}, 493*3d8817e4Smiod { "mov", 0xf028, 0xfffc, 0, FMT_D0, AM33, {MSP, AN0}}, 494*3d8817e4Smiod { "mov", 0xf02c, 0xfffc, 0, FMT_D0, AM33, {PC, AN0}}, 495*3d8817e4Smiod { "mov", 0xf030, 0xfff3, 0, FMT_D0, AM33, {AN1, USP}}, 496*3d8817e4Smiod { "mov", 0xf031, 0xfff3, 0, FMT_D0, AM33, {AN1, SSP}}, 497*3d8817e4Smiod { "mov", 0xf032, 0xfff3, 0, FMT_D0, AM33, {AN1, MSP}}, 498*3d8817e4Smiod { "mov", 0xf2ec, 0xfffc, 0, FMT_D0, AM33, {EPSW, DN0}}, 499*3d8817e4Smiod { "mov", 0xf2f1, 0xfff3, 0, FMT_D0, AM33, {DM1, EPSW}}, 500*3d8817e4Smiod { "mov", 0xf500, 0xffc0, 0, FMT_D0, AM33, {AM2, RN0}}, 501*3d8817e4Smiod { "mov", 0xf540, 0xffc0, 0, FMT_D0, AM33, {DM2, RN0}}, 502*3d8817e4Smiod { "mov", 0xf580, 0xffc0, 0, FMT_D0, AM33, {RM1, AN0}}, 503*3d8817e4Smiod { "mov", 0xf5c0, 0xffc0, 0, FMT_D0, AM33, {RM1, DN0}}, 504*3d8817e4Smiod { "mov", 0xf90800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 505*3d8817e4Smiod { "mov", 0xf9e800, 0xffff00, 0, FMT_D6, AM33, {XRM2, RN0}}, 506*3d8817e4Smiod { "mov", 0xf9f800, 0xffff00, 0, FMT_D6, AM33, {RM2, XRN0}}, 507*3d8817e4Smiod { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, 508*3d8817e4Smiod { "mov", 0xf98a00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, 509*3d8817e4Smiod { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, 510*3d8817e4Smiod { "mov", 0xfb0e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, 511*3d8817e4Smiod { "mov", 0xfd0e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, 512*3d8817e4Smiod { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, 513*3d8817e4Smiod { "mov", 0xf99a00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, 514*3d8817e4Smiod { "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, 515*3d8817e4Smiod { "mov", 0xfb1e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, 516*3d8817e4Smiod { "mov", 0xfd1e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, 517*3d8817e4Smiod { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, 518*3d8817e4Smiod { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, 519*3d8817e4Smiod { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, 520*3d8817e4Smiod { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, 521*3d8817e4Smiod { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, 522*3d8817e4Smiod { "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, 523*3d8817e4Smiod { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, 524*3d8817e4Smiod { "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, 525*3d8817e4Smiod { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, 526*3d8817e4Smiod { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, 527*3d8817e4Smiod { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 528*3d8817e4Smiod { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 529*3d8817e4Smiod { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, 530*3d8817e4Smiod { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, 531*3d8817e4Smiod { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, 532*3d8817e4Smiod { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, 533*3d8817e4Smiod /* These must come after most of the other move instructions to avoid matching 534*3d8817e4Smiod a symbolic name with IMMxx operands. Ugh. */ 535*3d8817e4Smiod { "mov", 0x2c0000, 0xfc0000, 0, FMT_S2, 0, {SIMM16, DN0}}, 536*3d8817e4Smiod { "mov", 0xfccc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 537*3d8817e4Smiod { "mov", 0x240000, 0xfc0000, 0, FMT_S2, 0, {IMM16, AN0}}, 538*3d8817e4Smiod { "mov", 0xfcdc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, 539*3d8817e4Smiod { "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, 540*3d8817e4Smiod { "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}}, 541*3d8817e4Smiod { "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, 542*3d8817e4Smiod { "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}}, 543*3d8817e4Smiod { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, 544*3d8817e4Smiod { "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, 545*3d8817e4Smiod { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, 546*3d8817e4Smiod { "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}}, 547*3d8817e4Smiod { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, 548*3d8817e4Smiod { "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, 549*3d8817e4Smiod { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, 550*3d8817e4Smiod { "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}}, 551*3d8817e4Smiod /* These non-promoting variants need to come after all the other memory 552*3d8817e4Smiod moves. */ 553*3d8817e4Smiod { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM30, {MEM2(SD8N, AM0), SP}}, 554*3d8817e4Smiod { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM30, {SP, MEM2(SD8N, AN0)}}, 555*3d8817e4Smiod /* These are the same as the previous non-promoting versions. The am33 556*3d8817e4Smiod does not have restrictions on the offsets used to load/store the stack 557*3d8817e4Smiod pointer. */ 558*3d8817e4Smiod { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}}, 559*3d8817e4Smiod { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}}, 560*3d8817e4Smiod /* These must come last so that we favor shorter move instructions for 561*3d8817e4Smiod loading immediates into d0-d3/a0-a3. */ 562*3d8817e4Smiod { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 563*3d8817e4Smiod { "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, 564*3d8817e4Smiod { "mov", 0xfe080000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 565*3d8817e4Smiod { "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, XRN02}}, 566*3d8817e4Smiod { "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, XRN02}}, 567*3d8817e4Smiod { "mov", 0xfef80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, XRN02}}, 568*3d8817e4Smiod { "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, 569*3d8817e4Smiod { "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, 570*3d8817e4Smiod { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, 571*3d8817e4Smiod { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, 572*3d8817e4Smiod { "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, 573*3d8817e4Smiod { "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, 574*3d8817e4Smiod 575*3d8817e4Smiod { "movu", 0xfb180000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 576*3d8817e4Smiod { "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 577*3d8817e4Smiod { "movu", 0xfe180000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 578*3d8817e4Smiod 579*3d8817e4Smiod { "mcst9", 0xf630, 0xfff0, 0, FMT_D0, AM33, {DN01}}, 580*3d8817e4Smiod { "mcst48", 0xf660, 0xfff0, 0, FMT_D0, AM33, {DN01}}, 581*3d8817e4Smiod { "swap", 0xf680, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}}, 582*3d8817e4Smiod { "swap", 0xf9cb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 583*3d8817e4Smiod { "swaph", 0xf690, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}}, 584*3d8817e4Smiod { "swaph", 0xf9db00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 585*3d8817e4Smiod { "getchx", 0xf6c0, 0xfff0, 0, FMT_D0, AM33, {DN01}}, 586*3d8817e4Smiod { "getclx", 0xf6d0, 0xfff0, 0, FMT_D0, AM33, {DN01}}, 587*3d8817e4Smiod { "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, 588*3d8817e4Smiod { "mac", 0xf90b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 589*3d8817e4Smiod { "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 590*3d8817e4Smiod { "mac", 0xfd0b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, 591*3d8817e4Smiod { "mac", 0xfe0b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 592*3d8817e4Smiod { "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, 593*3d8817e4Smiod { "macu", 0xf91b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 594*3d8817e4Smiod { "macu", 0xfb1b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 595*3d8817e4Smiod { "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 596*3d8817e4Smiod { "macu", 0xfe1b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 597*3d8817e4Smiod { "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 598*3d8817e4Smiod { "macb", 0xf92b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 599*3d8817e4Smiod { "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 600*3d8817e4Smiod { "macb", 0xfd2b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, 601*3d8817e4Smiod { "macb", 0xfe2b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 602*3d8817e4Smiod { "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 603*3d8817e4Smiod { "macbu", 0xf93b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 604*3d8817e4Smiod { "macbu", 0xfb3b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 605*3d8817e4Smiod { "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 606*3d8817e4Smiod { "macbu", 0xfe3b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 607*3d8817e4Smiod { "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, 608*3d8817e4Smiod { "mach", 0xf94b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 609*3d8817e4Smiod { "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 610*3d8817e4Smiod { "mach", 0xfd4b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, 611*3d8817e4Smiod { "mach", 0xfe4b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 612*3d8817e4Smiod { "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, 613*3d8817e4Smiod { "machu", 0xf95b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 614*3d8817e4Smiod { "machu", 0xfb5b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 615*3d8817e4Smiod { "machu", 0xfd5b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 616*3d8817e4Smiod { "machu", 0xfe5b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 617*3d8817e4Smiod { "dmach", 0xfb6f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 618*3d8817e4Smiod { "dmach", 0xf96b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 619*3d8817e4Smiod { "dmach", 0xfe6b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 620*3d8817e4Smiod { "dmachu", 0xfb7f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 621*3d8817e4Smiod { "dmachu", 0xf97b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 622*3d8817e4Smiod { "dmachu", 0xfe7b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 623*3d8817e4Smiod { "dmulh", 0xfb8f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, 624*3d8817e4Smiod { "dmulh", 0xf98b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 625*3d8817e4Smiod { "dmulh", 0xfe8b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 626*3d8817e4Smiod { "dmulhu", 0xfb9f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, 627*3d8817e4Smiod { "dmulhu", 0xf99b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 628*3d8817e4Smiod { "dmulhu", 0xfe9b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 629*3d8817e4Smiod { "mcste", 0xf9bb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 630*3d8817e4Smiod { "mcste", 0xfbbb0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 631*3d8817e4Smiod { "swhw", 0xf9eb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 632*3d8817e4Smiod 633*3d8817e4Smiod { "movbu", 0xf040, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, 634*3d8817e4Smiod { "movbu", 0xf84000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, 635*3d8817e4Smiod { "movbu", 0xfa400000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, 636*3d8817e4Smiod { "movbu", 0xf8b800, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}}, 637*3d8817e4Smiod { "movbu", 0xf8b800, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, 638*3d8817e4Smiod { "movbu", 0xfab80000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, 639*3d8817e4Smiod { "movbu", 0xf400, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, 640*3d8817e4Smiod { "movbu", 0x340000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, 641*3d8817e4Smiod { "movbu", 0xf050, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, 642*3d8817e4Smiod { "movbu", 0xf85000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, 643*3d8817e4Smiod { "movbu", 0xfa500000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, 644*3d8817e4Smiod { "movbu", 0xf89200, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}}, 645*3d8817e4Smiod { "movbu", 0xf89200, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, 646*3d8817e4Smiod { "movbu", 0xfa920000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, 647*3d8817e4Smiod { "movbu", 0xf440, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, 648*3d8817e4Smiod { "movbu", 0x020000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, 649*3d8817e4Smiod { "movbu", 0xf92a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, 650*3d8817e4Smiod { "movbu", 0xf93a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, 651*3d8817e4Smiod { "movbu", 0xf9aa00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, 652*3d8817e4Smiod { "movbu", 0xf9ba00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, 653*3d8817e4Smiod { "movbu", 0xfb2a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, 654*3d8817e4Smiod { "movbu", 0xfd2a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, 655*3d8817e4Smiod { "movbu", 0xfb3a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, 656*3d8817e4Smiod { "movbu", 0xfd3a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, 657*3d8817e4Smiod { "movbu", 0xfbaa0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, 658*3d8817e4Smiod { "movbu", 0xfdaa0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, 659*3d8817e4Smiod { "movbu", 0xfbba0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, 660*3d8817e4Smiod { "movbu", 0xfdba0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, 661*3d8817e4Smiod { "movbu", 0xfb2e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, 662*3d8817e4Smiod { "movbu", 0xfd2e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, 663*3d8817e4Smiod { "movbu", 0xfb3e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, 664*3d8817e4Smiod { "movbu", 0xfd3e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, 665*3d8817e4Smiod { "movbu", 0xfbae0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, 666*3d8817e4Smiod { "movbu", 0xfbbe0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, 667*3d8817e4Smiod { "movbu", 0xfc400000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, 668*3d8817e4Smiod { "movbu", 0xfcb80000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, 669*3d8817e4Smiod { "movbu", 0xfca80000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, 670*3d8817e4Smiod { "movbu", 0xfc500000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, 671*3d8817e4Smiod { "movbu", 0xfc920000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, 672*3d8817e4Smiod { "movbu", 0xfc820000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, 673*3d8817e4Smiod { "movbu", 0xfe2a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, 674*3d8817e4Smiod { "movbu", 0xfe3a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, 675*3d8817e4Smiod { "movbu", 0xfeaa0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,SP), RN2}}, 676*3d8817e4Smiod { "movbu", 0xfeba0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, 677*3d8817e4Smiod { "movbu", 0xfe2e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, 678*3d8817e4Smiod { "movbu", 0xfe3e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, 679*3d8817e4Smiod 680*3d8817e4Smiod { "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, 681*3d8817e4Smiod { "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, 682*3d8817e4Smiod { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, 683*3d8817e4Smiod { "movhu", 0xf8bc00, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}}, 684*3d8817e4Smiod { "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, 685*3d8817e4Smiod { "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, 686*3d8817e4Smiod { "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, 687*3d8817e4Smiod { "movhu", 0x380000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, 688*3d8817e4Smiod { "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, 689*3d8817e4Smiod { "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, 690*3d8817e4Smiod { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, 691*3d8817e4Smiod { "movhu", 0xf89300, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}}, 692*3d8817e4Smiod { "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, 693*3d8817e4Smiod { "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, 694*3d8817e4Smiod { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, 695*3d8817e4Smiod { "movhu", 0x030000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, 696*3d8817e4Smiod { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, 697*3d8817e4Smiod { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, 698*3d8817e4Smiod { "movhu", 0xf9ca00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, 699*3d8817e4Smiod { "movhu", 0xf9da00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, 700*3d8817e4Smiod { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, 701*3d8817e4Smiod { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, 702*3d8817e4Smiod { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, 703*3d8817e4Smiod { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, 704*3d8817e4Smiod { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, 705*3d8817e4Smiod { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, 706*3d8817e4Smiod { "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, 707*3d8817e4Smiod { "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, 708*3d8817e4Smiod { "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, 709*3d8817e4Smiod { "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, 710*3d8817e4Smiod { "movhu", 0xfb4e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, 711*3d8817e4Smiod { "movhu", 0xfd4e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, 712*3d8817e4Smiod { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, 713*3d8817e4Smiod { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, 714*3d8817e4Smiod { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, 715*3d8817e4Smiod { "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, 716*3d8817e4Smiod { "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, 717*3d8817e4Smiod { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, 718*3d8817e4Smiod { "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, 719*3d8817e4Smiod { "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, 720*3d8817e4Smiod { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, 721*3d8817e4Smiod { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, 722*3d8817e4Smiod { "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, 723*3d8817e4Smiod { "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, 724*3d8817e4Smiod { "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, 725*3d8817e4Smiod { "movhu", 0xfb5e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, 726*3d8817e4Smiod { "movhu", 0xfd5e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, 727*3d8817e4Smiod { "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, 728*3d8817e4Smiod { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 729*3d8817e4Smiod { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 730*3d8817e4Smiod { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, 731*3d8817e4Smiod { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, 732*3d8817e4Smiod { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, 733*3d8817e4Smiod { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, 734*3d8817e4Smiod 735*3d8817e4Smiod { "ext", 0xf2d0, 0xfffc, 0, FMT_D0, 0, {DN0}}, 736*3d8817e4Smiod { "ext", 0xf91800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 737*3d8817e4Smiod 738*3d8817e4Smiod { "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 739*3d8817e4Smiod { "extb", 0x10, 0xfc, 0, FMT_S0, 0, {DN0}}, 740*3d8817e4Smiod { "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 741*3d8817e4Smiod 742*3d8817e4Smiod { "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 743*3d8817e4Smiod { "extbu", 0x14, 0xfc, 0, FMT_S0, 0, {DN0}}, 744*3d8817e4Smiod { "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 745*3d8817e4Smiod 746*3d8817e4Smiod { "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 747*3d8817e4Smiod { "exth", 0x18, 0xfc, 0, FMT_S0, 0, {DN0}}, 748*3d8817e4Smiod { "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 749*3d8817e4Smiod 750*3d8817e4Smiod { "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 751*3d8817e4Smiod { "exthu", 0x1c, 0xfc, 0, FMT_S0, 0, {DN0}}, 752*3d8817e4Smiod { "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 753*3d8817e4Smiod 754*3d8817e4Smiod { "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}}, 755*3d8817e4Smiod { "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}}, 756*3d8817e4Smiod { "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}}, 757*3d8817e4Smiod { "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}}, 758*3d8817e4Smiod 759*3d8817e4Smiod { "clr", 0x00, 0xf3, 0, FMT_S0, 0, {DN1}}, 760*3d8817e4Smiod { "clr", 0xf96800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 761*3d8817e4Smiod 762*3d8817e4Smiod { "add", 0xfb7c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 763*3d8817e4Smiod { "add", 0xe0, 0xf0, 0, FMT_S0, 0, {DM1, DN0}}, 764*3d8817e4Smiod { "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, 765*3d8817e4Smiod { "add", 0xf150, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, 766*3d8817e4Smiod { "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}}, 767*3d8817e4Smiod { "add", 0x2800, 0xfc00, 0, FMT_S1, 0, {SIMM8, DN0}}, 768*3d8817e4Smiod { "add", 0xfac00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 769*3d8817e4Smiod { "add", 0x2000, 0xfc00, 0, FMT_S1, 0, {SIMM8, AN0}}, 770*3d8817e4Smiod { "add", 0xfad00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, AN0}}, 771*3d8817e4Smiod { "add", 0xf8fe00, 0xffff00, 0, FMT_D1, 0, {SIMM8, SP}}, 772*3d8817e4Smiod { "add", 0xfafe0000, 0xffff0000, 0, FMT_D2, 0, {SIMM16, SP}}, 773*3d8817e4Smiod { "add", 0xf97800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 774*3d8817e4Smiod { "add", 0xfcc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 775*3d8817e4Smiod { "add", 0xfcd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, 776*3d8817e4Smiod { "add", 0xfcfe0000, 0xffff0000, 0, FMT_D4, 0, {IMM32, SP}}, 777*3d8817e4Smiod { "add", 0xfb780000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 778*3d8817e4Smiod { "add", 0xfd780000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, 779*3d8817e4Smiod { "add", 0xfe780000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 780*3d8817e4Smiod 781*3d8817e4Smiod { "addc", 0xfb8c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 782*3d8817e4Smiod { "addc", 0xf140, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 783*3d8817e4Smiod { "addc", 0xf98800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 784*3d8817e4Smiod { "addc", 0xfb880000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 785*3d8817e4Smiod { "addc", 0xfd880000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, 786*3d8817e4Smiod { "addc", 0xfe880000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 787*3d8817e4Smiod 788*3d8817e4Smiod { "sub", 0xfb9c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 789*3d8817e4Smiod { "sub", 0xf100, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 790*3d8817e4Smiod { "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, 791*3d8817e4Smiod { "sub", 0xf110, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, 792*3d8817e4Smiod { "sub", 0xf130, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}}, 793*3d8817e4Smiod { "sub", 0xf99800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 794*3d8817e4Smiod { "sub", 0xfcc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 795*3d8817e4Smiod { "sub", 0xfcd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, 796*3d8817e4Smiod { "sub", 0xfb980000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 797*3d8817e4Smiod { "sub", 0xfd980000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, 798*3d8817e4Smiod { "sub", 0xfe980000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 799*3d8817e4Smiod 800*3d8817e4Smiod { "subc", 0xfbac0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 801*3d8817e4Smiod { "subc", 0xf180, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 802*3d8817e4Smiod { "subc", 0xf9a800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 803*3d8817e4Smiod { "subc", 0xfba80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 804*3d8817e4Smiod { "subc", 0xfda80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, 805*3d8817e4Smiod { "subc", 0xfea80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 806*3d8817e4Smiod 807*3d8817e4Smiod { "mul", 0xfbad0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, 808*3d8817e4Smiod { "mul", 0xf240, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 809*3d8817e4Smiod { "mul", 0xf9a900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 810*3d8817e4Smiod { "mul", 0xfba90000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 811*3d8817e4Smiod { "mul", 0xfda90000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, 812*3d8817e4Smiod { "mul", 0xfea90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 813*3d8817e4Smiod 814*3d8817e4Smiod { "mulu", 0xfbbd0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, 815*3d8817e4Smiod { "mulu", 0xf250, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 816*3d8817e4Smiod { "mulu", 0xf9b900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 817*3d8817e4Smiod { "mulu", 0xfbb90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 818*3d8817e4Smiod { "mulu", 0xfdb90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 819*3d8817e4Smiod { "mulu", 0xfeb90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 820*3d8817e4Smiod 821*3d8817e4Smiod { "div", 0xf260, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 822*3d8817e4Smiod { "div", 0xf9c900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 823*3d8817e4Smiod 824*3d8817e4Smiod { "divu", 0xf270, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 825*3d8817e4Smiod { "divu", 0xf9d900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 826*3d8817e4Smiod 827*3d8817e4Smiod { "inc", 0x40, 0xf3, 0, FMT_S0, 0, {DN1}}, 828*3d8817e4Smiod { "inc", 0x41, 0xf3, 0, FMT_S0, 0, {AN1}}, 829*3d8817e4Smiod { "inc", 0xf9b800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 830*3d8817e4Smiod 831*3d8817e4Smiod { "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}}, 832*3d8817e4Smiod { "inc4", 0xf9c800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 833*3d8817e4Smiod 834*3d8817e4Smiod { "cmp", 0xa000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, 835*3d8817e4Smiod { "cmp", 0xa0, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}}, 836*3d8817e4Smiod { "cmp", 0xf1a0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, 837*3d8817e4Smiod { "cmp", 0xf190, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, 838*3d8817e4Smiod { "cmp", 0xb000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}}, 839*3d8817e4Smiod { "cmp", 0xb0, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}}, 840*3d8817e4Smiod { "cmp", 0xfac80000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 841*3d8817e4Smiod { "cmp", 0xfad80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, AN0}}, 842*3d8817e4Smiod { "cmp", 0xf9d800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 843*3d8817e4Smiod { "cmp", 0xfcc80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 844*3d8817e4Smiod { "cmp", 0xfcd80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, 845*3d8817e4Smiod { "cmp", 0xfbd80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 846*3d8817e4Smiod { "cmp", 0xfdd80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, 847*3d8817e4Smiod { "cmp", 0xfed80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 848*3d8817e4Smiod 849*3d8817e4Smiod { "and", 0xfb0d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 850*3d8817e4Smiod { "and", 0xf200, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 851*3d8817e4Smiod { "and", 0xf8e000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 852*3d8817e4Smiod { "and", 0xfae00000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 853*3d8817e4Smiod { "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}}, 854*3d8817e4Smiod { "and", 0xfcfc0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}}, 855*3d8817e4Smiod { "and", 0xf90900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 856*3d8817e4Smiod { "and", 0xfce00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 857*3d8817e4Smiod { "and", 0xfb090000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 858*3d8817e4Smiod { "and", 0xfd090000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 859*3d8817e4Smiod { "and", 0xfe090000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 860*3d8817e4Smiod 861*3d8817e4Smiod { "or", 0xfb1d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 862*3d8817e4Smiod { "or", 0xf210, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 863*3d8817e4Smiod { "or", 0xf8e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 864*3d8817e4Smiod { "or", 0xfae40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 865*3d8817e4Smiod { "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}}, 866*3d8817e4Smiod { "or", 0xfcfd0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}}, 867*3d8817e4Smiod { "or", 0xf91900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 868*3d8817e4Smiod { "or", 0xfce40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 869*3d8817e4Smiod { "or", 0xfb190000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 870*3d8817e4Smiod { "or", 0xfd190000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 871*3d8817e4Smiod { "or", 0xfe190000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 872*3d8817e4Smiod 873*3d8817e4Smiod { "xor", 0xfb2d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 874*3d8817e4Smiod { "xor", 0xf220, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 875*3d8817e4Smiod { "xor", 0xfae80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 876*3d8817e4Smiod { "xor", 0xf92900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 877*3d8817e4Smiod { "xor", 0xfce80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 878*3d8817e4Smiod { "xor", 0xfb290000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 879*3d8817e4Smiod { "xor", 0xfd290000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 880*3d8817e4Smiod { "xor", 0xfe290000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 881*3d8817e4Smiod 882*3d8817e4Smiod { "not", 0xf230, 0xfffc, 0, FMT_D0, 0, {DN0}}, 883*3d8817e4Smiod { "not", 0xf93900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 884*3d8817e4Smiod 885*3d8817e4Smiod { "btst", 0xf8ec00, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 886*3d8817e4Smiod { "btst", 0xfaec0000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 887*3d8817e4Smiod { "btst", 0xfcec0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 888*3d8817e4Smiod /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the 889*3d8817e4Smiod them to match last since they do not promote. */ 890*3d8817e4Smiod { "btst", 0xfbe90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 891*3d8817e4Smiod { "btst", 0xfde90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 892*3d8817e4Smiod { "btst", 0xfee90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 893*3d8817e4Smiod { "btst", 0xfe820000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}}, 894*3d8817e4Smiod { "btst", 0xfe020000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, 895*3d8817e4Smiod { "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}}, 896*3d8817e4Smiod 897*3d8817e4Smiod { "bset", 0xf080, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, 898*3d8817e4Smiod { "bset", 0xfe800000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}}, 899*3d8817e4Smiod { "bset", 0xfe000000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, 900*3d8817e4Smiod { "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}}, 901*3d8817e4Smiod 902*3d8817e4Smiod { "bclr", 0xf090, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, 903*3d8817e4Smiod { "bclr", 0xfe810000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}}, 904*3d8817e4Smiod { "bclr", 0xfe010000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, 905*3d8817e4Smiod { "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}}, 906*3d8817e4Smiod 907*3d8817e4Smiod { "asr", 0xfb4d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 908*3d8817e4Smiod { "asr", 0xf2b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 909*3d8817e4Smiod { "asr", 0xf8c800, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 910*3d8817e4Smiod { "asr", 0xf94900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 911*3d8817e4Smiod { "asr", 0xfb490000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 912*3d8817e4Smiod { "asr", 0xfd490000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 913*3d8817e4Smiod { "asr", 0xfe490000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 914*3d8817e4Smiod { "asr", 0xf8c801, 0xfffcff, 0, FMT_D1, 0, {DN0}}, 915*3d8817e4Smiod { "asr", 0xfb490001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, 916*3d8817e4Smiod 917*3d8817e4Smiod { "lsr", 0xfb5d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 918*3d8817e4Smiod { "lsr", 0xf2a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 919*3d8817e4Smiod { "lsr", 0xf8c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 920*3d8817e4Smiod { "lsr", 0xf95900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 921*3d8817e4Smiod { "lsr", 0xfb590000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, 922*3d8817e4Smiod { "lsr", 0xfd590000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 923*3d8817e4Smiod { "lsr", 0xfe590000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 924*3d8817e4Smiod { "lsr", 0xf8c401, 0xfffcff, 0, FMT_D1, 0, {DN0}}, 925*3d8817e4Smiod { "lsr", 0xfb590001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, 926*3d8817e4Smiod 927*3d8817e4Smiod { "asl", 0xfb6d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 928*3d8817e4Smiod { "asl", 0xf290, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 929*3d8817e4Smiod { "asl", 0xf8c000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 930*3d8817e4Smiod { "asl", 0xf96900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 931*3d8817e4Smiod { "asl", 0xfb690000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, 932*3d8817e4Smiod { "asl", 0xfd690000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, 933*3d8817e4Smiod { "asl", 0xfe690000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, 934*3d8817e4Smiod { "asl", 0xf8c001, 0xfffcff, 0, FMT_D1, 0, {DN0}}, 935*3d8817e4Smiod { "asl", 0xfb690001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, 936*3d8817e4Smiod 937*3d8817e4Smiod { "asl2", 0x54, 0xfc, 0, FMT_S0, 0, {DN0}}, 938*3d8817e4Smiod { "asl2", 0xf97900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 939*3d8817e4Smiod 940*3d8817e4Smiod { "ror", 0xf284, 0xfffc, 0, FMT_D0, 0, {DN0}}, 941*3d8817e4Smiod { "ror", 0xf98900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 942*3d8817e4Smiod 943*3d8817e4Smiod { "rol", 0xf280, 0xfffc, 0, FMT_D0, 0, {DN0}}, 944*3d8817e4Smiod { "rol", 0xf99900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, 945*3d8817e4Smiod 946*3d8817e4Smiod { "beq", 0xc800, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 947*3d8817e4Smiod { "bne", 0xc900, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 948*3d8817e4Smiod { "bgt", 0xc100, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 949*3d8817e4Smiod { "bge", 0xc200, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 950*3d8817e4Smiod { "ble", 0xc300, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 951*3d8817e4Smiod { "blt", 0xc000, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 952*3d8817e4Smiod { "bhi", 0xc500, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 953*3d8817e4Smiod { "bcc", 0xc600, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 954*3d8817e4Smiod { "bls", 0xc700, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 955*3d8817e4Smiod { "bcs", 0xc400, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 956*3d8817e4Smiod { "bvc", 0xf8e800, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, 957*3d8817e4Smiod { "bvs", 0xf8e900, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, 958*3d8817e4Smiod { "bnc", 0xf8ea00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, 959*3d8817e4Smiod { "bns", 0xf8eb00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, 960*3d8817e4Smiod { "bra", 0xca00, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, 961*3d8817e4Smiod 962*3d8817e4Smiod { "leq", 0xd8, 0xff, 0, FMT_S0, 0, {UNUSED}}, 963*3d8817e4Smiod { "lne", 0xd9, 0xff, 0, FMT_S0, 0, {UNUSED}}, 964*3d8817e4Smiod { "lgt", 0xd1, 0xff, 0, FMT_S0, 0, {UNUSED}}, 965*3d8817e4Smiod { "lge", 0xd2, 0xff, 0, FMT_S0, 0, {UNUSED}}, 966*3d8817e4Smiod { "lle", 0xd3, 0xff, 0, FMT_S0, 0, {UNUSED}}, 967*3d8817e4Smiod { "llt", 0xd0, 0xff, 0, FMT_S0, 0, {UNUSED}}, 968*3d8817e4Smiod { "lhi", 0xd5, 0xff, 0, FMT_S0, 0, {UNUSED}}, 969*3d8817e4Smiod { "lcc", 0xd6, 0xff, 0, FMT_S0, 0, {UNUSED}}, 970*3d8817e4Smiod { "lls", 0xd7, 0xff, 0, FMT_S0, 0, {UNUSED}}, 971*3d8817e4Smiod { "lcs", 0xd4, 0xff, 0, FMT_S0, 0, {UNUSED}}, 972*3d8817e4Smiod { "lra", 0xda, 0xff, 0, FMT_S0, 0, {UNUSED}}, 973*3d8817e4Smiod { "setlb", 0xdb, 0xff, 0, FMT_S0, 0, {UNUSED}}, 974*3d8817e4Smiod 975*3d8817e4Smiod { "fbeq", 0xf8d000, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 976*3d8817e4Smiod { "fbne", 0xf8d100, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 977*3d8817e4Smiod { "fbgt", 0xf8d200, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 978*3d8817e4Smiod { "fbge", 0xf8d300, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 979*3d8817e4Smiod { "fblt", 0xf8d400, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 980*3d8817e4Smiod { "fble", 0xf8d500, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 981*3d8817e4Smiod { "fbuo", 0xf8d600, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 982*3d8817e4Smiod { "fblg", 0xf8d700, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 983*3d8817e4Smiod { "fbleg", 0xf8d800, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 984*3d8817e4Smiod { "fbug", 0xf8d900, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 985*3d8817e4Smiod { "fbuge", 0xf8da00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 986*3d8817e4Smiod { "fbul", 0xf8db00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 987*3d8817e4Smiod { "fbule", 0xf8dc00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 988*3d8817e4Smiod { "fbue", 0xf8dd00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, 989*3d8817e4Smiod 990*3d8817e4Smiod { "fleq", 0xf0d0, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 991*3d8817e4Smiod { "flne", 0xf0d1, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 992*3d8817e4Smiod { "flgt", 0xf0d2, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 993*3d8817e4Smiod { "flge", 0xf0d3, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 994*3d8817e4Smiod { "fllt", 0xf0d4, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 995*3d8817e4Smiod { "flle", 0xf0d5, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 996*3d8817e4Smiod { "fluo", 0xf0d6, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 997*3d8817e4Smiod { "fllg", 0xf0d7, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 998*3d8817e4Smiod { "flleg", 0xf0d8, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 999*3d8817e4Smiod { "flug", 0xf0d9, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 1000*3d8817e4Smiod { "fluge", 0xf0da, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 1001*3d8817e4Smiod { "flul", 0xf0db, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 1002*3d8817e4Smiod { "flule", 0xf0dc, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 1003*3d8817e4Smiod { "flue", 0xf0dd, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, 1004*3d8817e4Smiod 1005*3d8817e4Smiod { "jmp", 0xf0f4, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}}, 1006*3d8817e4Smiod { "jmp", 0xcc0000, 0xff0000, 0, FMT_S2, 0, {IMM16_PCREL}}, 1007*3d8817e4Smiod { "jmp", 0xdc000000, 0xff000000, 0, FMT_S4, 0, {IMM32_HIGH24}}, 1008*3d8817e4Smiod { "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}}, 1009*3d8817e4Smiod { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}}, 1010*3d8817e4Smiod { "calls", 0xf0f0, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}}, 1011*3d8817e4Smiod { "calls", 0xfaff0000, 0xffff0000, 0, FMT_D2, 0, {IMM16_PCREL}}, 1012*3d8817e4Smiod { "calls", 0xfcff0000, 0xffff0000, 0, FMT_D4, 0, {IMM32_PCREL}}, 1013*3d8817e4Smiod 1014*3d8817e4Smiod { "ret", 0xdf0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}}, 1015*3d8817e4Smiod { "retf", 0xde0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}}, 1016*3d8817e4Smiod { "rets", 0xf0fc, 0xffff, 0, FMT_D0, 0, {UNUSED}}, 1017*3d8817e4Smiod { "rti", 0xf0fd, 0xffff, 0, FMT_D0, 0, {UNUSED}}, 1018*3d8817e4Smiod { "trap", 0xf0fe, 0xffff, 0, FMT_D0, 0, {UNUSED}}, 1019*3d8817e4Smiod { "rtm", 0xf0ff, 0xffff, 0, FMT_D0, 0, {UNUSED}}, 1020*3d8817e4Smiod { "nop", 0xcb, 0xff, 0, FMT_S0, 0, {UNUSED}}, 1021*3d8817e4Smiod 1022*3d8817e4Smiod { "dcpf", 0xf9a600, 0xffff0f, 0, FMT_D6, AM33_2, {MEM (RM2)}}, 1023*3d8817e4Smiod { "dcpf", 0xf9a700, 0xffffff, 0, FMT_D6, AM33_2, {MEM (SP)}}, 1024*3d8817e4Smiod { "dcpf", 0xfba60000, 0xffff00ff, 0, FMT_D7, AM33_2, {MEM2 (RI,RM0)}}, 1025*3d8817e4Smiod { "dcpf", 0xfba70000, 0xffff0f00, 0, FMT_D7, AM33_2, {MEM2 (SD8,RM2)}}, 1026*3d8817e4Smiod { "dcpf", 0xfda70000, 0xffff0f00, 0, FMT_D8, AM33_2, {MEM2 (SD24,RM2)}}, 1027*3d8817e4Smiod { "dcpf", 0xfe460000, 0xffff0f00, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8,RM2)}}, 1028*3d8817e4Smiod 1029*3d8817e4Smiod { "fmov", 0xf92000, 0xfffe00, 0, FMT_D6, AM33_2, {MEM (RM2), FSM0}}, 1030*3d8817e4Smiod { "fmov", 0xf92200, 0xfffe00, 0, FMT_D6, AM33_2, {MEMINC (RM2), FSM0}}, 1031*3d8817e4Smiod { "fmov", 0xf92400, 0xfffef0, 0, FMT_D6, AM33_2, {MEM (SP), FSM0}}, 1032*3d8817e4Smiod { "fmov", 0xf92600, 0xfffe00, 0, FMT_D6, AM33_2, {RM2, FSM0}}, 1033*3d8817e4Smiod { "fmov", 0xf93000, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, MEM (RM0)}}, 1034*3d8817e4Smiod { "fmov", 0xf93100, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, MEMINC (RM0)}}, 1035*3d8817e4Smiod { "fmov", 0xf93400, 0xfffd0f, 0, FMT_D6, AM33_2, {FSM1, MEM (SP)}}, 1036*3d8817e4Smiod { "fmov", 0xf93500, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, RM0}}, 1037*3d8817e4Smiod { "fmov", 0xf94000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, 1038*3d8817e4Smiod { "fmov", 0xf9a000, 0xfffe01, 0, FMT_D6, AM33_2, {MEM (RM2), FDM0}}, 1039*3d8817e4Smiod { "fmov", 0xf9a200, 0xfffe01, 0, FMT_D6, AM33_2, {MEMINC (RM2), FDM0}}, 1040*3d8817e4Smiod { "fmov", 0xf9a400, 0xfffef1, 0, FMT_D6, AM33_2, {MEM (SP), FDM0}}, 1041*3d8817e4Smiod { "fmov", 0xf9b000, 0xfffd10, 0, FMT_D6, AM33_2, {FDM1, MEM (RM0)}}, 1042*3d8817e4Smiod { "fmov", 0xf9b100, 0xfffd10, 0, FMT_D6, AM33_2, {FDM1, MEMINC (RM0)}}, 1043*3d8817e4Smiod { "fmov", 0xf9b400, 0xfffd1f, 0, FMT_D6, AM33_2, {FDM1, MEM (SP)}}, 1044*3d8817e4Smiod { "fmov", 0xf9b500, 0xffff0f, 0, FMT_D6, AM33_2, {RM2, FPCR}}, 1045*3d8817e4Smiod { "fmov", 0xf9b700, 0xfffff0, 0, FMT_D6, AM33_2, {FPCR, RM0}}, 1046*3d8817e4Smiod { "fmov", 0xf9c000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, 1047*3d8817e4Smiod { "fmov", 0xfb200000, 0xfffe0000, 0, FMT_D7, AM33_2, {MEM2 (SD8, RM2), FSM2}}, 1048*3d8817e4Smiod { "fmov", 0xfb220000, 0xfffe0000, 0, FMT_D7, AM33_2, {MEMINC2 (RM2, SIMM8), FSM2}}, 1049*3d8817e4Smiod { "fmov", 0xfb240000, 0xfffef000, 0, FMT_D7, AM33_2, {MEM2 (IMM8, SP), FSM2}}, 1050*3d8817e4Smiod { "fmov", 0xfb270000, 0xffff000d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FSN1}}, 1051*3d8817e4Smiod { "fmov", 0xfb300000, 0xfffd0000, 0, FMT_D7, AM33_2, {FSM3, MEM2 (SD8, RM0)}}, 1052*3d8817e4Smiod { "fmov", 0xfb310000, 0xfffd0000, 0, FMT_D7, AM33_2, {FSM3, MEMINC2 (RM0, SIMM8)}}, 1053*3d8817e4Smiod { "fmov", 0xfb340000, 0xfffd0f00, 0, FMT_D7, AM33_2, {FSM3, MEM2 (IMM8, SP)}}, 1054*3d8817e4Smiod { "fmov", 0xfb370000, 0xffff000d, 0, FMT_D7, AM33_2, {FSN1, MEM2(RI, RM0)}}, 1055*3d8817e4Smiod /* FIXME: the spec doesn't say the fd register must be even for the 1056*3d8817e4Smiod * next two insns. Assuming it was a mistake in the spec. */ 1057*3d8817e4Smiod { "fmov", 0xfb470000, 0xffff001d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FDN1}}, 1058*3d8817e4Smiod { "fmov", 0xfb570000, 0xffff001d, 0, FMT_D7, AM33_2, {FDN1, MEM2(RI, RM0)}}, 1059*3d8817e4Smiod /* END of FIXME */ 1060*3d8817e4Smiod { "fmov", 0xfba00000, 0xfffe0100, 0, FMT_D7, AM33_2, {MEM2 (SD8, RM2), FDM2}}, 1061*3d8817e4Smiod { "fmov", 0xfba20000, 0xfffe0100, 0, FMT_D7, AM33_2, {MEMINC2 (RM2, SIMM8), FDM2}}, 1062*3d8817e4Smiod { "fmov", 0xfba40000, 0xfffef100, 0, FMT_D7, AM33_2, {MEM2 (IMM8, SP), FDM2}}, 1063*3d8817e4Smiod { "fmov", 0xfbb00000, 0xfffd1000, 0, FMT_D7, AM33_2, {FDM3, MEM2 (SD8, RM0)}}, 1064*3d8817e4Smiod { "fmov", 0xfbb10000, 0xfffd1000, 0, FMT_D7, AM33_2, {FDM3, MEMINC2 (RM0, SIMM8)}}, 1065*3d8817e4Smiod { "fmov", 0xfbb40000, 0xfffd1f00, 0, FMT_D7, AM33_2, {FDM3, MEM2 (IMM8, SP)}}, 1066*3d8817e4Smiod { "fmov", 0xfd200000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FSM2}}, 1067*3d8817e4Smiod { "fmov", 0xfd220000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FSM2}}, 1068*3d8817e4Smiod { "fmov", 0xfd240000, 0xfffef000, 0, FMT_D8, AM33_2, {MEM2 (IMM24, SP), FSM2}}, 1069*3d8817e4Smiod { "fmov", 0xfd300000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEM2 (SIMM24, RM0)}}, 1070*3d8817e4Smiod { "fmov", 0xfd310000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEMINC2 (RM0, SIMM24)}}, 1071*3d8817e4Smiod { "fmov", 0xfd340000, 0xfffd0f00, 0, FMT_D8, AM33_2, {FSM3, MEM2 (IMM24, SP)}}, 1072*3d8817e4Smiod { "fmov", 0xfda00000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FDM2}}, 1073*3d8817e4Smiod { "fmov", 0xfda20000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FDM2}}, 1074*3d8817e4Smiod { "fmov", 0xfda40000, 0xfffef100, 0, FMT_D8, AM33_2, {MEM2 (IMM24, SP), FDM2}}, 1075*3d8817e4Smiod { "fmov", 0xfdb00000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEM2 (SIMM24, RM0)}}, 1076*3d8817e4Smiod { "fmov", 0xfdb10000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEMINC2 (RM0, SIMM24)}}, 1077*3d8817e4Smiod { "fmov", 0xfdb40000, 0xfffd1f00, 0, FMT_D8, AM33_2, {FDM3, MEM2 (IMM24, SP)}}, 1078*3d8817e4Smiod { "fmov", 0xfdb50000, 0xffff0000, 0, FMT_D4, AM33_2, {IMM32, FPCR}}, 1079*3d8817e4Smiod { "fmov", 0xfe200000, 0xfffe0000, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, RM2), FSM2}}, 1080*3d8817e4Smiod { "fmov", 0xfe220000, 0xfffe0000, 0, FMT_D9, AM33_2, {MEMINC2 (RM2, IMM32_HIGH8), FSM2}}, 1081*3d8817e4Smiod { "fmov", 0xfe240000, 0xfffef000, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, SP), FSM2}}, 1082*3d8817e4Smiod { "fmov", 0xfe260000, 0xfffef000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM2}}, 1083*3d8817e4Smiod { "fmov", 0xfe300000, 0xfffd0000, 0, FMT_D9, AM33_2, {FSM3, MEM2 (IMM32_HIGH8, RM0)}}, 1084*3d8817e4Smiod { "fmov", 0xfe310000, 0xfffd0000, 0, FMT_D9, AM33_2, {FSM3, MEMINC2 (RM0, IMM32_HIGH8)}}, 1085*3d8817e4Smiod { "fmov", 0xfe340000, 0xfffd0f00, 0, FMT_D9, AM33_2, {FSM3, MEM2 (IMM32_HIGH8, SP)}}, 1086*3d8817e4Smiod { "fmov", 0xfe400000, 0xfffe0100, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, RM2), FDM2}}, 1087*3d8817e4Smiod { "fmov", 0xfe420000, 0xfffe0100, 0, FMT_D9, AM33_2, {MEMINC2 (RM2, IMM32_HIGH8), FDM2}}, 1088*3d8817e4Smiod { "fmov", 0xfe440000, 0xfffef100, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, SP), FDM2}}, 1089*3d8817e4Smiod { "fmov", 0xfe500000, 0xfffd1000, 0, FMT_D9, AM33_2, {FDM3, MEM2 (IMM32_HIGH8, RM0)}}, 1090*3d8817e4Smiod { "fmov", 0xfe510000, 0xfffd1000, 0, FMT_D9, AM33_2, {FDM3, MEMINC2 (RM0, IMM32_HIGH8)}}, 1091*3d8817e4Smiod { "fmov", 0xfe540000, 0xfffd1f00, 0, FMT_D9, AM33_2, {FDM3, MEM2 (IMM32_HIGH8, SP)}}, 1092*3d8817e4Smiod 1093*3d8817e4Smiod /* FIXME: these are documented in the instruction bitmap, but not in 1094*3d8817e4Smiod * the instruction manual. */ 1095*3d8817e4Smiod { "ftoi", 0xfb400000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, 1096*3d8817e4Smiod { "itof", 0xfb420000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, 1097*3d8817e4Smiod { "ftod", 0xfb520000, 0xffff0f15, 0, FMT_D10,AM33_2, {FSN3, FDN1}}, 1098*3d8817e4Smiod { "dtof", 0xfb560000, 0xffff1f05, 0, FMT_D10,AM33_2, {FDN3, FSN1}}, 1099*3d8817e4Smiod /* END of FIXME */ 1100*3d8817e4Smiod 1101*3d8817e4Smiod { "fabs", 0xfb440000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, 1102*3d8817e4Smiod { "fabs", 0xfbc40000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, 1103*3d8817e4Smiod { "fabs", 0xf94400, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, 1104*3d8817e4Smiod { "fabs", 0xf9c400, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, 1105*3d8817e4Smiod 1106*3d8817e4Smiod { "fneg", 0xfb460000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, 1107*3d8817e4Smiod { "fneg", 0xfbc60000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, 1108*3d8817e4Smiod { "fneg", 0xf94600, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, 1109*3d8817e4Smiod { "fneg", 0xf9c600, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, 1110*3d8817e4Smiod 1111*3d8817e4Smiod { "frsqrt", 0xfb500000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, 1112*3d8817e4Smiod { "frsqrt", 0xfbd00000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, 1113*3d8817e4Smiod { "frsqrt", 0xf95000, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, 1114*3d8817e4Smiod { "frsqrt", 0xf9d000, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, 1115*3d8817e4Smiod 1116*3d8817e4Smiod /* FIXME: this is documented in the instruction bitmap, but not in 1117*3d8817e4Smiod * the instruction manual. */ 1118*3d8817e4Smiod { "fsqrt", 0xfb540000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, 1119*3d8817e4Smiod { "fsqrt", 0xfbd40000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, 1120*3d8817e4Smiod { "fsqrt", 0xf95200, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, 1121*3d8817e4Smiod { "fsqrt", 0xf9d200, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, 1122*3d8817e4Smiod /* END of FIXME */ 1123*3d8817e4Smiod 1124*3d8817e4Smiod { "fcmp", 0xf95400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, 1125*3d8817e4Smiod { "fcmp", 0xf9d400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, 1126*3d8817e4Smiod { "fcmp", 0xfe350000, 0xfffd0f00, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3}}, 1127*3d8817e4Smiod 1128*3d8817e4Smiod { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1129*3d8817e4Smiod { "fadd", 0xfbe00000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, 1130*3d8817e4Smiod { "fadd", 0xf96000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, 1131*3d8817e4Smiod { "fadd", 0xf9e000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, 1132*3d8817e4Smiod { "fadd", 0xfe600000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, 1133*3d8817e4Smiod 1134*3d8817e4Smiod { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1135*3d8817e4Smiod { "fsub", 0xfbe40000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, 1136*3d8817e4Smiod { "fsub", 0xf96400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, 1137*3d8817e4Smiod { "fsub", 0xf9e400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, 1138*3d8817e4Smiod { "fsub", 0xfe640000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, 1139*3d8817e4Smiod 1140*3d8817e4Smiod { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1141*3d8817e4Smiod { "fmul", 0xfbf00000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, 1142*3d8817e4Smiod { "fmul", 0xf97000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, 1143*3d8817e4Smiod { "fmul", 0xf9f000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, 1144*3d8817e4Smiod { "fmul", 0xfe700000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, 1145*3d8817e4Smiod 1146*3d8817e4Smiod { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, 1147*3d8817e4Smiod { "fdiv", 0xfbf40000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, 1148*3d8817e4Smiod { "fdiv", 0xf97400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, 1149*3d8817e4Smiod { "fdiv", 0xf9f400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, 1150*3d8817e4Smiod { "fdiv", 0xfe740000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, 1151*3d8817e4Smiod 1152*3d8817e4Smiod { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1153*3d8817e4Smiod { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1154*3d8817e4Smiod { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1155*3d8817e4Smiod { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, 1156*3d8817e4Smiod 1157*3d8817e4Smiod /* UDF instructions. */ 1158*3d8817e4Smiod { "udf00", 0xf600, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1159*3d8817e4Smiod { "udf00", 0xf90000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1160*3d8817e4Smiod { "udf00", 0xfb000000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1161*3d8817e4Smiod { "udf00", 0xfd000000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1162*3d8817e4Smiod { "udf01", 0xf610, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1163*3d8817e4Smiod { "udf01", 0xf91000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1164*3d8817e4Smiod { "udf01", 0xfb100000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1165*3d8817e4Smiod { "udf01", 0xfd100000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1166*3d8817e4Smiod { "udf02", 0xf620, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1167*3d8817e4Smiod { "udf02", 0xf92000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1168*3d8817e4Smiod { "udf02", 0xfb200000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1169*3d8817e4Smiod { "udf02", 0xfd200000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1170*3d8817e4Smiod { "udf03", 0xf630, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1171*3d8817e4Smiod { "udf03", 0xf93000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1172*3d8817e4Smiod { "udf03", 0xfb300000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1173*3d8817e4Smiod { "udf03", 0xfd300000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1174*3d8817e4Smiod { "udf04", 0xf640, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1175*3d8817e4Smiod { "udf04", 0xf94000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1176*3d8817e4Smiod { "udf04", 0xfb400000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1177*3d8817e4Smiod { "udf04", 0xfd400000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1178*3d8817e4Smiod { "udf05", 0xf650, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1179*3d8817e4Smiod { "udf05", 0xf95000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1180*3d8817e4Smiod { "udf05", 0xfb500000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1181*3d8817e4Smiod { "udf05", 0xfd500000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1182*3d8817e4Smiod { "udf06", 0xf660, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1183*3d8817e4Smiod { "udf06", 0xf96000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1184*3d8817e4Smiod { "udf06", 0xfb600000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1185*3d8817e4Smiod { "udf06", 0xfd600000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1186*3d8817e4Smiod { "udf07", 0xf670, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1187*3d8817e4Smiod { "udf07", 0xf97000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1188*3d8817e4Smiod { "udf07", 0xfb700000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1189*3d8817e4Smiod { "udf07", 0xfd700000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1190*3d8817e4Smiod { "udf08", 0xf680, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1191*3d8817e4Smiod { "udf08", 0xf98000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1192*3d8817e4Smiod { "udf08", 0xfb800000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1193*3d8817e4Smiod { "udf08", 0xfd800000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1194*3d8817e4Smiod { "udf09", 0xf690, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1195*3d8817e4Smiod { "udf09", 0xf99000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1196*3d8817e4Smiod { "udf09", 0xfb900000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1197*3d8817e4Smiod { "udf09", 0xfd900000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1198*3d8817e4Smiod { "udf10", 0xf6a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1199*3d8817e4Smiod { "udf10", 0xf9a000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1200*3d8817e4Smiod { "udf10", 0xfba00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1201*3d8817e4Smiod { "udf10", 0xfda00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1202*3d8817e4Smiod { "udf11", 0xf6b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1203*3d8817e4Smiod { "udf11", 0xf9b000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1204*3d8817e4Smiod { "udf11", 0xfbb00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1205*3d8817e4Smiod { "udf11", 0xfdb00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1206*3d8817e4Smiod { "udf12", 0xf6c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1207*3d8817e4Smiod { "udf12", 0xf9c000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1208*3d8817e4Smiod { "udf12", 0xfbc00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1209*3d8817e4Smiod { "udf12", 0xfdc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1210*3d8817e4Smiod { "udf13", 0xf6d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1211*3d8817e4Smiod { "udf13", 0xf9d000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1212*3d8817e4Smiod { "udf13", 0xfbd00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1213*3d8817e4Smiod { "udf13", 0xfdd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1214*3d8817e4Smiod { "udf14", 0xf6e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1215*3d8817e4Smiod { "udf14", 0xf9e000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1216*3d8817e4Smiod { "udf14", 0xfbe00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1217*3d8817e4Smiod { "udf14", 0xfde00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1218*3d8817e4Smiod { "udf15", 0xf6f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1219*3d8817e4Smiod { "udf15", 0xf9f000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, 1220*3d8817e4Smiod { "udf15", 0xfbf00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, 1221*3d8817e4Smiod { "udf15", 0xfdf00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1222*3d8817e4Smiod { "udf20", 0xf500, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1223*3d8817e4Smiod { "udf21", 0xf510, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1224*3d8817e4Smiod { "udf22", 0xf520, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1225*3d8817e4Smiod { "udf23", 0xf530, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1226*3d8817e4Smiod { "udf24", 0xf540, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1227*3d8817e4Smiod { "udf25", 0xf550, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1228*3d8817e4Smiod { "udf26", 0xf560, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1229*3d8817e4Smiod { "udf27", 0xf570, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1230*3d8817e4Smiod { "udf28", 0xf580, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1231*3d8817e4Smiod { "udf29", 0xf590, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1232*3d8817e4Smiod { "udf30", 0xf5a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1233*3d8817e4Smiod { "udf31", 0xf5b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1234*3d8817e4Smiod { "udf32", 0xf5c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1235*3d8817e4Smiod { "udf33", 0xf5d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1236*3d8817e4Smiod { "udf34", 0xf5e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1237*3d8817e4Smiod { "udf35", 0xf5f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, 1238*3d8817e4Smiod { "udfu00", 0xf90400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1239*3d8817e4Smiod { "udfu00", 0xfb040000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1240*3d8817e4Smiod { "udfu00", 0xfd040000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1241*3d8817e4Smiod { "udfu01", 0xf91400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1242*3d8817e4Smiod { "udfu01", 0xfb140000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1243*3d8817e4Smiod { "udfu01", 0xfd140000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1244*3d8817e4Smiod { "udfu02", 0xf92400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1245*3d8817e4Smiod { "udfu02", 0xfb240000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1246*3d8817e4Smiod { "udfu02", 0xfd240000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1247*3d8817e4Smiod { "udfu03", 0xf93400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1248*3d8817e4Smiod { "udfu03", 0xfb340000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1249*3d8817e4Smiod { "udfu03", 0xfd340000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1250*3d8817e4Smiod { "udfu04", 0xf94400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1251*3d8817e4Smiod { "udfu04", 0xfb440000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1252*3d8817e4Smiod { "udfu04", 0xfd440000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1253*3d8817e4Smiod { "udfu05", 0xf95400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1254*3d8817e4Smiod { "udfu05", 0xfb540000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1255*3d8817e4Smiod { "udfu05", 0xfd540000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1256*3d8817e4Smiod { "udfu06", 0xf96400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1257*3d8817e4Smiod { "udfu06", 0xfb640000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1258*3d8817e4Smiod { "udfu06", 0xfd640000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1259*3d8817e4Smiod { "udfu07", 0xf97400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1260*3d8817e4Smiod { "udfu07", 0xfb740000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1261*3d8817e4Smiod { "udfu07", 0xfd740000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1262*3d8817e4Smiod { "udfu08", 0xf98400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1263*3d8817e4Smiod { "udfu08", 0xfb840000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1264*3d8817e4Smiod { "udfu08", 0xfd840000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1265*3d8817e4Smiod { "udfu09", 0xf99400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1266*3d8817e4Smiod { "udfu09", 0xfb940000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1267*3d8817e4Smiod { "udfu09", 0xfd940000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1268*3d8817e4Smiod { "udfu10", 0xf9a400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1269*3d8817e4Smiod { "udfu10", 0xfba40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1270*3d8817e4Smiod { "udfu10", 0xfda40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1271*3d8817e4Smiod { "udfu11", 0xf9b400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1272*3d8817e4Smiod { "udfu11", 0xfbb40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1273*3d8817e4Smiod { "udfu11", 0xfdb40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1274*3d8817e4Smiod { "udfu12", 0xf9c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1275*3d8817e4Smiod { "udfu12", 0xfbc40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1276*3d8817e4Smiod { "udfu12", 0xfdc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1277*3d8817e4Smiod { "udfu13", 0xf9d400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1278*3d8817e4Smiod { "udfu13", 0xfbd40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1279*3d8817e4Smiod { "udfu13", 0xfdd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1280*3d8817e4Smiod { "udfu14", 0xf9e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1281*3d8817e4Smiod { "udfu14", 0xfbe40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1282*3d8817e4Smiod { "udfu14", 0xfde40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1283*3d8817e4Smiod { "udfu15", 0xf9f400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, 1284*3d8817e4Smiod { "udfu15", 0xfbf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, 1285*3d8817e4Smiod { "udfu15", 0xfdf40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, 1286*3d8817e4Smiod 1287*3d8817e4Smiod { "putx", 0xf500, 0xfff0, 0, FMT_D0, AM30, {DN01}}, 1288*3d8817e4Smiod { "getx", 0xf6f0, 0xfff0, 0, FMT_D0, AM30, {DN01}}, 1289*3d8817e4Smiod { "mulq", 0xf600, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, 1290*3d8817e4Smiod { "mulq", 0xf90000, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}}, 1291*3d8817e4Smiod { "mulq", 0xfb000000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}}, 1292*3d8817e4Smiod { "mulq", 0xfd000000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}}, 1293*3d8817e4Smiod { "mulqu", 0xf610, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, 1294*3d8817e4Smiod { "mulqu", 0xf91400, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}}, 1295*3d8817e4Smiod { "mulqu", 0xfb140000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}}, 1296*3d8817e4Smiod { "mulqu", 0xfd140000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}}, 1297*3d8817e4Smiod { "sat16", 0xf640, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, 1298*3d8817e4Smiod { "sat16", 0xf9ab00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 1299*3d8817e4Smiod 1300*3d8817e4Smiod { "sat24", 0xf650, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, 1301*3d8817e4Smiod { "sat24", 0xfbaf0000, 0xffff00ff, 0, FMT_D7, AM33, {RM2, RN0}}, 1302*3d8817e4Smiod 1303*3d8817e4Smiod { "bsch", 0xfbff0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, 1304*3d8817e4Smiod { "bsch", 0xf670, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, 1305*3d8817e4Smiod { "bsch", 0xf9fb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, 1306*3d8817e4Smiod 1307*3d8817e4Smiod /* Extension. We need some instruction to trigger "emulated syscalls" 1308*3d8817e4Smiod for our simulator. */ 1309*3d8817e4Smiod { "syscall", 0xf0e0, 0xfff0, 0, FMT_D0, AM33, {IMM4}}, 1310*3d8817e4Smiod { "syscall", 0xf0c0, 0xffff, 0, FMT_D0, 0, {UNUSED}}, 1311*3d8817e4Smiod 1312*3d8817e4Smiod /* Extension. When talking to the simulator, gdb requires some instruction 1313*3d8817e4Smiod that will trigger a "breakpoint" (really just an instruction that isn't 1314*3d8817e4Smiod otherwise used by the tools. This instruction must be the same size 1315*3d8817e4Smiod as the smallest instruction on the target machine. In the case of the 1316*3d8817e4Smiod mn10x00 the "break" instruction must be one byte. 0xff is available on 1317*3d8817e4Smiod both mn10x00 architectures. */ 1318*3d8817e4Smiod { "break", 0xff, 0xff, 0, FMT_S0, 0, {UNUSED}}, 1319*3d8817e4Smiod 1320*3d8817e4Smiod { "add_add", 0xf7000000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1321*3d8817e4Smiod { "add_add", 0xf7100000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1322*3d8817e4Smiod { "add_add", 0xf7040000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1323*3d8817e4Smiod { "add_add", 0xf7140000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1324*3d8817e4Smiod { "add_sub", 0xf7200000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1325*3d8817e4Smiod { "add_sub", 0xf7300000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1326*3d8817e4Smiod { "add_sub", 0xf7240000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1327*3d8817e4Smiod { "add_sub", 0xf7340000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1328*3d8817e4Smiod { "add_cmp", 0xf7400000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1329*3d8817e4Smiod { "add_cmp", 0xf7500000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1330*3d8817e4Smiod { "add_cmp", 0xf7440000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1331*3d8817e4Smiod { "add_cmp", 0xf7540000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1332*3d8817e4Smiod { "add_mov", 0xf7600000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1333*3d8817e4Smiod { "add_mov", 0xf7700000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1334*3d8817e4Smiod { "add_mov", 0xf7640000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1335*3d8817e4Smiod { "add_mov", 0xf7740000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1336*3d8817e4Smiod { "add_asr", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1337*3d8817e4Smiod { "add_asr", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1338*3d8817e4Smiod { "add_asr", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1339*3d8817e4Smiod { "add_asr", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1340*3d8817e4Smiod { "add_lsr", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1341*3d8817e4Smiod { "add_lsr", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1342*3d8817e4Smiod { "add_lsr", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1343*3d8817e4Smiod { "add_lsr", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1344*3d8817e4Smiod { "add_asl", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1345*3d8817e4Smiod { "add_asl", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1346*3d8817e4Smiod { "add_asl", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1347*3d8817e4Smiod { "add_asl", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1348*3d8817e4Smiod { "cmp_add", 0xf7010000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1349*3d8817e4Smiod { "cmp_add", 0xf7110000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1350*3d8817e4Smiod { "cmp_add", 0xf7050000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1351*3d8817e4Smiod { "cmp_add", 0xf7150000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1352*3d8817e4Smiod { "cmp_sub", 0xf7210000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1353*3d8817e4Smiod { "cmp_sub", 0xf7310000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1354*3d8817e4Smiod { "cmp_sub", 0xf7250000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1355*3d8817e4Smiod { "cmp_sub", 0xf7350000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1356*3d8817e4Smiod { "cmp_mov", 0xf7610000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1357*3d8817e4Smiod { "cmp_mov", 0xf7710000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1358*3d8817e4Smiod { "cmp_mov", 0xf7650000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1359*3d8817e4Smiod { "cmp_mov", 0xf7750000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1360*3d8817e4Smiod { "cmp_asr", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1361*3d8817e4Smiod { "cmp_asr", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1362*3d8817e4Smiod { "cmp_asr", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1363*3d8817e4Smiod { "cmp_asr", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1364*3d8817e4Smiod { "cmp_lsr", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1365*3d8817e4Smiod { "cmp_lsr", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1366*3d8817e4Smiod { "cmp_lsr", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1367*3d8817e4Smiod { "cmp_lsr", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1368*3d8817e4Smiod { "cmp_asl", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1369*3d8817e4Smiod { "cmp_asl", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1370*3d8817e4Smiod { "cmp_asl", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1371*3d8817e4Smiod { "cmp_asl", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1372*3d8817e4Smiod { "sub_add", 0xf7020000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1373*3d8817e4Smiod { "sub_add", 0xf7120000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1374*3d8817e4Smiod { "sub_add", 0xf7060000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1375*3d8817e4Smiod { "sub_add", 0xf7160000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1376*3d8817e4Smiod { "sub_sub", 0xf7220000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1377*3d8817e4Smiod { "sub_sub", 0xf7320000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1378*3d8817e4Smiod { "sub_sub", 0xf7260000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1379*3d8817e4Smiod { "sub_sub", 0xf7360000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1380*3d8817e4Smiod { "sub_cmp", 0xf7420000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1381*3d8817e4Smiod { "sub_cmp", 0xf7520000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1382*3d8817e4Smiod { "sub_cmp", 0xf7460000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1383*3d8817e4Smiod { "sub_cmp", 0xf7560000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1384*3d8817e4Smiod { "sub_mov", 0xf7620000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1385*3d8817e4Smiod { "sub_mov", 0xf7720000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1386*3d8817e4Smiod { "sub_mov", 0xf7660000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1387*3d8817e4Smiod { "sub_mov", 0xf7760000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1388*3d8817e4Smiod { "sub_asr", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1389*3d8817e4Smiod { "sub_asr", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1390*3d8817e4Smiod { "sub_asr", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1391*3d8817e4Smiod { "sub_asr", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1392*3d8817e4Smiod { "sub_lsr", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1393*3d8817e4Smiod { "sub_lsr", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1394*3d8817e4Smiod { "sub_lsr", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1395*3d8817e4Smiod { "sub_lsr", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1396*3d8817e4Smiod { "sub_asl", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1397*3d8817e4Smiod { "sub_asl", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1398*3d8817e4Smiod { "sub_asl", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1399*3d8817e4Smiod { "sub_asl", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1400*3d8817e4Smiod { "mov_add", 0xf7030000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1401*3d8817e4Smiod { "mov_add", 0xf7130000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1402*3d8817e4Smiod { "mov_add", 0xf7070000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1403*3d8817e4Smiod { "mov_add", 0xf7170000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1404*3d8817e4Smiod { "mov_sub", 0xf7230000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1405*3d8817e4Smiod { "mov_sub", 0xf7330000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1406*3d8817e4Smiod { "mov_sub", 0xf7270000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1407*3d8817e4Smiod { "mov_sub", 0xf7370000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1408*3d8817e4Smiod { "mov_cmp", 0xf7430000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1409*3d8817e4Smiod { "mov_cmp", 0xf7530000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1410*3d8817e4Smiod { "mov_cmp", 0xf7470000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1411*3d8817e4Smiod { "mov_cmp", 0xf7570000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1412*3d8817e4Smiod { "mov_mov", 0xf7630000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1413*3d8817e4Smiod { "mov_mov", 0xf7730000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1414*3d8817e4Smiod { "mov_mov", 0xf7670000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1415*3d8817e4Smiod { "mov_mov", 0xf7770000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, 1416*3d8817e4Smiod { "mov_asr", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1417*3d8817e4Smiod { "mov_asr", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1418*3d8817e4Smiod { "mov_asr", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1419*3d8817e4Smiod { "mov_asr", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1420*3d8817e4Smiod { "mov_lsr", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1421*3d8817e4Smiod { "mov_lsr", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1422*3d8817e4Smiod { "mov_lsr", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1423*3d8817e4Smiod { "mov_lsr", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1424*3d8817e4Smiod { "mov_asl", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1425*3d8817e4Smiod { "mov_asl", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1426*3d8817e4Smiod { "mov_asl", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, 1427*3d8817e4Smiod { "mov_asl", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, 1428*3d8817e4Smiod { "and_add", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1429*3d8817e4Smiod { "and_add", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1430*3d8817e4Smiod { "and_sub", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1431*3d8817e4Smiod { "and_sub", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1432*3d8817e4Smiod { "and_cmp", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1433*3d8817e4Smiod { "and_cmp", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1434*3d8817e4Smiod { "and_mov", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1435*3d8817e4Smiod { "and_mov", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1436*3d8817e4Smiod { "and_asr", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1437*3d8817e4Smiod { "and_asr", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1438*3d8817e4Smiod { "and_lsr", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1439*3d8817e4Smiod { "and_lsr", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1440*3d8817e4Smiod { "and_asl", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1441*3d8817e4Smiod { "and_asl", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1442*3d8817e4Smiod { "dmach_add", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1443*3d8817e4Smiod { "dmach_add", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1444*3d8817e4Smiod { "dmach_sub", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1445*3d8817e4Smiod { "dmach_sub", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1446*3d8817e4Smiod { "dmach_cmp", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1447*3d8817e4Smiod { "dmach_cmp", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1448*3d8817e4Smiod { "dmach_mov", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1449*3d8817e4Smiod { "dmach_mov", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1450*3d8817e4Smiod { "dmach_asr", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1451*3d8817e4Smiod { "dmach_asr", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1452*3d8817e4Smiod { "dmach_lsr", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1453*3d8817e4Smiod { "dmach_lsr", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1454*3d8817e4Smiod { "dmach_asl", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1455*3d8817e4Smiod { "dmach_asl", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1456*3d8817e4Smiod { "xor_add", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1457*3d8817e4Smiod { "xor_add", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1458*3d8817e4Smiod { "xor_sub", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1459*3d8817e4Smiod { "xor_sub", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1460*3d8817e4Smiod { "xor_cmp", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1461*3d8817e4Smiod { "xor_cmp", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1462*3d8817e4Smiod { "xor_mov", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1463*3d8817e4Smiod { "xor_mov", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1464*3d8817e4Smiod { "xor_asr", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1465*3d8817e4Smiod { "xor_asr", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1466*3d8817e4Smiod { "xor_lsr", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1467*3d8817e4Smiod { "xor_lsr", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1468*3d8817e4Smiod { "xor_asl", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1469*3d8817e4Smiod { "xor_asl", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1470*3d8817e4Smiod { "swhw_add", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1471*3d8817e4Smiod { "swhw_add", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1472*3d8817e4Smiod { "swhw_sub", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1473*3d8817e4Smiod { "swhw_sub", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1474*3d8817e4Smiod { "swhw_cmp", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1475*3d8817e4Smiod { "swhw_cmp", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1476*3d8817e4Smiod { "swhw_mov", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1477*3d8817e4Smiod { "swhw_mov", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1478*3d8817e4Smiod { "swhw_asr", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1479*3d8817e4Smiod { "swhw_asr", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1480*3d8817e4Smiod { "swhw_lsr", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1481*3d8817e4Smiod { "swhw_lsr", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1482*3d8817e4Smiod { "swhw_asl", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1483*3d8817e4Smiod { "swhw_asl", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1484*3d8817e4Smiod { "or_add", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1485*3d8817e4Smiod { "or_add", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1486*3d8817e4Smiod { "or_sub", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1487*3d8817e4Smiod { "or_sub", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1488*3d8817e4Smiod { "or_cmp", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1489*3d8817e4Smiod { "or_cmp", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1490*3d8817e4Smiod { "or_mov", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1491*3d8817e4Smiod { "or_mov", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1492*3d8817e4Smiod { "or_asr", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1493*3d8817e4Smiod { "or_asr", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1494*3d8817e4Smiod { "or_lsr", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1495*3d8817e4Smiod { "or_lsr", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1496*3d8817e4Smiod { "or_asl", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1497*3d8817e4Smiod { "or_asl", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1498*3d8817e4Smiod { "sat16_add", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1499*3d8817e4Smiod { "sat16_add", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1500*3d8817e4Smiod { "sat16_sub", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1501*3d8817e4Smiod { "sat16_sub", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1502*3d8817e4Smiod { "sat16_cmp", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1503*3d8817e4Smiod { "sat16_cmp", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1504*3d8817e4Smiod { "sat16_mov", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1505*3d8817e4Smiod { "sat16_mov", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, 1506*3d8817e4Smiod { "sat16_asr", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1507*3d8817e4Smiod { "sat16_asr", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1508*3d8817e4Smiod { "sat16_lsr", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1509*3d8817e4Smiod { "sat16_lsr", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1510*3d8817e4Smiod { "sat16_asl", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, 1511*3d8817e4Smiod { "sat16_asl", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, 1512*3d8817e4Smiod /* Ugh. Synthetic instructions. */ 1513*3d8817e4Smiod { "add_and", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1514*3d8817e4Smiod { "add_and", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1515*3d8817e4Smiod { "add_dmach", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1516*3d8817e4Smiod { "add_dmach", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1517*3d8817e4Smiod { "add_or", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1518*3d8817e4Smiod { "add_or", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1519*3d8817e4Smiod { "add_sat16", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1520*3d8817e4Smiod { "add_sat16", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1521*3d8817e4Smiod { "add_swhw", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1522*3d8817e4Smiod { "add_swhw", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1523*3d8817e4Smiod { "add_xor", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1524*3d8817e4Smiod { "add_xor", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1525*3d8817e4Smiod { "asl_add", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1526*3d8817e4Smiod { "asl_add", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1527*3d8817e4Smiod { "asl_add", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1528*3d8817e4Smiod { "asl_add", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1529*3d8817e4Smiod { "asl_and", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1530*3d8817e4Smiod { "asl_and", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1531*3d8817e4Smiod { "asl_cmp", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1532*3d8817e4Smiod { "asl_cmp", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, 1533*3d8817e4Smiod { "asl_cmp", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1534*3d8817e4Smiod { "asl_cmp", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1535*3d8817e4Smiod { "asl_dmach", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1536*3d8817e4Smiod { "asl_dmach", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1537*3d8817e4Smiod { "asl_mov", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1538*3d8817e4Smiod { "asl_mov", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1539*3d8817e4Smiod { "asl_mov", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1540*3d8817e4Smiod { "asl_mov", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1541*3d8817e4Smiod { "asl_or", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1542*3d8817e4Smiod { "asl_or", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1543*3d8817e4Smiod { "asl_sat16", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1544*3d8817e4Smiod { "asl_sat16", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1545*3d8817e4Smiod { "asl_sub", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1546*3d8817e4Smiod { "asl_sub", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1547*3d8817e4Smiod { "asl_sub", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1548*3d8817e4Smiod { "asl_sub", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1549*3d8817e4Smiod { "asl_swhw", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1550*3d8817e4Smiod { "asl_swhw", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1551*3d8817e4Smiod { "asl_xor", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1552*3d8817e4Smiod { "asl_xor", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1553*3d8817e4Smiod { "asr_add", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1554*3d8817e4Smiod { "asr_add", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1555*3d8817e4Smiod { "asr_add", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1556*3d8817e4Smiod { "asr_add", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1557*3d8817e4Smiod { "asr_and", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1558*3d8817e4Smiod { "asr_and", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1559*3d8817e4Smiod { "asr_cmp", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1560*3d8817e4Smiod { "asr_cmp", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, 1561*3d8817e4Smiod { "asr_cmp", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1562*3d8817e4Smiod { "asr_cmp", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1563*3d8817e4Smiod { "asr_dmach", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1564*3d8817e4Smiod { "asr_dmach", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1565*3d8817e4Smiod { "asr_mov", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1566*3d8817e4Smiod { "asr_mov", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1567*3d8817e4Smiod { "asr_mov", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1568*3d8817e4Smiod { "asr_mov", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1569*3d8817e4Smiod { "asr_or", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1570*3d8817e4Smiod { "asr_or", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1571*3d8817e4Smiod { "asr_sat16", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1572*3d8817e4Smiod { "asr_sat16", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1573*3d8817e4Smiod { "asr_sub", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1574*3d8817e4Smiod { "asr_sub", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1575*3d8817e4Smiod { "asr_sub", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1576*3d8817e4Smiod { "asr_sub", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1577*3d8817e4Smiod { "asr_swhw", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1578*3d8817e4Smiod { "asr_swhw", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1579*3d8817e4Smiod { "asr_xor", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1580*3d8817e4Smiod { "asr_xor", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1581*3d8817e4Smiod { "cmp_and", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1582*3d8817e4Smiod { "cmp_and", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1583*3d8817e4Smiod { "cmp_dmach", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1584*3d8817e4Smiod { "cmp_dmach", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1585*3d8817e4Smiod { "cmp_or", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1586*3d8817e4Smiod { "cmp_or", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1587*3d8817e4Smiod { "cmp_sat16", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1588*3d8817e4Smiod { "cmp_sat16", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1589*3d8817e4Smiod { "cmp_swhw", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1590*3d8817e4Smiod { "cmp_swhw", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1591*3d8817e4Smiod { "cmp_xor", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1592*3d8817e4Smiod { "cmp_xor", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1593*3d8817e4Smiod { "lsr_add", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1594*3d8817e4Smiod { "lsr_add", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1595*3d8817e4Smiod { "lsr_add", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1596*3d8817e4Smiod { "lsr_add", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1597*3d8817e4Smiod { "lsr_and", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1598*3d8817e4Smiod { "lsr_and", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1599*3d8817e4Smiod { "lsr_cmp", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1600*3d8817e4Smiod { "lsr_cmp", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, 1601*3d8817e4Smiod { "lsr_cmp", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1602*3d8817e4Smiod { "lsr_cmp", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1603*3d8817e4Smiod { "lsr_dmach", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1604*3d8817e4Smiod { "lsr_dmach", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1605*3d8817e4Smiod { "lsr_mov", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1606*3d8817e4Smiod { "lsr_mov", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1607*3d8817e4Smiod { "lsr_mov", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1608*3d8817e4Smiod { "lsr_mov", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1609*3d8817e4Smiod { "lsr_or", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1610*3d8817e4Smiod { "lsr_or", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1611*3d8817e4Smiod { "lsr_sat16", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1612*3d8817e4Smiod { "lsr_sat16", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1613*3d8817e4Smiod { "lsr_sub", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1614*3d8817e4Smiod { "lsr_sub", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1615*3d8817e4Smiod { "lsr_sub", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, 1616*3d8817e4Smiod { "lsr_sub", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, 1617*3d8817e4Smiod { "lsr_swhw", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1618*3d8817e4Smiod { "lsr_swhw", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1619*3d8817e4Smiod { "lsr_xor", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1620*3d8817e4Smiod { "lsr_xor", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, 1621*3d8817e4Smiod { "mov_and", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1622*3d8817e4Smiod { "mov_and", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1623*3d8817e4Smiod { "mov_dmach", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1624*3d8817e4Smiod { "mov_dmach", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1625*3d8817e4Smiod { "mov_or", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1626*3d8817e4Smiod { "mov_or", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1627*3d8817e4Smiod { "mov_sat16", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1628*3d8817e4Smiod { "mov_sat16", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1629*3d8817e4Smiod { "mov_swhw", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1630*3d8817e4Smiod { "mov_swhw", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1631*3d8817e4Smiod { "mov_xor", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1632*3d8817e4Smiod { "mov_xor", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1633*3d8817e4Smiod { "sub_and", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1634*3d8817e4Smiod { "sub_and", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1635*3d8817e4Smiod { "sub_dmach", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1636*3d8817e4Smiod { "sub_dmach", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1637*3d8817e4Smiod { "sub_or", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1638*3d8817e4Smiod { "sub_or", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1639*3d8817e4Smiod { "sub_sat16", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1640*3d8817e4Smiod { "sub_sat16", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1641*3d8817e4Smiod { "sub_swhw", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1642*3d8817e4Smiod { "sub_swhw", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1643*3d8817e4Smiod { "sub_xor", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, 1644*3d8817e4Smiod { "sub_xor", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, 1645*3d8817e4Smiod { "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1646*3d8817e4Smiod { "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1647*3d8817e4Smiod { "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1648*3d8817e4Smiod { "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1649*3d8817e4Smiod { "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1650*3d8817e4Smiod { "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1651*3d8817e4Smiod { "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1652*3d8817e4Smiod { "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1653*3d8817e4Smiod { "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1654*3d8817e4Smiod { "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1655*3d8817e4Smiod { "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1656*3d8817e4Smiod { "llt_mov", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1657*3d8817e4Smiod { "lgt_mov", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1658*3d8817e4Smiod { "lge_mov", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1659*3d8817e4Smiod { "lle_mov", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1660*3d8817e4Smiod { "lcs_mov", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1661*3d8817e4Smiod { "lhi_mov", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1662*3d8817e4Smiod { "lcc_mov", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1663*3d8817e4Smiod { "lls_mov", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1664*3d8817e4Smiod { "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1665*3d8817e4Smiod { "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1666*3d8817e4Smiod { "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, 1667*3d8817e4Smiod 1668*3d8817e4Smiod { 0, 0, 0, 0, 0, 0, {0}}, 1669*3d8817e4Smiod 1670*3d8817e4Smiod } ; 1671*3d8817e4Smiod 1672*3d8817e4Smiod const int mn10300_num_opcodes = 1673*3d8817e4Smiod sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]); 1674*3d8817e4Smiod 1675*3d8817e4Smiod 1676