1*3d8817e4Smiod /* CPU data header for m32c. 2*3d8817e4Smiod 3*3d8817e4Smiod THIS FILE IS MACHINE GENERATED WITH CGEN. 4*3d8817e4Smiod 5*3d8817e4Smiod Copyright 1996-2005 Free Software Foundation, Inc. 6*3d8817e4Smiod 7*3d8817e4Smiod This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8*3d8817e4Smiod 9*3d8817e4Smiod This program is free software; you can redistribute it and/or modify 10*3d8817e4Smiod it under the terms of the GNU General Public License as published by 11*3d8817e4Smiod the Free Software Foundation; either version 2, or (at your option) 12*3d8817e4Smiod any later version. 13*3d8817e4Smiod 14*3d8817e4Smiod This program is distributed in the hope that it will be useful, 15*3d8817e4Smiod but WITHOUT ANY WARRANTY; without even the implied warranty of 16*3d8817e4Smiod MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*3d8817e4Smiod GNU General Public License for more details. 18*3d8817e4Smiod 19*3d8817e4Smiod You should have received a copy of the GNU General Public License along 20*3d8817e4Smiod with this program; if not, write to the Free Software Foundation, Inc., 21*3d8817e4Smiod 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22*3d8817e4Smiod 23*3d8817e4Smiod */ 24*3d8817e4Smiod 25*3d8817e4Smiod #ifndef M32C_CPU_H 26*3d8817e4Smiod #define M32C_CPU_H 27*3d8817e4Smiod 28*3d8817e4Smiod #include "opcode/cgen-bitset.h" 29*3d8817e4Smiod 30*3d8817e4Smiod #define CGEN_ARCH m32c 31*3d8817e4Smiod 32*3d8817e4Smiod /* Given symbol S, return m32c_cgen_<S>. */ 33*3d8817e4Smiod #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 34*3d8817e4Smiod #define CGEN_SYM(s) m32c##_cgen_##s 35*3d8817e4Smiod #else 36*3d8817e4Smiod #define CGEN_SYM(s) m32c/**/_cgen_/**/s 37*3d8817e4Smiod #endif 38*3d8817e4Smiod 39*3d8817e4Smiod 40*3d8817e4Smiod /* Selected cpu families. */ 41*3d8817e4Smiod #define HAVE_CPU_M16CBF 42*3d8817e4Smiod #define HAVE_CPU_M32CBF 43*3d8817e4Smiod 44*3d8817e4Smiod #define CGEN_INSN_LSB0_P 0 45*3d8817e4Smiod 46*3d8817e4Smiod /* Minimum size of any insn (in bytes). */ 47*3d8817e4Smiod #define CGEN_MIN_INSN_SIZE 1 48*3d8817e4Smiod 49*3d8817e4Smiod /* Maximum size of any insn (in bytes). */ 50*3d8817e4Smiod #define CGEN_MAX_INSN_SIZE 10 51*3d8817e4Smiod 52*3d8817e4Smiod #define CGEN_INT_INSN_P 0 53*3d8817e4Smiod 54*3d8817e4Smiod /* Maximum number of syntax elements in an instruction. */ 55*3d8817e4Smiod #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 21 56*3d8817e4Smiod 57*3d8817e4Smiod /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 58*3d8817e4Smiod e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 59*3d8817e4Smiod we can't hash on everything up to the space. */ 60*3d8817e4Smiod #define CGEN_MNEMONIC_OPERANDS 61*3d8817e4Smiod 62*3d8817e4Smiod /* Maximum number of fields in an instruction. */ 63*3d8817e4Smiod #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 13 64*3d8817e4Smiod 65*3d8817e4Smiod /* Enums. */ 66*3d8817e4Smiod 67*3d8817e4Smiod /* Attributes. */ 68*3d8817e4Smiod 69*3d8817e4Smiod /* Enum declaration for machine type selection. */ 70*3d8817e4Smiod typedef enum mach_attr { 71*3d8817e4Smiod MACH_BASE, MACH_M16C, MACH_M32C, MACH_MAX 72*3d8817e4Smiod } MACH_ATTR; 73*3d8817e4Smiod 74*3d8817e4Smiod /* Enum declaration for instruction set selection. */ 75*3d8817e4Smiod typedef enum isa_attr { 76*3d8817e4Smiod ISA_M16C, ISA_M32C, ISA_MAX 77*3d8817e4Smiod } ISA_ATTR; 78*3d8817e4Smiod 79*3d8817e4Smiod /* Enum declaration for . */ 80*3d8817e4Smiod typedef enum rl_type_attr { 81*3d8817e4Smiod RL_TYPE_NONE, RL_TYPE_JUMP, RL_TYPE_1ADDR, RL_TYPE_2ADDR 82*3d8817e4Smiod } RL_TYPE_ATTR; 83*3d8817e4Smiod 84*3d8817e4Smiod /* Number of architecture variants. */ 85*3d8817e4Smiod #define MAX_ISAS ((int) ISA_MAX) 86*3d8817e4Smiod #define MAX_MACHS ((int) MACH_MAX) 87*3d8817e4Smiod 88*3d8817e4Smiod /* Ifield support. */ 89*3d8817e4Smiod 90*3d8817e4Smiod /* Ifield attribute indices. */ 91*3d8817e4Smiod 92*3d8817e4Smiod /* Enum declaration for cgen_ifld attrs. */ 93*3d8817e4Smiod typedef enum cgen_ifld_attr { 94*3d8817e4Smiod CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 95*3d8817e4Smiod , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 96*3d8817e4Smiod , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_RL_TYPE, CGEN_IFLD_END_NBOOLS 97*3d8817e4Smiod } CGEN_IFLD_ATTR; 98*3d8817e4Smiod 99*3d8817e4Smiod /* Number of non-boolean elements in cgen_ifld_attr. */ 100*3d8817e4Smiod #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 101*3d8817e4Smiod 102*3d8817e4Smiod /* cgen_ifld attribute accessor macros. */ 103*3d8817e4Smiod #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 104*3d8817e4Smiod #define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) 105*3d8817e4Smiod #define CGEN_ATTR_CGEN_IFLD_RL_TYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_RL_TYPE-CGEN_IFLD_START_NBOOLS-1].nonbitset) 106*3d8817e4Smiod #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) 107*3d8817e4Smiod #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 108*3d8817e4Smiod #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 109*3d8817e4Smiod #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) 110*3d8817e4Smiod #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 111*3d8817e4Smiod #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) 112*3d8817e4Smiod 113*3d8817e4Smiod /* Enum declaration for m32c ifield types. */ 114*3d8817e4Smiod typedef enum ifield_type { 115*3d8817e4Smiod M32C_F_NIL, M32C_F_ANYOF, M32C_F_0_1, M32C_F_0_2 116*3d8817e4Smiod , M32C_F_0_3, M32C_F_0_4, M32C_F_1_3, M32C_F_2_2 117*3d8817e4Smiod , M32C_F_3_4, M32C_F_3_1, M32C_F_4_1, M32C_F_4_3 118*3d8817e4Smiod , M32C_F_4_4, M32C_F_4_6, M32C_F_5_1, M32C_F_5_3 119*3d8817e4Smiod , M32C_F_6_2, M32C_F_7_1, M32C_F_8_1, M32C_F_8_2 120*3d8817e4Smiod , M32C_F_8_3, M32C_F_8_4, M32C_F_8_8, M32C_F_9_3 121*3d8817e4Smiod , M32C_F_9_1, M32C_F_10_1, M32C_F_10_2, M32C_F_10_3 122*3d8817e4Smiod , M32C_F_11_1, M32C_F_12_1, M32C_F_12_2, M32C_F_12_3 123*3d8817e4Smiod , M32C_F_12_4, M32C_F_12_6, M32C_F_13_3, M32C_F_14_1 124*3d8817e4Smiod , M32C_F_14_2, M32C_F_15_1, M32C_F_16_1, M32C_F_16_2 125*3d8817e4Smiod , M32C_F_16_4, M32C_F_16_8, M32C_F_18_1, M32C_F_18_2 126*3d8817e4Smiod , M32C_F_18_3, M32C_F_20_1, M32C_F_20_3, M32C_F_20_2 127*3d8817e4Smiod , M32C_F_20_4, M32C_F_21_3, M32C_F_24_2, M32C_F_24_8 128*3d8817e4Smiod , M32C_F_32_16, M32C_F_SRC16_RN, M32C_F_SRC16_AN, M32C_F_SRC32_AN_UNPREFIXED 129*3d8817e4Smiod , M32C_F_SRC32_AN_PREFIXED, M32C_F_SRC32_RN_UNPREFIXED_QI, M32C_F_SRC32_RN_PREFIXED_QI, M32C_F_SRC32_RN_UNPREFIXED_HI 130*3d8817e4Smiod , M32C_F_SRC32_RN_PREFIXED_HI, M32C_F_SRC32_RN_UNPREFIXED_SI, M32C_F_SRC32_RN_PREFIXED_SI, M32C_F_DST32_RN_EXT_UNPREFIXED 131*3d8817e4Smiod , M32C_F_DST16_RN, M32C_F_DST16_RN_EXT, M32C_F_DST16_RN_QI_S, M32C_F_DST16_AN 132*3d8817e4Smiod , M32C_F_DST16_AN_S, M32C_F_DST32_AN_UNPREFIXED, M32C_F_DST32_AN_PREFIXED, M32C_F_DST32_RN_UNPREFIXED_QI 133*3d8817e4Smiod , M32C_F_DST32_RN_PREFIXED_QI, M32C_F_DST32_RN_UNPREFIXED_HI, M32C_F_DST32_RN_PREFIXED_HI, M32C_F_DST32_RN_UNPREFIXED_SI 134*3d8817e4Smiod , M32C_F_DST32_RN_PREFIXED_SI, M32C_F_DST16_1_S, M32C_F_IMM_8_S4, M32C_F_IMM_12_S4 135*3d8817e4Smiod , M32C_F_IMM_13_U3, M32C_F_IMM_20_S4, M32C_F_IMM1_S, M32C_F_IMM3_S 136*3d8817e4Smiod , M32C_F_DSP_8_U6, M32C_F_DSP_8_U8, M32C_F_DSP_8_S8, M32C_F_DSP_10_U6 137*3d8817e4Smiod , M32C_F_DSP_16_U8, M32C_F_DSP_16_S8, M32C_F_DSP_24_U8, M32C_F_DSP_24_S8 138*3d8817e4Smiod , M32C_F_DSP_32_U8, M32C_F_DSP_32_S8, M32C_F_DSP_40_U8, M32C_F_DSP_40_S8 139*3d8817e4Smiod , M32C_F_DSP_48_U8, M32C_F_DSP_48_S8, M32C_F_DSP_56_U8, M32C_F_DSP_56_S8 140*3d8817e4Smiod , M32C_F_DSP_64_U8, M32C_F_DSP_64_S8, M32C_F_DSP_8_U16, M32C_F_DSP_8_S16 141*3d8817e4Smiod , M32C_F_DSP_16_U16, M32C_F_DSP_16_S16, M32C_F_DSP_24_U16, M32C_F_DSP_24_S16 142*3d8817e4Smiod , M32C_F_DSP_32_U16, M32C_F_DSP_32_S16, M32C_F_DSP_40_U16, M32C_F_DSP_40_S16 143*3d8817e4Smiod , M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16, M32C_F_DSP_8_S24 144*3d8817e4Smiod , M32C_F_DSP_8_U24, M32C_F_DSP_16_U24, M32C_F_DSP_24_U24, M32C_F_DSP_32_U24 145*3d8817e4Smiod , M32C_F_DSP_40_U24, M32C_F_DSP_40_S32, M32C_F_DSP_48_U24, M32C_F_DSP_16_S32 146*3d8817e4Smiod , M32C_F_DSP_24_S32, M32C_F_DSP_32_S32, M32C_F_DSP_48_U32, M32C_F_DSP_48_S32 147*3d8817e4Smiod , M32C_F_DSP_56_S16, M32C_F_DSP_64_S16, M32C_F_BITNO16_S, M32C_F_BITNO32_PREFIXED 148*3d8817e4Smiod , M32C_F_BITNO32_UNPREFIXED, M32C_F_BITBASE16_U11_S, M32C_F_BITBASE32_16_U11_UNPREFIXED, M32C_F_BITBASE32_16_S11_UNPREFIXED 149*3d8817e4Smiod , M32C_F_BITBASE32_16_U19_UNPREFIXED, M32C_F_BITBASE32_16_S19_UNPREFIXED, M32C_F_BITBASE32_16_U27_UNPREFIXED, M32C_F_BITBASE32_24_U11_PREFIXED 150*3d8817e4Smiod , M32C_F_BITBASE32_24_S11_PREFIXED, M32C_F_BITBASE32_24_U19_PREFIXED, M32C_F_BITBASE32_24_S19_PREFIXED, M32C_F_BITBASE32_24_U27_PREFIXED 151*3d8817e4Smiod , M32C_F_LAB_5_3, M32C_F_LAB32_JMP_S, M32C_F_LAB_8_8, M32C_F_LAB_8_16 152*3d8817e4Smiod , M32C_F_LAB_8_24, M32C_F_LAB_16_8, M32C_F_LAB_24_8, M32C_F_LAB_32_8 153*3d8817e4Smiod , M32C_F_LAB_40_8, M32C_F_COND16, M32C_F_COND16J_5, M32C_F_COND32 154*3d8817e4Smiod , M32C_F_COND32J, M32C_F_MAX 155*3d8817e4Smiod } IFIELD_TYPE; 156*3d8817e4Smiod 157*3d8817e4Smiod #define MAX_IFLD ((int) M32C_F_MAX) 158*3d8817e4Smiod 159*3d8817e4Smiod /* Hardware attribute indices. */ 160*3d8817e4Smiod 161*3d8817e4Smiod /* Enum declaration for cgen_hw attrs. */ 162*3d8817e4Smiod typedef enum cgen_hw_attr { 163*3d8817e4Smiod CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 164*3d8817e4Smiod , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA 165*3d8817e4Smiod , CGEN_HW_RL_TYPE, CGEN_HW_END_NBOOLS 166*3d8817e4Smiod } CGEN_HW_ATTR; 167*3d8817e4Smiod 168*3d8817e4Smiod /* Number of non-boolean elements in cgen_hw_attr. */ 169*3d8817e4Smiod #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 170*3d8817e4Smiod 171*3d8817e4Smiod /* cgen_hw attribute accessor macros. */ 172*3d8817e4Smiod #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 173*3d8817e4Smiod #define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) 174*3d8817e4Smiod #define CGEN_ATTR_CGEN_HW_RL_TYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_RL_TYPE-CGEN_HW_START_NBOOLS-1].nonbitset) 175*3d8817e4Smiod #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) 176*3d8817e4Smiod #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) 177*3d8817e4Smiod #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) 178*3d8817e4Smiod #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) 179*3d8817e4Smiod 180*3d8817e4Smiod /* Enum declaration for m32c hardware types. */ 181*3d8817e4Smiod typedef enum cgen_hw_type { 182*3d8817e4Smiod HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 183*3d8817e4Smiod , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GR_QI 184*3d8817e4Smiod , HW_H_GR_HI, HW_H_GR_SI, HW_H_GR_EXT_QI, HW_H_GR_EXT_HI 185*3d8817e4Smiod , HW_H_R0L, HW_H_R0H, HW_H_R1L, HW_H_R1H 186*3d8817e4Smiod , HW_H_R0, HW_H_R1, HW_H_R2, HW_H_R3 187*3d8817e4Smiod , HW_H_R0L_R0H, HW_H_R2R0, HW_H_R3R1, HW_H_R1R2R0 188*3d8817e4Smiod , HW_H_AR, HW_H_AR_QI, HW_H_AR_HI, HW_H_AR_SI 189*3d8817e4Smiod , HW_H_A0, HW_H_A1, HW_H_SB, HW_H_FB 190*3d8817e4Smiod , HW_H_SP, HW_H_SBIT, HW_H_ZBIT, HW_H_OBIT 191*3d8817e4Smiod , HW_H_CBIT, HW_H_UBIT, HW_H_IBIT, HW_H_BBIT 192*3d8817e4Smiod , HW_H_DBIT, HW_H_DCT0, HW_H_DCT1, HW_H_SVF 193*3d8817e4Smiod , HW_H_DRC0, HW_H_DRC1, HW_H_DMD0, HW_H_DMD1 194*3d8817e4Smiod , HW_H_INTB, HW_H_SVP, HW_H_VCT, HW_H_ISP 195*3d8817e4Smiod , HW_H_DMA0, HW_H_DMA1, HW_H_DRA0, HW_H_DRA1 196*3d8817e4Smiod , HW_H_DSA0, HW_H_DSA1, HW_H_COND16, HW_H_COND16C 197*3d8817e4Smiod , HW_H_COND16J, HW_H_COND16J_5, HW_H_COND32, HW_H_CR1_32 198*3d8817e4Smiod , HW_H_CR2_32, HW_H_CR3_32, HW_H_CR_16, HW_H_FLAGS 199*3d8817e4Smiod , HW_H_SHIMM, HW_H_BIT_INDEX, HW_H_SRC_INDEX, HW_H_DST_INDEX 200*3d8817e4Smiod , HW_H_SRC_INDIRECT, HW_H_DST_INDIRECT, HW_H_NONE, HW_MAX 201*3d8817e4Smiod } CGEN_HW_TYPE; 202*3d8817e4Smiod 203*3d8817e4Smiod #define MAX_HW ((int) HW_MAX) 204*3d8817e4Smiod 205*3d8817e4Smiod /* Operand attribute indices. */ 206*3d8817e4Smiod 207*3d8817e4Smiod /* Enum declaration for cgen_operand attrs. */ 208*3d8817e4Smiod typedef enum cgen_operand_attr { 209*3d8817e4Smiod CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 210*3d8817e4Smiod , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 211*3d8817e4Smiod , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA 212*3d8817e4Smiod , CGEN_OPERAND_RL_TYPE, CGEN_OPERAND_END_NBOOLS 213*3d8817e4Smiod } CGEN_OPERAND_ATTR; 214*3d8817e4Smiod 215*3d8817e4Smiod /* Number of non-boolean elements in cgen_operand_attr. */ 216*3d8817e4Smiod #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 217*3d8817e4Smiod 218*3d8817e4Smiod /* cgen_operand attribute accessor macros. */ 219*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 220*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) 221*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_RL_TYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_RL_TYPE-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 222*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 223*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 224*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 225*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 226*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) 227*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 228*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) 229*3d8817e4Smiod #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 230*3d8817e4Smiod 231*3d8817e4Smiod /* Enum declaration for m32c operand types. */ 232*3d8817e4Smiod typedef enum cgen_operand_type { 233*3d8817e4Smiod M32C_OPERAND_PC, M32C_OPERAND_SRC16RNQI, M32C_OPERAND_SRC16RNHI, M32C_OPERAND_SRC32RNUNPREFIXEDQI 234*3d8817e4Smiod , M32C_OPERAND_SRC32RNUNPREFIXEDHI, M32C_OPERAND_SRC32RNUNPREFIXEDSI, M32C_OPERAND_SRC32RNPREFIXEDQI, M32C_OPERAND_SRC32RNPREFIXEDHI 235*3d8817e4Smiod , M32C_OPERAND_SRC32RNPREFIXEDSI, M32C_OPERAND_SRC16AN, M32C_OPERAND_SRC16ANQI, M32C_OPERAND_SRC16ANHI 236*3d8817e4Smiod , M32C_OPERAND_SRC32ANUNPREFIXED, M32C_OPERAND_SRC32ANUNPREFIXEDQI, M32C_OPERAND_SRC32ANUNPREFIXEDHI, M32C_OPERAND_SRC32ANUNPREFIXEDSI 237*3d8817e4Smiod , M32C_OPERAND_SRC32ANPREFIXED, M32C_OPERAND_SRC32ANPREFIXEDQI, M32C_OPERAND_SRC32ANPREFIXEDHI, M32C_OPERAND_SRC32ANPREFIXEDSI 238*3d8817e4Smiod , M32C_OPERAND_DST16RNQI, M32C_OPERAND_DST16RNHI, M32C_OPERAND_DST16RNSI, M32C_OPERAND_DST16RNEXTQI 239*3d8817e4Smiod , M32C_OPERAND_DST32R0QI_S, M32C_OPERAND_DST32R0HI_S, M32C_OPERAND_DST32RNUNPREFIXEDQI, M32C_OPERAND_DST32RNUNPREFIXEDHI 240*3d8817e4Smiod , M32C_OPERAND_DST32RNUNPREFIXEDSI, M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDQI 241*3d8817e4Smiod , M32C_OPERAND_DST32RNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDSI, M32C_OPERAND_DST16RNQI_S, M32C_OPERAND_DST16ANQI_S 242*3d8817e4Smiod , M32C_OPERAND_BIT16RN, M32C_OPERAND_BIT32RNPREFIXED, M32C_OPERAND_BIT32RNUNPREFIXED, M32C_OPERAND_R0 243*3d8817e4Smiod , M32C_OPERAND_R1, M32C_OPERAND_R2, M32C_OPERAND_R3, M32C_OPERAND_R0L 244*3d8817e4Smiod , M32C_OPERAND_R0H, M32C_OPERAND_R2R0, M32C_OPERAND_R3R1, M32C_OPERAND_R1R2R0 245*3d8817e4Smiod , M32C_OPERAND_DST16AN, M32C_OPERAND_DST16ANQI, M32C_OPERAND_DST16ANHI, M32C_OPERAND_DST16ANSI 246*3d8817e4Smiod , M32C_OPERAND_DST16AN_S, M32C_OPERAND_DST32ANUNPREFIXED, M32C_OPERAND_DST32ANUNPREFIXEDQI, M32C_OPERAND_DST32ANUNPREFIXEDHI 247*3d8817e4Smiod , M32C_OPERAND_DST32ANUNPREFIXEDSI, M32C_OPERAND_DST32ANEXTUNPREFIXED, M32C_OPERAND_DST32ANPREFIXED, M32C_OPERAND_DST32ANPREFIXEDQI 248*3d8817e4Smiod , M32C_OPERAND_DST32ANPREFIXEDHI, M32C_OPERAND_DST32ANPREFIXEDSI, M32C_OPERAND_BIT16AN, M32C_OPERAND_BIT32ANPREFIXED 249*3d8817e4Smiod , M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_SB 250*3d8817e4Smiod , M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, M32C_OPERAND_REGSETPOP 251*3d8817e4Smiod , M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S, M32C_OPERAND_DSP_8_U6 252*3d8817e4Smiod , M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_S24 253*3d8817e4Smiod , M32C_OPERAND_DSP_8_U24, M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16 254*3d8817e4Smiod , M32C_OPERAND_DSP_16_U20, M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16 255*3d8817e4Smiod , M32C_OPERAND_DSP_24_U8, M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24 256*3d8817e4Smiod , M32C_OPERAND_DSP_24_S8, M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16 257*3d8817e4Smiod , M32C_OPERAND_DSP_32_U24, M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16 258*3d8817e4Smiod , M32C_OPERAND_DSP_40_U8, M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16 259*3d8817e4Smiod , M32C_OPERAND_DSP_40_U24, M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16 260*3d8817e4Smiod , M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U24, M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_8_S4N 261*3d8817e4Smiod , M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI, M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4 262*3d8817e4Smiod , M32C_OPERAND_IMM_12_S4N, M32C_OPERAND_IMM_SH_12_S4, M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4 263*3d8817e4Smiod , M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI, M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI 264*3d8817e4Smiod , M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI, M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI 265*3d8817e4Smiod , M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI, M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI 266*3d8817e4Smiod , M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI, M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI 267*3d8817e4Smiod , M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI, M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S 268*3d8817e4Smiod , M32C_OPERAND_IMM3_S, M32C_OPERAND_BIT3_S, M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED 269*3d8817e4Smiod , M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16 270*3d8817e4Smiod , M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED 271*3d8817e4Smiod , M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED 272*3d8817e4Smiod , M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3 273*3d8817e4Smiod , M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24 274*3d8817e4Smiod , M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8 275*3d8817e4Smiod , M32C_OPERAND_SBIT, M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT 276*3d8817e4Smiod , M32C_OPERAND_UBIT, M32C_OPERAND_IBIT, M32C_OPERAND_BBIT, M32C_OPERAND_DBIT 277*3d8817e4Smiod , M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16 278*3d8817e4Smiod , M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C 279*3d8817e4Smiod , M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5, M32C_OPERAND_COND32, M32C_OPERAND_COND32J 280*3d8817e4Smiod , M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16 281*3d8817e4Smiod , M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32 282*3d8817e4Smiod , M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z, M32C_OPERAND_S, M32C_OPERAND_Q 283*3d8817e4Smiod , M32C_OPERAND_G, M32C_OPERAND_X, M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX 284*3d8817e4Smiod , M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI 285*3d8817e4Smiod , M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI 286*3d8817e4Smiod , M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI 287*3d8817e4Smiod , M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI 288*3d8817e4Smiod , M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI 289*3d8817e4Smiod , M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI 290*3d8817e4Smiod , M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI 291*3d8817e4Smiod , M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI 292*3d8817e4Smiod , M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI 293*3d8817e4Smiod , M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI 294*3d8817e4Smiod , M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI 295*3d8817e4Smiod , M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI 296*3d8817e4Smiod , M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI 297*3d8817e4Smiod , M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI 298*3d8817e4Smiod , M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI 299*3d8817e4Smiod , M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI 300*3d8817e4Smiod , M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI 301*3d8817e4Smiod , M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI 302*3d8817e4Smiod , M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI 303*3d8817e4Smiod , M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI 304*3d8817e4Smiod , M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI 305*3d8817e4Smiod , M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI 306*3d8817e4Smiod , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI 307*3d8817e4Smiod , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI 308*3d8817e4Smiod , M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI 309*3d8817e4Smiod , M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI 310*3d8817e4Smiod , M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI 311*3d8817e4Smiod , M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI 312*3d8817e4Smiod , M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI 313*3d8817e4Smiod , M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI 314*3d8817e4Smiod , M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI 315*3d8817e4Smiod , M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI 316*3d8817e4Smiod , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI 317*3d8817e4Smiod , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI 318*3d8817e4Smiod , M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI 319*3d8817e4Smiod , M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI 320*3d8817e4Smiod , M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI 321*3d8817e4Smiod , M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI 322*3d8817e4Smiod , M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI 323*3d8817e4Smiod , M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI 324*3d8817e4Smiod , M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI 325*3d8817e4Smiod , M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI 326*3d8817e4Smiod , M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI 327*3d8817e4Smiod , M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI 328*3d8817e4Smiod , M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI 329*3d8817e4Smiod , M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI 330*3d8817e4Smiod , M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI 331*3d8817e4Smiod , M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI 332*3d8817e4Smiod , M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI 333*3d8817e4Smiod , M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI 334*3d8817e4Smiod , M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI 335*3d8817e4Smiod , M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI 336*3d8817e4Smiod , M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI 337*3d8817e4Smiod , M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI 338*3d8817e4Smiod , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI 339*3d8817e4Smiod , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI 340*3d8817e4Smiod , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI 341*3d8817e4Smiod , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI 342*3d8817e4Smiod , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI 343*3d8817e4Smiod , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI 344*3d8817e4Smiod , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI 345*3d8817e4Smiod , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI 346*3d8817e4Smiod , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI 347*3d8817e4Smiod , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI 348*3d8817e4Smiod , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI 349*3d8817e4Smiod , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI 350*3d8817e4Smiod , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI 351*3d8817e4Smiod , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI 352*3d8817e4Smiod , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI 353*3d8817e4Smiod , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI 354*3d8817e4Smiod , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI 355*3d8817e4Smiod , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI 356*3d8817e4Smiod , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI 357*3d8817e4Smiod , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI 358*3d8817e4Smiod , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI 359*3d8817e4Smiod , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI 360*3d8817e4Smiod , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI 361*3d8817e4Smiod , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI 362*3d8817e4Smiod , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI 363*3d8817e4Smiod , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI 364*3d8817e4Smiod , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI 365*3d8817e4Smiod , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI 366*3d8817e4Smiod , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI 367*3d8817e4Smiod , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI 368*3d8817e4Smiod , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI 369*3d8817e4Smiod , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI 370*3d8817e4Smiod , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI 371*3d8817e4Smiod , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI 372*3d8817e4Smiod , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI 373*3d8817e4Smiod , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI 374*3d8817e4Smiod , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI 375*3d8817e4Smiod , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI 376*3d8817e4Smiod , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI 377*3d8817e4Smiod , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI 378*3d8817e4Smiod , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI 379*3d8817e4Smiod , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI 380*3d8817e4Smiod , M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI 381*3d8817e4Smiod , M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI 382*3d8817e4Smiod , M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI 383*3d8817e4Smiod , M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI 384*3d8817e4Smiod , M32C_OPERAND_DST16_32_16_ABSOLUTE_QI, M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI 385*3d8817e4Smiod , M32C_OPERAND_DST16_24_16_ABSOLUTE_HI, M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI 386*3d8817e4Smiod , M32C_OPERAND_DST16_16_16_ABSOLUTE_SI, M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI 387*3d8817e4Smiod , M32C_OPERAND_DST16_48_16_ABSOLUTE_SI, M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI 388*3d8817e4Smiod , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI 389*3d8817e4Smiod , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI 390*3d8817e4Smiod , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI 391*3d8817e4Smiod , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI 392*3d8817e4Smiod , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI 393*3d8817e4Smiod , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI 394*3d8817e4Smiod , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI 395*3d8817e4Smiod , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI 396*3d8817e4Smiod , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI 397*3d8817e4Smiod , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI 398*3d8817e4Smiod , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI 399*3d8817e4Smiod , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI 400*3d8817e4Smiod , M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED 401*3d8817e4Smiod , M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED 402*3d8817e4Smiod , M32C_OPERAND_BIT16_AN_INDIRECT, M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE 403*3d8817e4Smiod , M32C_OPERAND_BIT16_16_16_SB_RELATIVE, M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE 404*3d8817e4Smiod , M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED 405*3d8817e4Smiod , M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED 406*3d8817e4Smiod , M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED 407*3d8817e4Smiod , M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED 408*3d8817e4Smiod , M32C_OPERAND_AN16_PUSH_S_DERIVED, M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED 409*3d8817e4Smiod , M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI 410*3d8817e4Smiod , M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI 411*3d8817e4Smiod , M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI 412*3d8817e4Smiod , M32C_OPERAND_DST32_2_S_R0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI 413*3d8817e4Smiod , M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI 414*3d8817e4Smiod , M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI 415*3d8817e4Smiod , M32C_OPERAND_SRC16_BASIC_QI, M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI 416*3d8817e4Smiod , M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI, M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI 417*3d8817e4Smiod , M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI, M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI 418*3d8817e4Smiod , M32C_OPERAND_SRC16_16_16_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI 419*3d8817e4Smiod , M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI 420*3d8817e4Smiod , M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI 421*3d8817e4Smiod , M32C_OPERAND_SRC32_24_24_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI 422*3d8817e4Smiod , M32C_OPERAND_SRC32_24_8_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI 423*3d8817e4Smiod , M32C_OPERAND_DST16_BASIC_HI, M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI 424*3d8817e4Smiod , M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI, M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI 425*3d8817e4Smiod , M32C_OPERAND_DST16_16_QI, M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI 426*3d8817e4Smiod , M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI 427*3d8817e4Smiod , M32C_OPERAND_DST16_16_16_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI 428*3d8817e4Smiod , M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI 429*3d8817e4Smiod , M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI 430*3d8817e4Smiod , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI 431*3d8817e4Smiod , M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI 432*3d8817e4Smiod , M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI 433*3d8817e4Smiod , M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI 434*3d8817e4Smiod , M32C_OPERAND_DST32_16_24_UNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI 435*3d8817e4Smiod , M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI 436*3d8817e4Smiod , M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI 437*3d8817e4Smiod , M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI 438*3d8817e4Smiod , M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI 439*3d8817e4Smiod , M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI 440*3d8817e4Smiod , M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI 441*3d8817e4Smiod , M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI 442*3d8817e4Smiod , M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI 443*3d8817e4Smiod , M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI 444*3d8817e4Smiod , M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC 445*3d8817e4Smiod , M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED 446*3d8817e4Smiod , M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED 447*3d8817e4Smiod , M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8 448*3d8817e4Smiod , M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI 449*3d8817e4Smiod , M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI 450*3d8817e4Smiod , M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S 451*3d8817e4Smiod , M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX 452*3d8817e4Smiod } CGEN_OPERAND_TYPE; 453*3d8817e4Smiod 454*3d8817e4Smiod /* Number of operands types. */ 455*3d8817e4Smiod #define MAX_OPERANDS 874 456*3d8817e4Smiod 457*3d8817e4Smiod /* Maximum number of operands referenced by any insn. */ 458*3d8817e4Smiod #define MAX_OPERAND_INSTANCES 8 459*3d8817e4Smiod 460*3d8817e4Smiod /* Insn attribute indices. */ 461*3d8817e4Smiod 462*3d8817e4Smiod /* Enum declaration for cgen_insn attrs. */ 463*3d8817e4Smiod typedef enum cgen_insn_attr { 464*3d8817e4Smiod CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 465*3d8817e4Smiod , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 466*3d8817e4Smiod , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 467*3d8817e4Smiod , CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_RL_TYPE, CGEN_INSN_END_NBOOLS 468*3d8817e4Smiod } CGEN_INSN_ATTR; 469*3d8817e4Smiod 470*3d8817e4Smiod /* Number of non-boolean elements in cgen_insn_attr. */ 471*3d8817e4Smiod #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 472*3d8817e4Smiod 473*3d8817e4Smiod /* cgen_insn attribute accessor macros. */ 474*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 475*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) 476*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_RL_TYPE-CGEN_INSN_START_NBOOLS-1].nonbitset) 477*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) 478*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) 479*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 480*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) 481*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) 482*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 483*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) 484*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) 485*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) 486*3d8817e4Smiod #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) 487*3d8817e4Smiod 488*3d8817e4Smiod /* cgen.h uses things we just defined. */ 489*3d8817e4Smiod #include "opcode/cgen.h" 490*3d8817e4Smiod 491*3d8817e4Smiod extern const struct cgen_ifld m32c_cgen_ifld_table[]; 492*3d8817e4Smiod 493*3d8817e4Smiod /* Attributes. */ 494*3d8817e4Smiod extern const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[]; 495*3d8817e4Smiod extern const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[]; 496*3d8817e4Smiod extern const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[]; 497*3d8817e4Smiod extern const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[]; 498*3d8817e4Smiod 499*3d8817e4Smiod /* Hardware decls. */ 500*3d8817e4Smiod 501*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_gr; 502*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_gr_QI; 503*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_gr_HI; 504*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_gr_SI; 505*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI; 506*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI; 507*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r0l; 508*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r0h; 509*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r1l; 510*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r1h; 511*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r0; 512*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r1; 513*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r2; 514*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r3; 515*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h; 516*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r2r0; 517*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r3r1; 518*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0; 519*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_ar; 520*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_ar_QI; 521*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_ar_HI; 522*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_ar_SI; 523*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_a0; 524*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_a1; 525*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_cond16; 526*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_cond16c; 527*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_cond16j; 528*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5; 529*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_cond32; 530*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_cr1_32; 531*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_cr2_32; 532*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_cr3_32; 533*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_cr_16; 534*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_flags; 535*3d8817e4Smiod extern CGEN_KEYWORD m32c_cgen_opval_h_shimm; 536*3d8817e4Smiod 537*3d8817e4Smiod extern const CGEN_HW_ENTRY m32c_cgen_hw_table[]; 538*3d8817e4Smiod 539*3d8817e4Smiod 540*3d8817e4Smiod 541*3d8817e4Smiod #endif /* M32C_CPU_H */ 542