1 /* CPU data header for openrisc. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright 1996-2005 Free Software Foundation, Inc. 6 7 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2, or (at your option) 12 any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #ifndef OPENRISC_CPU_H 26 #define OPENRISC_CPU_H 27 28 #include "opcode/cgen-bitset.h" 29 30 #define CGEN_ARCH openrisc 31 32 /* Given symbol S, return openrisc_cgen_<S>. */ 33 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 34 #define CGEN_SYM(s) openrisc##_cgen_##s 35 #else 36 #define CGEN_SYM(s) openrisc/**/_cgen_/**/s 37 #endif 38 39 40 /* Selected cpu families. */ 41 #define HAVE_CPU_OPENRISCBF 42 43 #define CGEN_INSN_LSB0_P 1 44 45 /* Minimum size of any insn (in bytes). */ 46 #define CGEN_MIN_INSN_SIZE 4 47 48 /* Maximum size of any insn (in bytes). */ 49 #define CGEN_MAX_INSN_SIZE 4 50 51 #define CGEN_INT_INSN_P 1 52 53 /* Maximum number of syntax elements in an instruction. */ 54 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 14 55 56 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 57 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 58 we can't hash on everything up to the space. */ 59 #define CGEN_MNEMONIC_OPERANDS 60 61 /* Maximum number of fields in an instruction. */ 62 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9 63 64 /* Enums. */ 65 66 /* Enum declaration for exception vectors. */ 67 typedef enum e_exception { 68 E_RESET, E_BUSERR, E_DPF, E_IPF 69 , E_EXTINT, E_ALIGN, E_ILLEGAL, E_PEINT 70 , E_DTLBMISS, E_ITLBMISS, E_RRANGE, E_SYSCALL 71 , E_BREAK, E_RESERVED 72 } E_EXCEPTION; 73 74 /* Enum declaration for FIXME. */ 75 typedef enum insn_class { 76 OP1_0, OP1_1, OP1_2, OP1_3 77 } INSN_CLASS; 78 79 /* Enum declaration for FIXME. */ 80 typedef enum insn_sub { 81 OP2_0, OP2_1, OP2_2, OP2_3 82 , OP2_4, OP2_5, OP2_6, OP2_7 83 , OP2_8, OP2_9, OP2_10, OP2_11 84 , OP2_12, OP2_13, OP2_14, OP2_15 85 } INSN_SUB; 86 87 /* Enum declaration for FIXME. */ 88 typedef enum insn_op3 { 89 OP3_0, OP3_1, OP3_2, OP3_3 90 } INSN_OP3; 91 92 /* Enum declaration for FIXME. */ 93 typedef enum insn_op4 { 94 OP4_0, OP4_1, OP4_2, OP4_3 95 , OP4_4, OP4_5, OP4_6, OP4_7 96 } INSN_OP4; 97 98 /* Enum declaration for FIXME. */ 99 typedef enum insn_op5 { 100 OP5_0, OP5_1, OP5_2, OP5_3 101 , OP5_4, OP5_5, OP5_6, OP5_7 102 , OP5_8, OP5_9, OP5_10, OP5_11 103 , OP5_12, OP5_13, OP5_14, OP5_15 104 , OP5_16, OP5_17, OP5_18, OP5_19 105 , OP5_20, OP5_21, OP5_22, OP5_23 106 , OP5_24, OP5_25, OP5_26, OP5_27 107 , OP5_28, OP5_29, OP5_30, OP5_31 108 } INSN_OP5; 109 110 /* Enum declaration for FIXME. */ 111 typedef enum insn_op6 { 112 OP6_0, OP6_1, OP6_2, OP6_3 113 , OP6_4, OP6_5, OP6_6, OP6_7 114 } INSN_OP6; 115 116 /* Enum declaration for FIXME. */ 117 typedef enum insn_op7 { 118 OP7_0, OP7_1, OP7_2, OP7_3 119 , OP7_4, OP7_5, OP7_6, OP7_7 120 , OP7_8, OP7_9, OP7_10, OP7_11 121 , OP7_12, OP7_13, OP7_14, OP7_15 122 } INSN_OP7; 123 124 /* Attributes. */ 125 126 /* Enum declaration for machine type selection. */ 127 typedef enum mach_attr { 128 MACH_BASE, MACH_OPENRISC, MACH_OR1300, MACH_MAX 129 } MACH_ATTR; 130 131 /* Enum declaration for instruction set selection. */ 132 typedef enum isa_attr { 133 ISA_OR32, ISA_MAX 134 } ISA_ATTR; 135 136 /* Enum declaration for if this model has caches. */ 137 typedef enum has_cache_attr { 138 HAS_CACHE_DATA_CACHE, HAS_CACHE_INSN_CACHE 139 } HAS_CACHE_ATTR; 140 141 /* Number of architecture variants. */ 142 #define MAX_ISAS 1 143 #define MAX_MACHS ((int) MACH_MAX) 144 145 /* Ifield support. */ 146 147 /* Ifield attribute indices. */ 148 149 /* Enum declaration for cgen_ifld attrs. */ 150 typedef enum cgen_ifld_attr { 151 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 152 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 153 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 154 } CGEN_IFLD_ATTR; 155 156 /* Number of non-boolean elements in cgen_ifld_attr. */ 157 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 158 159 /* cgen_ifld attribute accessor macros. */ 160 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 161 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) 162 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 163 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 164 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) 165 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 166 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) 167 168 /* Enum declaration for openrisc ifield types. */ 169 typedef enum ifield_type { 170 OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB 171 , OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3, OPENRISC_F_SIMM16 172 , OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16, OPENRISC_F_LO16 173 , OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3, OPENRISC_F_OP4 174 , OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7, OPENRISC_F_I16_1 175 , OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26, OPENRISC_F_I16NC 176 , OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1, OPENRISC_F_F_7_3 177 , OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX 178 } IFIELD_TYPE; 179 180 #define MAX_IFLD ((int) OPENRISC_F_MAX) 181 182 /* Hardware attribute indices. */ 183 184 /* Enum declaration for cgen_hw attrs. */ 185 typedef enum cgen_hw_attr { 186 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 187 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 188 } CGEN_HW_ATTR; 189 190 /* Number of non-boolean elements in cgen_hw_attr. */ 191 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 192 193 /* cgen_hw attribute accessor macros. */ 194 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 195 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) 196 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) 197 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) 198 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) 199 200 /* Enum declaration for openrisc hardware types. */ 201 typedef enum cgen_hw_type { 202 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 203 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_SR 204 , HW_H_HI16, HW_H_LO16, HW_H_CBIT, HW_H_DELAY_INSN 205 , HW_MAX 206 } CGEN_HW_TYPE; 207 208 #define MAX_HW ((int) HW_MAX) 209 210 /* Operand attribute indices. */ 211 212 /* Enum declaration for cgen_operand attrs. */ 213 typedef enum cgen_operand_attr { 214 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 215 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 216 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS 217 } CGEN_OPERAND_ATTR; 218 219 /* Number of non-boolean elements in cgen_operand_attr. */ 220 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 221 222 /* cgen_operand attribute accessor macros. */ 223 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 224 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 225 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 226 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 227 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 228 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) 229 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 230 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) 231 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 232 233 /* Enum declaration for openrisc operand types. */ 234 typedef enum cgen_operand_type { 235 OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16 236 , OPENRISC_OPERAND_UIMM_16, OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5 237 , OPENRISC_OPERAND_RD, OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23 238 , OPENRISC_OPERAND_OP_F_3, OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC 239 , OPENRISC_OPERAND_MAX 240 } CGEN_OPERAND_TYPE; 241 242 /* Number of operands types. */ 243 #define MAX_OPERANDS 16 244 245 /* Maximum number of operands referenced by any insn. */ 246 #define MAX_OPERAND_INSTANCES 8 247 248 /* Insn attribute indices. */ 249 250 /* Enum declaration for cgen_insn attrs. */ 251 typedef enum cgen_insn_attr { 252 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 253 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 254 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS 255 , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS 256 } CGEN_INSN_ATTR; 257 258 /* Number of non-boolean elements in cgen_insn_attr. */ 259 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 260 261 /* cgen_insn attribute accessor macros. */ 262 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 263 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) 264 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) 265 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 266 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) 267 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) 268 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 269 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) 270 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) 271 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) 272 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) 273 #define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) 274 275 /* cgen.h uses things we just defined. */ 276 #include "opcode/cgen.h" 277 278 extern const struct cgen_ifld openrisc_cgen_ifld_table[]; 279 280 /* Attributes. */ 281 extern const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[]; 282 extern const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[]; 283 extern const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[]; 284 extern const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[]; 285 286 /* Hardware decls. */ 287 288 extern CGEN_KEYWORD openrisc_cgen_opval_h_gr; 289 290 extern const CGEN_HW_ENTRY openrisc_cgen_hw_table[]; 291 292 293 294 #endif /* OPENRISC_CPU_H */ 295