1*3d8817e4Smiod /* Assemble V850 instructions.
2*3d8817e4Smiod Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005
3*3d8817e4Smiod Free Software Foundation, Inc.
4*3d8817e4Smiod
5*3d8817e4Smiod This program is free software; you can redistribute it and/or modify
6*3d8817e4Smiod it under the terms of the GNU General Public License as published by
7*3d8817e4Smiod the Free Software Foundation; either version 2 of the License, or
8*3d8817e4Smiod (at your option) any later version.
9*3d8817e4Smiod
10*3d8817e4Smiod This program is distributed in the hope that it will be useful,
11*3d8817e4Smiod but WITHOUT ANY WARRANTY; without even the implied warranty of
12*3d8817e4Smiod MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13*3d8817e4Smiod GNU General Public License for more details.
14*3d8817e4Smiod
15*3d8817e4Smiod You should have received a copy of the GNU General Public License
16*3d8817e4Smiod along with this program; if not, write to the Free Software
17*3d8817e4Smiod Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
18*3d8817e4Smiod MA 02110-1301, USA. */
19*3d8817e4Smiod
20*3d8817e4Smiod #include "sysdep.h"
21*3d8817e4Smiod #include "opcode/v850.h"
22*3d8817e4Smiod #include <stdio.h>
23*3d8817e4Smiod #include "opintl.h"
24*3d8817e4Smiod
25*3d8817e4Smiod /* Regular opcodes. */
26*3d8817e4Smiod #define OP(x) ((x & 0x3f) << 5)
27*3d8817e4Smiod #define OP_MASK OP (0x3f)
28*3d8817e4Smiod
29*3d8817e4Smiod /* Conditional branch opcodes. */
30*3d8817e4Smiod #define BOP(x) ((0x0b << 7) | (x & 0x0f))
31*3d8817e4Smiod #define BOP_MASK ((0x0f << 7) | 0x0f)
32*3d8817e4Smiod
33*3d8817e4Smiod /* One-word opcodes. */
34*3d8817e4Smiod #define one(x) ((unsigned int) (x))
35*3d8817e4Smiod
36*3d8817e4Smiod /* Two-word opcodes. */
37*3d8817e4Smiod #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
38*3d8817e4Smiod
39*3d8817e4Smiod /* The functions used to insert and extract complicated operands. */
40*3d8817e4Smiod
41*3d8817e4Smiod /* Note: There is a conspiracy between these functions and
42*3d8817e4Smiod v850_insert_operand() in gas/config/tc-v850.c. Error messages
43*3d8817e4Smiod containing the string 'out of range' will be ignored unless a
44*3d8817e4Smiod specific command line option is given to GAS. */
45*3d8817e4Smiod
46*3d8817e4Smiod static const char * not_valid = N_ ("displacement value is not in range and is not aligned");
47*3d8817e4Smiod static const char * out_of_range = N_ ("displacement value is out of range");
48*3d8817e4Smiod static const char * not_aligned = N_ ("displacement value is not aligned");
49*3d8817e4Smiod
50*3d8817e4Smiod static const char * immediate_out_of_range = N_ ("immediate value is out of range");
51*3d8817e4Smiod
52*3d8817e4Smiod static unsigned long
insert_d9(unsigned long insn,long value,const char ** errmsg)53*3d8817e4Smiod insert_d9 (unsigned long insn, long value, const char ** errmsg)
54*3d8817e4Smiod {
55*3d8817e4Smiod if (value > 0xff || value < -0x100)
56*3d8817e4Smiod {
57*3d8817e4Smiod if ((value % 2) != 0)
58*3d8817e4Smiod * errmsg = _("branch value not in range and to odd offset");
59*3d8817e4Smiod else
60*3d8817e4Smiod * errmsg = _("branch value out of range");
61*3d8817e4Smiod }
62*3d8817e4Smiod else if ((value % 2) != 0)
63*3d8817e4Smiod * errmsg = _("branch to odd offset");
64*3d8817e4Smiod
65*3d8817e4Smiod return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3);
66*3d8817e4Smiod }
67*3d8817e4Smiod
68*3d8817e4Smiod static unsigned long
extract_d9(unsigned long insn,int * invalid ATTRIBUTE_UNUSED)69*3d8817e4Smiod extract_d9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
70*3d8817e4Smiod {
71*3d8817e4Smiod unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
72*3d8817e4Smiod
73*3d8817e4Smiod if ((insn & 0x8000) != 0)
74*3d8817e4Smiod ret -= 0x0200;
75*3d8817e4Smiod
76*3d8817e4Smiod return ret;
77*3d8817e4Smiod }
78*3d8817e4Smiod
79*3d8817e4Smiod static unsigned long
insert_d22(unsigned long insn,long value,const char ** errmsg)80*3d8817e4Smiod insert_d22 (unsigned long insn, long value, const char ** errmsg)
81*3d8817e4Smiod {
82*3d8817e4Smiod if (value > 0x1fffff || value < -0x200000)
83*3d8817e4Smiod {
84*3d8817e4Smiod if ((value % 2) != 0)
85*3d8817e4Smiod * errmsg = _("branch value not in range and to an odd offset");
86*3d8817e4Smiod else
87*3d8817e4Smiod * errmsg = _("branch value out of range");
88*3d8817e4Smiod }
89*3d8817e4Smiod else if ((value % 2) != 0)
90*3d8817e4Smiod * errmsg = _("branch to odd offset");
91*3d8817e4Smiod
92*3d8817e4Smiod return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16);
93*3d8817e4Smiod }
94*3d8817e4Smiod
95*3d8817e4Smiod static unsigned long
extract_d22(unsigned long insn,int * invalid ATTRIBUTE_UNUSED)96*3d8817e4Smiod extract_d22 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
97*3d8817e4Smiod {
98*3d8817e4Smiod signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
99*3d8817e4Smiod
100*3d8817e4Smiod return (unsigned long) ((ret << 10) >> 10);
101*3d8817e4Smiod }
102*3d8817e4Smiod
103*3d8817e4Smiod static unsigned long
insert_d16_15(unsigned long insn,long value,const char ** errmsg)104*3d8817e4Smiod insert_d16_15 (unsigned long insn, long value, const char ** errmsg)
105*3d8817e4Smiod {
106*3d8817e4Smiod if (value > 0x7fff || value < -0x8000)
107*3d8817e4Smiod {
108*3d8817e4Smiod if ((value % 2) != 0)
109*3d8817e4Smiod * errmsg = _(not_valid);
110*3d8817e4Smiod else
111*3d8817e4Smiod * errmsg = _(out_of_range);
112*3d8817e4Smiod }
113*3d8817e4Smiod else if ((value % 2) != 0)
114*3d8817e4Smiod * errmsg = _(not_aligned);
115*3d8817e4Smiod
116*3d8817e4Smiod return insn | ((value & 0xfffe) << 16);
117*3d8817e4Smiod }
118*3d8817e4Smiod
119*3d8817e4Smiod static unsigned long
extract_d16_15(unsigned long insn,int * invalid ATTRIBUTE_UNUSED)120*3d8817e4Smiod extract_d16_15 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
121*3d8817e4Smiod {
122*3d8817e4Smiod signed long ret = (insn & 0xfffe0000);
123*3d8817e4Smiod
124*3d8817e4Smiod return ret >> 16;
125*3d8817e4Smiod }
126*3d8817e4Smiod
127*3d8817e4Smiod static unsigned long
insert_d8_7(unsigned long insn,long value,const char ** errmsg)128*3d8817e4Smiod insert_d8_7 (unsigned long insn, long value, const char ** errmsg)
129*3d8817e4Smiod {
130*3d8817e4Smiod if (value > 0xff || value < 0)
131*3d8817e4Smiod {
132*3d8817e4Smiod if ((value % 2) != 0)
133*3d8817e4Smiod * errmsg = _(not_valid);
134*3d8817e4Smiod else
135*3d8817e4Smiod * errmsg = _(out_of_range);
136*3d8817e4Smiod }
137*3d8817e4Smiod else if ((value % 2) != 0)
138*3d8817e4Smiod * errmsg = _(not_aligned);
139*3d8817e4Smiod
140*3d8817e4Smiod value >>= 1;
141*3d8817e4Smiod
142*3d8817e4Smiod return insn | (value & 0x7f);
143*3d8817e4Smiod }
144*3d8817e4Smiod
145*3d8817e4Smiod static unsigned long
extract_d8_7(unsigned long insn,int * invalid ATTRIBUTE_UNUSED)146*3d8817e4Smiod extract_d8_7 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
147*3d8817e4Smiod {
148*3d8817e4Smiod unsigned long ret = (insn & 0x7f);
149*3d8817e4Smiod
150*3d8817e4Smiod return ret << 1;
151*3d8817e4Smiod }
152*3d8817e4Smiod
153*3d8817e4Smiod static unsigned long
insert_d8_6(unsigned long insn,long value,const char ** errmsg)154*3d8817e4Smiod insert_d8_6 (unsigned long insn, long value, const char ** errmsg)
155*3d8817e4Smiod {
156*3d8817e4Smiod if (value > 0xff || value < 0)
157*3d8817e4Smiod {
158*3d8817e4Smiod if ((value % 4) != 0)
159*3d8817e4Smiod *errmsg = _(not_valid);
160*3d8817e4Smiod else
161*3d8817e4Smiod * errmsg = _(out_of_range);
162*3d8817e4Smiod }
163*3d8817e4Smiod else if ((value % 4) != 0)
164*3d8817e4Smiod * errmsg = _(not_aligned);
165*3d8817e4Smiod
166*3d8817e4Smiod value >>= 1;
167*3d8817e4Smiod
168*3d8817e4Smiod return insn | (value & 0x7e);
169*3d8817e4Smiod }
170*3d8817e4Smiod
171*3d8817e4Smiod static unsigned long
extract_d8_6(unsigned long insn,int * invalid ATTRIBUTE_UNUSED)172*3d8817e4Smiod extract_d8_6 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
173*3d8817e4Smiod {
174*3d8817e4Smiod unsigned long ret = (insn & 0x7e);
175*3d8817e4Smiod
176*3d8817e4Smiod return ret << 1;
177*3d8817e4Smiod }
178*3d8817e4Smiod
179*3d8817e4Smiod static unsigned long
insert_d5_4(unsigned long insn,long value,const char ** errmsg)180*3d8817e4Smiod insert_d5_4 (unsigned long insn, long value, const char ** errmsg)
181*3d8817e4Smiod {
182*3d8817e4Smiod if (value > 0x1f || value < 0)
183*3d8817e4Smiod {
184*3d8817e4Smiod if (value & 1)
185*3d8817e4Smiod * errmsg = _(not_valid);
186*3d8817e4Smiod else
187*3d8817e4Smiod *errmsg = _(out_of_range);
188*3d8817e4Smiod }
189*3d8817e4Smiod else if (value & 1)
190*3d8817e4Smiod * errmsg = _(not_aligned);
191*3d8817e4Smiod
192*3d8817e4Smiod value >>= 1;
193*3d8817e4Smiod
194*3d8817e4Smiod return insn | (value & 0x0f);
195*3d8817e4Smiod }
196*3d8817e4Smiod
197*3d8817e4Smiod static unsigned long
extract_d5_4(unsigned long insn,int * invalid ATTRIBUTE_UNUSED)198*3d8817e4Smiod extract_d5_4 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
199*3d8817e4Smiod {
200*3d8817e4Smiod unsigned long ret = (insn & 0x0f);
201*3d8817e4Smiod
202*3d8817e4Smiod return ret << 1;
203*3d8817e4Smiod }
204*3d8817e4Smiod
205*3d8817e4Smiod static unsigned long
insert_d16_16(unsigned long insn,signed long value,const char ** errmsg)206*3d8817e4Smiod insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg)
207*3d8817e4Smiod {
208*3d8817e4Smiod if (value > 0x7fff || value < -0x8000)
209*3d8817e4Smiod * errmsg = _(out_of_range);
210*3d8817e4Smiod
211*3d8817e4Smiod return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5);
212*3d8817e4Smiod }
213*3d8817e4Smiod
214*3d8817e4Smiod static unsigned long
extract_d16_16(unsigned long insn,int * invalid ATTRIBUTE_UNUSED)215*3d8817e4Smiod extract_d16_16 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
216*3d8817e4Smiod {
217*3d8817e4Smiod signed long ret = insn & 0xfffe0000;
218*3d8817e4Smiod
219*3d8817e4Smiod ret >>= 16;
220*3d8817e4Smiod
221*3d8817e4Smiod ret |= ((insn & 0x20) >> 5);
222*3d8817e4Smiod
223*3d8817e4Smiod return ret;
224*3d8817e4Smiod }
225*3d8817e4Smiod
226*3d8817e4Smiod static unsigned long
insert_i9(unsigned long insn,signed long value,const char ** errmsg)227*3d8817e4Smiod insert_i9 (unsigned long insn, signed long value, const char ** errmsg)
228*3d8817e4Smiod {
229*3d8817e4Smiod if (value > 0xff || value < -0x100)
230*3d8817e4Smiod * errmsg = _(immediate_out_of_range);
231*3d8817e4Smiod
232*3d8817e4Smiod return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
233*3d8817e4Smiod }
234*3d8817e4Smiod
235*3d8817e4Smiod static unsigned long
extract_i9(unsigned long insn,int * invalid ATTRIBUTE_UNUSED)236*3d8817e4Smiod extract_i9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
237*3d8817e4Smiod {
238*3d8817e4Smiod signed long ret = insn & 0x003c0000;
239*3d8817e4Smiod
240*3d8817e4Smiod ret <<= 10;
241*3d8817e4Smiod ret >>= 23;
242*3d8817e4Smiod
243*3d8817e4Smiod ret |= (insn & 0x1f);
244*3d8817e4Smiod
245*3d8817e4Smiod return ret;
246*3d8817e4Smiod }
247*3d8817e4Smiod
248*3d8817e4Smiod static unsigned long
insert_u9(unsigned long insn,long v,const char ** errmsg)249*3d8817e4Smiod insert_u9 (unsigned long insn, long v, const char ** errmsg)
250*3d8817e4Smiod {
251*3d8817e4Smiod unsigned long value = (unsigned long) v;
252*3d8817e4Smiod
253*3d8817e4Smiod if (value > 0x1ff)
254*3d8817e4Smiod * errmsg = _(immediate_out_of_range);
255*3d8817e4Smiod
256*3d8817e4Smiod return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
257*3d8817e4Smiod }
258*3d8817e4Smiod
259*3d8817e4Smiod static unsigned long
extract_u9(unsigned long insn,int * invalid ATTRIBUTE_UNUSED)260*3d8817e4Smiod extract_u9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
261*3d8817e4Smiod {
262*3d8817e4Smiod unsigned long ret = insn & 0x003c0000;
263*3d8817e4Smiod
264*3d8817e4Smiod ret >>= 13;
265*3d8817e4Smiod
266*3d8817e4Smiod ret |= (insn & 0x1f);
267*3d8817e4Smiod
268*3d8817e4Smiod return ret;
269*3d8817e4Smiod }
270*3d8817e4Smiod
271*3d8817e4Smiod static unsigned long
insert_spe(unsigned long insn,long v,const char ** errmsg)272*3d8817e4Smiod insert_spe (unsigned long insn, long v, const char ** errmsg)
273*3d8817e4Smiod {
274*3d8817e4Smiod unsigned long value = (unsigned long) v;
275*3d8817e4Smiod
276*3d8817e4Smiod if (value != 3)
277*3d8817e4Smiod * errmsg = _("invalid register for stack adjustment");
278*3d8817e4Smiod
279*3d8817e4Smiod return insn & (~ 0x180000);
280*3d8817e4Smiod }
281*3d8817e4Smiod
282*3d8817e4Smiod static unsigned long
extract_spe(unsigned long insn ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)283*3d8817e4Smiod extract_spe (unsigned long insn ATTRIBUTE_UNUSED,
284*3d8817e4Smiod int * invalid ATTRIBUTE_UNUSED)
285*3d8817e4Smiod {
286*3d8817e4Smiod return 3;
287*3d8817e4Smiod }
288*3d8817e4Smiod
289*3d8817e4Smiod static unsigned long
insert_i5div(unsigned long insn,long v,const char ** errmsg)290*3d8817e4Smiod insert_i5div (unsigned long insn, long v, const char ** errmsg)
291*3d8817e4Smiod {
292*3d8817e4Smiod unsigned long value = (unsigned long) v;
293*3d8817e4Smiod
294*3d8817e4Smiod if (value > 0x1ff)
295*3d8817e4Smiod {
296*3d8817e4Smiod if (value & 1)
297*3d8817e4Smiod * errmsg = _("immediate value not in range and not even");
298*3d8817e4Smiod else
299*3d8817e4Smiod * errmsg = _(immediate_out_of_range);
300*3d8817e4Smiod }
301*3d8817e4Smiod else if (value & 1)
302*3d8817e4Smiod * errmsg = _("immediate value must be even");
303*3d8817e4Smiod
304*3d8817e4Smiod value = 32 - value;
305*3d8817e4Smiod
306*3d8817e4Smiod return insn | ((value & 0x1e) << 17);
307*3d8817e4Smiod }
308*3d8817e4Smiod
309*3d8817e4Smiod static unsigned long
extract_i5div(unsigned long insn,int * invalid ATTRIBUTE_UNUSED)310*3d8817e4Smiod extract_i5div (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
311*3d8817e4Smiod {
312*3d8817e4Smiod unsigned long ret = insn & 0x3c0000;
313*3d8817e4Smiod
314*3d8817e4Smiod ret >>= 17;
315*3d8817e4Smiod
316*3d8817e4Smiod ret = 32 - ret;
317*3d8817e4Smiod
318*3d8817e4Smiod return ret;
319*3d8817e4Smiod }
320*3d8817e4Smiod
321*3d8817e4Smiod
322*3d8817e4Smiod /* Warning: code in gas/config/tc-v850.c examines the contents of this array.
323*3d8817e4Smiod If you change any of the values here, be sure to look for side effects in
324*3d8817e4Smiod that code. */
325*3d8817e4Smiod const struct v850_operand v850_operands[] =
326*3d8817e4Smiod {
327*3d8817e4Smiod #define UNUSED 0
328*3d8817e4Smiod { 0, 0, NULL, NULL, 0 },
329*3d8817e4Smiod
330*3d8817e4Smiod /* The R1 field in a format 1, 6, 7, or 9 insn. */
331*3d8817e4Smiod #define R1 (UNUSED + 1)
332*3d8817e4Smiod { 5, 0, NULL, NULL, V850_OPERAND_REG },
333*3d8817e4Smiod
334*3d8817e4Smiod /* As above, but register 0 is not allowed. */
335*3d8817e4Smiod #define R1_NOTR0 (R1 + 1)
336*3d8817e4Smiod { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
337*3d8817e4Smiod
338*3d8817e4Smiod /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
339*3d8817e4Smiod #define R2 (R1_NOTR0 + 1)
340*3d8817e4Smiod { 5, 11, NULL, NULL, V850_OPERAND_REG },
341*3d8817e4Smiod
342*3d8817e4Smiod /* As above, but register 0 is not allowed. */
343*3d8817e4Smiod #define R2_NOTR0 (R2 + 1)
344*3d8817e4Smiod { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
345*3d8817e4Smiod
346*3d8817e4Smiod /* The imm5 field in a format 2 insn. */
347*3d8817e4Smiod #define I5 (R2_NOTR0 + 1)
348*3d8817e4Smiod { 5, 0, NULL, NULL, V850_OPERAND_SIGNED },
349*3d8817e4Smiod
350*3d8817e4Smiod /* The unsigned imm5 field in a format 2 insn. */
351*3d8817e4Smiod #define I5U (I5 + 1)
352*3d8817e4Smiod { 5, 0, NULL, NULL, 0 },
353*3d8817e4Smiod
354*3d8817e4Smiod /* The imm16 field in a format 6 insn. */
355*3d8817e4Smiod #define I16 (I5U + 1)
356*3d8817e4Smiod { 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
357*3d8817e4Smiod
358*3d8817e4Smiod /* The signed disp7 field in a format 4 insn. */
359*3d8817e4Smiod #define D7 (I16 + 1)
360*3d8817e4Smiod { 7, 0, NULL, NULL, 0},
361*3d8817e4Smiod
362*3d8817e4Smiod /* The disp16 field in a format 6 insn. */
363*3d8817e4Smiod #define D16_15 (D7 + 1)
364*3d8817e4Smiod { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
365*3d8817e4Smiod
366*3d8817e4Smiod /* The 3 bit immediate field in format 8 insn. */
367*3d8817e4Smiod #define B3 (D16_15 + 1)
368*3d8817e4Smiod { 3, 11, NULL, NULL, 0 },
369*3d8817e4Smiod
370*3d8817e4Smiod /* The 4 bit condition code in a setf instruction */
371*3d8817e4Smiod #define CCCC (B3 + 1)
372*3d8817e4Smiod { 4, 0, NULL, NULL, V850_OPERAND_CC },
373*3d8817e4Smiod
374*3d8817e4Smiod /* The unsigned DISP8 field in a format 4 insn. */
375*3d8817e4Smiod #define D8_7 (CCCC + 1)
376*3d8817e4Smiod { 7, 0, insert_d8_7, extract_d8_7, 0 },
377*3d8817e4Smiod
378*3d8817e4Smiod /* The unsigned DISP8 field in a format 4 insn. */
379*3d8817e4Smiod #define D8_6 (D8_7 + 1)
380*3d8817e4Smiod { 6, 1, insert_d8_6, extract_d8_6, 0 },
381*3d8817e4Smiod
382*3d8817e4Smiod /* System register operands. */
383*3d8817e4Smiod #define SR1 (D8_6 + 1)
384*3d8817e4Smiod { 5, 0, NULL, NULL, V850_OPERAND_SRG },
385*3d8817e4Smiod
386*3d8817e4Smiod /* EP Register. */
387*3d8817e4Smiod #define EP (SR1 + 1)
388*3d8817e4Smiod { 0, 0, NULL, NULL, V850_OPERAND_EP },
389*3d8817e4Smiod
390*3d8817e4Smiod /* The imm16 field (unsigned) in a format 6 insn. */
391*3d8817e4Smiod #define I16U (EP + 1)
392*3d8817e4Smiod { 16, 16, NULL, NULL, 0},
393*3d8817e4Smiod
394*3d8817e4Smiod /* The R2 field as a system register. */
395*3d8817e4Smiod #define SR2 (I16U + 1)
396*3d8817e4Smiod { 5, 11, NULL, NULL, V850_OPERAND_SRG },
397*3d8817e4Smiod
398*3d8817e4Smiod /* The disp16 field in a format 8 insn. */
399*3d8817e4Smiod #define D16 (SR2 + 1)
400*3d8817e4Smiod { 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
401*3d8817e4Smiod
402*3d8817e4Smiod /* The DISP9 field in a format 3 insn, relaxable. */
403*3d8817e4Smiod #define D9_RELAX (D16 + 1)
404*3d8817e4Smiod { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP },
405*3d8817e4Smiod
406*3d8817e4Smiod /* The DISP22 field in a format 4 insn, relaxable.
407*3d8817e4Smiod This _must_ follow D9_RELAX; the assembler assumes that the longer
408*3d8817e4Smiod version immediately follows the shorter version for relaxing. */
409*3d8817e4Smiod #define D22 (D9_RELAX + 1)
410*3d8817e4Smiod { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
411*3d8817e4Smiod
412*3d8817e4Smiod /* The signed disp4 field in a format 4 insn. */
413*3d8817e4Smiod #define D4 (D22 + 1)
414*3d8817e4Smiod { 4, 0, NULL, NULL, 0},
415*3d8817e4Smiod
416*3d8817e4Smiod /* The unsigned disp5 field in a format 4 insn. */
417*3d8817e4Smiod #define D5_4 (D4 + 1)
418*3d8817e4Smiod { 4, 0, insert_d5_4, extract_d5_4, 0 },
419*3d8817e4Smiod
420*3d8817e4Smiod /* The disp16 field in an format 7 unsigned byte load insn. */
421*3d8817e4Smiod #define D16_16 (D5_4 + 1)
422*3d8817e4Smiod { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 },
423*3d8817e4Smiod
424*3d8817e4Smiod /* Third register in conditional moves. */
425*3d8817e4Smiod #define R3 (D16_16 + 1)
426*3d8817e4Smiod { 5, 27, NULL, NULL, V850_OPERAND_REG },
427*3d8817e4Smiod
428*3d8817e4Smiod /* Condition code in conditional moves. */
429*3d8817e4Smiod #define MOVCC (R3 + 1)
430*3d8817e4Smiod { 4, 17, NULL, NULL, V850_OPERAND_CC },
431*3d8817e4Smiod
432*3d8817e4Smiod /* The imm9 field in a multiply word. */
433*3d8817e4Smiod #define I9 (MOVCC + 1)
434*3d8817e4Smiod { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED },
435*3d8817e4Smiod
436*3d8817e4Smiod /* The unsigned imm9 field in a multiply word. */
437*3d8817e4Smiod #define U9 (I9 + 1)
438*3d8817e4Smiod { 9, 0, insert_u9, extract_u9, 0 },
439*3d8817e4Smiod
440*3d8817e4Smiod /* A list of registers in a prepare/dispose instruction. */
441*3d8817e4Smiod #define LIST12 (U9 + 1)
442*3d8817e4Smiod { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP },
443*3d8817e4Smiod
444*3d8817e4Smiod /* The IMM6 field in a call instruction. */
445*3d8817e4Smiod #define I6 (LIST12 + 1)
446*3d8817e4Smiod { 6, 0, NULL, NULL, 0 },
447*3d8817e4Smiod
448*3d8817e4Smiod /* The 16 bit immediate following a 32 bit instruction. */
449*3d8817e4Smiod #define IMM16 (I6 + 1)
450*3d8817e4Smiod { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 },
451*3d8817e4Smiod
452*3d8817e4Smiod /* The 32 bit immediate following a 32 bit instruction. */
453*3d8817e4Smiod #define IMM32 (IMM16 + 1)
454*3d8817e4Smiod { 0, 0, NULL, NULL, V850E_IMMEDIATE32 },
455*3d8817e4Smiod
456*3d8817e4Smiod /* The imm5 field in a push/pop instruction. */
457*3d8817e4Smiod #define IMM5 (IMM32 + 1)
458*3d8817e4Smiod { 5, 1, NULL, NULL, 0 },
459*3d8817e4Smiod
460*3d8817e4Smiod /* Reg2 in dispose instruction. */
461*3d8817e4Smiod #define R2DISPOSE (IMM5 + 1)
462*3d8817e4Smiod { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
463*3d8817e4Smiod
464*3d8817e4Smiod /* Stack pointer in prepare instruction. */
465*3d8817e4Smiod #define SP (R2DISPOSE + 1)
466*3d8817e4Smiod { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG },
467*3d8817e4Smiod
468*3d8817e4Smiod /* The IMM5 field in a divide N step instruction. */
469*3d8817e4Smiod #define I5DIV (SP + 1)
470*3d8817e4Smiod { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED },
471*3d8817e4Smiod
472*3d8817e4Smiod /* The list of registers in a PUSHMH/POPMH instruction. */
473*3d8817e4Smiod #define LIST18_H (I5DIV + 1)
474*3d8817e4Smiod { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP },
475*3d8817e4Smiod
476*3d8817e4Smiod /* The list of registers in a PUSHML/POPML instruction. */
477*3d8817e4Smiod #define LIST18_L (LIST18_H + 1)
478*3d8817e4Smiod /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c. */
479*3d8817e4Smiod { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP },
480*3d8817e4Smiod };
481*3d8817e4Smiod
482*3d8817e4Smiod
483*3d8817e4Smiod /* Reg - Reg instruction format (Format I). */
484*3d8817e4Smiod #define IF1 {R1, R2}
485*3d8817e4Smiod
486*3d8817e4Smiod /* Imm - Reg instruction format (Format II). */
487*3d8817e4Smiod #define IF2 {I5, R2}
488*3d8817e4Smiod
489*3d8817e4Smiod /* Conditional branch instruction format (Format III). */
490*3d8817e4Smiod #define IF3 {D9_RELAX}
491*3d8817e4Smiod
492*3d8817e4Smiod /* 3 operand instruction (Format VI). */
493*3d8817e4Smiod #define IF6 {I16, R1, R2}
494*3d8817e4Smiod
495*3d8817e4Smiod /* 3 operand instruction (Format VI). */
496*3d8817e4Smiod #define IF6U {I16U, R1, R2}
497*3d8817e4Smiod
498*3d8817e4Smiod
499*3d8817e4Smiod
500*3d8817e4Smiod /* The opcode table.
501*3d8817e4Smiod
502*3d8817e4Smiod The format of the opcode table is:
503*3d8817e4Smiod
504*3d8817e4Smiod NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR
505*3d8817e4Smiod
506*3d8817e4Smiod NAME is the name of the instruction.
507*3d8817e4Smiod OPCODE is the instruction opcode.
508*3d8817e4Smiod MASK is the opcode mask; this is used to tell the disassembler
509*3d8817e4Smiod which bits in the actual opcode must match OPCODE.
510*3d8817e4Smiod OPERANDS is the list of operands.
511*3d8817e4Smiod MEMOP specifies which operand (if any) is a memory operand.
512*3d8817e4Smiod PROCESSORS specifies which CPU(s) support the opcode.
513*3d8817e4Smiod
514*3d8817e4Smiod The disassembler reads the table in order and prints the first
515*3d8817e4Smiod instruction which matches, so this table is sorted to put more
516*3d8817e4Smiod specific instructions before more general instructions. It is also
517*3d8817e4Smiod sorted by major opcode.
518*3d8817e4Smiod
519*3d8817e4Smiod The table is also sorted by name. This is used by the assembler.
520*3d8817e4Smiod When parsing an instruction the assembler finds the first occurance
521*3d8817e4Smiod of the name of the instruciton in this table and then attempts to
522*3d8817e4Smiod match the instruction's arguments with description of the operands
523*3d8817e4Smiod associated with the entry it has just found in this table. If the
524*3d8817e4Smiod match fails the assembler looks at the next entry in this table.
525*3d8817e4Smiod If that entry has the same name as the previous entry, then it
526*3d8817e4Smiod tries to match the instruction against that entry and so on. This
527*3d8817e4Smiod is how the assembler copes with multiple, different formats of the
528*3d8817e4Smiod same instruction. */
529*3d8817e4Smiod
530*3d8817e4Smiod const struct v850_opcode v850_opcodes[] =
531*3d8817e4Smiod {
532*3d8817e4Smiod { "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL },
533*3d8817e4Smiod { "dbtrap", one (0xf840), one (0xffff), {UNUSED}, 0, PROCESSOR_V850E1 },
534*3d8817e4Smiod
535*3d8817e4Smiod { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL },
536*3d8817e4Smiod
537*3d8817e4Smiod /* Load/store instructions. */
538*3d8817e4Smiod { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 },
539*3d8817e4Smiod { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E },
540*3d8817e4Smiod
541*3d8817e4Smiod { "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 },
542*3d8817e4Smiod { "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E },
543*3d8817e4Smiod
544*3d8817e4Smiod { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E1 },
545*3d8817e4Smiod { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E },
546*3d8817e4Smiod { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 },
547*3d8817e4Smiod
548*3d8817e4Smiod { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E1 },
549*3d8817e4Smiod { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E },
550*3d8817e4Smiod { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 },
551*3d8817e4Smiod { "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL },
552*3d8817e4Smiod { "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2, PROCESSOR_ALL },
553*3d8817e4Smiod { "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2, PROCESSOR_ALL },
554*3d8817e4Smiod { "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2, PROCESSOR_ALL },
555*3d8817e4Smiod
556*3d8817e4Smiod { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 },
557*3d8817e4Smiod { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 },
558*3d8817e4Smiod { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 },
559*3d8817e4Smiod { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 },
560*3d8817e4Smiod { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 },
561*3d8817e4Smiod { "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0, PROCESSOR_NOT_V850 },
562*3d8817e4Smiod { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 },
563*3d8817e4Smiod
564*3d8817e4Smiod { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1, PROCESSOR_ALL },
565*3d8817e4Smiod { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL },
566*3d8817e4Smiod { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL },
567*3d8817e4Smiod { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 },
568*3d8817e4Smiod { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 },
569*3d8817e4Smiod { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL },
570*3d8817e4Smiod { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL },
571*3d8817e4Smiod { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL },
572*3d8817e4Smiod
573*3d8817e4Smiod /* Byte swap/extend instructions. */
574*3d8817e4Smiod { "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
575*3d8817e4Smiod { "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
576*3d8817e4Smiod { "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
577*3d8817e4Smiod { "sxh", one (0x00e0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
578*3d8817e4Smiod { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
579*3d8817e4Smiod { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
580*3d8817e4Smiod { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
581*3d8817e4Smiod
582*3d8817e4Smiod /* Jump table instructions. */
583*3d8817e4Smiod { "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 },
584*3d8817e4Smiod { "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 },
585*3d8817e4Smiod { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 },
586*3d8817e4Smiod
587*3d8817e4Smiod /* Arithmetic operation instructions. */
588*3d8817e4Smiod { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL },
589*3d8817e4Smiod { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
590*3d8817e4Smiod { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 },
591*3d8817e4Smiod
592*3d8817e4Smiod { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
593*3d8817e4Smiod { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 },
594*3d8817e4Smiod { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
595*3d8817e4Smiod { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 },
596*3d8817e4Smiod
597*3d8817e4Smiod { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
598*3d8817e4Smiod { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
599*3d8817e4Smiod { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
600*3d8817e4Smiod { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
601*3d8817e4Smiod { "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
602*3d8817e4Smiod
603*3d8817e4Smiod { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL },
604*3d8817e4Smiod { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
605*3d8817e4Smiod { "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
606*3d8817e4Smiod { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
607*3d8817e4Smiod { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
608*3d8817e4Smiod { "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
609*3d8817e4Smiod { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL },
610*3d8817e4Smiod { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL },
611*3d8817e4Smiod { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL },
612*3d8817e4Smiod { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL },
613*3d8817e4Smiod { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL },
614*3d8817e4Smiod { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
615*3d8817e4Smiod { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
616*3d8817e4Smiod { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
617*3d8817e4Smiod { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL },
618*3d8817e4Smiod { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL },
619*3d8817e4Smiod
620*3d8817e4Smiod /* Saturated operation instructions. */
621*3d8817e4Smiod { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
622*3d8817e4Smiod { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
623*3d8817e4Smiod { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
624*3d8817e4Smiod { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
625*3d8817e4Smiod { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
626*3d8817e4Smiod
627*3d8817e4Smiod /* Logical operation instructions. */
628*3d8817e4Smiod { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL },
629*3d8817e4Smiod { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL },
630*3d8817e4Smiod { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL },
631*3d8817e4Smiod { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL },
632*3d8817e4Smiod { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL },
633*3d8817e4Smiod { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL },
634*3d8817e4Smiod { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL },
635*3d8817e4Smiod { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL },
636*3d8817e4Smiod { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
637*3d8817e4Smiod { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
638*3d8817e4Smiod { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
639*3d8817e4Smiod { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
640*3d8817e4Smiod { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
641*3d8817e4Smiod { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
642*3d8817e4Smiod { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 },
643*3d8817e4Smiod
644*3d8817e4Smiod /* Branch instructions. */
645*3d8817e4Smiod /* Signed integer. */
646*3d8817e4Smiod { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
647*3d8817e4Smiod { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
648*3d8817e4Smiod { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
649*3d8817e4Smiod { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
650*3d8817e4Smiod /* Unsigned integer. */
651*3d8817e4Smiod { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
652*3d8817e4Smiod { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
653*3d8817e4Smiod { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
654*3d8817e4Smiod { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
655*3d8817e4Smiod /* Common. */
656*3d8817e4Smiod { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
657*3d8817e4Smiod { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
658*3d8817e4Smiod /* Others. */
659*3d8817e4Smiod { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
660*3d8817e4Smiod { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
661*3d8817e4Smiod { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
662*3d8817e4Smiod { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
663*3d8817e4Smiod { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
664*3d8817e4Smiod { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
665*3d8817e4Smiod { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
666*3d8817e4Smiod { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
667*3d8817e4Smiod { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
668*3d8817e4Smiod { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL },
669*3d8817e4Smiod
670*3d8817e4Smiod /* Branch macros.
671*3d8817e4Smiod
672*3d8817e4Smiod We use the short form in the opcode/mask fields. The assembler
673*3d8817e4Smiod will twiddle bits as necessary if the long form is needed. */
674*3d8817e4Smiod
675*3d8817e4Smiod /* Signed integer. */
676*3d8817e4Smiod { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
677*3d8817e4Smiod { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
678*3d8817e4Smiod { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
679*3d8817e4Smiod { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
680*3d8817e4Smiod /* Unsigned integer. */
681*3d8817e4Smiod { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
682*3d8817e4Smiod { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
683*3d8817e4Smiod { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
684*3d8817e4Smiod { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
685*3d8817e4Smiod /* Common. */
686*3d8817e4Smiod { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
687*3d8817e4Smiod { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
688*3d8817e4Smiod /* Others. */
689*3d8817e4Smiod { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
690*3d8817e4Smiod { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
691*3d8817e4Smiod { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
692*3d8817e4Smiod { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
693*3d8817e4Smiod { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
694*3d8817e4Smiod { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
695*3d8817e4Smiod { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
696*3d8817e4Smiod { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
697*3d8817e4Smiod { "jsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL },
698*3d8817e4Smiod { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
699*3d8817e4Smiod
700*3d8817e4Smiod { "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL },
701*3d8817e4Smiod { "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL },
702*3d8817e4Smiod
703*3d8817e4Smiod /* Bit manipulation instructions. */
704*3d8817e4Smiod { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
705*3d8817e4Smiod { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 },
706*3d8817e4Smiod { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
707*3d8817e4Smiod { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 },
708*3d8817e4Smiod { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
709*3d8817e4Smiod { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 },
710*3d8817e4Smiod { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
711*3d8817e4Smiod { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 },
712*3d8817e4Smiod
713*3d8817e4Smiod /* Special instructions. */
714*3d8817e4Smiod { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
715*3d8817e4Smiod { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
716*3d8817e4Smiod { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
717*3d8817e4Smiod { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
718*3d8817e4Smiod { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL },
719*3d8817e4Smiod { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL },
720*3d8817e4Smiod { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL },
721*3d8817e4Smiod { "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {UNUSED}, 0, PROCESSOR_V850E1 },
722*3d8817e4Smiod { 0, 0, 0, {0}, 0, 0 },
723*3d8817e4Smiod
724*3d8817e4Smiod } ;
725*3d8817e4Smiod
726*3d8817e4Smiod const int v850_num_opcodes =
727*3d8817e4Smiod sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
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