1 /* tc-mips.c -- assemble code for a MIPS chip. 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 3 2003, 2004 Free Software Foundation, Inc. 4 Contributed by the OSF and Ralph Campbell. 5 Written by Keith Knowles and Ralph Campbell, working independently. 6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus 7 Support. 8 9 This file is part of GAS. 10 11 GAS is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 2, or (at your option) 14 any later version. 15 16 GAS is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with GAS; see the file COPYING. If not, write to the Free 23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 24 02111-1307, USA. */ 25 26 #include "as.h" 27 #include "config.h" 28 #include "subsegs.h" 29 #include "safe-ctype.h" 30 31 #include <stdarg.h> 32 33 #include "opcode/mips.h" 34 #include "itbl-ops.h" 35 #include "dwarf2dbg.h" 36 #include "dw2gencfi.h" 37 38 #ifdef DEBUG 39 #define DBG(x) printf x 40 #else 41 #define DBG(x) 42 #endif 43 44 #ifdef OBJ_MAYBE_ELF 45 /* Clean up namespace so we can include obj-elf.h too. */ 46 static int mips_output_flavor (void); 47 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } 48 #undef OBJ_PROCESS_STAB 49 #undef OUTPUT_FLAVOR 50 #undef S_GET_ALIGN 51 #undef S_GET_SIZE 52 #undef S_SET_ALIGN 53 #undef S_SET_SIZE 54 #undef obj_frob_file 55 #undef obj_frob_file_after_relocs 56 #undef obj_frob_symbol 57 #undef obj_pop_insert 58 #undef obj_sec_sym_ok_for_reloc 59 #undef OBJ_COPY_SYMBOL_ATTRIBUTES 60 61 #include "obj-elf.h" 62 /* Fix any of them that we actually care about. */ 63 #undef OUTPUT_FLAVOR 64 #define OUTPUT_FLAVOR mips_output_flavor() 65 #endif 66 67 #if defined (OBJ_ELF) 68 #include "elf/mips.h" 69 #endif 70 71 #ifndef ECOFF_DEBUGGING 72 #define NO_ECOFF_DEBUGGING 73 #define ECOFF_DEBUGGING 0 74 #endif 75 76 int mips_flag_mdebug = -1; 77 78 /* Control generation of .pdr sections. Off by default on IRIX: the native 79 linker doesn't know about and discards them, but relocations against them 80 remain, leading to rld crashes. */ 81 #ifdef TE_IRIX 82 int mips_flag_pdr = FALSE; 83 #else 84 int mips_flag_pdr = TRUE; 85 #endif 86 87 #include "ecoff.h" 88 89 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 90 static char *mips_regmask_frag; 91 #endif 92 93 #define ZERO 0 94 #define AT 1 95 #define TREG 24 96 #define PIC_CALL_REG 25 97 #define KT0 26 98 #define KT1 27 99 #define GP 28 100 #define SP 29 101 #define FP 30 102 #define RA 31 103 104 #define ILLEGAL_REG (32) 105 106 /* Allow override of standard little-endian ECOFF format. */ 107 108 #ifndef ECOFF_LITTLE_FORMAT 109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" 110 #endif 111 112 extern int target_big_endian; 113 114 /* The name of the readonly data section. */ 115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ 116 ? ".data" \ 117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ 118 ? ".rdata" \ 119 : OUTPUT_FLAVOR == bfd_target_coff_flavour \ 120 ? ".rdata" \ 121 : OUTPUT_FLAVOR == bfd_target_elf_flavour \ 122 ? ".rodata" \ 123 : (abort (), "")) 124 125 /* The ABI to use. */ 126 enum mips_abi_level 127 { 128 NO_ABI = 0, 129 O32_ABI, 130 O64_ABI, 131 N32_ABI, 132 N64_ABI, 133 EABI_ABI 134 }; 135 136 /* MIPS ABI we are using for this output file. */ 137 static enum mips_abi_level mips_abi = NO_ABI; 138 139 /* Whether or not we have code that can call pic code. */ 140 int mips_abicalls = FALSE; 141 142 /* This is the set of options which may be modified by the .set 143 pseudo-op. We use a struct so that .set push and .set pop are more 144 reliable. */ 145 146 struct mips_set_options 147 { 148 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 149 if it has not been initialized. Changed by `.set mipsN', and the 150 -mipsN command line option, and the default CPU. */ 151 int isa; 152 /* Enabled Application Specific Extensions (ASEs). These are set to -1 153 if they have not been initialized. Changed by `.set <asename>', by 154 command line options, and based on the default architecture. */ 155 int ase_mips3d; 156 int ase_mdmx; 157 /* Whether we are assembling for the mips16 processor. 0 if we are 158 not, 1 if we are, and -1 if the value has not been initialized. 159 Changed by `.set mips16' and `.set nomips16', and the -mips16 and 160 -nomips16 command line options, and the default CPU. */ 161 int mips16; 162 /* Non-zero if we should not reorder instructions. Changed by `.set 163 reorder' and `.set noreorder'. */ 164 int noreorder; 165 /* Non-zero if we should not permit the $at ($1) register to be used 166 in instructions. Changed by `.set at' and `.set noat'. */ 167 int noat; 168 /* Non-zero if we should warn when a macro instruction expands into 169 more than one machine instruction. Changed by `.set nomacro' and 170 `.set macro'. */ 171 int warn_about_macros; 172 /* Non-zero if we should not move instructions. Changed by `.set 173 move', `.set volatile', `.set nomove', and `.set novolatile'. */ 174 int nomove; 175 /* Non-zero if we should not optimize branches by moving the target 176 of the branch into the delay slot. Actually, we don't perform 177 this optimization anyhow. Changed by `.set bopt' and `.set 178 nobopt'. */ 179 int nobopt; 180 /* Non-zero if we should not autoextend mips16 instructions. 181 Changed by `.set autoextend' and `.set noautoextend'. */ 182 int noautoextend; 183 /* Restrict general purpose registers and floating point registers 184 to 32 bit. This is initially determined when -mgp32 or -mfp32 185 is passed but can changed if the assembler code uses .set mipsN. */ 186 int gp32; 187 int fp32; 188 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march 189 command line option, and the default CPU. */ 190 int arch; 191 }; 192 193 /* True if -mgp32 was passed. */ 194 static int file_mips_gp32 = -1; 195 196 /* True if -mfp32 was passed. */ 197 static int file_mips_fp32 = -1; 198 199 /* This is the struct we use to hold the current set of options. Note 200 that we must set the isa field to ISA_UNKNOWN and the ASE fields to 201 -1 to indicate that they have not been initialized. */ 202 203 static struct mips_set_options mips_opts = 204 { 205 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN 206 }; 207 208 /* These variables are filled in with the masks of registers used. 209 The object format code reads them and puts them in the appropriate 210 place. */ 211 unsigned long mips_gprmask; 212 unsigned long mips_cprmask[4]; 213 214 /* MIPS ISA we are using for this output file. */ 215 static int file_mips_isa = ISA_UNKNOWN; 216 217 /* True if -mips16 was passed or implied by arguments passed on the 218 command line (e.g., by -march). */ 219 static int file_ase_mips16; 220 221 /* True if -mips3d was passed or implied by arguments passed on the 222 command line (e.g., by -march). */ 223 static int file_ase_mips3d; 224 225 /* True if -mdmx was passed or implied by arguments passed on the 226 command line (e.g., by -march). */ 227 static int file_ase_mdmx; 228 229 /* The argument of the -march= flag. The architecture we are assembling. */ 230 static int file_mips_arch = CPU_UNKNOWN; 231 static const char *mips_arch_string; 232 233 /* The argument of the -mtune= flag. The architecture for which we 234 are optimizing. */ 235 static int mips_tune = CPU_UNKNOWN; 236 static const char *mips_tune_string; 237 238 /* True when generating 32-bit code for a 64-bit processor. */ 239 static int mips_32bitmode = 0; 240 241 /* True if the given ABI requires 32-bit registers. */ 242 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) 243 244 /* Likewise 64-bit registers. */ 245 #define ABI_NEEDS_64BIT_REGS(ABI) \ 246 ((ABI) == N32_ABI \ 247 || (ABI) == N64_ABI \ 248 || (ABI) == O64_ABI) 249 250 /* Return true if ISA supports 64 bit gp register instructions. */ 251 #define ISA_HAS_64BIT_REGS(ISA) ( \ 252 (ISA) == ISA_MIPS3 \ 253 || (ISA) == ISA_MIPS4 \ 254 || (ISA) == ISA_MIPS5 \ 255 || (ISA) == ISA_MIPS64 \ 256 || (ISA) == ISA_MIPS64R2 \ 257 ) 258 259 /* Return true if ISA supports 64 bit wide float registers. */ 260 #define ISA_HAS_64BIT_FPRS(ISA) ( \ 261 (ISA) == ISA_MIPS3 \ 262 || (ISA) == ISA_MIPS4 \ 263 || (ISA) == ISA_MIPS5 \ 264 || (ISA) == ISA_MIPS32R2 \ 265 || (ISA) == ISA_MIPS64 \ 266 || (ISA) == ISA_MIPS64R2) 267 268 /* Return true if ISA supports 64-bit right rotate (dror et al.) 269 instructions. */ 270 #define ISA_HAS_DROR(ISA) ( \ 271 (ISA) == ISA_MIPS64R2 \ 272 ) 273 274 /* Return true if ISA supports 32-bit right rotate (ror et al.) 275 instructions. */ 276 #define ISA_HAS_ROR(ISA) ( \ 277 (ISA) == ISA_MIPS32R2 \ 278 || (ISA) == ISA_MIPS64R2 \ 279 ) 280 281 /* Return true if ISA supports single-precision floats in odd registers. */ 282 #define ISA_HAS_ODD_SINGLE_FPR(ISA) ( \ 283 (ISA) == ISA_MIPS32 \ 284 || (ISA) == ISA_MIPS32R2 \ 285 || (ISA) == ISA_MIPS64 \ 286 || (ISA) == ISA_MIPS64R2) 287 288 /* Return true if ISA supports move to/from high part of a 64-bit 289 floating register. */ 290 #define ISA_HAS_MXHC1(ISA) ( \ 291 (ISA) == ISA_MIPS32R2 \ 292 || (ISA) == ISA_MIPS64R2) 293 294 #define HAVE_32BIT_GPRS \ 295 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) 296 297 #define HAVE_32BIT_FPRS \ 298 (mips_opts.fp32 || ! ISA_HAS_64BIT_FPRS (mips_opts.isa)) 299 300 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) 301 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) 302 303 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) 304 305 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) 306 307 /* True if relocations are stored in-place. */ 308 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) 309 310 /* We can only have 64bit addresses if the object file format 311 supports it. */ 312 #define HAVE_32BIT_ADDRESSES \ 313 (HAVE_32BIT_GPRS \ 314 || ((bfd_arch_bits_per_address (stdoutput) == 32 \ 315 || ! HAVE_64BIT_OBJECTS) \ 316 && mips_pic != EMBEDDED_PIC)) 317 318 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) 319 320 /* The size of symbolic constants (i.e., expressions of the form 321 "SYMBOL" or "SYMBOL + OFFSET"). */ 322 #define HAVE_32BIT_SYMBOLS \ 323 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) 324 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) 325 326 /* Addresses are loaded in different ways, depending on the address size 327 in use. The n32 ABI Documentation also mandates the use of additions 328 with overflow checking, but existing implementations don't follow it. */ 329 #define ADDRESS_ADD_INSN \ 330 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") 331 332 #define ADDRESS_ADDI_INSN \ 333 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") 334 335 #define ADDRESS_LOAD_INSN \ 336 (HAVE_32BIT_ADDRESSES ? "lw" : "ld") 337 338 #define ADDRESS_STORE_INSN \ 339 (HAVE_32BIT_ADDRESSES ? "sw" : "sd") 340 341 /* Return true if the given CPU supports the MIPS16 ASE. */ 342 #define CPU_HAS_MIPS16(cpu) \ 343 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ 344 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) 345 346 /* Return true if the given CPU supports the MIPS3D ASE. */ 347 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ 348 ) 349 350 /* Return true if the given CPU supports the MDMX ASE. */ 351 #define CPU_HAS_MDMX(cpu) (FALSE \ 352 ) 353 354 /* True if CPU has a dror instruction. */ 355 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) 356 357 /* True if CPU has a ror instruction. */ 358 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) 359 360 /* True if mflo and mfhi can be immediately followed by instructions 361 which write to the HI and LO registers. 362 363 According to MIPS specifications, MIPS ISAs I, II, and III need 364 (at least) two instructions between the reads of HI/LO and 365 instructions which write them, and later ISAs do not. Contradicting 366 the MIPS specifications, some MIPS IV processor user manuals (e.g. 367 the UM for the NEC Vr5000) document needing the instructions between 368 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 369 MIPS64 and later ISAs to have the interlocks, plus any specific 370 earlier-ISA CPUs for which CPU documentation declares that the 371 instructions are really interlocked. */ 372 #define hilo_interlocks \ 373 (mips_opts.isa == ISA_MIPS32 \ 374 || mips_opts.isa == ISA_MIPS32R2 \ 375 || mips_opts.isa == ISA_MIPS64 \ 376 || mips_opts.isa == ISA_MIPS64R2 \ 377 || mips_opts.arch == CPU_R4010 \ 378 || mips_opts.arch == CPU_R10000 \ 379 || mips_opts.arch == CPU_R12000 \ 380 || mips_opts.arch == CPU_RM7000 \ 381 || mips_opts.arch == CPU_SB1 \ 382 || mips_opts.arch == CPU_VR5500 \ 383 ) 384 385 /* Whether the processor uses hardware interlocks to protect reads 386 from the GPRs after they are loaded from memory, and thus does not 387 require nops to be inserted. This applies to instructions marked 388 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA 389 level I. */ 390 #define gpr_interlocks \ 391 (mips_opts.isa != ISA_MIPS1 \ 392 || mips_opts.arch == CPU_VR5400 \ 393 || mips_opts.arch == CPU_VR5500 \ 394 || mips_opts.arch == CPU_R3900) 395 396 /* Whether the processor uses hardware interlocks to avoid delays 397 required by coprocessor instructions, and thus does not require 398 nops to be inserted. This applies to instructions marked 399 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays 400 between instructions marked INSN_WRITE_COND_CODE and ones marked 401 INSN_READ_COND_CODE. These nops are only required at MIPS ISA 402 levels I, II, and III. */ 403 /* Itbl support may require additional care here. */ 404 #define cop_interlocks \ 405 ((mips_opts.isa != ISA_MIPS1 \ 406 && mips_opts.isa != ISA_MIPS2 \ 407 && mips_opts.isa != ISA_MIPS3) \ 408 || mips_opts.arch == CPU_R4300 \ 409 || mips_opts.arch == CPU_VR5400 \ 410 || mips_opts.arch == CPU_VR5500 \ 411 || mips_opts.arch == CPU_SB1 \ 412 ) 413 414 /* Whether the processor uses hardware interlocks to protect reads 415 from coprocessor registers after they are loaded from memory, and 416 thus does not require nops to be inserted. This applies to 417 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only 418 requires at MIPS ISA level I. */ 419 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) 420 421 /* Is this a mfhi or mflo instruction? */ 422 #define MF_HILO_INSN(PINFO) \ 423 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) 424 425 /* MIPS PIC level. */ 426 427 enum mips_pic_level mips_pic; 428 429 /* 1 if we should generate 32 bit offsets from the $gp register in 430 SVR4_PIC mode. Currently has no meaning in other modes. */ 431 static int mips_big_got = 0; 432 433 /* 1 if trap instructions should used for overflow rather than break 434 instructions. */ 435 static int mips_trap = 0; 436 437 /* 1 if double width floating point constants should not be constructed 438 by assembling two single width halves into two single width floating 439 point registers which just happen to alias the double width destination 440 register. On some architectures this aliasing can be disabled by a bit 441 in the status register, and the setting of this bit cannot be determined 442 automatically at assemble time. */ 443 static int mips_disable_float_construction; 444 445 /* Non-zero if any .set noreorder directives were used. */ 446 447 static int mips_any_noreorder; 448 449 /* Non-zero if nops should be inserted when the register referenced in 450 an mfhi/mflo instruction is read in the next two instructions. */ 451 static int mips_7000_hilo_fix; 452 453 /* The size of the small data section. */ 454 static unsigned int g_switch_value = 8; 455 /* Whether the -G option was used. */ 456 static int g_switch_seen = 0; 457 458 #define N_RMASK 0xc4 459 #define N_VFP 0xd4 460 461 /* If we can determine in advance that GP optimization won't be 462 possible, we can skip the relaxation stuff that tries to produce 463 GP-relative references. This makes delay slot optimization work 464 better. 465 466 This function can only provide a guess, but it seems to work for 467 gcc output. It needs to guess right for gcc, otherwise gcc 468 will put what it thinks is a GP-relative instruction in a branch 469 delay slot. 470 471 I don't know if a fix is needed for the SVR4_PIC mode. I've only 472 fixed it for the non-PIC mode. KR 95/04/07 */ 473 static int nopic_need_relax (symbolS *, int); 474 475 /* handle of the OPCODE hash table */ 476 static struct hash_control *op_hash = NULL; 477 478 /* The opcode hash table we use for the mips16. */ 479 static struct hash_control *mips16_op_hash = NULL; 480 481 /* This array holds the chars that always start a comment. If the 482 pre-processor is disabled, these aren't very useful */ 483 const char comment_chars[] = "#"; 484 485 /* This array holds the chars that only start a comment at the beginning of 486 a line. If the line seems to have the form '# 123 filename' 487 .line and .file directives will appear in the pre-processed output */ 488 /* Note that input_file.c hand checks for '#' at the beginning of the 489 first line of the input file. This is because the compiler outputs 490 #NO_APP at the beginning of its output. */ 491 /* Also note that C style comments are always supported. */ 492 const char line_comment_chars[] = "#"; 493 494 /* This array holds machine specific line separator characters. */ 495 const char line_separator_chars[] = ";"; 496 497 /* Chars that can be used to separate mant from exp in floating point nums */ 498 const char EXP_CHARS[] = "eE"; 499 500 /* Chars that mean this number is a floating point constant */ 501 /* As in 0f12.456 */ 502 /* or 0d1.2345e12 */ 503 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 504 505 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 506 changed in read.c . Ideally it shouldn't have to know about it at all, 507 but nothing is ideal around here. 508 */ 509 510 static char *insn_error; 511 512 static int auto_align = 1; 513 514 /* When outputting SVR4 PIC code, the assembler needs to know the 515 offset in the stack frame from which to restore the $gp register. 516 This is set by the .cprestore pseudo-op, and saved in this 517 variable. */ 518 static offsetT mips_cprestore_offset = -1; 519 520 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some 521 more optimizations, it can use a register value instead of a memory-saved 522 offset and even an other register than $gp as global pointer. */ 523 static offsetT mips_cpreturn_offset = -1; 524 static int mips_cpreturn_register = -1; 525 static int mips_gp_register = GP; 526 static int mips_gprel_offset = 0; 527 528 /* Whether mips_cprestore_offset has been set in the current function 529 (or whether it has already been warned about, if not). */ 530 static int mips_cprestore_valid = 0; 531 532 /* This is the register which holds the stack frame, as set by the 533 .frame pseudo-op. This is needed to implement .cprestore. */ 534 static int mips_frame_reg = SP; 535 536 /* Whether mips_frame_reg has been set in the current function 537 (or whether it has already been warned about, if not). */ 538 static int mips_frame_reg_valid = 0; 539 540 /* To output NOP instructions correctly, we need to keep information 541 about the previous two instructions. */ 542 543 /* Whether we are optimizing. The default value of 2 means to remove 544 unneeded NOPs and swap branch instructions when possible. A value 545 of 1 means to not swap branches. A value of 0 means to always 546 insert NOPs. */ 547 static int mips_optimize = 2; 548 549 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is 550 equivalent to seeing no -g option at all. */ 551 static int mips_debug = 0; 552 553 /* The previous instruction. */ 554 static struct mips_cl_insn prev_insn; 555 556 /* The instruction before prev_insn. */ 557 static struct mips_cl_insn prev_prev_insn; 558 559 /* If we don't want information for prev_insn or prev_prev_insn, we 560 point the insn_mo field at this dummy integer. */ 561 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; 562 563 /* Non-zero if prev_insn is valid. */ 564 static int prev_insn_valid; 565 566 /* The frag for the previous instruction. */ 567 static struct frag *prev_insn_frag; 568 569 /* The offset into prev_insn_frag for the previous instruction. */ 570 static long prev_insn_where; 571 572 /* The reloc type for the previous instruction, if any. */ 573 static bfd_reloc_code_real_type prev_insn_reloc_type[3]; 574 575 /* The reloc for the previous instruction, if any. */ 576 static fixS *prev_insn_fixp[3]; 577 578 /* Non-zero if the previous instruction was in a delay slot. */ 579 static int prev_insn_is_delay_slot; 580 581 /* Non-zero if the previous instruction was in a .set noreorder. */ 582 static int prev_insn_unreordered; 583 584 /* Non-zero if the previous instruction uses an extend opcode (if 585 mips16). */ 586 static int prev_insn_extended; 587 588 /* Non-zero if the previous previous instruction was in a .set 589 noreorder. */ 590 static int prev_prev_insn_unreordered; 591 592 /* If this is set, it points to a frag holding nop instructions which 593 were inserted before the start of a noreorder section. If those 594 nops turn out to be unnecessary, the size of the frag can be 595 decreased. */ 596 static fragS *prev_nop_frag; 597 598 /* The number of nop instructions we created in prev_nop_frag. */ 599 static int prev_nop_frag_holds; 600 601 /* The number of nop instructions that we know we need in 602 prev_nop_frag. */ 603 static int prev_nop_frag_required; 604 605 /* The number of instructions we've seen since prev_nop_frag. */ 606 static int prev_nop_frag_since; 607 608 /* For ECOFF and ELF, relocations against symbols are done in two 609 parts, with a HI relocation and a LO relocation. Each relocation 610 has only 16 bits of space to store an addend. This means that in 611 order for the linker to handle carries correctly, it must be able 612 to locate both the HI and the LO relocation. This means that the 613 relocations must appear in order in the relocation table. 614 615 In order to implement this, we keep track of each unmatched HI 616 relocation. We then sort them so that they immediately precede the 617 corresponding LO relocation. */ 618 619 struct mips_hi_fixup 620 { 621 /* Next HI fixup. */ 622 struct mips_hi_fixup *next; 623 /* This fixup. */ 624 fixS *fixp; 625 /* The section this fixup is in. */ 626 segT seg; 627 }; 628 629 /* The list of unmatched HI relocs. */ 630 631 static struct mips_hi_fixup *mips_hi_fixup_list; 632 633 /* The frag containing the last explicit relocation operator. 634 Null if explicit relocations have not been used. */ 635 636 static fragS *prev_reloc_op_frag; 637 638 /* Map normal MIPS register numbers to mips16 register numbers. */ 639 640 #define X ILLEGAL_REG 641 static const int mips32_to_16_reg_map[] = 642 { 643 X, X, 2, 3, 4, 5, 6, 7, 644 X, X, X, X, X, X, X, X, 645 0, 1, X, X, X, X, X, X, 646 X, X, X, X, X, X, X, X 647 }; 648 #undef X 649 650 /* Map mips16 register numbers to normal MIPS register numbers. */ 651 652 static const unsigned int mips16_to_32_reg_map[] = 653 { 654 16, 17, 2, 3, 4, 5, 6, 7 655 }; 656 657 static int mips_fix_vr4120; 658 659 /* We don't relax branches by default, since this causes us to expand 660 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we 661 fail to compute the offset before expanding the macro to the most 662 efficient expansion. */ 663 664 static int mips_relax_branch; 665 666 static int mips_fix_loongson2f_btb; 667 668 /* The expansion of many macros depends on the type of symbol that 669 they refer to. For example, when generating position-dependent code, 670 a macro that refers to a symbol may have two different expansions, 671 one which uses GP-relative addresses and one which uses absolute 672 addresses. When generating SVR4-style PIC, a macro may have 673 different expansions for local and global symbols. 674 675 We handle these situations by generating both sequences and putting 676 them in variant frags. In position-dependent code, the first sequence 677 will be the GP-relative one and the second sequence will be the 678 absolute one. In SVR4 PIC, the first sequence will be for global 679 symbols and the second will be for local symbols. 680 681 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and 682 SECOND are the lengths of the two sequences in bytes. These fields 683 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, 684 the subtype has the following flags: 685 686 RELAX_USE_SECOND 687 Set if it has been decided that we should use the second 688 sequence instead of the first. 689 690 RELAX_SECOND_LONGER 691 Set in the first variant frag if the macro's second implementation 692 is longer than its first. This refers to the macro as a whole, 693 not an individual relaxation. 694 695 RELAX_NOMACRO 696 Set in the first variant frag if the macro appeared in a .set nomacro 697 block and if one alternative requires a warning but the other does not. 698 699 RELAX_DELAY_SLOT 700 Like RELAX_NOMACRO, but indicates that the macro appears in a branch 701 delay slot. 702 703 The frag's "opcode" points to the first fixup for relaxable code. 704 705 Relaxable macros are generated using a sequence such as: 706 707 relax_start (SYMBOL); 708 ... generate first expansion ... 709 relax_switch (); 710 ... generate second expansion ... 711 relax_end (); 712 713 The code and fixups for the unwanted alternative are discarded 714 by md_convert_frag. */ 715 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) 716 717 #define RELAX_FIRST(X) (((X) >> 8) & 0xff) 718 #define RELAX_SECOND(X) ((X) & 0xff) 719 #define RELAX_USE_SECOND 0x10000 720 #define RELAX_SECOND_LONGER 0x20000 721 #define RELAX_NOMACRO 0x40000 722 #define RELAX_DELAY_SLOT 0x80000 723 724 /* Branch without likely bit. If label is out of range, we turn: 725 726 beq reg1, reg2, label 727 delay slot 728 729 into 730 731 bne reg1, reg2, 0f 732 nop 733 j label 734 0: delay slot 735 736 with the following opcode replacements: 737 738 beq <-> bne 739 blez <-> bgtz 740 bltz <-> bgez 741 bc1f <-> bc1t 742 743 bltzal <-> bgezal (with jal label instead of j label) 744 745 Even though keeping the delay slot instruction in the delay slot of 746 the branch would be more efficient, it would be very tricky to do 747 correctly, because we'd have to introduce a variable frag *after* 748 the delay slot instruction, and expand that instead. Let's do it 749 the easy way for now, even if the branch-not-taken case now costs 750 one additional instruction. Out-of-range branches are not supposed 751 to be common, anyway. 752 753 Branch likely. If label is out of range, we turn: 754 755 beql reg1, reg2, label 756 delay slot (annulled if branch not taken) 757 758 into 759 760 beql reg1, reg2, 1f 761 nop 762 beql $0, $0, 2f 763 nop 764 1: j[al] label 765 delay slot (executed only if branch taken) 766 2: 767 768 It would be possible to generate a shorter sequence by losing the 769 likely bit, generating something like: 770 771 bne reg1, reg2, 0f 772 nop 773 j[al] label 774 delay slot (executed only if branch taken) 775 0: 776 777 beql -> bne 778 bnel -> beq 779 blezl -> bgtz 780 bgtzl -> blez 781 bltzl -> bgez 782 bgezl -> bltz 783 bc1fl -> bc1t 784 bc1tl -> bc1f 785 786 bltzall -> bgezal (with jal label instead of j label) 787 bgezall -> bltzal (ditto) 788 789 790 but it's not clear that it would actually improve performance. */ 791 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ 792 ((relax_substateT) \ 793 (0xc0000000 \ 794 | ((toofar) ? 1 : 0) \ 795 | ((link) ? 2 : 0) \ 796 | ((likely) ? 4 : 0) \ 797 | ((uncond) ? 8 : 0))) 798 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 799 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) 800 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) 801 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) 802 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) 803 804 /* For mips16 code, we use an entirely different form of relaxation. 805 mips16 supports two versions of most instructions which take 806 immediate values: a small one which takes some small value, and a 807 larger one which takes a 16 bit value. Since branches also follow 808 this pattern, relaxing these values is required. 809 810 We can assemble both mips16 and normal MIPS code in a single 811 object. Therefore, we need to support this type of relaxation at 812 the same time that we support the relaxation described above. We 813 use the high bit of the subtype field to distinguish these cases. 814 815 The information we store for this type of relaxation is the 816 argument code found in the opcode file for this relocation, whether 817 the user explicitly requested a small or extended form, and whether 818 the relocation is in a jump or jal delay slot. That tells us the 819 size of the value, and how it should be stored. We also store 820 whether the fragment is considered to be extended or not. We also 821 store whether this is known to be a branch to a different section, 822 whether we have tried to relax this frag yet, and whether we have 823 ever extended a PC relative fragment because of a shift count. */ 824 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ 825 (0x80000000 \ 826 | ((type) & 0xff) \ 827 | ((small) ? 0x100 : 0) \ 828 | ((ext) ? 0x200 : 0) \ 829 | ((dslot) ? 0x400 : 0) \ 830 | ((jal_dslot) ? 0x800 : 0)) 831 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) 832 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) 833 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) 834 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) 835 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) 836 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) 837 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) 838 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) 839 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) 840 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) 841 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) 842 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) 843 844 /* Is the given value a sign-extended 32-bit value? */ 845 #define IS_SEXT_32BIT_NUM(x) \ 846 (((x) &~ (offsetT) 0x7fffffff) == 0 \ 847 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) 848 849 /* Is the given value a sign-extended 16-bit value? */ 850 #define IS_SEXT_16BIT_NUM(x) \ 851 (((x) &~ (offsetT) 0x7fff) == 0 \ 852 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) 853 854 855 /* Global variables used when generating relaxable macros. See the 856 comment above RELAX_ENCODE for more details about how relaxation 857 is used. */ 858 static struct { 859 /* 0 if we're not emitting a relaxable macro. 860 1 if we're emitting the first of the two relaxation alternatives. 861 2 if we're emitting the second alternative. */ 862 int sequence; 863 864 /* The first relaxable fixup in the current frag. (In other words, 865 the first fixup that refers to relaxable code.) */ 866 fixS *first_fixup; 867 868 /* sizes[0] says how many bytes of the first alternative are stored in 869 the current frag. Likewise sizes[1] for the second alternative. */ 870 unsigned int sizes[2]; 871 872 /* The symbol on which the choice of sequence depends. */ 873 symbolS *symbol; 874 } mips_relax; 875 876 /* Global variables used to decide whether a macro needs a warning. */ 877 static struct { 878 /* True if the macro is in a branch delay slot. */ 879 bfd_boolean delay_slot_p; 880 881 /* For relaxable macros, sizes[0] is the length of the first alternative 882 in bytes and sizes[1] is the length of the second alternative. 883 For non-relaxable macros, both elements give the length of the 884 macro in bytes. */ 885 unsigned int sizes[2]; 886 887 /* The first variant frag for this macro. */ 888 fragS *first_frag; 889 } mips_macro_warning; 890 891 /* Prototypes for static functions. */ 892 893 #define internalError() \ 894 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) 895 896 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; 897 898 static void append_insn 899 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); 900 static void mips_no_prev_insn (int); 901 static void mips16_macro_build 902 (expressionS *, const char *, const char *, va_list); 903 static void load_register (int, expressionS *, int); 904 static void macro_build (expressionS *, const char *, const char *, ...); 905 static void macro_start (void); 906 static void macro_end (void); 907 static void macro (struct mips_cl_insn * ip); 908 static void mips16_macro (struct mips_cl_insn * ip); 909 #ifdef LOSING_COMPILER 910 static void macro2 (struct mips_cl_insn * ip); 911 #endif 912 static void mips_ip (char *str, struct mips_cl_insn * ip); 913 static void mips16_ip (char *str, struct mips_cl_insn * ip); 914 static void mips16_immed 915 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, 916 unsigned long *, bfd_boolean *, unsigned short *); 917 static size_t my_getSmallExpression 918 (expressionS *, bfd_reloc_code_real_type *, char *); 919 static void my_getExpression (expressionS *, char *); 920 static void s_align (int); 921 static void s_change_sec (int); 922 static void s_change_section (int); 923 static void s_cons (int); 924 static void s_float_cons (int); 925 static void s_mips_globl (int); 926 static void s_option (int); 927 static void s_mipsset (int); 928 static void s_abicalls (int); 929 static void s_cpload (int); 930 static void s_cpsetup (int); 931 static void s_cplocal (int); 932 static void s_cprestore (int); 933 static void s_cpreturn (int); 934 static void s_gpvalue (int); 935 static void s_gpword (int); 936 static void s_gpdword (int); 937 static void s_cpadd (int); 938 static void s_insn (int); 939 static void md_obj_begin (void); 940 static void md_obj_end (void); 941 static void s_mips_ent (int); 942 static void s_mips_end (int); 943 static void s_mips_frame (int); 944 static void s_mips_mask (int reg_type); 945 static void s_mips_stab (int); 946 static void s_mips_weakext (int); 947 static void s_mips_file (int); 948 static void s_mips_loc (int); 949 static bfd_boolean pic_need_relax (symbolS *, asection *); 950 static int relaxed_branch_length (fragS *, asection *, int); 951 static int validate_mips_insn (const struct mips_opcode *); 952 953 /* Table and functions used to map between CPU/ISA names, and 954 ISA levels, and CPU numbers. */ 955 956 struct mips_cpu_info 957 { 958 const char *name; /* CPU or ISA name. */ 959 int flags; /* ASEs available, or ISA flag. */ 960 int isa; /* ISA level. */ 961 int cpu; /* CPU number (default CPU if ISA). */ 962 }; 963 964 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ 965 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ 966 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ 967 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ 968 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ 969 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ 970 971 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); 972 static const struct mips_cpu_info *mips_cpu_info_from_isa (int); 973 static const struct mips_cpu_info *mips_cpu_info_from_arch (int); 974 975 /* Pseudo-op table. 976 977 The following pseudo-ops from the Kane and Heinrich MIPS book 978 should be defined here, but are currently unsupported: .alias, 979 .galive, .gjaldef, .gjrlive, .livereg, .noalias. 980 981 The following pseudo-ops from the Kane and Heinrich MIPS book are 982 specific to the type of debugging information being generated, and 983 should be defined by the object format: .aent, .begin, .bend, 984 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, 985 .vreg. 986 987 The following pseudo-ops from the Kane and Heinrich MIPS book are 988 not MIPS CPU specific, but are also not specific to the object file 989 format. This file is probably the best place to define them, but 990 they are not currently supported: .asm0, .endr, .lab, .repeat, 991 .struct. */ 992 993 static const pseudo_typeS mips_pseudo_table[] = 994 { 995 /* MIPS specific pseudo-ops. */ 996 {"option", s_option, 0}, 997 {"set", s_mipsset, 0}, 998 {"rdata", s_change_sec, 'r'}, 999 {"sdata", s_change_sec, 's'}, 1000 {"livereg", s_ignore, 0}, 1001 {"abicalls", s_abicalls, 0}, 1002 {"cpload", s_cpload, 0}, 1003 {"cpsetup", s_cpsetup, 0}, 1004 {"cplocal", s_cplocal, 0}, 1005 {"cprestore", s_cprestore, 0}, 1006 {"cpreturn", s_cpreturn, 0}, 1007 {"gpvalue", s_gpvalue, 0}, 1008 {"gpword", s_gpword, 0}, 1009 {"gpdword", s_gpdword, 0}, 1010 {"cpadd", s_cpadd, 0}, 1011 {"insn", s_insn, 0}, 1012 1013 /* Relatively generic pseudo-ops that happen to be used on MIPS 1014 chips. */ 1015 {"asciiz", stringer, 1}, 1016 {"bss", s_change_sec, 'b'}, 1017 {"err", s_err, 0}, 1018 {"half", s_cons, 1}, 1019 {"dword", s_cons, 3}, 1020 {"weakext", s_mips_weakext, 0}, 1021 1022 /* These pseudo-ops are defined in read.c, but must be overridden 1023 here for one reason or another. */ 1024 {"align", s_align, 0}, 1025 {"byte", s_cons, 0}, 1026 {"data", s_change_sec, 'd'}, 1027 {"double", s_float_cons, 'd'}, 1028 {"float", s_float_cons, 'f'}, 1029 {"globl", s_mips_globl, 0}, 1030 {"global", s_mips_globl, 0}, 1031 {"hword", s_cons, 1}, 1032 {"int", s_cons, 2}, 1033 {"long", s_cons, 2}, 1034 {"octa", s_cons, 4}, 1035 {"quad", s_cons, 3}, 1036 {"section", s_change_section, 0}, 1037 {"short", s_cons, 1}, 1038 {"single", s_float_cons, 'f'}, 1039 {"stabn", s_mips_stab, 'n'}, 1040 {"text", s_change_sec, 't'}, 1041 {"word", s_cons, 2}, 1042 1043 { "extern", ecoff_directive_extern, 0}, 1044 1045 { NULL, NULL, 0 }, 1046 }; 1047 1048 static const pseudo_typeS mips_nonecoff_pseudo_table[] = 1049 { 1050 /* These pseudo-ops should be defined by the object file format. 1051 However, a.out doesn't support them, so we have versions here. */ 1052 {"aent", s_mips_ent, 1}, 1053 {"bgnb", s_ignore, 0}, 1054 {"end", s_mips_end, 0}, 1055 {"endb", s_ignore, 0}, 1056 {"ent", s_mips_ent, 0}, 1057 {"file", s_mips_file, 0}, 1058 {"fmask", s_mips_mask, 'F'}, 1059 {"frame", s_mips_frame, 0}, 1060 {"loc", s_mips_loc, 0}, 1061 {"mask", s_mips_mask, 'R'}, 1062 {"verstamp", s_ignore, 0}, 1063 { NULL, NULL, 0 }, 1064 }; 1065 1066 extern void pop_insert (const pseudo_typeS *); 1067 1068 void 1069 mips_pop_insert (void) 1070 { 1071 pop_insert (mips_pseudo_table); 1072 if (! ECOFF_DEBUGGING) 1073 pop_insert (mips_nonecoff_pseudo_table); 1074 } 1075 1076 /* Symbols labelling the current insn. */ 1077 1078 struct insn_label_list 1079 { 1080 struct insn_label_list *next; 1081 symbolS *label; 1082 }; 1083 1084 static struct insn_label_list *insn_labels; 1085 static struct insn_label_list *free_insn_labels; 1086 1087 static void mips_clear_insn_labels (void); 1088 1089 static inline void 1090 mips_clear_insn_labels (void) 1091 { 1092 register struct insn_label_list **pl; 1093 1094 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 1095 ; 1096 *pl = insn_labels; 1097 insn_labels = NULL; 1098 } 1099 1100 static char *expr_end; 1101 1102 /* Expressions which appear in instructions. These are set by 1103 mips_ip. */ 1104 1105 static expressionS imm_expr; 1106 static expressionS imm2_expr; 1107 static expressionS offset_expr; 1108 1109 /* Relocs associated with imm_expr and offset_expr. */ 1110 1111 static bfd_reloc_code_real_type imm_reloc[3] 1112 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1113 static bfd_reloc_code_real_type offset_reloc[3] 1114 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1115 1116 /* These are set by mips16_ip if an explicit extension is used. */ 1117 1118 static bfd_boolean mips16_small, mips16_ext; 1119 1120 #ifdef OBJ_ELF 1121 /* The pdr segment for per procedure frame/regmask info. Not used for 1122 ECOFF debugging. */ 1123 1124 static segT pdr_seg; 1125 #endif 1126 1127 /* The default target format to use. */ 1128 1129 const char * 1130 mips_target_format (void) 1131 { 1132 switch (OUTPUT_FLAVOR) 1133 { 1134 case bfd_target_aout_flavour: 1135 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; 1136 case bfd_target_ecoff_flavour: 1137 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; 1138 case bfd_target_coff_flavour: 1139 return "pe-mips"; 1140 case bfd_target_elf_flavour: 1141 #ifdef TE_TMIPS 1142 /* This is traditional mips. */ 1143 return (target_big_endian 1144 ? (HAVE_64BIT_OBJECTS 1145 ? "elf64-tradbigmips" 1146 : (HAVE_NEWABI 1147 ? "elf32-ntradbigmips" : "elf32-tradbigmips")) 1148 : (HAVE_64BIT_OBJECTS 1149 ? "elf64-tradlittlemips" 1150 : (HAVE_NEWABI 1151 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); 1152 #else 1153 return (target_big_endian 1154 ? (HAVE_64BIT_OBJECTS 1155 ? "elf64-bigmips" 1156 : (HAVE_NEWABI 1157 ? "elf32-nbigmips" : "elf32-bigmips")) 1158 : (HAVE_64BIT_OBJECTS 1159 ? "elf64-littlemips" 1160 : (HAVE_NEWABI 1161 ? "elf32-nlittlemips" : "elf32-littlemips"))); 1162 #endif 1163 default: 1164 abort (); 1165 return NULL; 1166 } 1167 } 1168 1169 /* Defining all the symbolic register names. */ 1170 struct regname { 1171 const char *name; 1172 unsigned int num; 1173 }; 1174 1175 #define RTYPE_MASK 0x1ff00 1176 #define RTYPE_NUM 0x00100 1177 #define RTYPE_FPU 0x00200 1178 #define RTYPE_FCC 0x00400 1179 #define RTYPE_VEC 0x00800 1180 #define RTYPE_GP 0x01000 1181 #define RTYPE_CP0 0x02000 1182 #define RTYPE_PC 0x04000 1183 #define RTYPE_ACC 0x08000 1184 #define RTYPE_CCC 0x10000 1185 #define RNUM_MASK 0x000ff 1186 #define RWARN 0x80000 1187 1188 #define GENERIC_REGISTER_NUMBERS \ 1189 {"$0", RTYPE_NUM | 0}, \ 1190 {"$1", RTYPE_NUM | 1}, \ 1191 {"$2", RTYPE_NUM | 2}, \ 1192 {"$3", RTYPE_NUM | 3}, \ 1193 {"$4", RTYPE_NUM | 4}, \ 1194 {"$5", RTYPE_NUM | 5}, \ 1195 {"$6", RTYPE_NUM | 6}, \ 1196 {"$7", RTYPE_NUM | 7}, \ 1197 {"$8", RTYPE_NUM | 8}, \ 1198 {"$9", RTYPE_NUM | 9}, \ 1199 {"$10", RTYPE_NUM | 10}, \ 1200 {"$11", RTYPE_NUM | 11}, \ 1201 {"$12", RTYPE_NUM | 12}, \ 1202 {"$13", RTYPE_NUM | 13}, \ 1203 {"$14", RTYPE_NUM | 14}, \ 1204 {"$15", RTYPE_NUM | 15}, \ 1205 {"$16", RTYPE_NUM | 16}, \ 1206 {"$17", RTYPE_NUM | 17}, \ 1207 {"$18", RTYPE_NUM | 18}, \ 1208 {"$19", RTYPE_NUM | 19}, \ 1209 {"$20", RTYPE_NUM | 20}, \ 1210 {"$21", RTYPE_NUM | 21}, \ 1211 {"$22", RTYPE_NUM | 22}, \ 1212 {"$23", RTYPE_NUM | 23}, \ 1213 {"$24", RTYPE_NUM | 24}, \ 1214 {"$25", RTYPE_NUM | 25}, \ 1215 {"$26", RTYPE_NUM | 26}, \ 1216 {"$27", RTYPE_NUM | 27}, \ 1217 {"$28", RTYPE_NUM | 28}, \ 1218 {"$29", RTYPE_NUM | 29}, \ 1219 {"$30", RTYPE_NUM | 30}, \ 1220 {"$31", RTYPE_NUM | 31} 1221 1222 #define FPU_REGISTER_NAMES \ 1223 {"$f0", RTYPE_FPU | 0}, \ 1224 {"$f1", RTYPE_FPU | 1}, \ 1225 {"$f2", RTYPE_FPU | 2}, \ 1226 {"$f3", RTYPE_FPU | 3}, \ 1227 {"$f4", RTYPE_FPU | 4}, \ 1228 {"$f5", RTYPE_FPU | 5}, \ 1229 {"$f6", RTYPE_FPU | 6}, \ 1230 {"$f7", RTYPE_FPU | 7}, \ 1231 {"$f8", RTYPE_FPU | 8}, \ 1232 {"$f9", RTYPE_FPU | 9}, \ 1233 {"$f10", RTYPE_FPU | 10}, \ 1234 {"$f11", RTYPE_FPU | 11}, \ 1235 {"$f12", RTYPE_FPU | 12}, \ 1236 {"$f13", RTYPE_FPU | 13}, \ 1237 {"$f14", RTYPE_FPU | 14}, \ 1238 {"$f15", RTYPE_FPU | 15}, \ 1239 {"$f16", RTYPE_FPU | 16}, \ 1240 {"$f17", RTYPE_FPU | 17}, \ 1241 {"$f18", RTYPE_FPU | 18}, \ 1242 {"$f19", RTYPE_FPU | 19}, \ 1243 {"$f20", RTYPE_FPU | 20}, \ 1244 {"$f21", RTYPE_FPU | 21}, \ 1245 {"$f22", RTYPE_FPU | 22}, \ 1246 {"$f23", RTYPE_FPU | 23}, \ 1247 {"$f24", RTYPE_FPU | 24}, \ 1248 {"$f25", RTYPE_FPU | 25}, \ 1249 {"$f26", RTYPE_FPU | 26}, \ 1250 {"$f27", RTYPE_FPU | 27}, \ 1251 {"$f28", RTYPE_FPU | 28}, \ 1252 {"$f29", RTYPE_FPU | 29}, \ 1253 {"$f30", RTYPE_FPU | 30}, \ 1254 {"$f31", RTYPE_FPU | 31} 1255 1256 #define FPU_CONDITION_CODE_NAMES \ 1257 {"$fcc0", RTYPE_FCC | 0}, \ 1258 {"$fcc1", RTYPE_FCC | 1}, \ 1259 {"$fcc2", RTYPE_FCC | 2}, \ 1260 {"$fcc3", RTYPE_FCC | 3}, \ 1261 {"$fcc4", RTYPE_FCC | 4}, \ 1262 {"$fcc5", RTYPE_FCC | 5}, \ 1263 {"$fcc6", RTYPE_FCC | 6}, \ 1264 {"$fcc7", RTYPE_FCC | 7} 1265 1266 #define COPROC_CONDITION_CODE_NAMES \ 1267 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ 1268 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ 1269 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ 1270 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ 1271 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ 1272 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ 1273 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ 1274 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} 1275 1276 #define N32N64_SYMBOLIC_REGISTER_NAMES \ 1277 {"$a4", RTYPE_GP | 8}, \ 1278 {"$a5", RTYPE_GP | 9}, \ 1279 {"$a6", RTYPE_GP | 10}, \ 1280 {"$a7", RTYPE_GP | 11}, \ 1281 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ 1282 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ 1283 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ 1284 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ 1285 {"$t0", RTYPE_GP | 12}, \ 1286 {"$t1", RTYPE_GP | 13}, \ 1287 {"$t2", RTYPE_GP | 14}, \ 1288 {"$t3", RTYPE_GP | 15} 1289 1290 #define O32_SYMBOLIC_REGISTER_NAMES \ 1291 {"$t0", RTYPE_GP | 8}, \ 1292 {"$t1", RTYPE_GP | 9}, \ 1293 {"$t2", RTYPE_GP | 10}, \ 1294 {"$t3", RTYPE_GP | 11}, \ 1295 {"$t4", RTYPE_GP | 12}, \ 1296 {"$t5", RTYPE_GP | 13}, \ 1297 {"$t6", RTYPE_GP | 14}, \ 1298 {"$t7", RTYPE_GP | 15}, \ 1299 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ 1300 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ 1301 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ 1302 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ 1303 1304 /* Remaining symbolic register names */ 1305 #define SYMBOLIC_REGISTER_NAMES \ 1306 {"$zero", RTYPE_GP | 0}, \ 1307 {"$at", RTYPE_GP | 1}, \ 1308 {"$AT", RTYPE_GP | 1}, \ 1309 {"$v0", RTYPE_GP | 2}, \ 1310 {"$v1", RTYPE_GP | 3}, \ 1311 {"$a0", RTYPE_GP | 4}, \ 1312 {"$a1", RTYPE_GP | 5}, \ 1313 {"$a2", RTYPE_GP | 6}, \ 1314 {"$a3", RTYPE_GP | 7}, \ 1315 {"$s0", RTYPE_GP | 16}, \ 1316 {"$s1", RTYPE_GP | 17}, \ 1317 {"$s2", RTYPE_GP | 18}, \ 1318 {"$s3", RTYPE_GP | 19}, \ 1319 {"$s4", RTYPE_GP | 20}, \ 1320 {"$s5", RTYPE_GP | 21}, \ 1321 {"$s6", RTYPE_GP | 22}, \ 1322 {"$s7", RTYPE_GP | 23}, \ 1323 {"$t8", RTYPE_GP | 24}, \ 1324 {"$t9", RTYPE_GP | 25}, \ 1325 {"$k0", RTYPE_GP | 26}, \ 1326 {"$kt0", RTYPE_GP | 26}, \ 1327 {"$k1", RTYPE_GP | 27}, \ 1328 {"$kt1", RTYPE_GP | 27}, \ 1329 {"$gp", RTYPE_GP | 28}, \ 1330 {"$sp", RTYPE_GP | 29}, \ 1331 {"$s8", RTYPE_GP | 30}, \ 1332 {"$fp", RTYPE_GP | 30}, \ 1333 {"$ra", RTYPE_GP | 31} 1334 1335 #define MIPS16_SPECIAL_REGISTER_NAMES \ 1336 {"$pc", RTYPE_PC | 0} 1337 1338 #define MDMX_VECTOR_REGISTER_NAMES \ 1339 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ 1340 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ 1341 {"$v2", RTYPE_VEC | 2}, \ 1342 {"$v3", RTYPE_VEC | 3}, \ 1343 {"$v4", RTYPE_VEC | 4}, \ 1344 {"$v5", RTYPE_VEC | 5}, \ 1345 {"$v6", RTYPE_VEC | 6}, \ 1346 {"$v7", RTYPE_VEC | 7}, \ 1347 {"$v8", RTYPE_VEC | 8}, \ 1348 {"$v9", RTYPE_VEC | 9}, \ 1349 {"$v10", RTYPE_VEC | 10}, \ 1350 {"$v11", RTYPE_VEC | 11}, \ 1351 {"$v12", RTYPE_VEC | 12}, \ 1352 {"$v13", RTYPE_VEC | 13}, \ 1353 {"$v14", RTYPE_VEC | 14}, \ 1354 {"$v15", RTYPE_VEC | 15}, \ 1355 {"$v16", RTYPE_VEC | 16}, \ 1356 {"$v17", RTYPE_VEC | 17}, \ 1357 {"$v18", RTYPE_VEC | 18}, \ 1358 {"$v19", RTYPE_VEC | 19}, \ 1359 {"$v20", RTYPE_VEC | 20}, \ 1360 {"$v21", RTYPE_VEC | 21}, \ 1361 {"$v22", RTYPE_VEC | 22}, \ 1362 {"$v23", RTYPE_VEC | 23}, \ 1363 {"$v24", RTYPE_VEC | 24}, \ 1364 {"$v25", RTYPE_VEC | 25}, \ 1365 {"$v26", RTYPE_VEC | 26}, \ 1366 {"$v27", RTYPE_VEC | 27}, \ 1367 {"$v28", RTYPE_VEC | 28}, \ 1368 {"$v29", RTYPE_VEC | 29}, \ 1369 {"$v30", RTYPE_VEC | 30}, \ 1370 {"$v31", RTYPE_VEC | 31} 1371 1372 #define MIPS_DSP_ACCUMULATOR_NAMES \ 1373 {"$ac0", RTYPE_ACC | 0}, \ 1374 {"$ac1", RTYPE_ACC | 1}, \ 1375 {"$ac2", RTYPE_ACC | 2}, \ 1376 {"$ac3", RTYPE_ACC | 3} 1377 1378 static const struct regname reg_names[] = { 1379 GENERIC_REGISTER_NUMBERS, 1380 FPU_REGISTER_NAMES, 1381 FPU_CONDITION_CODE_NAMES, 1382 COPROC_CONDITION_CODE_NAMES, 1383 1384 /* The $txx registers depends on the abi, 1385 these will be added later into the symbol table from 1386 one of the tables below once mips_abi is set after 1387 parsing of arguments from the command line. */ 1388 SYMBOLIC_REGISTER_NAMES, 1389 1390 MIPS16_SPECIAL_REGISTER_NAMES, 1391 MDMX_VECTOR_REGISTER_NAMES, 1392 MIPS_DSP_ACCUMULATOR_NAMES, 1393 {0, 0} 1394 }; 1395 1396 static const struct regname reg_names_o32[] = { 1397 O32_SYMBOLIC_REGISTER_NAMES, 1398 {0, 0} 1399 }; 1400 1401 static const struct regname reg_names_n32n64[] = { 1402 N32N64_SYMBOLIC_REGISTER_NAMES, 1403 {0, 0} 1404 }; 1405 1406 static int 1407 reg_lookup (char **s, unsigned int types, unsigned int *regnop) 1408 { 1409 symbolS *symbolP; 1410 char *e; 1411 char save_c; 1412 int reg = -1; 1413 1414 /* Find end of name. */ 1415 e = *s; 1416 if (is_name_beginner (*e)) 1417 ++e; 1418 while (is_part_of_name (*e)) 1419 ++e; 1420 1421 /* Terminate name. */ 1422 save_c = *e; 1423 *e = '\0'; 1424 1425 /* Look for a register symbol. */ 1426 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) 1427 { 1428 int r = S_GET_VALUE (symbolP); 1429 if (r & types) 1430 reg = r & RNUM_MASK; 1431 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) 1432 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ 1433 reg = (r & RNUM_MASK) - 2; 1434 } 1435 /* Else see if this is a register defined in an itbl entry. */ 1436 else if ((types & RTYPE_GP) && itbl_have_entries) 1437 { 1438 char *n = *s; 1439 unsigned long r; 1440 1441 if (*n == '$') 1442 ++n; 1443 if (itbl_get_reg_val (n, &r)) 1444 reg = r & RNUM_MASK; 1445 } 1446 1447 /* Advance to next token if a register was recognised. */ 1448 if (reg >= 0) 1449 *s = e; 1450 else if (types & RWARN) 1451 as_warn ("Unrecognized register name `%s'", *s); 1452 1453 *e = save_c; 1454 if (regnop) 1455 *regnop = reg; 1456 return reg >= 0; 1457 } 1458 1459 /* This function is called once, at assembler startup time. It should 1460 set up all the tables, etc. that the MD part of the assembler will need. */ 1461 1462 void 1463 md_begin (void) 1464 { 1465 register const char *retval = NULL; 1466 int i = 0; 1467 int broken = 0; 1468 1469 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) 1470 as_warn (_("Could not set architecture and machine")); 1471 1472 op_hash = hash_new (); 1473 1474 for (i = 0; i < NUMOPCODES;) 1475 { 1476 const char *name = mips_opcodes[i].name; 1477 1478 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); 1479 if (retval != NULL) 1480 { 1481 fprintf (stderr, _("internal error: can't hash `%s': %s\n"), 1482 mips_opcodes[i].name, retval); 1483 /* Probably a memory allocation problem? Give up now. */ 1484 as_fatal (_("Broken assembler. No assembly attempted.")); 1485 } 1486 do 1487 { 1488 if (mips_opcodes[i].pinfo != INSN_MACRO) 1489 { 1490 if (!validate_mips_insn (&mips_opcodes[i])) 1491 broken = 1; 1492 } 1493 ++i; 1494 } 1495 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); 1496 } 1497 1498 mips16_op_hash = hash_new (); 1499 1500 i = 0; 1501 while (i < bfd_mips16_num_opcodes) 1502 { 1503 const char *name = mips16_opcodes[i].name; 1504 1505 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); 1506 if (retval != NULL) 1507 as_fatal (_("internal: can't hash `%s': %s"), 1508 mips16_opcodes[i].name, retval); 1509 do 1510 { 1511 if (mips16_opcodes[i].pinfo != INSN_MACRO 1512 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) 1513 != mips16_opcodes[i].match)) 1514 { 1515 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), 1516 mips16_opcodes[i].name, mips16_opcodes[i].args); 1517 broken = 1; 1518 } 1519 ++i; 1520 } 1521 while (i < bfd_mips16_num_opcodes 1522 && strcmp (mips16_opcodes[i].name, name) == 0); 1523 } 1524 1525 if (broken) 1526 as_fatal (_("Broken assembler. No assembly attempted.")); 1527 1528 /* We add all the general register names to the symbol table. This 1529 helps us detect invalid uses of them. */ 1530 for (i = 0; reg_names[i].name; i++) 1531 symbol_table_insert (symbol_new (reg_names[i].name, reg_section, 1532 reg_names[i].num, // & RNUM_MASK, 1533 &zero_address_frag)); 1534 if (HAVE_NEWABI) 1535 for (i = 0; reg_names_n32n64[i].name; i++) 1536 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, 1537 reg_names_n32n64[i].num, // & RNUM_MASK, 1538 &zero_address_frag)); 1539 else 1540 for (i = 0; reg_names_o32[i].name; i++) 1541 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, 1542 reg_names_o32[i].num, // & RNUM_MASK, 1543 &zero_address_frag)); 1544 1545 mips_no_prev_insn (FALSE); 1546 1547 mips_gprmask = 0; 1548 mips_cprmask[0] = 0; 1549 mips_cprmask[1] = 0; 1550 mips_cprmask[2] = 0; 1551 mips_cprmask[3] = 0; 1552 1553 /* set the default alignment for the text section (2**2) */ 1554 record_alignment (text_section, 2); 1555 1556 if (USE_GLOBAL_POINTER_OPT) 1557 bfd_set_gp_size (stdoutput, g_switch_value); 1558 1559 #ifdef OBJ_ELF 1560 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 1561 { 1562 /* On a native system, sections must be aligned to 16 byte 1563 boundaries. When configured for an embedded ELF target, we 1564 don't bother. */ 1565 if (strcmp (TARGET_OS, "elf") != 0) 1566 { 1567 (void) bfd_set_section_alignment (stdoutput, text_section, 4); 1568 (void) bfd_set_section_alignment (stdoutput, data_section, 4); 1569 (void) bfd_set_section_alignment (stdoutput, bss_section, 4); 1570 } 1571 1572 /* Create a .reginfo section for register masks and a .mdebug 1573 section for debugging information. */ 1574 { 1575 segT seg; 1576 subsegT subseg; 1577 flagword flags; 1578 segT sec; 1579 1580 seg = now_seg; 1581 subseg = now_subseg; 1582 1583 /* The ABI says this section should be loaded so that the 1584 running program can access it. However, we don't load it 1585 if we are configured for an embedded target */ 1586 flags = SEC_READONLY | SEC_DATA; 1587 if (strcmp (TARGET_OS, "elf") != 0) 1588 flags |= SEC_ALLOC | SEC_LOAD; 1589 1590 if (mips_abi != N64_ABI) 1591 { 1592 sec = subseg_new (".reginfo", (subsegT) 0); 1593 1594 bfd_set_section_flags (stdoutput, sec, flags); 1595 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); 1596 1597 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); 1598 } 1599 else 1600 { 1601 /* The 64-bit ABI uses a .MIPS.options section rather than 1602 .reginfo section. */ 1603 sec = subseg_new (".MIPS.options", (subsegT) 0); 1604 bfd_set_section_flags (stdoutput, sec, flags); 1605 bfd_set_section_alignment (stdoutput, sec, 3); 1606 1607 /* Set up the option header. */ 1608 { 1609 Elf_Internal_Options opthdr; 1610 char *f; 1611 1612 opthdr.kind = ODK_REGINFO; 1613 opthdr.size = (sizeof (Elf_External_Options) 1614 + sizeof (Elf64_External_RegInfo)); 1615 opthdr.section = 0; 1616 opthdr.info = 0; 1617 f = frag_more (sizeof (Elf_External_Options)); 1618 bfd_mips_elf_swap_options_out (stdoutput, &opthdr, 1619 (Elf_External_Options *) f); 1620 1621 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); 1622 } 1623 } 1624 1625 if (ECOFF_DEBUGGING) 1626 { 1627 sec = subseg_new (".mdebug", (subsegT) 0); 1628 (void) bfd_set_section_flags (stdoutput, sec, 1629 SEC_HAS_CONTENTS | SEC_READONLY); 1630 (void) bfd_set_section_alignment (stdoutput, sec, 2); 1631 } 1632 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) 1633 { 1634 pdr_seg = subseg_new (".pdr", (subsegT) 0); 1635 (void) bfd_set_section_flags (stdoutput, pdr_seg, 1636 SEC_READONLY | SEC_RELOC 1637 | SEC_DEBUGGING); 1638 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); 1639 } 1640 1641 subseg_set (seg, subseg); 1642 } 1643 } 1644 #endif /* OBJ_ELF */ 1645 1646 if (! ECOFF_DEBUGGING) 1647 md_obj_begin (); 1648 } 1649 1650 void 1651 md_mips_end (void) 1652 { 1653 if (! ECOFF_DEBUGGING) 1654 md_obj_end (); 1655 } 1656 1657 void 1658 md_assemble (char *str) 1659 { 1660 struct mips_cl_insn insn; 1661 bfd_reloc_code_real_type unused_reloc[3] 1662 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1663 1664 imm_expr.X_op = O_absent; 1665 imm2_expr.X_op = O_absent; 1666 offset_expr.X_op = O_absent; 1667 imm_reloc[0] = BFD_RELOC_UNUSED; 1668 imm_reloc[1] = BFD_RELOC_UNUSED; 1669 imm_reloc[2] = BFD_RELOC_UNUSED; 1670 offset_reloc[0] = BFD_RELOC_UNUSED; 1671 offset_reloc[1] = BFD_RELOC_UNUSED; 1672 offset_reloc[2] = BFD_RELOC_UNUSED; 1673 1674 if (mips_opts.mips16) 1675 mips16_ip (str, &insn); 1676 else 1677 { 1678 mips_ip (str, &insn); 1679 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), 1680 str, insn.insn_opcode)); 1681 } 1682 1683 if (insn_error) 1684 { 1685 as_bad ("%s `%s'", insn_error, str); 1686 return; 1687 } 1688 1689 if (insn.insn_mo->pinfo == INSN_MACRO) 1690 { 1691 macro_start (); 1692 if (mips_opts.mips16) 1693 mips16_macro (&insn); 1694 else 1695 macro (&insn); 1696 macro_end (); 1697 } 1698 else 1699 { 1700 if (imm_expr.X_op != O_absent) 1701 append_insn (&insn, &imm_expr, imm_reloc); 1702 else if (offset_expr.X_op != O_absent) 1703 append_insn (&insn, &offset_expr, offset_reloc); 1704 else 1705 append_insn (&insn, NULL, unused_reloc); 1706 } 1707 } 1708 1709 /* Return true if the given relocation might need a matching %lo(). 1710 Note that R_MIPS_GOT16 relocations only need a matching %lo() when 1711 applied to local symbols. */ 1712 1713 static inline bfd_boolean 1714 reloc_needs_lo_p (bfd_reloc_code_real_type reloc) 1715 { 1716 return (reloc == BFD_RELOC_HI16_S 1717 || reloc == BFD_RELOC_MIPS_GOT16); 1718 } 1719 1720 /* Return true if the given fixup is followed by a matching R_MIPS_LO16 1721 relocation. */ 1722 1723 static inline bfd_boolean 1724 fixup_has_matching_lo_p (fixS *fixp) 1725 { 1726 return (fixp->fx_next != NULL 1727 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 1728 && fixp->fx_addsy == fixp->fx_next->fx_addsy 1729 && fixp->fx_offset == fixp->fx_next->fx_offset); 1730 } 1731 1732 /* See whether instruction IP reads register REG. CLASS is the type 1733 of register. */ 1734 1735 static int 1736 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, 1737 enum mips_regclass class) 1738 { 1739 if (class == MIPS16_REG) 1740 { 1741 assert (mips_opts.mips16); 1742 reg = mips16_to_32_reg_map[reg]; 1743 class = MIPS_GR_REG; 1744 } 1745 1746 /* Don't report on general register ZERO, since it never changes. */ 1747 if (class == MIPS_GR_REG && reg == ZERO) 1748 return 0; 1749 1750 if (class == MIPS_FP_REG) 1751 { 1752 assert (! mips_opts.mips16); 1753 /* If we are called with either $f0 or $f1, we must check $f0. 1754 This is not optimal, because it will introduce an unnecessary 1755 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would 1756 need to distinguish reading both $f0 and $f1 or just one of 1757 them. Note that we don't have to check the other way, 1758 because there is no instruction that sets both $f0 and $f1 1759 and requires a delay. */ 1760 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) 1761 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) 1762 == (reg &~ (unsigned) 1))) 1763 return 1; 1764 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) 1765 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) 1766 == (reg &~ (unsigned) 1))) 1767 return 1; 1768 } 1769 else if (! mips_opts.mips16) 1770 { 1771 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) 1772 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) 1773 return 1; 1774 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) 1775 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) 1776 return 1; 1777 } 1778 else 1779 { 1780 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) 1781 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) 1782 & MIPS16OP_MASK_RX)] 1783 == reg)) 1784 return 1; 1785 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) 1786 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) 1787 & MIPS16OP_MASK_RY)] 1788 == reg)) 1789 return 1; 1790 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) 1791 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) 1792 & MIPS16OP_MASK_MOVE32Z)] 1793 == reg)) 1794 return 1; 1795 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) 1796 return 1; 1797 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) 1798 return 1; 1799 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) 1800 return 1; 1801 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) 1802 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) 1803 & MIPS16OP_MASK_REGR32) == reg) 1804 return 1; 1805 } 1806 1807 return 0; 1808 } 1809 1810 /* This function returns true if modifying a register requires a 1811 delay. */ 1812 1813 static int 1814 reg_needs_delay (unsigned int reg) 1815 { 1816 unsigned long prev_pinfo; 1817 1818 prev_pinfo = prev_insn.insn_mo->pinfo; 1819 if (! mips_opts.noreorder 1820 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) 1821 && ! gpr_interlocks) 1822 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) 1823 && ! cop_interlocks))) 1824 { 1825 /* A load from a coprocessor or from memory. All load delays 1826 delay the use of general register rt for one instruction. */ 1827 /* Itbl support may require additional care here. */ 1828 know (prev_pinfo & INSN_WRITE_GPR_T); 1829 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) 1830 return 1; 1831 } 1832 1833 return 0; 1834 } 1835 1836 /* Mark instruction labels in mips16 mode. This permits the linker to 1837 handle them specially, such as generating jalx instructions when 1838 needed. We also make them odd for the duration of the assembly, in 1839 order to generate the right sort of code. We will make them even 1840 in the adjust_symtab routine, while leaving them marked. This is 1841 convenient for the debugger and the disassembler. The linker knows 1842 to make them odd again. */ 1843 1844 static void 1845 mips16_mark_labels (void) 1846 { 1847 if (mips_opts.mips16) 1848 { 1849 struct insn_label_list *l; 1850 valueT val; 1851 1852 for (l = insn_labels; l != NULL; l = l->next) 1853 { 1854 #ifdef OBJ_ELF 1855 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 1856 S_SET_OTHER (l->label, STO_MIPS16); 1857 #endif 1858 val = S_GET_VALUE (l->label); 1859 if ((val & 1) == 0) 1860 S_SET_VALUE (l->label, val + 1); 1861 } 1862 } 1863 } 1864 1865 /* End the current frag. Make it a variant frag and record the 1866 relaxation info. */ 1867 1868 static void 1869 relax_close_frag (void) 1870 { 1871 mips_macro_warning.first_frag = frag_now; 1872 frag_var (rs_machine_dependent, 0, 0, 1873 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), 1874 mips_relax.symbol, 0, (char *) mips_relax.first_fixup); 1875 1876 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); 1877 mips_relax.first_fixup = 0; 1878 } 1879 1880 /* Start a new relaxation sequence whose expansion depends on SYMBOL. 1881 See the comment above RELAX_ENCODE for more details. */ 1882 1883 static void 1884 relax_start (symbolS *symbol) 1885 { 1886 assert (mips_relax.sequence == 0); 1887 mips_relax.sequence = 1; 1888 mips_relax.symbol = symbol; 1889 } 1890 1891 /* Start generating the second version of a relaxable sequence. 1892 See the comment above RELAX_ENCODE for more details. */ 1893 1894 static void 1895 relax_switch (void) 1896 { 1897 assert (mips_relax.sequence == 1); 1898 mips_relax.sequence = 2; 1899 } 1900 1901 /* End the current relaxable sequence. */ 1902 1903 static void 1904 relax_end (void) 1905 { 1906 assert (mips_relax.sequence == 2); 1907 relax_close_frag (); 1908 mips_relax.sequence = 0; 1909 } 1910 1911 /* Output an instruction. IP is the instruction information. 1912 ADDRESS_EXPR is an operand of the instruction to be used with 1913 RELOC_TYPE. */ 1914 1915 static void 1916 append_insn (struct mips_cl_insn *ip, expressionS *address_expr, 1917 bfd_reloc_code_real_type *reloc_type) 1918 { 1919 register unsigned long prev_pinfo, pinfo; 1920 char *f; 1921 fixS *fixp[3]; 1922 int nops = 0; 1923 relax_stateT prev_insn_frag_type = 0; 1924 bfd_boolean relaxed_branch = FALSE; 1925 bfd_boolean force_new_frag = FALSE; 1926 1927 /* Mark instruction labels in mips16 mode. */ 1928 mips16_mark_labels (); 1929 1930 prev_pinfo = prev_insn.insn_mo->pinfo; 1931 pinfo = ip->insn_mo->pinfo; 1932 1933 if (mips_relax.sequence != 2 1934 && (!mips_opts.noreorder || prev_nop_frag != NULL)) 1935 { 1936 int prev_prev_nop; 1937 1938 /* If the previous insn required any delay slots, see if we need 1939 to insert a NOP or two. There are eight kinds of possible 1940 hazards, of which an instruction can have at most one type. 1941 (1) a load from memory delay 1942 (2) a load from a coprocessor delay 1943 (3) an unconditional branch delay 1944 (4) a conditional branch delay 1945 (5) a move to coprocessor register delay 1946 (6) a load coprocessor register from memory delay 1947 (7) a coprocessor condition code delay 1948 (8) a HI/LO special register delay 1949 1950 There are a lot of optimizations we could do that we don't. 1951 In particular, we do not, in general, reorder instructions. 1952 If you use gcc with optimization, it will reorder 1953 instructions and generally do much more optimization then we 1954 do here; repeating all that work in the assembler would only 1955 benefit hand written assembly code, and does not seem worth 1956 it. */ 1957 1958 /* This is how a NOP is emitted. */ 1959 #define emit_nop() \ 1960 (mips_opts.mips16 \ 1961 ? md_number_to_chars (frag_more (2), 0x6500, 2) \ 1962 : md_number_to_chars (frag_more (4), 0, 4)) 1963 1964 /* The previous insn might require a delay slot, depending upon 1965 the contents of the current insn. */ 1966 if (! mips_opts.mips16 1967 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) 1968 && ! gpr_interlocks) 1969 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) 1970 && ! cop_interlocks))) 1971 { 1972 /* A load from a coprocessor or from memory. All load 1973 delays delay the use of general register rt for one 1974 instruction. */ 1975 /* Itbl support may require additional care here. */ 1976 know (prev_pinfo & INSN_WRITE_GPR_T); 1977 if (mips_optimize == 0 1978 || insn_uses_reg (ip, 1979 ((prev_insn.insn_opcode >> OP_SH_RT) 1980 & OP_MASK_RT), 1981 MIPS_GR_REG)) 1982 ++nops; 1983 } 1984 else if (! mips_opts.mips16 1985 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) 1986 && ! cop_interlocks) 1987 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) 1988 && ! cop_mem_interlocks))) 1989 { 1990 /* A generic coprocessor delay. The previous instruction 1991 modified a coprocessor general or control register. If 1992 it modified a control register, we need to avoid any 1993 coprocessor instruction (this is probably not always 1994 required, but it sometimes is). If it modified a general 1995 register, we avoid using that register. 1996 1997 This case is not handled very well. There is no special 1998 knowledge of CP0 handling, and the coprocessors other 1999 than the floating point unit are not distinguished at 2000 all. */ 2001 /* Itbl support may require additional care here. FIXME! 2002 Need to modify this to include knowledge about 2003 user specified delays! */ 2004 if (prev_pinfo & INSN_WRITE_FPR_T) 2005 { 2006 if (mips_optimize == 0 2007 || insn_uses_reg (ip, 2008 ((prev_insn.insn_opcode >> OP_SH_FT) 2009 & OP_MASK_FT), 2010 MIPS_FP_REG)) 2011 ++nops; 2012 } 2013 else if (prev_pinfo & INSN_WRITE_FPR_S) 2014 { 2015 if (mips_optimize == 0 2016 || insn_uses_reg (ip, 2017 ((prev_insn.insn_opcode >> OP_SH_FS) 2018 & OP_MASK_FS), 2019 MIPS_FP_REG)) 2020 ++nops; 2021 } 2022 else 2023 { 2024 /* We don't know exactly what the previous instruction 2025 does. If the current instruction uses a coprocessor 2026 register, we must insert a NOP. If previous 2027 instruction may set the condition codes, and the 2028 current instruction uses them, we must insert two 2029 NOPS. */ 2030 /* Itbl support may require additional care here. */ 2031 if (mips_optimize == 0 2032 || ((prev_pinfo & INSN_WRITE_COND_CODE) 2033 && (pinfo & INSN_READ_COND_CODE))) 2034 nops += 2; 2035 else if (pinfo & INSN_COP) 2036 ++nops; 2037 } 2038 } 2039 else if (! mips_opts.mips16 2040 && (prev_pinfo & INSN_WRITE_COND_CODE) 2041 && ! cop_interlocks) 2042 { 2043 /* The previous instruction sets the coprocessor condition 2044 codes, but does not require a general coprocessor delay 2045 (this means it is a floating point comparison 2046 instruction). If this instruction uses the condition 2047 codes, we need to insert a single NOP. */ 2048 /* Itbl support may require additional care here. */ 2049 if (mips_optimize == 0 2050 || (pinfo & INSN_READ_COND_CODE)) 2051 ++nops; 2052 } 2053 2054 /* If we're fixing up mfhi/mflo for the r7000 and the 2055 previous insn was an mfhi/mflo and the current insn 2056 reads the register that the mfhi/mflo wrote to, then 2057 insert two nops. */ 2058 2059 else if (mips_7000_hilo_fix 2060 && MF_HILO_INSN (prev_pinfo) 2061 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) 2062 & OP_MASK_RD), 2063 MIPS_GR_REG)) 2064 { 2065 nops += 2; 2066 } 2067 2068 /* If we're fixing up mfhi/mflo for the r7000 and the 2069 2nd previous insn was an mfhi/mflo and the current insn 2070 reads the register that the mfhi/mflo wrote to, then 2071 insert one nop. */ 2072 2073 else if (mips_7000_hilo_fix 2074 && MF_HILO_INSN (prev_prev_insn.insn_opcode) 2075 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) 2076 & OP_MASK_RD), 2077 MIPS_GR_REG)) 2078 2079 { 2080 ++nops; 2081 } 2082 2083 else if (prev_pinfo & INSN_READ_LO) 2084 { 2085 /* The previous instruction reads the LO register; if the 2086 current instruction writes to the LO register, we must 2087 insert two NOPS. Some newer processors have interlocks. 2088 Also the tx39's multiply instructions can be executed 2089 immediately after a read from HI/LO (without the delay), 2090 though the tx39's divide insns still do require the 2091 delay. */ 2092 if (! (hilo_interlocks 2093 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) 2094 && (mips_optimize == 0 2095 || (pinfo & INSN_WRITE_LO))) 2096 nops += 2; 2097 /* Most mips16 branch insns don't have a delay slot. 2098 If a read from LO is immediately followed by a branch 2099 to a write to LO we have a read followed by a write 2100 less than 2 insns away. We assume the target of 2101 a branch might be a write to LO, and insert a nop 2102 between a read and an immediately following branch. */ 2103 else if (mips_opts.mips16 2104 && (mips_optimize == 0 2105 || (pinfo & MIPS16_INSN_BRANCH))) 2106 ++nops; 2107 } 2108 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) 2109 { 2110 /* The previous instruction reads the HI register; if the 2111 current instruction writes to the HI register, we must 2112 insert a NOP. Some newer processors have interlocks. 2113 Also the note tx39's multiply above. */ 2114 if (! (hilo_interlocks 2115 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) 2116 && (mips_optimize == 0 2117 || (pinfo & INSN_WRITE_HI))) 2118 nops += 2; 2119 /* Most mips16 branch insns don't have a delay slot. 2120 If a read from HI is immediately followed by a branch 2121 to a write to HI we have a read followed by a write 2122 less than 2 insns away. We assume the target of 2123 a branch might be a write to HI, and insert a nop 2124 between a read and an immediately following branch. */ 2125 else if (mips_opts.mips16 2126 && (mips_optimize == 0 2127 || (pinfo & MIPS16_INSN_BRANCH))) 2128 ++nops; 2129 } 2130 2131 /* If the previous instruction was in a noreorder section, then 2132 we don't want to insert the nop after all. */ 2133 /* Itbl support may require additional care here. */ 2134 if (prev_insn_unreordered) 2135 nops = 0; 2136 2137 /* There are two cases which require two intervening 2138 instructions: 1) setting the condition codes using a move to 2139 coprocessor instruction which requires a general coprocessor 2140 delay and then reading the condition codes 2) reading the HI 2141 or LO register and then writing to it (except on processors 2142 which have interlocks). If we are not already emitting a NOP 2143 instruction, we must check for these cases compared to the 2144 instruction previous to the previous instruction. */ 2145 if ((! mips_opts.mips16 2146 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) 2147 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) 2148 && (pinfo & INSN_READ_COND_CODE) 2149 && ! cop_interlocks) 2150 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) 2151 && (pinfo & INSN_WRITE_LO) 2152 && ! (hilo_interlocks 2153 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) 2154 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) 2155 && (pinfo & INSN_WRITE_HI) 2156 && ! (hilo_interlocks 2157 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) 2158 prev_prev_nop = 1; 2159 else 2160 prev_prev_nop = 0; 2161 2162 if (prev_prev_insn_unreordered) 2163 prev_prev_nop = 0; 2164 2165 if (prev_prev_nop && nops == 0) 2166 ++nops; 2167 2168 if (mips_fix_vr4120 && prev_insn.insn_mo->name) 2169 { 2170 /* We're out of bits in pinfo, so we must resort to string 2171 ops here. Shortcuts are selected based on opcodes being 2172 limited to the VR4120 instruction set. */ 2173 int min_nops = 0; 2174 const char *pn = prev_insn.insn_mo->name; 2175 const char *tn = ip->insn_mo->name; 2176 if (strncmp(pn, "macc", 4) == 0 2177 || strncmp(pn, "dmacc", 5) == 0) 2178 { 2179 /* Errata 21 - [D]DIV[U] after [D]MACC */ 2180 if (strstr (tn, "div")) 2181 { 2182 min_nops = 1; 2183 } 2184 2185 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ 2186 if (pn[0] == 'd' /* dmacc */ 2187 && (strncmp(tn, "dmult", 5) == 0 2188 || strncmp(tn, "dmacc", 5) == 0)) 2189 { 2190 min_nops = 1; 2191 } 2192 2193 /* Errata 24 - MT{LO,HI} after [D]MACC */ 2194 if (strcmp (tn, "mtlo") == 0 2195 || strcmp (tn, "mthi") == 0) 2196 { 2197 min_nops = 1; 2198 } 2199 2200 } 2201 else if (strncmp(pn, "dmult", 5) == 0 2202 && (strncmp(tn, "dmult", 5) == 0 2203 || strncmp(tn, "dmacc", 5) == 0)) 2204 { 2205 /* Here is the rest of errata 23. */ 2206 min_nops = 1; 2207 } 2208 if (nops < min_nops) 2209 nops = min_nops; 2210 } 2211 2212 /* If we are being given a nop instruction, don't bother with 2213 one of the nops we would otherwise output. This will only 2214 happen when a nop instruction is used with mips_optimize set 2215 to 0. */ 2216 if (nops > 0 2217 && ! mips_opts.noreorder 2218 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) 2219 --nops; 2220 2221 /* Now emit the right number of NOP instructions. */ 2222 if (nops > 0 && ! mips_opts.noreorder) 2223 { 2224 fragS *old_frag; 2225 unsigned long old_frag_offset; 2226 int i; 2227 struct insn_label_list *l; 2228 2229 old_frag = frag_now; 2230 old_frag_offset = frag_now_fix (); 2231 2232 for (i = 0; i < nops; i++) 2233 emit_nop (); 2234 2235 if (listing) 2236 { 2237 listing_prev_line (); 2238 /* We may be at the start of a variant frag. In case we 2239 are, make sure there is enough space for the frag 2240 after the frags created by listing_prev_line. The 2241 argument to frag_grow here must be at least as large 2242 as the argument to all other calls to frag_grow in 2243 this file. We don't have to worry about being in the 2244 middle of a variant frag, because the variants insert 2245 all needed nop instructions themselves. */ 2246 frag_grow (40); 2247 } 2248 2249 for (l = insn_labels; l != NULL; l = l->next) 2250 { 2251 valueT val; 2252 2253 assert (S_GET_SEGMENT (l->label) == now_seg); 2254 symbol_set_frag (l->label, frag_now); 2255 val = (valueT) frag_now_fix (); 2256 /* mips16 text labels are stored as odd. */ 2257 if (mips_opts.mips16) 2258 ++val; 2259 S_SET_VALUE (l->label, val); 2260 } 2261 2262 #ifndef NO_ECOFF_DEBUGGING 2263 if (ECOFF_DEBUGGING) 2264 ecoff_fix_loc (old_frag, old_frag_offset); 2265 #endif 2266 } 2267 else if (prev_nop_frag != NULL) 2268 { 2269 /* We have a frag holding nops we may be able to remove. If 2270 we don't need any nops, we can decrease the size of 2271 prev_nop_frag by the size of one instruction. If we do 2272 need some nops, we count them in prev_nops_required. */ 2273 if (prev_nop_frag_since == 0) 2274 { 2275 if (nops == 0) 2276 { 2277 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; 2278 --prev_nop_frag_holds; 2279 } 2280 else 2281 prev_nop_frag_required += nops; 2282 } 2283 else 2284 { 2285 if (prev_prev_nop == 0) 2286 { 2287 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; 2288 --prev_nop_frag_holds; 2289 } 2290 else 2291 ++prev_nop_frag_required; 2292 } 2293 2294 if (prev_nop_frag_holds <= prev_nop_frag_required) 2295 prev_nop_frag = NULL; 2296 2297 ++prev_nop_frag_since; 2298 2299 /* Sanity check: by the time we reach the second instruction 2300 after prev_nop_frag, we should have used up all the nops 2301 one way or another. */ 2302 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); 2303 } 2304 } 2305 2306 /* Record the frag type before frag_var. */ 2307 if (prev_insn_frag) 2308 prev_insn_frag_type = prev_insn_frag->fr_type; 2309 2310 if (address_expr 2311 && *reloc_type == BFD_RELOC_16_PCREL_S2 2312 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY 2313 || pinfo & INSN_COND_BRANCH_LIKELY) 2314 && mips_relax_branch 2315 /* Don't try branch relaxation within .set nomacro, or within 2316 .set noat if we use $at for PIC computations. If it turns 2317 out that the branch was out-of-range, we'll get an error. */ 2318 && !mips_opts.warn_about_macros 2319 && !(mips_opts.noat && mips_pic != NO_PIC) 2320 && !mips_opts.mips16) 2321 { 2322 relaxed_branch = TRUE; 2323 f = frag_var (rs_machine_dependent, 2324 relaxed_branch_length 2325 (NULL, NULL, 2326 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 2327 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, 2328 RELAX_BRANCH_ENCODE 2329 (pinfo & INSN_UNCOND_BRANCH_DELAY, 2330 pinfo & INSN_COND_BRANCH_LIKELY, 2331 pinfo & INSN_WRITE_GPR_31, 2332 0), 2333 address_expr->X_add_symbol, 2334 address_expr->X_add_number, 2335 0); 2336 *reloc_type = BFD_RELOC_UNUSED; 2337 } 2338 else if (*reloc_type > BFD_RELOC_UNUSED) 2339 { 2340 /* We need to set up a variant frag. */ 2341 assert (mips_opts.mips16 && address_expr != NULL); 2342 f = frag_var (rs_machine_dependent, 4, 0, 2343 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, 2344 mips16_small, mips16_ext, 2345 (prev_pinfo 2346 & INSN_UNCOND_BRANCH_DELAY), 2347 (*prev_insn_reloc_type 2348 == BFD_RELOC_MIPS16_JMP)), 2349 make_expr_symbol (address_expr), 0, NULL); 2350 } 2351 else if (mips_opts.mips16 2352 && ! ip->use_extend 2353 && *reloc_type != BFD_RELOC_MIPS16_JMP) 2354 { 2355 /* Make sure there is enough room to swap this instruction with 2356 a following jump instruction. */ 2357 frag_grow (6); 2358 f = frag_more (2); 2359 } 2360 else 2361 { 2362 if (mips_opts.mips16 2363 && mips_opts.noreorder 2364 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 2365 as_warn (_("extended instruction in delay slot")); 2366 2367 if (mips_relax.sequence) 2368 { 2369 /* If we've reached the end of this frag, turn it into a variant 2370 frag and record the information for the instructions we've 2371 written so far. */ 2372 if (frag_room () < 4) 2373 relax_close_frag (); 2374 mips_relax.sizes[mips_relax.sequence - 1] += 4; 2375 } 2376 2377 if (mips_relax.sequence != 2) 2378 mips_macro_warning.sizes[0] += 4; 2379 if (mips_relax.sequence != 1) 2380 mips_macro_warning.sizes[1] += 4; 2381 2382 f = frag_more (4); 2383 } 2384 2385 fixp[0] = fixp[1] = fixp[2] = NULL; 2386 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) 2387 { 2388 if (address_expr->X_op == O_constant) 2389 { 2390 valueT tmp; 2391 2392 switch (*reloc_type) 2393 { 2394 case BFD_RELOC_32: 2395 ip->insn_opcode |= address_expr->X_add_number; 2396 break; 2397 2398 case BFD_RELOC_MIPS_HIGHEST: 2399 tmp = (address_expr->X_add_number 2400 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; 2401 tmp >>= 16; 2402 ip->insn_opcode |= (tmp >> 16) & 0xffff; 2403 break; 2404 2405 case BFD_RELOC_MIPS_HIGHER: 2406 tmp = (address_expr->X_add_number + 0x80008000) >> 16; 2407 ip->insn_opcode |= (tmp >> 16) & 0xffff; 2408 break; 2409 2410 case BFD_RELOC_HI16_S: 2411 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) 2412 >> 16) & 0xffff; 2413 break; 2414 2415 case BFD_RELOC_HI16: 2416 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; 2417 break; 2418 2419 case BFD_RELOC_LO16: 2420 case BFD_RELOC_MIPS_GOT_DISP: 2421 ip->insn_opcode |= address_expr->X_add_number & 0xffff; 2422 break; 2423 2424 case BFD_RELOC_MIPS_JMP: 2425 if ((address_expr->X_add_number & 3) != 0) 2426 as_bad (_("jump to misaligned address (0x%lx)"), 2427 (unsigned long) address_expr->X_add_number); 2428 if (address_expr->X_add_number & ~0xfffffff) 2429 as_bad (_("jump address range overflow (0x%lx)"), 2430 (unsigned long) address_expr->X_add_number); 2431 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; 2432 break; 2433 2434 case BFD_RELOC_MIPS16_JMP: 2435 if ((address_expr->X_add_number & 3) != 0) 2436 as_bad (_("jump to misaligned address (0x%lx)"), 2437 (unsigned long) address_expr->X_add_number); 2438 if (address_expr->X_add_number & ~0xfffffff) 2439 as_bad (_("jump address range overflow (0x%lx)"), 2440 (unsigned long) address_expr->X_add_number); 2441 ip->insn_opcode |= 2442 (((address_expr->X_add_number & 0x7c0000) << 3) 2443 | ((address_expr->X_add_number & 0xf800000) >> 7) 2444 | ((address_expr->X_add_number & 0x3fffc) >> 2)); 2445 break; 2446 2447 case BFD_RELOC_16_PCREL_S2: 2448 goto need_reloc; 2449 2450 default: 2451 internalError (); 2452 } 2453 } 2454 else 2455 need_reloc: 2456 { 2457 reloc_howto_type *howto; 2458 int i; 2459 2460 /* In a compound relocation, it is the final (outermost) 2461 operator that determines the relocated field. */ 2462 for (i = 1; i < 3; i++) 2463 if (reloc_type[i] == BFD_RELOC_UNUSED) 2464 break; 2465 2466 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); 2467 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 2468 bfd_get_reloc_size(howto), 2469 address_expr, 2470 reloc_type[0] == BFD_RELOC_16_PCREL_S2, 2471 reloc_type[0]); 2472 2473 /* These relocations can have an addend that won't fit in 2474 4 octets for 64bit assembly. */ 2475 if (HAVE_64BIT_GPRS 2476 && ! howto->partial_inplace 2477 && (reloc_type[0] == BFD_RELOC_16 2478 || reloc_type[0] == BFD_RELOC_32 2479 || reloc_type[0] == BFD_RELOC_MIPS_JMP 2480 || reloc_type[0] == BFD_RELOC_HI16_S 2481 || reloc_type[0] == BFD_RELOC_LO16 2482 || reloc_type[0] == BFD_RELOC_GPREL16 2483 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL 2484 || reloc_type[0] == BFD_RELOC_GPREL32 2485 || reloc_type[0] == BFD_RELOC_64 2486 || reloc_type[0] == BFD_RELOC_CTOR 2487 || reloc_type[0] == BFD_RELOC_MIPS_SUB 2488 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST 2489 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER 2490 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP 2491 || reloc_type[0] == BFD_RELOC_MIPS_REL16 2492 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) 2493 fixp[0]->fx_no_overflow = 1; 2494 2495 if (mips_relax.sequence) 2496 { 2497 if (mips_relax.first_fixup == 0) 2498 mips_relax.first_fixup = fixp[0]; 2499 } 2500 else if (reloc_needs_lo_p (*reloc_type)) 2501 { 2502 struct mips_hi_fixup *hi_fixup; 2503 2504 /* Reuse the last entry if it already has a matching %lo. */ 2505 hi_fixup = mips_hi_fixup_list; 2506 if (hi_fixup == 0 2507 || !fixup_has_matching_lo_p (hi_fixup->fixp)) 2508 { 2509 hi_fixup = ((struct mips_hi_fixup *) 2510 xmalloc (sizeof (struct mips_hi_fixup))); 2511 hi_fixup->next = mips_hi_fixup_list; 2512 mips_hi_fixup_list = hi_fixup; 2513 } 2514 hi_fixup->fixp = fixp[0]; 2515 hi_fixup->seg = now_seg; 2516 } 2517 2518 /* Add fixups for the second and third relocations, if given. 2519 Note that the ABI allows the second relocation to be 2520 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the 2521 moment we only use RSS_UNDEF, but we could add support 2522 for the others if it ever becomes necessary. */ 2523 for (i = 1; i < 3; i++) 2524 if (reloc_type[i] != BFD_RELOC_UNUSED) 2525 { 2526 address_expr->X_op = O_absent; 2527 address_expr->X_add_symbol = 0; 2528 address_expr->X_add_number = 0; 2529 2530 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, 2531 fixp[0]->fx_size, address_expr, 2532 FALSE, reloc_type[i]); 2533 } 2534 } 2535 } 2536 2537 if (! mips_opts.mips16) 2538 { 2539 md_number_to_chars (f, ip->insn_opcode, 4); 2540 #ifdef OBJ_ELF 2541 dwarf2_emit_insn (4); 2542 #endif 2543 } 2544 else if (*reloc_type == BFD_RELOC_MIPS16_JMP) 2545 { 2546 md_number_to_chars (f, ip->insn_opcode >> 16, 2); 2547 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); 2548 #ifdef OBJ_ELF 2549 dwarf2_emit_insn (4); 2550 #endif 2551 } 2552 else 2553 { 2554 if (ip->use_extend) 2555 { 2556 md_number_to_chars (f, 0xf000 | ip->extend, 2); 2557 f += 2; 2558 } 2559 md_number_to_chars (f, ip->insn_opcode, 2); 2560 #ifdef OBJ_ELF 2561 dwarf2_emit_insn (ip->use_extend ? 4 : 2); 2562 #endif 2563 } 2564 2565 /* Update the register mask information. */ 2566 if (! mips_opts.mips16) 2567 { 2568 if (pinfo & INSN_WRITE_GPR_D) 2569 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); 2570 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) 2571 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); 2572 if (pinfo & INSN_READ_GPR_S) 2573 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); 2574 if (pinfo & INSN_WRITE_GPR_31) 2575 mips_gprmask |= 1 << RA; 2576 if (pinfo & INSN_WRITE_FPR_D) 2577 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); 2578 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) 2579 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); 2580 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) 2581 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); 2582 if ((pinfo & INSN_READ_FPR_R) != 0) 2583 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); 2584 if (pinfo & INSN_COP) 2585 { 2586 /* We don't keep enough information to sort these cases out. 2587 The itbl support does keep this information however, although 2588 we currently don't support itbl fprmats as part of the cop 2589 instruction. May want to add this support in the future. */ 2590 } 2591 /* Never set the bit for $0, which is always zero. */ 2592 mips_gprmask &= ~1 << 0; 2593 } 2594 else 2595 { 2596 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) 2597 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) 2598 & MIPS16OP_MASK_RX); 2599 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) 2600 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) 2601 & MIPS16OP_MASK_RY); 2602 if (pinfo & MIPS16_INSN_WRITE_Z) 2603 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) 2604 & MIPS16OP_MASK_RZ); 2605 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) 2606 mips_gprmask |= 1 << TREG; 2607 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) 2608 mips_gprmask |= 1 << SP; 2609 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) 2610 mips_gprmask |= 1 << RA; 2611 if (pinfo & MIPS16_INSN_WRITE_GPR_Y) 2612 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); 2613 if (pinfo & MIPS16_INSN_READ_Z) 2614 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) 2615 & MIPS16OP_MASK_MOVE32Z); 2616 if (pinfo & MIPS16_INSN_READ_GPR_X) 2617 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) 2618 & MIPS16OP_MASK_REGR32); 2619 } 2620 2621 if (mips_relax.sequence != 2 && !mips_opts.noreorder) 2622 { 2623 /* Filling the branch delay slot is more complex. We try to 2624 switch the branch with the previous instruction, which we can 2625 do if the previous instruction does not set up a condition 2626 that the branch tests and if the branch is not itself the 2627 target of any branch. */ 2628 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) 2629 || (pinfo & INSN_COND_BRANCH_DELAY)) 2630 { 2631 if (mips_optimize < 2 2632 /* If we have seen .set volatile or .set nomove, don't 2633 optimize. */ 2634 || mips_opts.nomove != 0 2635 /* If we had to emit any NOP instructions, then we 2636 already know we can not swap. */ 2637 || nops != 0 2638 /* If we don't even know the previous insn, we can not 2639 swap. */ 2640 || ! prev_insn_valid 2641 /* If the previous insn is already in a branch delay 2642 slot, then we can not swap. */ 2643 || prev_insn_is_delay_slot 2644 /* If the previous previous insn was in a .set 2645 noreorder, we can't swap. Actually, the MIPS 2646 assembler will swap in this situation. However, gcc 2647 configured -with-gnu-as will generate code like 2648 .set noreorder 2649 lw $4,XXX 2650 .set reorder 2651 INSN 2652 bne $4,$0,foo 2653 in which we can not swap the bne and INSN. If gcc is 2654 not configured -with-gnu-as, it does not output the 2655 .set pseudo-ops. We don't have to check 2656 prev_insn_unreordered, because prev_insn_valid will 2657 be 0 in that case. We don't want to use 2658 prev_prev_insn_valid, because we do want to be able 2659 to swap at the start of a function. */ 2660 || prev_prev_insn_unreordered 2661 /* If the branch is itself the target of a branch, we 2662 can not swap. We cheat on this; all we check for is 2663 whether there is a label on this instruction. If 2664 there are any branches to anything other than a 2665 label, users must use .set noreorder. */ 2666 || insn_labels != NULL 2667 /* If the previous instruction is in a variant frag 2668 other than this branch's one, we cannot do the swap. 2669 This does not apply to the mips16, which uses variant 2670 frags for different purposes. */ 2671 || (! mips_opts.mips16 2672 && prev_insn_frag_type == rs_machine_dependent) 2673 /* If the branch reads the condition codes, we don't 2674 even try to swap, because in the sequence 2675 ctc1 $X,$31 2676 INSN 2677 INSN 2678 bc1t LABEL 2679 we can not swap, and I don't feel like handling that 2680 case. */ 2681 || (! mips_opts.mips16 2682 && (pinfo & INSN_READ_COND_CODE) 2683 && ! cop_interlocks) 2684 /* We can not swap with an instruction that requires a 2685 delay slot, because the target of the branch might 2686 interfere with that instruction. */ 2687 || (! mips_opts.mips16 2688 && (prev_pinfo 2689 /* Itbl support may require additional care here. */ 2690 & (INSN_LOAD_COPROC_DELAY 2691 | INSN_COPROC_MOVE_DELAY 2692 | INSN_WRITE_COND_CODE)) 2693 && ! cop_interlocks) 2694 || (! (hilo_interlocks 2695 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) 2696 && (prev_pinfo 2697 & (INSN_READ_LO 2698 | INSN_READ_HI))) 2699 || (! mips_opts.mips16 2700 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) 2701 && ! gpr_interlocks) 2702 || (! mips_opts.mips16 2703 /* Itbl support may require additional care here. */ 2704 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) 2705 && ! cop_mem_interlocks) 2706 /* We can not swap with a branch instruction. */ 2707 || (prev_pinfo 2708 & (INSN_UNCOND_BRANCH_DELAY 2709 | INSN_COND_BRANCH_DELAY 2710 | INSN_COND_BRANCH_LIKELY)) 2711 /* We do not swap with a trap instruction, since it 2712 complicates trap handlers to have the trap 2713 instruction be in a delay slot. */ 2714 || (prev_pinfo & INSN_TRAP) 2715 /* If the branch reads a register that the previous 2716 instruction sets, we can not swap. */ 2717 || (! mips_opts.mips16 2718 && (prev_pinfo & INSN_WRITE_GPR_T) 2719 && insn_uses_reg (ip, 2720 ((prev_insn.insn_opcode >> OP_SH_RT) 2721 & OP_MASK_RT), 2722 MIPS_GR_REG)) 2723 || (! mips_opts.mips16 2724 && (prev_pinfo & INSN_WRITE_GPR_D) 2725 && insn_uses_reg (ip, 2726 ((prev_insn.insn_opcode >> OP_SH_RD) 2727 & OP_MASK_RD), 2728 MIPS_GR_REG)) 2729 || (mips_opts.mips16 2730 && (((prev_pinfo & MIPS16_INSN_WRITE_X) 2731 && insn_uses_reg (ip, 2732 ((prev_insn.insn_opcode 2733 >> MIPS16OP_SH_RX) 2734 & MIPS16OP_MASK_RX), 2735 MIPS16_REG)) 2736 || ((prev_pinfo & MIPS16_INSN_WRITE_Y) 2737 && insn_uses_reg (ip, 2738 ((prev_insn.insn_opcode 2739 >> MIPS16OP_SH_RY) 2740 & MIPS16OP_MASK_RY), 2741 MIPS16_REG)) 2742 || ((prev_pinfo & MIPS16_INSN_WRITE_Z) 2743 && insn_uses_reg (ip, 2744 ((prev_insn.insn_opcode 2745 >> MIPS16OP_SH_RZ) 2746 & MIPS16OP_MASK_RZ), 2747 MIPS16_REG)) 2748 || ((prev_pinfo & MIPS16_INSN_WRITE_T) 2749 && insn_uses_reg (ip, TREG, MIPS_GR_REG)) 2750 || ((prev_pinfo & MIPS16_INSN_WRITE_31) 2751 && insn_uses_reg (ip, RA, MIPS_GR_REG)) 2752 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) 2753 && insn_uses_reg (ip, 2754 MIPS16OP_EXTRACT_REG32R (prev_insn. 2755 insn_opcode), 2756 MIPS_GR_REG)))) 2757 /* If the branch writes a register that the previous 2758 instruction sets, we can not swap (we know that 2759 branches write only to RD or to $31). */ 2760 || (! mips_opts.mips16 2761 && (prev_pinfo & INSN_WRITE_GPR_T) 2762 && (((pinfo & INSN_WRITE_GPR_D) 2763 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) 2764 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) 2765 || ((pinfo & INSN_WRITE_GPR_31) 2766 && (((prev_insn.insn_opcode >> OP_SH_RT) 2767 & OP_MASK_RT) 2768 == RA)))) 2769 || (! mips_opts.mips16 2770 && (prev_pinfo & INSN_WRITE_GPR_D) 2771 && (((pinfo & INSN_WRITE_GPR_D) 2772 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) 2773 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) 2774 || ((pinfo & INSN_WRITE_GPR_31) 2775 && (((prev_insn.insn_opcode >> OP_SH_RD) 2776 & OP_MASK_RD) 2777 == RA)))) 2778 || (mips_opts.mips16 2779 && (pinfo & MIPS16_INSN_WRITE_31) 2780 && ((prev_pinfo & MIPS16_INSN_WRITE_31) 2781 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) 2782 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) 2783 == RA)))) 2784 /* If the branch writes a register that the previous 2785 instruction reads, we can not swap (we know that 2786 branches only write to RD or to $31). */ 2787 || (! mips_opts.mips16 2788 && (pinfo & INSN_WRITE_GPR_D) 2789 && insn_uses_reg (&prev_insn, 2790 ((ip->insn_opcode >> OP_SH_RD) 2791 & OP_MASK_RD), 2792 MIPS_GR_REG)) 2793 || (! mips_opts.mips16 2794 && (pinfo & INSN_WRITE_GPR_31) 2795 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) 2796 || (mips_opts.mips16 2797 && (pinfo & MIPS16_INSN_WRITE_31) 2798 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) 2799 /* If we are generating embedded PIC code, the branch 2800 might be expanded into a sequence which uses $at, so 2801 we can't swap with an instruction which reads it. */ 2802 || (mips_pic == EMBEDDED_PIC 2803 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) 2804 /* If the previous previous instruction has a load 2805 delay, and sets a register that the branch reads, we 2806 can not swap. */ 2807 || (! mips_opts.mips16 2808 /* Itbl support may require additional care here. */ 2809 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) 2810 && ! cop_interlocks) 2811 || ((prev_prev_insn.insn_mo->pinfo 2812 & INSN_LOAD_MEMORY_DELAY) 2813 && ! gpr_interlocks)) 2814 && insn_uses_reg (ip, 2815 ((prev_prev_insn.insn_opcode >> OP_SH_RT) 2816 & OP_MASK_RT), 2817 MIPS_GR_REG)) 2818 /* If one instruction sets a condition code and the 2819 other one uses a condition code, we can not swap. */ 2820 || ((pinfo & INSN_READ_COND_CODE) 2821 && (prev_pinfo & INSN_WRITE_COND_CODE)) 2822 || ((pinfo & INSN_WRITE_COND_CODE) 2823 && (prev_pinfo & INSN_READ_COND_CODE)) 2824 /* If the previous instruction uses the PC, we can not 2825 swap. */ 2826 || (mips_opts.mips16 2827 && (prev_pinfo & MIPS16_INSN_READ_PC)) 2828 /* If the previous instruction was extended, we can not 2829 swap. */ 2830 || (mips_opts.mips16 && prev_insn_extended) 2831 /* If the previous instruction had a fixup in mips16 2832 mode, we can not swap. This normally means that the 2833 previous instruction was a 4 byte branch anyhow. */ 2834 || (mips_opts.mips16 && prev_insn_fixp[0]) 2835 /* If the previous instruction is a sync, sync.l, or 2836 sync.p, we can not swap. */ 2837 || (prev_pinfo & INSN_SYNC)) 2838 { 2839 /* We could do even better for unconditional branches to 2840 portions of this object file; we could pick up the 2841 instruction at the destination, put it in the delay 2842 slot, and bump the destination address. */ 2843 emit_nop (); 2844 /* Update the previous insn information. */ 2845 prev_prev_insn = *ip; 2846 prev_insn.insn_mo = &dummy_opcode; 2847 } 2848 else 2849 { 2850 /* It looks like we can actually do the swap. */ 2851 if (! mips_opts.mips16) 2852 { 2853 char *prev_f; 2854 char temp[4]; 2855 2856 prev_f = prev_insn_frag->fr_literal + prev_insn_where; 2857 if (!relaxed_branch) 2858 { 2859 /* If this is not a relaxed branch, then just 2860 swap the instructions. */ 2861 memcpy (temp, prev_f, 4); 2862 memcpy (prev_f, f, 4); 2863 memcpy (f, temp, 4); 2864 } 2865 else 2866 { 2867 /* If this is a relaxed branch, then we move the 2868 instruction to be placed in the delay slot to 2869 the current frag, shrinking the fixed part of 2870 the originating frag. If the branch occupies 2871 the tail of the latter, we move it backwards, 2872 into the space freed by the moved instruction. */ 2873 f = frag_more (4); 2874 memcpy (f, prev_f, 4); 2875 prev_insn_frag->fr_fix -= 4; 2876 if (prev_insn_frag->fr_type == rs_machine_dependent) 2877 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var); 2878 } 2879 2880 if (prev_insn_fixp[0]) 2881 { 2882 prev_insn_fixp[0]->fx_frag = frag_now; 2883 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; 2884 } 2885 if (prev_insn_fixp[1]) 2886 { 2887 prev_insn_fixp[1]->fx_frag = frag_now; 2888 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; 2889 } 2890 if (prev_insn_fixp[2]) 2891 { 2892 prev_insn_fixp[2]->fx_frag = frag_now; 2893 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; 2894 } 2895 if (prev_insn_fixp[0] && HAVE_NEWABI 2896 && prev_insn_frag != frag_now 2897 && (prev_insn_fixp[0]->fx_r_type 2898 == BFD_RELOC_MIPS_GOT_DISP 2899 || (prev_insn_fixp[0]->fx_r_type 2900 == BFD_RELOC_MIPS_CALL16))) 2901 { 2902 /* To avoid confusion in tc_gen_reloc, we must 2903 ensure that this does not become a variant 2904 frag. */ 2905 force_new_frag = TRUE; 2906 } 2907 2908 if (!relaxed_branch) 2909 { 2910 if (fixp[0]) 2911 { 2912 fixp[0]->fx_frag = prev_insn_frag; 2913 fixp[0]->fx_where = prev_insn_where; 2914 } 2915 if (fixp[1]) 2916 { 2917 fixp[1]->fx_frag = prev_insn_frag; 2918 fixp[1]->fx_where = prev_insn_where; 2919 } 2920 if (fixp[2]) 2921 { 2922 fixp[2]->fx_frag = prev_insn_frag; 2923 fixp[2]->fx_where = prev_insn_where; 2924 } 2925 } 2926 else if (prev_insn_frag->fr_type == rs_machine_dependent) 2927 { 2928 if (fixp[0]) 2929 fixp[0]->fx_where -= 4; 2930 if (fixp[1]) 2931 fixp[1]->fx_where -= 4; 2932 if (fixp[2]) 2933 fixp[2]->fx_where -= 4; 2934 } 2935 } 2936 else 2937 { 2938 char *prev_f; 2939 char temp[2]; 2940 2941 assert (prev_insn_fixp[0] == NULL); 2942 assert (prev_insn_fixp[1] == NULL); 2943 assert (prev_insn_fixp[2] == NULL); 2944 prev_f = prev_insn_frag->fr_literal + prev_insn_where; 2945 memcpy (temp, prev_f, 2); 2946 memcpy (prev_f, f, 2); 2947 if (*reloc_type != BFD_RELOC_MIPS16_JMP) 2948 { 2949 assert (*reloc_type == BFD_RELOC_UNUSED); 2950 memcpy (f, temp, 2); 2951 } 2952 else 2953 { 2954 memcpy (f, f + 2, 2); 2955 memcpy (f + 2, temp, 2); 2956 } 2957 if (fixp[0]) 2958 { 2959 fixp[0]->fx_frag = prev_insn_frag; 2960 fixp[0]->fx_where = prev_insn_where; 2961 } 2962 if (fixp[1]) 2963 { 2964 fixp[1]->fx_frag = prev_insn_frag; 2965 fixp[1]->fx_where = prev_insn_where; 2966 } 2967 if (fixp[2]) 2968 { 2969 fixp[2]->fx_frag = prev_insn_frag; 2970 fixp[2]->fx_where = prev_insn_where; 2971 } 2972 } 2973 2974 /* Update the previous insn information; leave prev_insn 2975 unchanged. */ 2976 prev_prev_insn = *ip; 2977 } 2978 prev_insn_is_delay_slot = 1; 2979 2980 /* If that was an unconditional branch, forget the previous 2981 insn information. */ 2982 if (pinfo & INSN_UNCOND_BRANCH_DELAY) 2983 { 2984 prev_prev_insn.insn_mo = &dummy_opcode; 2985 prev_insn.insn_mo = &dummy_opcode; 2986 } 2987 2988 prev_insn_fixp[0] = NULL; 2989 prev_insn_fixp[1] = NULL; 2990 prev_insn_fixp[2] = NULL; 2991 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; 2992 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; 2993 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; 2994 prev_insn_extended = 0; 2995 } 2996 else if (pinfo & INSN_COND_BRANCH_LIKELY) 2997 { 2998 /* We don't yet optimize a branch likely. What we should do 2999 is look at the target, copy the instruction found there 3000 into the delay slot, and increment the branch to jump to 3001 the next instruction. */ 3002 emit_nop (); 3003 /* Update the previous insn information. */ 3004 prev_prev_insn = *ip; 3005 prev_insn.insn_mo = &dummy_opcode; 3006 prev_insn_fixp[0] = NULL; 3007 prev_insn_fixp[1] = NULL; 3008 prev_insn_fixp[2] = NULL; 3009 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; 3010 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; 3011 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; 3012 prev_insn_extended = 0; 3013 } 3014 else 3015 { 3016 /* Update the previous insn information. */ 3017 if (nops > 0) 3018 prev_prev_insn.insn_mo = &dummy_opcode; 3019 else 3020 prev_prev_insn = prev_insn; 3021 prev_insn = *ip; 3022 3023 /* Any time we see a branch, we always fill the delay slot 3024 immediately; since this insn is not a branch, we know it 3025 is not in a delay slot. */ 3026 prev_insn_is_delay_slot = 0; 3027 3028 prev_insn_fixp[0] = fixp[0]; 3029 prev_insn_fixp[1] = fixp[1]; 3030 prev_insn_fixp[2] = fixp[2]; 3031 prev_insn_reloc_type[0] = reloc_type[0]; 3032 prev_insn_reloc_type[1] = reloc_type[1]; 3033 prev_insn_reloc_type[2] = reloc_type[2]; 3034 if (mips_opts.mips16) 3035 prev_insn_extended = (ip->use_extend 3036 || *reloc_type > BFD_RELOC_UNUSED); 3037 } 3038 3039 prev_prev_insn_unreordered = prev_insn_unreordered; 3040 prev_insn_unreordered = 0; 3041 prev_insn_frag = frag_now; 3042 prev_insn_where = f - frag_now->fr_literal; 3043 prev_insn_valid = 1; 3044 } 3045 else if (mips_relax.sequence != 2) 3046 { 3047 /* We need to record a bit of information even when we are not 3048 reordering, in order to determine the base address for mips16 3049 PC relative relocs. */ 3050 prev_prev_insn = prev_insn; 3051 prev_insn = *ip; 3052 prev_insn_reloc_type[0] = reloc_type[0]; 3053 prev_insn_reloc_type[1] = reloc_type[1]; 3054 prev_insn_reloc_type[2] = reloc_type[2]; 3055 prev_prev_insn_unreordered = prev_insn_unreordered; 3056 prev_insn_unreordered = 1; 3057 } 3058 3059 /* We just output an insn, so the next one doesn't have a label. */ 3060 mips_clear_insn_labels (); 3061 } 3062 3063 /* This function forgets that there was any previous instruction or 3064 label. If PRESERVE is non-zero, it remembers enough information to 3065 know whether nops are needed before a noreorder section. */ 3066 3067 static void 3068 mips_no_prev_insn (int preserve) 3069 { 3070 if (! preserve) 3071 { 3072 prev_insn.insn_mo = &dummy_opcode; 3073 prev_prev_insn.insn_mo = &dummy_opcode; 3074 prev_nop_frag = NULL; 3075 prev_nop_frag_holds = 0; 3076 prev_nop_frag_required = 0; 3077 prev_nop_frag_since = 0; 3078 } 3079 prev_insn_valid = 0; 3080 prev_insn_is_delay_slot = 0; 3081 prev_insn_unreordered = 0; 3082 prev_insn_extended = 0; 3083 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; 3084 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; 3085 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; 3086 prev_prev_insn_unreordered = 0; 3087 mips_clear_insn_labels (); 3088 } 3089 3090 /* This function must be called whenever we turn on noreorder or emit 3091 something other than instructions. It inserts any NOPS which might 3092 be needed by the previous instruction, and clears the information 3093 kept for the previous instructions. The INSNS parameter is true if 3094 instructions are to follow. */ 3095 3096 static void 3097 mips_emit_delays (bfd_boolean insns) 3098 { 3099 if (! mips_opts.noreorder) 3100 { 3101 int nops; 3102 3103 nops = 0; 3104 if ((! mips_opts.mips16 3105 && ((prev_insn.insn_mo->pinfo 3106 & (INSN_LOAD_COPROC_DELAY 3107 | INSN_COPROC_MOVE_DELAY 3108 | INSN_WRITE_COND_CODE)) 3109 && ! cop_interlocks)) 3110 || (! hilo_interlocks 3111 && (prev_insn.insn_mo->pinfo 3112 & (INSN_READ_LO 3113 | INSN_READ_HI))) 3114 || (! mips_opts.mips16 3115 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) 3116 && ! gpr_interlocks) 3117 || (! mips_opts.mips16 3118 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) 3119 && ! cop_mem_interlocks)) 3120 { 3121 /* Itbl support may require additional care here. */ 3122 ++nops; 3123 if ((! mips_opts.mips16 3124 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) 3125 && ! cop_interlocks)) 3126 || (! hilo_interlocks 3127 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) 3128 || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) 3129 ++nops; 3130 3131 if (prev_insn_unreordered) 3132 nops = 0; 3133 } 3134 else if ((! mips_opts.mips16 3135 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) 3136 && ! cop_interlocks)) 3137 || (! hilo_interlocks 3138 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) 3139 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) 3140 { 3141 /* Itbl support may require additional care here. */ 3142 if (! prev_prev_insn_unreordered) 3143 ++nops; 3144 } 3145 3146 if (mips_fix_vr4120 && prev_insn.insn_mo->name) 3147 { 3148 int min_nops = 0; 3149 const char *pn = prev_insn.insn_mo->name; 3150 if (strncmp(pn, "macc", 4) == 0 3151 || strncmp(pn, "dmacc", 5) == 0 3152 || strncmp(pn, "dmult", 5) == 0) 3153 { 3154 min_nops = 1; 3155 } 3156 if (nops < min_nops) 3157 nops = min_nops; 3158 } 3159 3160 if (nops > 0) 3161 { 3162 struct insn_label_list *l; 3163 3164 if (insns) 3165 { 3166 /* Record the frag which holds the nop instructions, so 3167 that we can remove them if we don't need them. */ 3168 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); 3169 prev_nop_frag = frag_now; 3170 prev_nop_frag_holds = nops; 3171 prev_nop_frag_required = 0; 3172 prev_nop_frag_since = 0; 3173 } 3174 3175 for (; nops > 0; --nops) 3176 emit_nop (); 3177 3178 if (insns) 3179 { 3180 /* Move on to a new frag, so that it is safe to simply 3181 decrease the size of prev_nop_frag. */ 3182 frag_wane (frag_now); 3183 frag_new (0); 3184 } 3185 3186 for (l = insn_labels; l != NULL; l = l->next) 3187 { 3188 valueT val; 3189 3190 assert (S_GET_SEGMENT (l->label) == now_seg); 3191 symbol_set_frag (l->label, frag_now); 3192 val = (valueT) frag_now_fix (); 3193 /* mips16 text labels are stored as odd. */ 3194 if (mips_opts.mips16) 3195 ++val; 3196 S_SET_VALUE (l->label, val); 3197 } 3198 } 3199 } 3200 3201 /* Mark instruction labels in mips16 mode. */ 3202 if (insns) 3203 mips16_mark_labels (); 3204 3205 mips_no_prev_insn (insns); 3206 } 3207 3208 /* Set up global variables for the start of a new macro. */ 3209 3210 static void 3211 macro_start (void) 3212 { 3213 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); 3214 mips_macro_warning.delay_slot_p = (mips_opts.noreorder 3215 && (prev_insn.insn_mo->pinfo 3216 & (INSN_UNCOND_BRANCH_DELAY 3217 | INSN_COND_BRANCH_DELAY 3218 | INSN_COND_BRANCH_LIKELY)) != 0); 3219 } 3220 3221 /* Given that a macro is longer than 4 bytes, return the appropriate warning 3222 for it. Return null if no warning is needed. SUBTYPE is a bitmask of 3223 RELAX_DELAY_SLOT and RELAX_NOMACRO. */ 3224 3225 static const char * 3226 macro_warning (relax_substateT subtype) 3227 { 3228 if (subtype & RELAX_DELAY_SLOT) 3229 return _("Macro instruction expanded into multiple instructions" 3230 " in a branch delay slot"); 3231 else if (subtype & RELAX_NOMACRO) 3232 return _("Macro instruction expanded into multiple instructions"); 3233 else 3234 return 0; 3235 } 3236 3237 /* Finish up a macro. Emit warnings as appropriate. */ 3238 3239 static void 3240 macro_end (void) 3241 { 3242 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) 3243 { 3244 relax_substateT subtype; 3245 3246 /* Set up the relaxation warning flags. */ 3247 subtype = 0; 3248 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) 3249 subtype |= RELAX_SECOND_LONGER; 3250 if (mips_opts.warn_about_macros) 3251 subtype |= RELAX_NOMACRO; 3252 if (mips_macro_warning.delay_slot_p) 3253 subtype |= RELAX_DELAY_SLOT; 3254 3255 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) 3256 { 3257 /* Either the macro has a single implementation or both 3258 implementations are longer than 4 bytes. Emit the 3259 warning now. */ 3260 const char *msg = macro_warning (subtype); 3261 if (msg != 0) 3262 as_warn (msg); 3263 } 3264 else 3265 { 3266 /* One implementation might need a warning but the other 3267 definitely doesn't. */ 3268 mips_macro_warning.first_frag->fr_subtype |= subtype; 3269 } 3270 } 3271 } 3272 3273 /* Fix jump through register issue on loongson2f processor for kernel code: 3274 force a BTB clear before the jump to prevent it from being incorrectly 3275 prefetched by the branch prediction engine. */ 3276 3277 static void 3278 macro_build_jrpatch (expressionS *ep, unsigned int sreg) 3279 { 3280 if (!mips_fix_loongson2f_btb) 3281 return; 3282 3283 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == AT) 3284 return; 3285 3286 if (mips_opts.noat) 3287 { 3288 as_warn (_("unable to apply loongson2f BTB workaround when .set noat")); 3289 return; 3290 } 3291 3292 /* li $at, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE */ 3293 ep->X_op = O_constant; 3294 ep->X_add_number = 3; 3295 macro_build (ep, "ori", "t,r,i", AT, ZERO, BFD_RELOC_LO16); 3296 3297 /* dmtc0 $at, COP_0_DIAG */ 3298 macro_build (NULL, "dmtc0", "t,G", AT, 22); 3299 3300 /* Hide these two instructions to avoid getting a ``macro expanded into 3301 multiple instructions'' warning. */ 3302 if (mips_relax.sequence != 2) 3303 mips_macro_warning.sizes[0] -= 2 * 4; 3304 if (mips_relax.sequence != 1) 3305 mips_macro_warning.sizes[1] -= 2 * 4; 3306 } 3307 3308 /* Build an instruction created by a macro expansion. This is passed 3309 a pointer to the count of instructions created so far, an 3310 expression, the name of the instruction to build, an operand format 3311 string, and corresponding arguments. */ 3312 3313 static void 3314 macro_build (expressionS *ep, const char *name, const char *fmt, ...) 3315 { 3316 struct mips_cl_insn insn; 3317 bfd_reloc_code_real_type r[3]; 3318 va_list args; 3319 3320 va_start (args, fmt); 3321 3322 if (mips_opts.mips16) 3323 { 3324 mips16_macro_build (ep, name, fmt, args); 3325 va_end (args); 3326 return; 3327 } 3328 3329 r[0] = BFD_RELOC_UNUSED; 3330 r[1] = BFD_RELOC_UNUSED; 3331 r[2] = BFD_RELOC_UNUSED; 3332 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); 3333 assert (insn.insn_mo); 3334 assert (strcmp (name, insn.insn_mo->name) == 0); 3335 3336 /* Search until we get a match for NAME. */ 3337 while (1) 3338 { 3339 /* It is assumed here that macros will never generate 3340 MDMX or MIPS-3D instructions. */ 3341 if (strcmp (fmt, insn.insn_mo->args) == 0 3342 && insn.insn_mo->pinfo != INSN_MACRO 3343 && OPCODE_IS_MEMBER (insn.insn_mo, 3344 (mips_opts.isa 3345 | (file_ase_mips16 ? INSN_MIPS16 : 0)), 3346 mips_opts.arch) 3347 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) 3348 break; 3349 3350 ++insn.insn_mo; 3351 assert (insn.insn_mo->name); 3352 assert (strcmp (name, insn.insn_mo->name) == 0); 3353 } 3354 3355 insn.insn_opcode = insn.insn_mo->match; 3356 for (;;) 3357 { 3358 switch (*fmt++) 3359 { 3360 case '\0': 3361 break; 3362 3363 case ',': 3364 case '(': 3365 case ')': 3366 continue; 3367 3368 case '+': 3369 switch (*fmt++) 3370 { 3371 case 'A': 3372 case 'E': 3373 insn.insn_opcode |= (va_arg (args, int) 3374 & OP_MASK_SHAMT) << OP_SH_SHAMT; 3375 continue; 3376 3377 case 'B': 3378 case 'F': 3379 /* Note that in the macro case, these arguments are already 3380 in MSB form. (When handling the instruction in the 3381 non-macro case, these arguments are sizes from which 3382 MSB values must be calculated.) */ 3383 insn.insn_opcode |= (va_arg (args, int) 3384 & OP_MASK_INSMSB) << OP_SH_INSMSB; 3385 continue; 3386 3387 case 'C': 3388 case 'G': 3389 case 'H': 3390 /* Note that in the macro case, these arguments are already 3391 in MSBD form. (When handling the instruction in the 3392 non-macro case, these arguments are sizes from which 3393 MSBD values must be calculated.) */ 3394 insn.insn_opcode |= (va_arg (args, int) 3395 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; 3396 continue; 3397 3398 default: 3399 internalError (); 3400 } 3401 continue; 3402 3403 case 't': 3404 case 'w': 3405 case 'E': 3406 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; 3407 continue; 3408 3409 case 'c': 3410 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; 3411 continue; 3412 3413 case 'T': 3414 case 'W': 3415 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; 3416 continue; 3417 3418 case 'd': 3419 case 'G': 3420 case 'K': 3421 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; 3422 continue; 3423 3424 case 'U': 3425 { 3426 int tmp = va_arg (args, int); 3427 3428 insn.insn_opcode |= tmp << OP_SH_RT; 3429 insn.insn_opcode |= tmp << OP_SH_RD; 3430 continue; 3431 } 3432 3433 case 'V': 3434 case 'S': 3435 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; 3436 continue; 3437 3438 case 'z': 3439 continue; 3440 3441 case '<': 3442 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; 3443 continue; 3444 3445 case 'D': 3446 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; 3447 continue; 3448 3449 case 'B': 3450 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; 3451 continue; 3452 3453 case 'J': 3454 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; 3455 continue; 3456 3457 case 'q': 3458 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; 3459 continue; 3460 3461 case 'b': 3462 case 's': 3463 case 'r': 3464 case 'v': 3465 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; 3466 continue; 3467 3468 case 'i': 3469 case 'j': 3470 case 'o': 3471 *r = (bfd_reloc_code_real_type) va_arg (args, int); 3472 assert (*r == BFD_RELOC_GPREL16 3473 || *r == BFD_RELOC_MIPS_LITERAL 3474 || *r == BFD_RELOC_MIPS_HIGHER 3475 || *r == BFD_RELOC_HI16_S 3476 || *r == BFD_RELOC_LO16 3477 || *r == BFD_RELOC_MIPS_GOT16 3478 || *r == BFD_RELOC_MIPS_CALL16 3479 || *r == BFD_RELOC_MIPS_GOT_DISP 3480 || *r == BFD_RELOC_MIPS_GOT_PAGE 3481 || *r == BFD_RELOC_MIPS_GOT_OFST 3482 || *r == BFD_RELOC_MIPS_GOT_LO16 3483 || *r == BFD_RELOC_MIPS_CALL_LO16 3484 || (ep->X_op == O_subtract 3485 && *r == BFD_RELOC_PCREL_LO16)); 3486 continue; 3487 3488 case 'u': 3489 *r = (bfd_reloc_code_real_type) va_arg (args, int); 3490 assert (ep != NULL 3491 && (ep->X_op == O_constant 3492 || (ep->X_op == O_symbol 3493 && (*r == BFD_RELOC_MIPS_HIGHEST 3494 || *r == BFD_RELOC_HI16_S 3495 || *r == BFD_RELOC_HI16 3496 || *r == BFD_RELOC_GPREL16 3497 || *r == BFD_RELOC_MIPS_GOT_HI16 3498 || *r == BFD_RELOC_MIPS_CALL_HI16)) 3499 || (ep->X_op == O_subtract 3500 && *r == BFD_RELOC_PCREL_HI16_S))); 3501 continue; 3502 3503 case 'p': 3504 assert (ep != NULL); 3505 /* 3506 * This allows macro() to pass an immediate expression for 3507 * creating short branches without creating a symbol. 3508 * Note that the expression still might come from the assembly 3509 * input, in which case the value is not checked for range nor 3510 * is a relocation entry generated (yuck). 3511 */ 3512 if (ep->X_op == O_constant) 3513 { 3514 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; 3515 ep = NULL; 3516 } 3517 else 3518 *r = BFD_RELOC_16_PCREL_S2; 3519 continue; 3520 3521 case 'a': 3522 assert (ep != NULL); 3523 *r = BFD_RELOC_MIPS_JMP; 3524 continue; 3525 3526 case 'C': 3527 insn.insn_opcode |= va_arg (args, unsigned long); 3528 continue; 3529 3530 default: 3531 internalError (); 3532 } 3533 break; 3534 } 3535 va_end (args); 3536 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 3537 3538 append_insn (&insn, ep, r); 3539 } 3540 3541 static void 3542 mips16_macro_build (expressionS *ep, const char *name, const char *fmt, 3543 va_list args) 3544 { 3545 struct mips_cl_insn insn; 3546 bfd_reloc_code_real_type r[3] 3547 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 3548 3549 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); 3550 assert (insn.insn_mo); 3551 assert (strcmp (name, insn.insn_mo->name) == 0); 3552 3553 while (strcmp (fmt, insn.insn_mo->args) != 0 3554 || insn.insn_mo->pinfo == INSN_MACRO) 3555 { 3556 ++insn.insn_mo; 3557 assert (insn.insn_mo->name); 3558 assert (strcmp (name, insn.insn_mo->name) == 0); 3559 } 3560 3561 insn.insn_opcode = insn.insn_mo->match; 3562 insn.use_extend = FALSE; 3563 3564 for (;;) 3565 { 3566 int c; 3567 3568 c = *fmt++; 3569 switch (c) 3570 { 3571 case '\0': 3572 break; 3573 3574 case ',': 3575 case '(': 3576 case ')': 3577 continue; 3578 3579 case 'y': 3580 case 'w': 3581 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; 3582 continue; 3583 3584 case 'x': 3585 case 'v': 3586 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; 3587 continue; 3588 3589 case 'z': 3590 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; 3591 continue; 3592 3593 case 'Z': 3594 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; 3595 continue; 3596 3597 case '0': 3598 case 'S': 3599 case 'P': 3600 case 'R': 3601 continue; 3602 3603 case 'X': 3604 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; 3605 continue; 3606 3607 case 'Y': 3608 { 3609 int regno; 3610 3611 regno = va_arg (args, int); 3612 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); 3613 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; 3614 } 3615 continue; 3616 3617 case '<': 3618 case '>': 3619 case '4': 3620 case '5': 3621 case 'H': 3622 case 'W': 3623 case 'D': 3624 case 'j': 3625 case '8': 3626 case 'V': 3627 case 'C': 3628 case 'U': 3629 case 'k': 3630 case 'K': 3631 case 'p': 3632 case 'q': 3633 { 3634 assert (ep != NULL); 3635 3636 if (ep->X_op != O_constant) 3637 *r = (int) BFD_RELOC_UNUSED + c; 3638 else 3639 { 3640 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, 3641 FALSE, &insn.insn_opcode, &insn.use_extend, 3642 &insn.extend); 3643 ep = NULL; 3644 *r = BFD_RELOC_UNUSED; 3645 } 3646 } 3647 continue; 3648 3649 case '6': 3650 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; 3651 continue; 3652 } 3653 3654 break; 3655 } 3656 3657 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 3658 3659 append_insn (&insn, ep, r); 3660 } 3661 3662 /* 3663 * Generate a "jalr" instruction with a relocation hint to the called 3664 * function. This occurs in NewABI PIC code. 3665 */ 3666 static void 3667 macro_build_jalr (expressionS *ep) 3668 { 3669 char *f = NULL; 3670 3671 if (HAVE_NEWABI) 3672 { 3673 frag_grow (8); 3674 f = frag_more (0); 3675 } 3676 macro_build_jrpatch (ep, PIC_CALL_REG); 3677 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); 3678 if (HAVE_NEWABI) 3679 fix_new_exp (frag_now, f - frag_now->fr_literal, 3680 4, ep, FALSE, BFD_RELOC_MIPS_JALR); 3681 } 3682 3683 /* 3684 * Generate a "lui" instruction. 3685 */ 3686 static void 3687 macro_build_lui (expressionS *ep, int regnum) 3688 { 3689 expressionS high_expr; 3690 struct mips_cl_insn insn; 3691 bfd_reloc_code_real_type r[3] 3692 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 3693 const char *name = "lui"; 3694 const char *fmt = "t,u"; 3695 3696 assert (! mips_opts.mips16); 3697 3698 high_expr = *ep; 3699 3700 if (high_expr.X_op == O_constant) 3701 { 3702 /* we can compute the instruction now without a relocation entry */ 3703 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) 3704 >> 16) & 0xffff; 3705 *r = BFD_RELOC_UNUSED; 3706 } 3707 else 3708 { 3709 assert (ep->X_op == O_symbol); 3710 /* _gp_disp is a special case, used from s_cpload. */ 3711 assert (mips_pic == NO_PIC 3712 || (! HAVE_NEWABI 3713 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); 3714 *r = BFD_RELOC_HI16_S; 3715 } 3716 3717 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); 3718 assert (insn.insn_mo); 3719 assert (strcmp (name, insn.insn_mo->name) == 0); 3720 assert (strcmp (fmt, insn.insn_mo->args) == 0); 3721 3722 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); 3723 if (*r == BFD_RELOC_UNUSED) 3724 { 3725 insn.insn_opcode |= high_expr.X_add_number; 3726 append_insn (&insn, NULL, r); 3727 } 3728 else 3729 append_insn (&insn, &high_expr, r); 3730 } 3731 3732 /* Generate a sequence of instructions to do a load or store from a constant 3733 offset off of a base register (breg) into/from a target register (treg), 3734 using AT if necessary. */ 3735 static void 3736 macro_build_ldst_constoffset (expressionS *ep, const char *op, 3737 int treg, int breg, int dbl) 3738 { 3739 assert (ep->X_op == O_constant); 3740 3741 /* Sign-extending 32-bit constants makes their handling easier. */ 3742 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) 3743 == ~((bfd_vma) 0x7fffffff))) 3744 { 3745 if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) 3746 as_bad (_("constant too large")); 3747 3748 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) 3749 - 0x80000000); 3750 } 3751 3752 /* Right now, this routine can only handle signed 32-bit constants. */ 3753 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) 3754 as_warn (_("operand overflow")); 3755 3756 if (IS_SEXT_16BIT_NUM(ep->X_add_number)) 3757 { 3758 /* Signed 16-bit offset will fit in the op. Easy! */ 3759 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); 3760 } 3761 else 3762 { 3763 /* 32-bit offset, need multiple instructions and AT, like: 3764 lui $tempreg,const_hi (BFD_RELOC_HI16_S) 3765 addu $tempreg,$tempreg,$breg 3766 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) 3767 to handle the complete offset. */ 3768 macro_build_lui (ep, AT); 3769 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 3770 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); 3771 3772 if (mips_opts.noat) 3773 as_warn (_("Macro used $at after \".set noat\"")); 3774 } 3775 } 3776 3777 /* set_at() 3778 * Generates code to set the $at register to true (one) 3779 * if reg is less than the immediate expression. 3780 */ 3781 static void 3782 set_at (int reg, int unsignedp) 3783 { 3784 if (imm_expr.X_op == O_constant 3785 && imm_expr.X_add_number >= -0x8000 3786 && imm_expr.X_add_number < 0x8000) 3787 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", 3788 AT, reg, BFD_RELOC_LO16); 3789 else 3790 { 3791 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 3792 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); 3793 } 3794 } 3795 3796 static void 3797 normalize_constant_expr (expressionS *ex) 3798 { 3799 if (ex->X_op == O_constant && HAVE_32BIT_GPRS) 3800 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 3801 - 0x80000000); 3802 } 3803 3804 /* Warn if an expression is not a constant. */ 3805 3806 static void 3807 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) 3808 { 3809 if (ex->X_op == O_big) 3810 as_bad (_("unsupported large constant")); 3811 else if (ex->X_op != O_constant) 3812 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); 3813 3814 normalize_constant_expr (ex); 3815 } 3816 3817 /* Count the leading zeroes by performing a binary chop. This is a 3818 bulky bit of source, but performance is a LOT better for the 3819 majority of values than a simple loop to count the bits: 3820 for (lcnt = 0; (lcnt < 32); lcnt++) 3821 if ((v) & (1 << (31 - lcnt))) 3822 break; 3823 However it is not code size friendly, and the gain will drop a bit 3824 on certain cached systems. 3825 */ 3826 #define COUNT_TOP_ZEROES(v) \ 3827 (((v) & ~0xffff) == 0 \ 3828 ? ((v) & ~0xff) == 0 \ 3829 ? ((v) & ~0xf) == 0 \ 3830 ? ((v) & ~0x3) == 0 \ 3831 ? ((v) & ~0x1) == 0 \ 3832 ? !(v) \ 3833 ? 32 \ 3834 : 31 \ 3835 : 30 \ 3836 : ((v) & ~0x7) == 0 \ 3837 ? 29 \ 3838 : 28 \ 3839 : ((v) & ~0x3f) == 0 \ 3840 ? ((v) & ~0x1f) == 0 \ 3841 ? 27 \ 3842 : 26 \ 3843 : ((v) & ~0x7f) == 0 \ 3844 ? 25 \ 3845 : 24 \ 3846 : ((v) & ~0xfff) == 0 \ 3847 ? ((v) & ~0x3ff) == 0 \ 3848 ? ((v) & ~0x1ff) == 0 \ 3849 ? 23 \ 3850 : 22 \ 3851 : ((v) & ~0x7ff) == 0 \ 3852 ? 21 \ 3853 : 20 \ 3854 : ((v) & ~0x3fff) == 0 \ 3855 ? ((v) & ~0x1fff) == 0 \ 3856 ? 19 \ 3857 : 18 \ 3858 : ((v) & ~0x7fff) == 0 \ 3859 ? 17 \ 3860 : 16 \ 3861 : ((v) & ~0xffffff) == 0 \ 3862 ? ((v) & ~0xfffff) == 0 \ 3863 ? ((v) & ~0x3ffff) == 0 \ 3864 ? ((v) & ~0x1ffff) == 0 \ 3865 ? 15 \ 3866 : 14 \ 3867 : ((v) & ~0x7ffff) == 0 \ 3868 ? 13 \ 3869 : 12 \ 3870 : ((v) & ~0x3fffff) == 0 \ 3871 ? ((v) & ~0x1fffff) == 0 \ 3872 ? 11 \ 3873 : 10 \ 3874 : ((v) & ~0x7fffff) == 0 \ 3875 ? 9 \ 3876 : 8 \ 3877 : ((v) & ~0xfffffff) == 0 \ 3878 ? ((v) & ~0x3ffffff) == 0 \ 3879 ? ((v) & ~0x1ffffff) == 0 \ 3880 ? 7 \ 3881 : 6 \ 3882 : ((v) & ~0x7ffffff) == 0 \ 3883 ? 5 \ 3884 : 4 \ 3885 : ((v) & ~0x3fffffff) == 0 \ 3886 ? ((v) & ~0x1fffffff) == 0 \ 3887 ? 3 \ 3888 : 2 \ 3889 : ((v) & ~0x7fffffff) == 0 \ 3890 ? 1 \ 3891 : 0) 3892 3893 /* load_register() 3894 * This routine generates the least number of instructions necessary to load 3895 * an absolute expression value into a register. 3896 */ 3897 static void 3898 load_register (int reg, expressionS *ep, int dbl) 3899 { 3900 int freg; 3901 expressionS hi32, lo32; 3902 3903 if (ep->X_op != O_big) 3904 { 3905 assert (ep->X_op == O_constant); 3906 3907 /* Sign-extending 32-bit constants makes their handling easier. */ 3908 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) 3909 == ~((bfd_vma) 0x7fffffff))) 3910 { 3911 if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) 3912 as_bad (_("constant too large")); 3913 3914 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) 3915 - 0x80000000); 3916 } 3917 3918 if (IS_SEXT_16BIT_NUM (ep->X_add_number)) 3919 { 3920 /* We can handle 16 bit signed values with an addiu to 3921 $zero. No need to ever use daddiu here, since $zero and 3922 the result are always correct in 32 bit mode. */ 3923 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 3924 return; 3925 } 3926 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) 3927 { 3928 /* We can handle 16 bit unsigned values with an ori to 3929 $zero. */ 3930 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 3931 return; 3932 } 3933 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) 3934 { 3935 /* 32 bit values require an lui. */ 3936 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); 3937 if ((ep->X_add_number & 0xffff) != 0) 3938 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 3939 return; 3940 } 3941 } 3942 3943 /* The value is larger than 32 bits. */ 3944 3945 if (HAVE_32BIT_GPRS) 3946 { 3947 as_bad (_("Number (0x%lx) larger than 32 bits"), 3948 (unsigned long) ep->X_add_number); 3949 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 3950 return; 3951 } 3952 3953 if (ep->X_op != O_big) 3954 { 3955 hi32 = *ep; 3956 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 3957 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 3958 hi32.X_add_number &= 0xffffffff; 3959 lo32 = *ep; 3960 lo32.X_add_number &= 0xffffffff; 3961 } 3962 else 3963 { 3964 assert (ep->X_add_number > 2); 3965 if (ep->X_add_number == 3) 3966 generic_bignum[3] = 0; 3967 else if (ep->X_add_number > 4) 3968 as_bad (_("Number larger than 64 bits")); 3969 lo32.X_op = O_constant; 3970 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); 3971 hi32.X_op = O_constant; 3972 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); 3973 } 3974 3975 if (hi32.X_add_number == 0) 3976 freg = 0; 3977 else 3978 { 3979 int shift, bit; 3980 unsigned long hi, lo; 3981 3982 if (hi32.X_add_number == (offsetT) 0xffffffff) 3983 { 3984 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) 3985 { 3986 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 3987 return; 3988 } 3989 if (lo32.X_add_number & 0x80000000) 3990 { 3991 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); 3992 if (lo32.X_add_number & 0xffff) 3993 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 3994 return; 3995 } 3996 } 3997 3998 /* Check for 16bit shifted constant. We know that hi32 is 3999 non-zero, so start the mask on the first bit of the hi32 4000 value. */ 4001 shift = 17; 4002 do 4003 { 4004 unsigned long himask, lomask; 4005 4006 if (shift < 32) 4007 { 4008 himask = 0xffff >> (32 - shift); 4009 lomask = (0xffff << shift) & 0xffffffff; 4010 } 4011 else 4012 { 4013 himask = 0xffff << (shift - 32); 4014 lomask = 0; 4015 } 4016 if ((hi32.X_add_number & ~(offsetT) himask) == 0 4017 && (lo32.X_add_number & ~(offsetT) lomask) == 0) 4018 { 4019 expressionS tmp; 4020 4021 tmp.X_op = O_constant; 4022 if (shift < 32) 4023 tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) 4024 | (lo32.X_add_number >> shift)); 4025 else 4026 tmp.X_add_number = hi32.X_add_number >> (shift - 32); 4027 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 4028 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", 4029 reg, reg, (shift >= 32) ? shift - 32 : shift); 4030 return; 4031 } 4032 ++shift; 4033 } 4034 while (shift <= (64 - 16)); 4035 4036 /* Find the bit number of the lowest one bit, and store the 4037 shifted value in hi/lo. */ 4038 hi = (unsigned long) (hi32.X_add_number & 0xffffffff); 4039 lo = (unsigned long) (lo32.X_add_number & 0xffffffff); 4040 if (lo != 0) 4041 { 4042 bit = 0; 4043 while ((lo & 1) == 0) 4044 { 4045 lo >>= 1; 4046 ++bit; 4047 } 4048 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); 4049 hi >>= bit; 4050 } 4051 else 4052 { 4053 bit = 32; 4054 while ((hi & 1) == 0) 4055 { 4056 hi >>= 1; 4057 ++bit; 4058 } 4059 lo = hi; 4060 hi = 0; 4061 } 4062 4063 /* Optimize if the shifted value is a (power of 2) - 1. */ 4064 if ((hi == 0 && ((lo + 1) & lo) == 0) 4065 || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) 4066 { 4067 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); 4068 if (shift != 0) 4069 { 4070 expressionS tmp; 4071 4072 /* This instruction will set the register to be all 4073 ones. */ 4074 tmp.X_op = O_constant; 4075 tmp.X_add_number = (offsetT) -1; 4076 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 4077 if (bit != 0) 4078 { 4079 bit += shift; 4080 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", 4081 reg, reg, (bit >= 32) ? bit - 32 : bit); 4082 } 4083 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", 4084 reg, reg, (shift >= 32) ? shift - 32 : shift); 4085 return; 4086 } 4087 } 4088 4089 /* Sign extend hi32 before calling load_register, because we can 4090 generally get better code when we load a sign extended value. */ 4091 if ((hi32.X_add_number & 0x80000000) != 0) 4092 hi32.X_add_number |= ~(offsetT) 0xffffffff; 4093 load_register (reg, &hi32, 0); 4094 freg = reg; 4095 } 4096 if ((lo32.X_add_number & 0xffff0000) == 0) 4097 { 4098 if (freg != 0) 4099 { 4100 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); 4101 freg = reg; 4102 } 4103 } 4104 else 4105 { 4106 expressionS mid16; 4107 4108 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) 4109 { 4110 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); 4111 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); 4112 return; 4113 } 4114 4115 if (freg != 0) 4116 { 4117 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); 4118 freg = reg; 4119 } 4120 mid16 = lo32; 4121 mid16.X_add_number >>= 16; 4122 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 4123 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); 4124 freg = reg; 4125 } 4126 if ((lo32.X_add_number & 0xffff) != 0) 4127 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 4128 } 4129 4130 /* Load an address into a register. */ 4131 4132 static void 4133 load_address (int reg, expressionS *ep, int *used_at) 4134 { 4135 if (ep->X_op != O_constant 4136 && ep->X_op != O_symbol) 4137 { 4138 as_bad (_("expression too complex")); 4139 ep->X_op = O_constant; 4140 } 4141 4142 if (ep->X_op == O_constant) 4143 { 4144 load_register (reg, ep, HAVE_64BIT_ADDRESSES); 4145 return; 4146 } 4147 4148 if (mips_pic == NO_PIC) 4149 { 4150 /* If this is a reference to a GP relative symbol, we want 4151 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) 4152 Otherwise we want 4153 lui $reg,<sym> (BFD_RELOC_HI16_S) 4154 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 4155 If we have an addend, we always use the latter form. 4156 4157 With 64bit address space and a usable $at we want 4158 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 4159 lui $at,<sym> (BFD_RELOC_HI16_S) 4160 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 4161 daddiu $at,<sym> (BFD_RELOC_LO16) 4162 dsll32 $reg,0 4163 daddu $reg,$reg,$at 4164 4165 If $at is already in use, we use a path which is suboptimal 4166 on superscalar processors. 4167 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 4168 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 4169 dsll $reg,16 4170 daddiu $reg,<sym> (BFD_RELOC_HI16_S) 4171 dsll $reg,16 4172 daddiu $reg,<sym> (BFD_RELOC_LO16) 4173 */ 4174 if (HAVE_64BIT_ADDRESSES) 4175 { 4176 /* ??? We don't provide a GP-relative alternative for these macros. 4177 It used not to be possible with the original relaxation code, 4178 but it could be done now. */ 4179 4180 if (*used_at == 0 && ! mips_opts.noat) 4181 { 4182 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); 4183 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); 4184 macro_build (ep, "daddiu", "t,r,j", reg, reg, 4185 BFD_RELOC_MIPS_HIGHER); 4186 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); 4187 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); 4188 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); 4189 *used_at = 1; 4190 } 4191 else 4192 { 4193 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); 4194 macro_build (ep, "daddiu", "t,r,j", reg, reg, 4195 BFD_RELOC_MIPS_HIGHER); 4196 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); 4197 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); 4198 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); 4199 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); 4200 } 4201 } 4202 else 4203 { 4204 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 4205 && ! nopic_need_relax (ep->X_add_symbol, 1)) 4206 { 4207 relax_start (ep->X_add_symbol); 4208 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 4209 mips_gp_register, BFD_RELOC_GPREL16); 4210 relax_switch (); 4211 } 4212 macro_build_lui (ep, reg); 4213 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", 4214 reg, reg, BFD_RELOC_LO16); 4215 if (mips_relax.sequence) 4216 relax_end (); 4217 } 4218 } 4219 else if (mips_pic == SVR4_PIC && ! mips_big_got) 4220 { 4221 expressionS ex; 4222 4223 /* If this is a reference to an external symbol, we want 4224 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 4225 Otherwise we want 4226 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 4227 nop 4228 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 4229 If there is a constant, it must be added in after. 4230 4231 If we have NewABI, we want 4232 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) 4233 unless we're referencing a global symbol with a non-zero 4234 offset, in which case cst must be added separately. */ 4235 if (HAVE_NEWABI) 4236 { 4237 if (ep->X_add_number) 4238 { 4239 ex.X_add_number = ep->X_add_number; 4240 ep->X_add_number = 0; 4241 relax_start (ep->X_add_symbol); 4242 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4243 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 4244 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 4245 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 4246 ex.X_op = O_constant; 4247 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 4248 reg, reg, BFD_RELOC_LO16); 4249 ep->X_add_number = ex.X_add_number; 4250 relax_switch (); 4251 } 4252 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4253 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 4254 if (mips_relax.sequence) 4255 relax_end (); 4256 } 4257 else 4258 { 4259 ex.X_add_number = ep->X_add_number; 4260 ep->X_add_number = 0; 4261 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4262 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4263 macro_build (NULL, "nop", ""); 4264 relax_start (ep->X_add_symbol); 4265 relax_switch (); 4266 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4267 BFD_RELOC_LO16); 4268 relax_end (); 4269 4270 if (ex.X_add_number != 0) 4271 { 4272 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 4273 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 4274 ex.X_op = O_constant; 4275 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 4276 reg, reg, BFD_RELOC_LO16); 4277 } 4278 } 4279 } 4280 else if (mips_pic == SVR4_PIC) 4281 { 4282 expressionS ex; 4283 4284 /* This is the large GOT case. If this is a reference to an 4285 external symbol, we want 4286 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 4287 addu $reg,$reg,$gp 4288 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) 4289 4290 Otherwise, for a reference to a local symbol in old ABI, we want 4291 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 4292 nop 4293 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 4294 If there is a constant, it must be added in after. 4295 4296 In the NewABI, for local symbols, with or without offsets, we want: 4297 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 4298 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 4299 */ 4300 if (HAVE_NEWABI) 4301 { 4302 ex.X_add_number = ep->X_add_number; 4303 ep->X_add_number = 0; 4304 relax_start (ep->X_add_symbol); 4305 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); 4306 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 4307 reg, reg, mips_gp_register); 4308 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 4309 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 4310 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 4311 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 4312 else if (ex.X_add_number) 4313 { 4314 ex.X_op = O_constant; 4315 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4316 BFD_RELOC_LO16); 4317 } 4318 4319 ep->X_add_number = ex.X_add_number; 4320 relax_switch (); 4321 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4322 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 4323 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4324 BFD_RELOC_MIPS_GOT_OFST); 4325 relax_end (); 4326 } 4327 else 4328 { 4329 ex.X_add_number = ep->X_add_number; 4330 ep->X_add_number = 0; 4331 relax_start (ep->X_add_symbol); 4332 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); 4333 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 4334 reg, reg, mips_gp_register); 4335 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 4336 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 4337 relax_switch (); 4338 if (reg_needs_delay (mips_gp_register)) 4339 { 4340 /* We need a nop before loading from $gp. This special 4341 check is required because the lui which starts the main 4342 instruction stream does not refer to $gp, and so will not 4343 insert the nop which may be required. */ 4344 macro_build (NULL, "nop", ""); 4345 } 4346 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4347 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4348 macro_build (NULL, "nop", ""); 4349 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4350 BFD_RELOC_LO16); 4351 relax_end (); 4352 4353 if (ex.X_add_number != 0) 4354 { 4355 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 4356 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 4357 ex.X_op = O_constant; 4358 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4359 BFD_RELOC_LO16); 4360 } 4361 } 4362 } 4363 else if (mips_pic == EMBEDDED_PIC) 4364 { 4365 /* We always do 4366 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) 4367 */ 4368 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", 4369 reg, mips_gp_register, BFD_RELOC_GPREL16); 4370 } 4371 else 4372 abort (); 4373 } 4374 4375 /* Move the contents of register SOURCE into register DEST. */ 4376 4377 static void 4378 move_register (int dest, int source) 4379 { 4380 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", 4381 dest, source, 0); 4382 } 4383 4384 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where 4385 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. 4386 The two alternatives are: 4387 4388 Global symbol Local sybmol 4389 ------------- ------------ 4390 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) 4391 ... ... 4392 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) 4393 4394 load_got_offset emits the first instruction and add_got_offset 4395 emits the second for a 16-bit offset or add_got_offset_hilo emits 4396 a sequence to add a 32-bit offset using a scratch register. */ 4397 4398 static void 4399 load_got_offset (int dest, expressionS *local) 4400 { 4401 expressionS global; 4402 4403 global = *local; 4404 global.X_add_number = 0; 4405 4406 relax_start (local->X_add_symbol); 4407 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, 4408 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4409 relax_switch (); 4410 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, 4411 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4412 relax_end (); 4413 } 4414 4415 static void 4416 add_got_offset (int dest, expressionS *local) 4417 { 4418 expressionS global; 4419 4420 global.X_op = O_constant; 4421 global.X_op_symbol = NULL; 4422 global.X_add_symbol = NULL; 4423 global.X_add_number = local->X_add_number; 4424 4425 relax_start (local->X_add_symbol); 4426 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", 4427 dest, dest, BFD_RELOC_LO16); 4428 relax_switch (); 4429 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); 4430 relax_end (); 4431 } 4432 4433 static void 4434 add_got_offset_hilo (int dest, expressionS *local, int tmp) 4435 { 4436 expressionS global; 4437 int hold_mips_optimize; 4438 4439 global.X_op = O_constant; 4440 global.X_op_symbol = NULL; 4441 global.X_add_symbol = NULL; 4442 global.X_add_number = local->X_add_number; 4443 4444 relax_start (local->X_add_symbol); 4445 load_register (tmp, &global, HAVE_64BIT_ADDRESSES); 4446 relax_switch (); 4447 /* Set mips_optimize around the lui instruction to avoid 4448 inserting an unnecessary nop after the lw. */ 4449 hold_mips_optimize = mips_optimize; 4450 mips_optimize = 2; 4451 macro_build_lui (&global, tmp); 4452 mips_optimize = hold_mips_optimize; 4453 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); 4454 relax_end (); 4455 4456 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); 4457 } 4458 4459 /* 4460 * Build macros 4461 * This routine implements the seemingly endless macro or synthesized 4462 * instructions and addressing modes in the mips assembly language. Many 4463 * of these macros are simple and are similar to each other. These could 4464 * probably be handled by some kind of table or grammar approach instead of 4465 * this verbose method. Others are not simple macros but are more like 4466 * optimizing code generation. 4467 * One interesting optimization is when several store macros appear 4468 * consecutively that would load AT with the upper half of the same address. 4469 * The ensuing load upper instructions are ommited. This implies some kind 4470 * of global optimization. We currently only optimize within a single macro. 4471 * For many of the load and store macros if the address is specified as a 4472 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we 4473 * first load register 'at' with zero and use it as the base register. The 4474 * mips assembler simply uses register $zero. Just one tiny optimization 4475 * we're missing. 4476 */ 4477 static void 4478 macro (struct mips_cl_insn *ip) 4479 { 4480 register int treg, sreg, dreg, breg; 4481 int tempreg; 4482 int mask; 4483 int used_at = 0; 4484 expressionS expr1; 4485 const char *s; 4486 const char *s2; 4487 const char *fmt; 4488 int likely = 0; 4489 int dbl = 0; 4490 int coproc = 0; 4491 int lr = 0; 4492 int imm = 0; 4493 int call = 0; 4494 int off; 4495 offsetT maxnum; 4496 bfd_reloc_code_real_type r; 4497 int hold_mips_optimize; 4498 4499 assert (! mips_opts.mips16); 4500 4501 treg = (ip->insn_opcode >> 16) & 0x1f; 4502 dreg = (ip->insn_opcode >> 11) & 0x1f; 4503 sreg = breg = (ip->insn_opcode >> 21) & 0x1f; 4504 mask = ip->insn_mo->mask; 4505 4506 expr1.X_op = O_constant; 4507 expr1.X_op_symbol = NULL; 4508 expr1.X_add_symbol = NULL; 4509 expr1.X_add_number = 1; 4510 4511 switch (mask) 4512 { 4513 case M_DABS: 4514 dbl = 1; 4515 case M_ABS: 4516 /* bgez $a0,.+12 4517 move v0,$a0 4518 sub v0,$zero,$a0 4519 */ 4520 4521 mips_emit_delays (TRUE); 4522 ++mips_opts.noreorder; 4523 mips_any_noreorder = 1; 4524 4525 expr1.X_add_number = 8; 4526 macro_build (&expr1, "bgez", "s,p", sreg); 4527 if (dreg == sreg) 4528 macro_build (NULL, "nop", "", 0); 4529 else 4530 move_register (dreg, sreg); 4531 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); 4532 4533 --mips_opts.noreorder; 4534 return; 4535 4536 case M_ADD_I: 4537 s = "addi"; 4538 s2 = "add"; 4539 goto do_addi; 4540 case M_ADDU_I: 4541 s = "addiu"; 4542 s2 = "addu"; 4543 goto do_addi; 4544 case M_DADD_I: 4545 dbl = 1; 4546 s = "daddi"; 4547 s2 = "dadd"; 4548 goto do_addi; 4549 case M_DADDU_I: 4550 dbl = 1; 4551 s = "daddiu"; 4552 s2 = "daddu"; 4553 do_addi: 4554 if (imm_expr.X_op == O_constant 4555 && imm_expr.X_add_number >= -0x8000 4556 && imm_expr.X_add_number < 0x8000) 4557 { 4558 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); 4559 return; 4560 } 4561 load_register (AT, &imm_expr, dbl); 4562 macro_build (NULL, s2, "d,v,t", treg, sreg, AT); 4563 break; 4564 4565 case M_AND_I: 4566 s = "andi"; 4567 s2 = "and"; 4568 goto do_bit; 4569 case M_OR_I: 4570 s = "ori"; 4571 s2 = "or"; 4572 goto do_bit; 4573 case M_NOR_I: 4574 s = ""; 4575 s2 = "nor"; 4576 goto do_bit; 4577 case M_XOR_I: 4578 s = "xori"; 4579 s2 = "xor"; 4580 do_bit: 4581 if (imm_expr.X_op == O_constant 4582 && imm_expr.X_add_number >= 0 4583 && imm_expr.X_add_number < 0x10000) 4584 { 4585 if (mask != M_NOR_I) 4586 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); 4587 else 4588 { 4589 macro_build (&imm_expr, "ori", "t,r,i", 4590 treg, sreg, BFD_RELOC_LO16); 4591 macro_build (NULL, "nor", "d,v,t", treg, treg, 0); 4592 } 4593 return; 4594 } 4595 4596 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 4597 macro_build (NULL, s2, "d,v,t", treg, sreg, AT); 4598 break; 4599 4600 case M_BEQ_I: 4601 s = "beq"; 4602 goto beq_i; 4603 case M_BEQL_I: 4604 s = "beql"; 4605 likely = 1; 4606 goto beq_i; 4607 case M_BNE_I: 4608 s = "bne"; 4609 goto beq_i; 4610 case M_BNEL_I: 4611 s = "bnel"; 4612 likely = 1; 4613 beq_i: 4614 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4615 { 4616 macro_build (&offset_expr, s, "s,t,p", sreg, 0); 4617 return; 4618 } 4619 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 4620 macro_build (&offset_expr, s, "s,t,p", sreg, AT); 4621 break; 4622 4623 case M_BGEL: 4624 likely = 1; 4625 case M_BGE: 4626 if (treg == 0) 4627 { 4628 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); 4629 return; 4630 } 4631 if (sreg == 0) 4632 { 4633 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); 4634 return; 4635 } 4636 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); 4637 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4638 break; 4639 4640 case M_BGTL_I: 4641 likely = 1; 4642 case M_BGT_I: 4643 /* check for > max integer */ 4644 maxnum = 0x7fffffff; 4645 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) 4646 { 4647 maxnum <<= 16; 4648 maxnum |= 0xffff; 4649 maxnum <<= 16; 4650 maxnum |= 0xffff; 4651 } 4652 if (imm_expr.X_op == O_constant 4653 && imm_expr.X_add_number >= maxnum 4654 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) 4655 { 4656 do_false: 4657 /* result is always false */ 4658 if (! likely) 4659 macro_build (NULL, "nop", "", 0); 4660 else 4661 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); 4662 return; 4663 } 4664 if (imm_expr.X_op != O_constant) 4665 as_bad (_("Unsupported large constant")); 4666 ++imm_expr.X_add_number; 4667 /* FALLTHROUGH */ 4668 case M_BGE_I: 4669 case M_BGEL_I: 4670 if (mask == M_BGEL_I) 4671 likely = 1; 4672 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4673 { 4674 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); 4675 return; 4676 } 4677 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4678 { 4679 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); 4680 return; 4681 } 4682 maxnum = 0x7fffffff; 4683 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) 4684 { 4685 maxnum <<= 16; 4686 maxnum |= 0xffff; 4687 maxnum <<= 16; 4688 maxnum |= 0xffff; 4689 } 4690 maxnum = - maxnum - 1; 4691 if (imm_expr.X_op == O_constant 4692 && imm_expr.X_add_number <= maxnum 4693 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) 4694 { 4695 do_true: 4696 /* result is always true */ 4697 as_warn (_("Branch %s is always true"), ip->insn_mo->name); 4698 macro_build (&offset_expr, "b", "p"); 4699 return; 4700 } 4701 set_at (sreg, 0); 4702 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4703 break; 4704 4705 case M_BGEUL: 4706 likely = 1; 4707 case M_BGEU: 4708 if (treg == 0) 4709 goto do_true; 4710 if (sreg == 0) 4711 { 4712 macro_build (&offset_expr, likely ? "beql" : "beq", 4713 "s,t,p", 0, treg); 4714 return; 4715 } 4716 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); 4717 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4718 break; 4719 4720 case M_BGTUL_I: 4721 likely = 1; 4722 case M_BGTU_I: 4723 if (sreg == 0 4724 || (HAVE_32BIT_GPRS 4725 && imm_expr.X_op == O_constant 4726 && imm_expr.X_add_number == (offsetT) 0xffffffff)) 4727 goto do_false; 4728 if (imm_expr.X_op != O_constant) 4729 as_bad (_("Unsupported large constant")); 4730 ++imm_expr.X_add_number; 4731 /* FALLTHROUGH */ 4732 case M_BGEU_I: 4733 case M_BGEUL_I: 4734 if (mask == M_BGEUL_I) 4735 likely = 1; 4736 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4737 goto do_true; 4738 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4739 { 4740 macro_build (&offset_expr, likely ? "bnel" : "bne", 4741 "s,t,p", sreg, 0); 4742 return; 4743 } 4744 set_at (sreg, 1); 4745 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4746 break; 4747 4748 case M_BGTL: 4749 likely = 1; 4750 case M_BGT: 4751 if (treg == 0) 4752 { 4753 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); 4754 return; 4755 } 4756 if (sreg == 0) 4757 { 4758 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); 4759 return; 4760 } 4761 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); 4762 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4763 break; 4764 4765 case M_BGTUL: 4766 likely = 1; 4767 case M_BGTU: 4768 if (treg == 0) 4769 { 4770 macro_build (&offset_expr, likely ? "bnel" : "bne", 4771 "s,t,p", sreg, 0); 4772 return; 4773 } 4774 if (sreg == 0) 4775 goto do_false; 4776 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); 4777 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4778 break; 4779 4780 case M_BLEL: 4781 likely = 1; 4782 case M_BLE: 4783 if (treg == 0) 4784 { 4785 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); 4786 return; 4787 } 4788 if (sreg == 0) 4789 { 4790 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); 4791 return; 4792 } 4793 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); 4794 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4795 break; 4796 4797 case M_BLEL_I: 4798 likely = 1; 4799 case M_BLE_I: 4800 maxnum = 0x7fffffff; 4801 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) 4802 { 4803 maxnum <<= 16; 4804 maxnum |= 0xffff; 4805 maxnum <<= 16; 4806 maxnum |= 0xffff; 4807 } 4808 if (imm_expr.X_op == O_constant 4809 && imm_expr.X_add_number >= maxnum 4810 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) 4811 goto do_true; 4812 if (imm_expr.X_op != O_constant) 4813 as_bad (_("Unsupported large constant")); 4814 ++imm_expr.X_add_number; 4815 /* FALLTHROUGH */ 4816 case M_BLT_I: 4817 case M_BLTL_I: 4818 if (mask == M_BLTL_I) 4819 likely = 1; 4820 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4821 { 4822 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); 4823 return; 4824 } 4825 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4826 { 4827 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); 4828 return; 4829 } 4830 set_at (sreg, 0); 4831 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4832 break; 4833 4834 case M_BLEUL: 4835 likely = 1; 4836 case M_BLEU: 4837 if (treg == 0) 4838 { 4839 macro_build (&offset_expr, likely ? "beql" : "beq", 4840 "s,t,p", sreg, 0); 4841 return; 4842 } 4843 if (sreg == 0) 4844 goto do_true; 4845 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); 4846 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4847 break; 4848 4849 case M_BLEUL_I: 4850 likely = 1; 4851 case M_BLEU_I: 4852 if (sreg == 0 4853 || (HAVE_32BIT_GPRS 4854 && imm_expr.X_op == O_constant 4855 && imm_expr.X_add_number == (offsetT) 0xffffffff)) 4856 goto do_true; 4857 if (imm_expr.X_op != O_constant) 4858 as_bad (_("Unsupported large constant")); 4859 ++imm_expr.X_add_number; 4860 /* FALLTHROUGH */ 4861 case M_BLTU_I: 4862 case M_BLTUL_I: 4863 if (mask == M_BLTUL_I) 4864 likely = 1; 4865 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4866 goto do_false; 4867 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4868 { 4869 macro_build (&offset_expr, likely ? "beql" : "beq", 4870 "s,t,p", sreg, 0); 4871 return; 4872 } 4873 set_at (sreg, 1); 4874 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4875 break; 4876 4877 case M_BLTL: 4878 likely = 1; 4879 case M_BLT: 4880 if (treg == 0) 4881 { 4882 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); 4883 return; 4884 } 4885 if (sreg == 0) 4886 { 4887 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); 4888 return; 4889 } 4890 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); 4891 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4892 break; 4893 4894 case M_BLTUL: 4895 likely = 1; 4896 case M_BLTU: 4897 if (treg == 0) 4898 goto do_false; 4899 if (sreg == 0) 4900 { 4901 macro_build (&offset_expr, likely ? "bnel" : "bne", 4902 "s,t,p", 0, treg); 4903 return; 4904 } 4905 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); 4906 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4907 break; 4908 4909 case M_DEXT: 4910 { 4911 unsigned long pos; 4912 unsigned long size; 4913 4914 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) 4915 { 4916 as_bad (_("Unsupported large constant")); 4917 pos = size = 1; 4918 } 4919 else 4920 { 4921 pos = (unsigned long) imm_expr.X_add_number; 4922 size = (unsigned long) imm2_expr.X_add_number; 4923 } 4924 4925 if (pos > 63) 4926 { 4927 as_bad (_("Improper position (%lu)"), pos); 4928 pos = 1; 4929 } 4930 if (size == 0 || size > 64 4931 || (pos + size - 1) > 63) 4932 { 4933 as_bad (_("Improper extract size (%lu, position %lu)"), 4934 size, pos); 4935 size = 1; 4936 } 4937 4938 if (size <= 32 && pos < 32) 4939 { 4940 s = "dext"; 4941 fmt = "t,r,+A,+C"; 4942 } 4943 else if (size <= 32) 4944 { 4945 s = "dextu"; 4946 fmt = "t,r,+E,+H"; 4947 } 4948 else 4949 { 4950 s = "dextm"; 4951 fmt = "t,r,+A,+G"; 4952 } 4953 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); 4954 } 4955 return; 4956 4957 case M_DINS: 4958 { 4959 unsigned long pos; 4960 unsigned long size; 4961 4962 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) 4963 { 4964 as_bad (_("Unsupported large constant")); 4965 pos = size = 1; 4966 } 4967 else 4968 { 4969 pos = (unsigned long) imm_expr.X_add_number; 4970 size = (unsigned long) imm2_expr.X_add_number; 4971 } 4972 4973 if (pos > 63) 4974 { 4975 as_bad (_("Improper position (%lu)"), pos); 4976 pos = 1; 4977 } 4978 if (size == 0 || size > 64 4979 || (pos + size - 1) > 63) 4980 { 4981 as_bad (_("Improper insert size (%lu, position %lu)"), 4982 size, pos); 4983 size = 1; 4984 } 4985 4986 if (pos < 32 && (pos + size - 1) < 32) 4987 { 4988 s = "dins"; 4989 fmt = "t,r,+A,+B"; 4990 } 4991 else if (pos >= 32) 4992 { 4993 s = "dinsu"; 4994 fmt = "t,r,+E,+F"; 4995 } 4996 else 4997 { 4998 s = "dinsm"; 4999 fmt = "t,r,+A,+F"; 5000 } 5001 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, 5002 pos + size - 1); 5003 } 5004 return; 5005 5006 case M_DDIV_3: 5007 dbl = 1; 5008 case M_DIV_3: 5009 s = "mflo"; 5010 goto do_div3; 5011 case M_DREM_3: 5012 dbl = 1; 5013 case M_REM_3: 5014 s = "mfhi"; 5015 do_div3: 5016 if (treg == 0) 5017 { 5018 as_warn (_("Divide by zero.")); 5019 if (mips_trap) 5020 macro_build (NULL, "teq", "s,t,q", 0, 0, 7); 5021 else 5022 macro_build (NULL, "break", "c", 7); 5023 return; 5024 } 5025 5026 mips_emit_delays (TRUE); 5027 ++mips_opts.noreorder; 5028 mips_any_noreorder = 1; 5029 if (mips_trap) 5030 { 5031 macro_build (NULL, "teq", "s,t,q", treg, 0, 7); 5032 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); 5033 } 5034 else 5035 { 5036 expr1.X_add_number = 8; 5037 macro_build (&expr1, "bne", "s,t,p", treg, 0); 5038 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); 5039 macro_build (NULL, "break", "c", 7); 5040 } 5041 expr1.X_add_number = -1; 5042 load_register (AT, &expr1, dbl); 5043 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); 5044 macro_build (&expr1, "bne", "s,t,p", treg, AT); 5045 if (dbl) 5046 { 5047 expr1.X_add_number = 1; 5048 load_register (AT, &expr1, dbl); 5049 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); 5050 } 5051 else 5052 { 5053 expr1.X_add_number = 0x80000000; 5054 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); 5055 } 5056 if (mips_trap) 5057 { 5058 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); 5059 /* We want to close the noreorder block as soon as possible, so 5060 that later insns are available for delay slot filling. */ 5061 --mips_opts.noreorder; 5062 } 5063 else 5064 { 5065 expr1.X_add_number = 8; 5066 macro_build (&expr1, "bne", "s,t,p", sreg, AT); 5067 macro_build (NULL, "nop", "", 0); 5068 5069 /* We want to close the noreorder block as soon as possible, so 5070 that later insns are available for delay slot filling. */ 5071 --mips_opts.noreorder; 5072 5073 macro_build (NULL, "break", "c", 6); 5074 } 5075 macro_build (NULL, s, "d", dreg); 5076 break; 5077 5078 case M_DIV_3I: 5079 s = "div"; 5080 s2 = "mflo"; 5081 goto do_divi; 5082 case M_DIVU_3I: 5083 s = "divu"; 5084 s2 = "mflo"; 5085 goto do_divi; 5086 case M_REM_3I: 5087 s = "div"; 5088 s2 = "mfhi"; 5089 goto do_divi; 5090 case M_REMU_3I: 5091 s = "divu"; 5092 s2 = "mfhi"; 5093 goto do_divi; 5094 case M_DDIV_3I: 5095 dbl = 1; 5096 s = "ddiv"; 5097 s2 = "mflo"; 5098 goto do_divi; 5099 case M_DDIVU_3I: 5100 dbl = 1; 5101 s = "ddivu"; 5102 s2 = "mflo"; 5103 goto do_divi; 5104 case M_DREM_3I: 5105 dbl = 1; 5106 s = "ddiv"; 5107 s2 = "mfhi"; 5108 goto do_divi; 5109 case M_DREMU_3I: 5110 dbl = 1; 5111 s = "ddivu"; 5112 s2 = "mfhi"; 5113 do_divi: 5114 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 5115 { 5116 as_warn (_("Divide by zero.")); 5117 if (mips_trap) 5118 macro_build (NULL, "teq", "s,t,q", 0, 0, 7); 5119 else 5120 macro_build (NULL, "break", "c", 7); 5121 return; 5122 } 5123 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 5124 { 5125 if (strcmp (s2, "mflo") == 0) 5126 move_register (dreg, sreg); 5127 else 5128 move_register (dreg, 0); 5129 return; 5130 } 5131 if (imm_expr.X_op == O_constant 5132 && imm_expr.X_add_number == -1 5133 && s[strlen (s) - 1] != 'u') 5134 { 5135 if (strcmp (s2, "mflo") == 0) 5136 { 5137 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); 5138 } 5139 else 5140 move_register (dreg, 0); 5141 return; 5142 } 5143 5144 load_register (AT, &imm_expr, dbl); 5145 macro_build (NULL, s, "z,s,t", sreg, AT); 5146 macro_build (NULL, s2, "d", dreg); 5147 break; 5148 5149 case M_DIVU_3: 5150 s = "divu"; 5151 s2 = "mflo"; 5152 goto do_divu3; 5153 case M_REMU_3: 5154 s = "divu"; 5155 s2 = "mfhi"; 5156 goto do_divu3; 5157 case M_DDIVU_3: 5158 s = "ddivu"; 5159 s2 = "mflo"; 5160 goto do_divu3; 5161 case M_DREMU_3: 5162 s = "ddivu"; 5163 s2 = "mfhi"; 5164 do_divu3: 5165 mips_emit_delays (TRUE); 5166 ++mips_opts.noreorder; 5167 mips_any_noreorder = 1; 5168 if (mips_trap) 5169 { 5170 macro_build (NULL, "teq", "s,t,q", treg, 0, 7); 5171 macro_build (NULL, s, "z,s,t", sreg, treg); 5172 /* We want to close the noreorder block as soon as possible, so 5173 that later insns are available for delay slot filling. */ 5174 --mips_opts.noreorder; 5175 } 5176 else 5177 { 5178 expr1.X_add_number = 8; 5179 macro_build (&expr1, "bne", "s,t,p", treg, 0); 5180 macro_build (NULL, s, "z,s,t", sreg, treg); 5181 5182 /* We want to close the noreorder block as soon as possible, so 5183 that later insns are available for delay slot filling. */ 5184 --mips_opts.noreorder; 5185 macro_build (NULL, "break", "c", 7); 5186 } 5187 macro_build (NULL, s2, "d", dreg); 5188 return; 5189 5190 case M_DLCA_AB: 5191 dbl = 1; 5192 case M_LCA_AB: 5193 call = 1; 5194 goto do_la; 5195 case M_DLA_AB: 5196 dbl = 1; 5197 case M_LA_AB: 5198 do_la: 5199 /* Load the address of a symbol into a register. If breg is not 5200 zero, we then add a base register to it. */ 5201 5202 if (dbl && HAVE_32BIT_GPRS) 5203 as_warn (_("dla used to load 32-bit register")); 5204 5205 if (! dbl && HAVE_64BIT_OBJECTS) 5206 as_warn (_("la used to load 64-bit address")); 5207 5208 if (offset_expr.X_op == O_constant 5209 && offset_expr.X_add_number >= -0x8000 5210 && offset_expr.X_add_number < 0x8000) 5211 { 5212 macro_build (&offset_expr, 5213 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", 5214 "t,r,j", treg, sreg, BFD_RELOC_LO16); 5215 return; 5216 } 5217 5218 if (treg == breg) 5219 { 5220 tempreg = AT; 5221 used_at = 1; 5222 } 5223 else 5224 { 5225 tempreg = treg; 5226 used_at = 0; 5227 } 5228 5229 /* When generating embedded PIC code, we permit expressions of 5230 the form 5231 la $treg,foo-bar 5232 la $treg,foo-bar($breg) 5233 where bar is an address in the current section. These are used 5234 when getting the addresses of functions. We don't permit 5235 X_add_number to be non-zero, because if the symbol is 5236 external the relaxing code needs to know that any addend is 5237 purely the offset to X_op_symbol. */ 5238 if (mips_pic == EMBEDDED_PIC 5239 && offset_expr.X_op == O_subtract 5240 && (symbol_constant_p (offset_expr.X_op_symbol) 5241 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg 5242 : (symbol_equated_p (offset_expr.X_op_symbol) 5243 && (S_GET_SEGMENT 5244 (symbol_get_value_expression (offset_expr.X_op_symbol) 5245 ->X_add_symbol) 5246 == now_seg))) 5247 && (offset_expr.X_add_number == 0 5248 || OUTPUT_FLAVOR == bfd_target_elf_flavour)) 5249 { 5250 if (breg == 0) 5251 { 5252 tempreg = treg; 5253 used_at = 0; 5254 macro_build (&offset_expr, "lui", "t,u", 5255 tempreg, BFD_RELOC_PCREL_HI16_S); 5256 } 5257 else 5258 { 5259 macro_build (&offset_expr, "lui", "t,u", 5260 tempreg, BFD_RELOC_PCREL_HI16_S); 5261 macro_build (NULL, 5262 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", 5263 "d,v,t", tempreg, tempreg, breg); 5264 } 5265 macro_build (&offset_expr, 5266 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", 5267 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16); 5268 if (! used_at) 5269 return; 5270 break; 5271 } 5272 5273 if (offset_expr.X_op != O_symbol 5274 && offset_expr.X_op != O_constant) 5275 { 5276 as_bad (_("expression too complex")); 5277 offset_expr.X_op = O_constant; 5278 } 5279 5280 if (offset_expr.X_op == O_constant) 5281 load_register (tempreg, &offset_expr, 5282 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) 5283 ? (dbl || HAVE_64BIT_ADDRESSES) 5284 : HAVE_64BIT_ADDRESSES)); 5285 else if (mips_pic == NO_PIC) 5286 { 5287 /* If this is a reference to a GP relative symbol, we want 5288 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) 5289 Otherwise we want 5290 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 5291 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 5292 If we have a constant, we need two instructions anyhow, 5293 so we may as well always use the latter form. 5294 5295 With 64bit address space and a usable $at we want 5296 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 5297 lui $at,<sym> (BFD_RELOC_HI16_S) 5298 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 5299 daddiu $at,<sym> (BFD_RELOC_LO16) 5300 dsll32 $tempreg,0 5301 daddu $tempreg,$tempreg,$at 5302 5303 If $at is already in use, we use a path which is suboptimal 5304 on superscalar processors. 5305 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 5306 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 5307 dsll $tempreg,16 5308 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 5309 dsll $tempreg,16 5310 daddiu $tempreg,<sym> (BFD_RELOC_LO16) 5311 */ 5312 if (HAVE_64BIT_ADDRESSES) 5313 { 5314 /* ??? We don't provide a GP-relative alternative for 5315 these macros. It used not to be possible with the 5316 original relaxation code, but it could be done now. */ 5317 5318 if (used_at == 0 && ! mips_opts.noat) 5319 { 5320 macro_build (&offset_expr, "lui", "t,u", 5321 tempreg, BFD_RELOC_MIPS_HIGHEST); 5322 macro_build (&offset_expr, "lui", "t,u", 5323 AT, BFD_RELOC_HI16_S); 5324 macro_build (&offset_expr, "daddiu", "t,r,j", 5325 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 5326 macro_build (&offset_expr, "daddiu", "t,r,j", 5327 AT, AT, BFD_RELOC_LO16); 5328 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); 5329 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 5330 used_at = 1; 5331 } 5332 else 5333 { 5334 macro_build (&offset_expr, "lui", "t,u", 5335 tempreg, BFD_RELOC_MIPS_HIGHEST); 5336 macro_build (&offset_expr, "daddiu", "t,r,j", 5337 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 5338 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 5339 macro_build (&offset_expr, "daddiu", "t,r,j", 5340 tempreg, tempreg, BFD_RELOC_HI16_S); 5341 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 5342 macro_build (&offset_expr, "daddiu", "t,r,j", 5343 tempreg, tempreg, BFD_RELOC_LO16); 5344 } 5345 } 5346 else 5347 { 5348 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 5349 && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) 5350 { 5351 relax_start (offset_expr.X_add_symbol); 5352 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5353 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 5354 relax_switch (); 5355 } 5356 macro_build_lui (&offset_expr, tempreg); 5357 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5358 tempreg, tempreg, BFD_RELOC_LO16); 5359 if (mips_relax.sequence) 5360 relax_end (); 5361 } 5362 } 5363 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) 5364 { 5365 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 5366 5367 /* If this is a reference to an external symbol, and there 5368 is no constant, we want 5369 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5370 or for lca or if tempreg is PIC_CALL_REG 5371 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 5372 For a local symbol, we want 5373 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5374 nop 5375 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 5376 5377 If we have a small constant, and this is a reference to 5378 an external symbol, we want 5379 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5380 nop 5381 addiu $tempreg,$tempreg,<constant> 5382 For a local symbol, we want the same instruction 5383 sequence, but we output a BFD_RELOC_LO16 reloc on the 5384 addiu instruction. 5385 5386 If we have a large constant, and this is a reference to 5387 an external symbol, we want 5388 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5389 lui $at,<hiconstant> 5390 addiu $at,$at,<loconstant> 5391 addu $tempreg,$tempreg,$at 5392 For a local symbol, we want the same instruction 5393 sequence, but we output a BFD_RELOC_LO16 reloc on the 5394 addiu instruction. 5395 */ 5396 5397 if (offset_expr.X_add_number == 0) 5398 { 5399 if (breg == 0 && (call || tempreg == PIC_CALL_REG)) 5400 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; 5401 5402 relax_start (offset_expr.X_add_symbol); 5403 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5404 lw_reloc_type, mips_gp_register); 5405 if (breg != 0) 5406 { 5407 /* We're going to put in an addu instruction using 5408 tempreg, so we may as well insert the nop right 5409 now. */ 5410 macro_build (NULL, "nop", ""); 5411 } 5412 relax_switch (); 5413 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5414 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); 5415 macro_build (NULL, "nop", ""); 5416 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5417 tempreg, tempreg, BFD_RELOC_LO16); 5418 relax_end (); 5419 /* FIXME: If breg == 0, and the next instruction uses 5420 $tempreg, then if this variant case is used an extra 5421 nop will be generated. */ 5422 } 5423 else if (offset_expr.X_add_number >= -0x8000 5424 && offset_expr.X_add_number < 0x8000) 5425 { 5426 load_got_offset (tempreg, &offset_expr); 5427 macro_build (NULL, "nop", ""); 5428 add_got_offset (tempreg, &offset_expr); 5429 } 5430 else 5431 { 5432 expr1.X_add_number = offset_expr.X_add_number; 5433 offset_expr.X_add_number = 5434 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; 5435 load_got_offset (tempreg, &offset_expr); 5436 offset_expr.X_add_number = expr1.X_add_number; 5437 /* If we are going to add in a base register, and the 5438 target register and the base register are the same, 5439 then we are using AT as a temporary register. Since 5440 we want to load the constant into AT, we add our 5441 current AT (from the global offset table) and the 5442 register into the register now, and pretend we were 5443 not using a base register. */ 5444 if (breg == treg) 5445 { 5446 macro_build (NULL, "nop", ""); 5447 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5448 treg, AT, breg); 5449 breg = 0; 5450 tempreg = treg; 5451 } 5452 add_got_offset_hilo (tempreg, &offset_expr, AT); 5453 used_at = 1; 5454 } 5455 } 5456 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) 5457 { 5458 int add_breg_early = 0; 5459 5460 /* If this is a reference to an external, and there is no 5461 constant, or local symbol (*), with or without a 5462 constant, we want 5463 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 5464 or for lca or if tempreg is PIC_CALL_REG 5465 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 5466 5467 If we have a small constant, and this is a reference to 5468 an external symbol, we want 5469 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 5470 addiu $tempreg,$tempreg,<constant> 5471 5472 If we have a large constant, and this is a reference to 5473 an external symbol, we want 5474 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 5475 lui $at,<hiconstant> 5476 addiu $at,$at,<loconstant> 5477 addu $tempreg,$tempreg,$at 5478 5479 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for 5480 local symbols, even though it introduces an additional 5481 instruction. */ 5482 5483 if (offset_expr.X_add_number) 5484 { 5485 expr1.X_add_number = offset_expr.X_add_number; 5486 offset_expr.X_add_number = 0; 5487 5488 relax_start (offset_expr.X_add_symbol); 5489 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5490 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5491 5492 if (expr1.X_add_number >= -0x8000 5493 && expr1.X_add_number < 0x8000) 5494 { 5495 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 5496 tempreg, tempreg, BFD_RELOC_LO16); 5497 } 5498 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 5499 { 5500 int dreg; 5501 5502 /* If we are going to add in a base register, and the 5503 target register and the base register are the same, 5504 then we are using AT as a temporary register. Since 5505 we want to load the constant into AT, we add our 5506 current AT (from the global offset table) and the 5507 register into the register now, and pretend we were 5508 not using a base register. */ 5509 if (breg != treg) 5510 dreg = tempreg; 5511 else 5512 { 5513 assert (tempreg == AT); 5514 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5515 treg, AT, breg); 5516 dreg = treg; 5517 add_breg_early = 1; 5518 } 5519 5520 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 5521 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5522 dreg, dreg, AT); 5523 5524 used_at = 1; 5525 } 5526 else 5527 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 5528 5529 relax_switch (); 5530 offset_expr.X_add_number = expr1.X_add_number; 5531 5532 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5533 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5534 if (add_breg_early) 5535 { 5536 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5537 treg, tempreg, breg); 5538 breg = 0; 5539 tempreg = treg; 5540 } 5541 relax_end (); 5542 } 5543 else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) 5544 { 5545 relax_start (offset_expr.X_add_symbol); 5546 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5547 BFD_RELOC_MIPS_CALL16, mips_gp_register); 5548 relax_switch (); 5549 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5550 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5551 relax_end (); 5552 } 5553 else 5554 { 5555 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5556 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5557 } 5558 } 5559 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) 5560 { 5561 int gpdelay; 5562 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 5563 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 5564 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 5565 5566 /* This is the large GOT case. If this is a reference to an 5567 external symbol, and there is no constant, we want 5568 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5569 addu $tempreg,$tempreg,$gp 5570 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5571 or for lca or if tempreg is PIC_CALL_REG 5572 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 5573 addu $tempreg,$tempreg,$gp 5574 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 5575 For a local symbol, we want 5576 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5577 nop 5578 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 5579 5580 If we have a small constant, and this is a reference to 5581 an external symbol, we want 5582 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5583 addu $tempreg,$tempreg,$gp 5584 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5585 nop 5586 addiu $tempreg,$tempreg,<constant> 5587 For a local symbol, we want 5588 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5589 nop 5590 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) 5591 5592 If we have a large constant, and this is a reference to 5593 an external symbol, we want 5594 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5595 addu $tempreg,$tempreg,$gp 5596 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5597 lui $at,<hiconstant> 5598 addiu $at,$at,<loconstant> 5599 addu $tempreg,$tempreg,$at 5600 For a local symbol, we want 5601 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5602 lui $at,<hiconstant> 5603 addiu $at,$at,<loconstant> (BFD_RELOC_LO16) 5604 addu $tempreg,$tempreg,$at 5605 */ 5606 5607 expr1.X_add_number = offset_expr.X_add_number; 5608 offset_expr.X_add_number = 0; 5609 relax_start (offset_expr.X_add_symbol); 5610 gpdelay = reg_needs_delay (mips_gp_register); 5611 if (expr1.X_add_number == 0 && breg == 0 5612 && (call || tempreg == PIC_CALL_REG)) 5613 { 5614 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 5615 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 5616 } 5617 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); 5618 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5619 tempreg, tempreg, mips_gp_register); 5620 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5621 tempreg, lw_reloc_type, tempreg); 5622 if (expr1.X_add_number == 0) 5623 { 5624 if (breg != 0) 5625 { 5626 /* We're going to put in an addu instruction using 5627 tempreg, so we may as well insert the nop right 5628 now. */ 5629 macro_build (NULL, "nop", ""); 5630 } 5631 } 5632 else if (expr1.X_add_number >= -0x8000 5633 && expr1.X_add_number < 0x8000) 5634 { 5635 macro_build (NULL, "nop", ""); 5636 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 5637 tempreg, tempreg, BFD_RELOC_LO16); 5638 } 5639 else 5640 { 5641 int dreg; 5642 5643 /* If we are going to add in a base register, and the 5644 target register and the base register are the same, 5645 then we are using AT as a temporary register. Since 5646 we want to load the constant into AT, we add our 5647 current AT (from the global offset table) and the 5648 register into the register now, and pretend we were 5649 not using a base register. */ 5650 if (breg != treg) 5651 dreg = tempreg; 5652 else 5653 { 5654 assert (tempreg == AT); 5655 macro_build (NULL, "nop", ""); 5656 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5657 treg, AT, breg); 5658 dreg = treg; 5659 } 5660 5661 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 5662 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 5663 5664 used_at = 1; 5665 } 5666 offset_expr.X_add_number = 5667 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; 5668 relax_switch (); 5669 5670 if (gpdelay) 5671 { 5672 /* This is needed because this instruction uses $gp, but 5673 the first instruction on the main stream does not. */ 5674 macro_build (NULL, "nop", ""); 5675 } 5676 5677 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5678 local_reloc_type, mips_gp_register); 5679 if (expr1.X_add_number >= -0x8000 5680 && expr1.X_add_number < 0x8000) 5681 { 5682 macro_build (NULL, "nop", ""); 5683 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5684 tempreg, tempreg, BFD_RELOC_LO16); 5685 /* FIXME: If add_number is 0, and there was no base 5686 register, the external symbol case ended with a load, 5687 so if the symbol turns out to not be external, and 5688 the next instruction uses tempreg, an unnecessary nop 5689 will be inserted. */ 5690 } 5691 else 5692 { 5693 if (breg == treg) 5694 { 5695 /* We must add in the base register now, as in the 5696 external symbol case. */ 5697 assert (tempreg == AT); 5698 macro_build (NULL, "nop", ""); 5699 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5700 treg, AT, breg); 5701 tempreg = treg; 5702 /* We set breg to 0 because we have arranged to add 5703 it in in both cases. */ 5704 breg = 0; 5705 } 5706 5707 macro_build_lui (&expr1, AT); 5708 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5709 AT, AT, BFD_RELOC_LO16); 5710 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5711 tempreg, tempreg, AT); 5712 } 5713 relax_end (); 5714 } 5715 else if (mips_pic == SVR4_PIC && HAVE_NEWABI) 5716 { 5717 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 5718 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 5719 int add_breg_early = 0; 5720 5721 /* This is the large GOT case. If this is a reference to an 5722 external symbol, and there is no constant, we want 5723 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5724 add $tempreg,$tempreg,$gp 5725 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5726 or for lca or if tempreg is PIC_CALL_REG 5727 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 5728 add $tempreg,$tempreg,$gp 5729 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 5730 5731 If we have a small constant, and this is a reference to 5732 an external symbol, we want 5733 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5734 add $tempreg,$tempreg,$gp 5735 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5736 addi $tempreg,$tempreg,<constant> 5737 5738 If we have a large constant, and this is a reference to 5739 an external symbol, we want 5740 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5741 addu $tempreg,$tempreg,$gp 5742 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5743 lui $at,<hiconstant> 5744 addi $at,$at,<loconstant> 5745 add $tempreg,$tempreg,$at 5746 5747 If we have NewABI, and we know it's a local symbol, we want 5748 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 5749 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 5750 otherwise we have to resort to GOT_HI16/GOT_LO16. */ 5751 5752 relax_start (offset_expr.X_add_symbol); 5753 5754 expr1.X_add_number = offset_expr.X_add_number; 5755 offset_expr.X_add_number = 0; 5756 5757 if (expr1.X_add_number == 0 && breg == 0 5758 && (call || tempreg == PIC_CALL_REG)) 5759 { 5760 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 5761 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 5762 } 5763 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); 5764 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5765 tempreg, tempreg, mips_gp_register); 5766 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5767 tempreg, lw_reloc_type, tempreg); 5768 5769 if (expr1.X_add_number == 0) 5770 ; 5771 else if (expr1.X_add_number >= -0x8000 5772 && expr1.X_add_number < 0x8000) 5773 { 5774 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 5775 tempreg, tempreg, BFD_RELOC_LO16); 5776 } 5777 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 5778 { 5779 int dreg; 5780 5781 /* If we are going to add in a base register, and the 5782 target register and the base register are the same, 5783 then we are using AT as a temporary register. Since 5784 we want to load the constant into AT, we add our 5785 current AT (from the global offset table) and the 5786 register into the register now, and pretend we were 5787 not using a base register. */ 5788 if (breg != treg) 5789 dreg = tempreg; 5790 else 5791 { 5792 assert (tempreg == AT); 5793 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5794 treg, AT, breg); 5795 dreg = treg; 5796 add_breg_early = 1; 5797 } 5798 5799 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 5800 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 5801 5802 used_at = 1; 5803 } 5804 else 5805 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 5806 5807 relax_switch (); 5808 offset_expr.X_add_number = expr1.X_add_number; 5809 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5810 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 5811 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 5812 tempreg, BFD_RELOC_MIPS_GOT_OFST); 5813 if (add_breg_early) 5814 { 5815 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5816 treg, tempreg, breg); 5817 breg = 0; 5818 tempreg = treg; 5819 } 5820 relax_end (); 5821 } 5822 else if (mips_pic == EMBEDDED_PIC) 5823 { 5824 /* We use 5825 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) 5826 */ 5827 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 5828 mips_gp_register, BFD_RELOC_GPREL16); 5829 } 5830 else 5831 abort (); 5832 5833 if (breg != 0) 5834 { 5835 char *s; 5836 5837 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) 5838 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; 5839 else 5840 s = ADDRESS_ADD_INSN; 5841 5842 macro_build (NULL, s, "d,v,t", treg, tempreg, breg); 5843 } 5844 5845 if (! used_at) 5846 return; 5847 5848 break; 5849 5850 case M_JR_S: 5851 macro_build_jrpatch (&expr1, sreg); 5852 macro_build (NULL, "jr", "s", sreg); 5853 return; /* didn't modify $at */ 5854 5855 case M_J_S: 5856 macro_build_jrpatch (&expr1, sreg); 5857 macro_build (NULL, "j", "s", sreg); 5858 return; /* didn't modify $at */ 5859 5860 case M_JALR_S: 5861 macro_build_jrpatch (&expr1, sreg); 5862 macro_build (NULL, "jalr", "s", sreg); 5863 return; /* didn't modify $at */ 5864 5865 case M_JALR_DS: 5866 macro_build_jrpatch (&expr1, sreg); 5867 macro_build (NULL, "jalr", "d,s", dreg, sreg); 5868 return; /* didn't modify $at */ 5869 5870 case M_J_A: 5871 /* The j instruction may not be used in PIC code, since it 5872 requires an absolute address. We convert it to a b 5873 instruction. */ 5874 if (mips_pic == NO_PIC) 5875 macro_build (&offset_expr, "j", "a"); 5876 else 5877 macro_build (&offset_expr, "b", "p"); 5878 return; 5879 5880 /* The jal instructions must be handled as macros because when 5881 generating PIC code they expand to multi-instruction 5882 sequences. Normally they are simple instructions. */ 5883 case M_JAL_1: 5884 dreg = RA; 5885 /* Fall through. */ 5886 case M_JAL_2: 5887 if (mips_pic == NO_PIC 5888 || mips_pic == EMBEDDED_PIC) 5889 { 5890 macro_build_jrpatch (&expr1, sreg); 5891 macro_build (NULL, "jalr", "d,s", dreg, sreg); 5892 } 5893 else if (mips_pic == SVR4_PIC) 5894 { 5895 if (sreg != PIC_CALL_REG) 5896 as_warn (_("MIPS PIC call to register other than $25")); 5897 5898 macro_build_jrpatch (&expr1, sreg); 5899 macro_build (NULL, "jalr", "d,s", dreg, sreg); 5900 if (! HAVE_NEWABI) 5901 { 5902 if (mips_cprestore_offset < 0) 5903 as_warn (_("No .cprestore pseudo-op used in PIC code")); 5904 else 5905 { 5906 if (! mips_frame_reg_valid) 5907 { 5908 as_warn (_("No .frame pseudo-op used in PIC code")); 5909 /* Quiet this warning. */ 5910 mips_frame_reg_valid = 1; 5911 } 5912 if (! mips_cprestore_valid) 5913 { 5914 as_warn (_("No .cprestore pseudo-op used in PIC code")); 5915 /* Quiet this warning. */ 5916 mips_cprestore_valid = 1; 5917 } 5918 expr1.X_add_number = mips_cprestore_offset; 5919 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 5920 mips_gp_register, 5921 mips_frame_reg, 5922 HAVE_64BIT_ADDRESSES); 5923 } 5924 } 5925 } 5926 else 5927 abort (); 5928 5929 return; 5930 5931 case M_JAL_A: 5932 if (mips_pic == NO_PIC) 5933 macro_build (&offset_expr, "jal", "a"); 5934 else if (mips_pic == SVR4_PIC) 5935 { 5936 /* If this is a reference to an external symbol, and we are 5937 using a small GOT, we want 5938 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 5939 nop 5940 jalr $ra,$25 5941 nop 5942 lw $gp,cprestore($sp) 5943 The cprestore value is set using the .cprestore 5944 pseudo-op. If we are using a big GOT, we want 5945 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) 5946 addu $25,$25,$gp 5947 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) 5948 nop 5949 jalr $ra,$25 5950 nop 5951 lw $gp,cprestore($sp) 5952 If the symbol is not external, we want 5953 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5954 nop 5955 addiu $25,$25,<sym> (BFD_RELOC_LO16) 5956 jalr $ra,$25 5957 nop 5958 lw $gp,cprestore($sp) 5959 5960 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 5961 sequences above, minus nops, unless the symbol is local, 5962 which enables us to use GOT_PAGE/GOT_OFST (big got) or 5963 GOT_DISP. */ 5964 if (HAVE_NEWABI) 5965 { 5966 if (! mips_big_got) 5967 { 5968 relax_start (offset_expr.X_add_symbol); 5969 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5970 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 5971 mips_gp_register); 5972 relax_switch (); 5973 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5974 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, 5975 mips_gp_register); 5976 relax_end (); 5977 } 5978 else 5979 { 5980 relax_start (offset_expr.X_add_symbol); 5981 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, 5982 BFD_RELOC_MIPS_CALL_HI16); 5983 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 5984 PIC_CALL_REG, mips_gp_register); 5985 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5986 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 5987 PIC_CALL_REG); 5988 relax_switch (); 5989 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5990 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, 5991 mips_gp_register); 5992 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5993 PIC_CALL_REG, PIC_CALL_REG, 5994 BFD_RELOC_MIPS_GOT_OFST); 5995 relax_end (); 5996 } 5997 5998 macro_build_jalr (&offset_expr); 5999 } 6000 else 6001 { 6002 relax_start (offset_expr.X_add_symbol); 6003 if (! mips_big_got) 6004 { 6005 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 6006 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 6007 mips_gp_register); 6008 macro_build (NULL, "nop", ""); 6009 relax_switch (); 6010 } 6011 else 6012 { 6013 int gpdelay; 6014 6015 gpdelay = reg_needs_delay (mips_gp_register); 6016 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, 6017 BFD_RELOC_MIPS_CALL_HI16); 6018 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 6019 PIC_CALL_REG, mips_gp_register); 6020 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 6021 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 6022 PIC_CALL_REG); 6023 macro_build (NULL, "nop", ""); 6024 relax_switch (); 6025 if (gpdelay) 6026 macro_build (NULL, "nop", ""); 6027 } 6028 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 6029 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, 6030 mips_gp_register); 6031 macro_build (NULL, "nop", ""); 6032 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 6033 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); 6034 relax_end (); 6035 macro_build_jalr (&offset_expr); 6036 6037 if (mips_cprestore_offset < 0) 6038 as_warn (_("No .cprestore pseudo-op used in PIC code")); 6039 else 6040 { 6041 if (! mips_frame_reg_valid) 6042 { 6043 as_warn (_("No .frame pseudo-op used in PIC code")); 6044 /* Quiet this warning. */ 6045 mips_frame_reg_valid = 1; 6046 } 6047 if (! mips_cprestore_valid) 6048 { 6049 as_warn (_("No .cprestore pseudo-op used in PIC code")); 6050 /* Quiet this warning. */ 6051 mips_cprestore_valid = 1; 6052 } 6053 if (mips_opts.noreorder) 6054 macro_build (NULL, "nop", ""); 6055 expr1.X_add_number = mips_cprestore_offset; 6056 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 6057 mips_gp_register, 6058 mips_frame_reg, 6059 HAVE_64BIT_ADDRESSES); 6060 } 6061 } 6062 } 6063 else if (mips_pic == EMBEDDED_PIC) 6064 { 6065 macro_build (&offset_expr, "bal", "p"); 6066 /* The linker may expand the call to a longer sequence which 6067 uses $at, so we must break rather than return. */ 6068 break; 6069 } 6070 else 6071 abort (); 6072 6073 return; 6074 6075 case M_LB_AB: 6076 s = "lb"; 6077 goto ld; 6078 case M_LBU_AB: 6079 s = "lbu"; 6080 goto ld; 6081 case M_LH_AB: 6082 s = "lh"; 6083 goto ld; 6084 case M_LHU_AB: 6085 s = "lhu"; 6086 goto ld; 6087 case M_LW_AB: 6088 s = "lw"; 6089 goto ld; 6090 case M_LWC0_AB: 6091 s = "lwc0"; 6092 /* Itbl support may require additional care here. */ 6093 coproc = 1; 6094 goto ld; 6095 case M_LWC1_AB: 6096 s = "lwc1"; 6097 /* Itbl support may require additional care here. */ 6098 coproc = 1; 6099 goto ld; 6100 case M_LWC2_AB: 6101 s = "lwc2"; 6102 /* Itbl support may require additional care here. */ 6103 coproc = 1; 6104 goto ld; 6105 case M_LWC3_AB: 6106 s = "lwc3"; 6107 /* Itbl support may require additional care here. */ 6108 coproc = 1; 6109 goto ld; 6110 case M_LWL_AB: 6111 s = "lwl"; 6112 lr = 1; 6113 goto ld; 6114 case M_LWR_AB: 6115 s = "lwr"; 6116 lr = 1; 6117 goto ld; 6118 case M_LDC1_AB: 6119 if (mips_opts.arch == CPU_R4650) 6120 { 6121 as_bad (_("opcode not supported on this processor")); 6122 return; 6123 } 6124 s = "ldc1"; 6125 /* Itbl support may require additional care here. */ 6126 coproc = 1; 6127 goto ld; 6128 case M_LDC2_AB: 6129 s = "ldc2"; 6130 /* Itbl support may require additional care here. */ 6131 coproc = 1; 6132 goto ld; 6133 case M_LDC3_AB: 6134 s = "ldc3"; 6135 /* Itbl support may require additional care here. */ 6136 coproc = 1; 6137 goto ld; 6138 case M_LDL_AB: 6139 s = "ldl"; 6140 lr = 1; 6141 goto ld; 6142 case M_LDR_AB: 6143 s = "ldr"; 6144 lr = 1; 6145 goto ld; 6146 case M_LL_AB: 6147 s = "ll"; 6148 goto ld; 6149 case M_LLD_AB: 6150 s = "lld"; 6151 goto ld; 6152 case M_LWU_AB: 6153 s = "lwu"; 6154 ld: 6155 if (breg == treg || coproc || lr) 6156 { 6157 tempreg = AT; 6158 used_at = 1; 6159 } 6160 else 6161 { 6162 tempreg = treg; 6163 used_at = 0; 6164 } 6165 goto ld_st; 6166 case M_SB_AB: 6167 s = "sb"; 6168 goto st; 6169 case M_SH_AB: 6170 s = "sh"; 6171 goto st; 6172 case M_SW_AB: 6173 s = "sw"; 6174 goto st; 6175 case M_SWC0_AB: 6176 s = "swc0"; 6177 /* Itbl support may require additional care here. */ 6178 coproc = 1; 6179 goto st; 6180 case M_SWC1_AB: 6181 s = "swc1"; 6182 /* Itbl support may require additional care here. */ 6183 coproc = 1; 6184 goto st; 6185 case M_SWC2_AB: 6186 s = "swc2"; 6187 /* Itbl support may require additional care here. */ 6188 coproc = 1; 6189 goto st; 6190 case M_SWC3_AB: 6191 s = "swc3"; 6192 /* Itbl support may require additional care here. */ 6193 coproc = 1; 6194 goto st; 6195 case M_SWL_AB: 6196 s = "swl"; 6197 goto st; 6198 case M_SWR_AB: 6199 s = "swr"; 6200 goto st; 6201 case M_SC_AB: 6202 s = "sc"; 6203 goto st; 6204 case M_SCD_AB: 6205 s = "scd"; 6206 goto st; 6207 case M_SDC1_AB: 6208 if (mips_opts.arch == CPU_R4650) 6209 { 6210 as_bad (_("opcode not supported on this processor")); 6211 return; 6212 } 6213 s = "sdc1"; 6214 coproc = 1; 6215 /* Itbl support may require additional care here. */ 6216 goto st; 6217 case M_SDC2_AB: 6218 s = "sdc2"; 6219 /* Itbl support may require additional care here. */ 6220 coproc = 1; 6221 goto st; 6222 case M_SDC3_AB: 6223 s = "sdc3"; 6224 /* Itbl support may require additional care here. */ 6225 coproc = 1; 6226 goto st; 6227 case M_SDL_AB: 6228 s = "sdl"; 6229 goto st; 6230 case M_SDR_AB: 6231 s = "sdr"; 6232 st: 6233 tempreg = AT; 6234 used_at = 1; 6235 ld_st: 6236 /* Itbl support may require additional care here. */ 6237 if (mask == M_LWC1_AB 6238 || mask == M_SWC1_AB 6239 || mask == M_LDC1_AB 6240 || mask == M_SDC1_AB 6241 || mask == M_L_DAB 6242 || mask == M_S_DAB) 6243 fmt = "T,o(b)"; 6244 else if (coproc) 6245 fmt = "E,o(b)"; 6246 else 6247 fmt = "t,o(b)"; 6248 6249 /* Sign-extending 32-bit constants makes their handling easier. 6250 The HAVE_64BIT_GPRS... part is due to the linux kernel hack 6251 described below. */ 6252 if ((! HAVE_64BIT_ADDRESSES 6253 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) 6254 && (offset_expr.X_op == O_constant) 6255 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) 6256 == ~((bfd_vma) 0x7fffffff))) 6257 { 6258 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) 6259 as_bad (_("constant too large")); 6260 6261 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) 6262 ^ 0x80000000) - 0x80000000); 6263 } 6264 6265 /* For embedded PIC, we allow loads where the offset is calculated 6266 by subtracting a symbol in the current segment from an unknown 6267 symbol, relative to a base register, e.g.: 6268 <op> $treg, <sym>-<localsym>($breg) 6269 This is used by the compiler for switch statements. */ 6270 if (mips_pic == EMBEDDED_PIC 6271 && offset_expr.X_op == O_subtract 6272 && (symbol_constant_p (offset_expr.X_op_symbol) 6273 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg 6274 : (symbol_equated_p (offset_expr.X_op_symbol) 6275 && (S_GET_SEGMENT 6276 (symbol_get_value_expression (offset_expr.X_op_symbol) 6277 ->X_add_symbol) 6278 == now_seg))) 6279 && breg != 0 6280 && (offset_expr.X_add_number == 0 6281 || OUTPUT_FLAVOR == bfd_target_elf_flavour)) 6282 { 6283 /* For this case, we output the instructions: 6284 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) 6285 addiu $tempreg,$tempreg,$breg 6286 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) 6287 If the relocation would fit entirely in 16 bits, it would be 6288 nice to emit: 6289 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) 6290 instead, but that seems quite difficult. */ 6291 macro_build (&offset_expr, "lui", "t,u", tempreg, 6292 BFD_RELOC_PCREL_HI16_S); 6293 macro_build (NULL, 6294 ((bfd_arch_bits_per_address (stdoutput) == 32 6295 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) 6296 ? "addu" : "daddu"), 6297 "d,v,t", tempreg, tempreg, breg); 6298 macro_build (&offset_expr, s, fmt, treg, 6299 BFD_RELOC_PCREL_LO16, tempreg); 6300 if (! used_at) 6301 return; 6302 break; 6303 } 6304 6305 if (offset_expr.X_op != O_constant 6306 && offset_expr.X_op != O_symbol) 6307 { 6308 as_bad (_("expression too complex")); 6309 offset_expr.X_op = O_constant; 6310 } 6311 6312 /* A constant expression in PIC code can be handled just as it 6313 is in non PIC code. */ 6314 if (mips_pic == NO_PIC 6315 || offset_expr.X_op == O_constant) 6316 { 6317 /* If this is a reference to a GP relative symbol, and there 6318 is no base register, we want 6319 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) 6320 Otherwise, if there is no base register, we want 6321 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 6322 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6323 If we have a constant, we need two instructions anyhow, 6324 so we always use the latter form. 6325 6326 If we have a base register, and this is a reference to a 6327 GP relative symbol, we want 6328 addu $tempreg,$breg,$gp 6329 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) 6330 Otherwise we want 6331 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 6332 addu $tempreg,$tempreg,$breg 6333 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6334 With a constant we always use the latter case. 6335 6336 With 64bit address space and no base register and $at usable, 6337 we want 6338 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 6339 lui $at,<sym> (BFD_RELOC_HI16_S) 6340 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 6341 dsll32 $tempreg,0 6342 daddu $tempreg,$at 6343 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6344 If we have a base register, we want 6345 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 6346 lui $at,<sym> (BFD_RELOC_HI16_S) 6347 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 6348 daddu $at,$breg 6349 dsll32 $tempreg,0 6350 daddu $tempreg,$at 6351 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6352 6353 Without $at we can't generate the optimal path for superscalar 6354 processors here since this would require two temporary registers. 6355 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 6356 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 6357 dsll $tempreg,16 6358 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 6359 dsll $tempreg,16 6360 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6361 If we have a base register, we want 6362 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 6363 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 6364 dsll $tempreg,16 6365 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 6366 dsll $tempreg,16 6367 daddu $tempreg,$tempreg,$breg 6368 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6369 6370 If we have 64-bit addresses, as an optimization, for 6371 addresses which are 32-bit constants (e.g. kseg0/kseg1 6372 addresses) we fall back to the 32-bit address generation 6373 mechanism since it is more efficient. Note that due to 6374 the signed offset used by memory operations, the 32-bit 6375 range is shifted down by 32768 here. This code should 6376 probably attempt to generate 64-bit constants more 6377 efficiently in general. 6378 6379 As an extension for architectures with 64-bit registers, 6380 we don't truncate 64-bit addresses given as literal 6381 constants down to 32 bits, to support existing practice 6382 in the mips64 Linux (the kernel), that compiles source 6383 files with -mabi=64, assembling them as o32 or n32 (with 6384 -Wa,-32 or -Wa,-n32). This is not beautiful, but since 6385 the whole kernel is loaded into a memory region that is 6386 addressable with sign-extended 32-bit addresses, it is 6387 wasteful to compute the upper 32 bits of every 6388 non-literal address, that takes more space and time. 6389 Some day this should probably be implemented as an 6390 assembler option, such that the kernel doesn't have to 6391 use such ugly hacks, even though it will still have to 6392 end up converting the binary to ELF32 for a number of 6393 platforms whose boot loaders don't support ELF64 6394 binaries. */ 6395 if ((HAVE_64BIT_ADDRESSES 6396 && ! (offset_expr.X_op == O_constant 6397 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) 6398 || (HAVE_64BIT_GPRS 6399 && offset_expr.X_op == O_constant 6400 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) 6401 { 6402 /* ??? We don't provide a GP-relative alternative for 6403 these macros. It used not to be possible with the 6404 original relaxation code, but it could be done now. */ 6405 6406 if (used_at == 0 && ! mips_opts.noat) 6407 { 6408 macro_build (&offset_expr, "lui", "t,u", tempreg, 6409 BFD_RELOC_MIPS_HIGHEST); 6410 macro_build (&offset_expr, "lui", "t,u", AT, 6411 BFD_RELOC_HI16_S); 6412 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 6413 tempreg, BFD_RELOC_MIPS_HIGHER); 6414 if (breg != 0) 6415 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); 6416 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); 6417 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 6418 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, 6419 tempreg); 6420 used_at = 1; 6421 } 6422 else 6423 { 6424 macro_build (&offset_expr, "lui", "t,u", tempreg, 6425 BFD_RELOC_MIPS_HIGHEST); 6426 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 6427 tempreg, BFD_RELOC_MIPS_HIGHER); 6428 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 6429 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 6430 tempreg, BFD_RELOC_HI16_S); 6431 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 6432 if (breg != 0) 6433 macro_build (NULL, "daddu", "d,v,t", 6434 tempreg, tempreg, breg); 6435 macro_build (&offset_expr, s, fmt, treg, 6436 BFD_RELOC_LO16, tempreg); 6437 } 6438 6439 return; 6440 } 6441 6442 if (offset_expr.X_op == O_constant 6443 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) 6444 as_bad (_("load/store address overflow (max 32 bits)")); 6445 6446 if (breg == 0) 6447 { 6448 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 6449 && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) 6450 { 6451 relax_start (offset_expr.X_add_symbol); 6452 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, 6453 mips_gp_register); 6454 relax_switch (); 6455 used_at = 0; 6456 } 6457 macro_build_lui (&offset_expr, tempreg); 6458 macro_build (&offset_expr, s, fmt, treg, 6459 BFD_RELOC_LO16, tempreg); 6460 if (mips_relax.sequence) 6461 relax_end (); 6462 } 6463 else 6464 { 6465 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 6466 && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) 6467 { 6468 relax_start (offset_expr.X_add_symbol); 6469 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6470 tempreg, breg, mips_gp_register); 6471 macro_build (&offset_expr, s, fmt, treg, 6472 BFD_RELOC_GPREL16, tempreg); 6473 relax_switch (); 6474 } 6475 macro_build_lui (&offset_expr, tempreg); 6476 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6477 tempreg, tempreg, breg); 6478 macro_build (&offset_expr, s, fmt, treg, 6479 BFD_RELOC_LO16, tempreg); 6480 if (mips_relax.sequence) 6481 relax_end (); 6482 } 6483 } 6484 else if (mips_pic == SVR4_PIC && ! mips_big_got) 6485 { 6486 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 6487 6488 /* If this is a reference to an external symbol, we want 6489 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6490 nop 6491 <op> $treg,0($tempreg) 6492 Otherwise we want 6493 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6494 nop 6495 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 6496 <op> $treg,0($tempreg) 6497 6498 For NewABI, we want 6499 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 6500 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) 6501 6502 If there is a base register, we add it to $tempreg before 6503 the <op>. If there is a constant, we stick it in the 6504 <op> instruction. We don't handle constants larger than 6505 16 bits, because we have no way to load the upper 16 bits 6506 (actually, we could handle them for the subset of cases 6507 in which we are not using $at). */ 6508 assert (offset_expr.X_op == O_symbol); 6509 if (HAVE_NEWABI) 6510 { 6511 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6512 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 6513 if (breg != 0) 6514 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6515 tempreg, tempreg, breg); 6516 macro_build (&offset_expr, s, fmt, treg, 6517 BFD_RELOC_MIPS_GOT_OFST, tempreg); 6518 6519 if (! used_at) 6520 return; 6521 6522 break; 6523 } 6524 expr1.X_add_number = offset_expr.X_add_number; 6525 offset_expr.X_add_number = 0; 6526 if (expr1.X_add_number < -0x8000 6527 || expr1.X_add_number >= 0x8000) 6528 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6529 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6530 lw_reloc_type, mips_gp_register); 6531 macro_build (NULL, "nop", ""); 6532 relax_start (offset_expr.X_add_symbol); 6533 relax_switch (); 6534 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 6535 tempreg, BFD_RELOC_LO16); 6536 relax_end (); 6537 if (breg != 0) 6538 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6539 tempreg, tempreg, breg); 6540 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); 6541 } 6542 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) 6543 { 6544 int gpdelay; 6545 6546 /* If this is a reference to an external symbol, we want 6547 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 6548 addu $tempreg,$tempreg,$gp 6549 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 6550 <op> $treg,0($tempreg) 6551 Otherwise we want 6552 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6553 nop 6554 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 6555 <op> $treg,0($tempreg) 6556 If there is a base register, we add it to $tempreg before 6557 the <op>. If there is a constant, we stick it in the 6558 <op> instruction. We don't handle constants larger than 6559 16 bits, because we have no way to load the upper 16 bits 6560 (actually, we could handle them for the subset of cases 6561 in which we are not using $at). */ 6562 assert (offset_expr.X_op == O_symbol); 6563 expr1.X_add_number = offset_expr.X_add_number; 6564 offset_expr.X_add_number = 0; 6565 if (expr1.X_add_number < -0x8000 6566 || expr1.X_add_number >= 0x8000) 6567 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6568 gpdelay = reg_needs_delay (mips_gp_register); 6569 relax_start (offset_expr.X_add_symbol); 6570 macro_build (&offset_expr, "lui", "t,u", tempreg, 6571 BFD_RELOC_MIPS_GOT_HI16); 6572 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 6573 mips_gp_register); 6574 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6575 BFD_RELOC_MIPS_GOT_LO16, tempreg); 6576 relax_switch (); 6577 if (gpdelay) 6578 macro_build (NULL, "nop", ""); 6579 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6580 BFD_RELOC_MIPS_GOT16, mips_gp_register); 6581 macro_build (NULL, "nop", ""); 6582 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 6583 tempreg, BFD_RELOC_LO16); 6584 relax_end (); 6585 6586 if (breg != 0) 6587 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6588 tempreg, tempreg, breg); 6589 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); 6590 } 6591 else if (mips_pic == SVR4_PIC && HAVE_NEWABI) 6592 { 6593 /* If this is a reference to an external symbol, we want 6594 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 6595 add $tempreg,$tempreg,$gp 6596 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 6597 <op> $treg,<ofst>($tempreg) 6598 Otherwise, for local symbols, we want: 6599 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 6600 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ 6601 assert (offset_expr.X_op == O_symbol); 6602 expr1.X_add_number = offset_expr.X_add_number; 6603 offset_expr.X_add_number = 0; 6604 if (expr1.X_add_number < -0x8000 6605 || expr1.X_add_number >= 0x8000) 6606 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6607 relax_start (offset_expr.X_add_symbol); 6608 macro_build (&offset_expr, "lui", "t,u", tempreg, 6609 BFD_RELOC_MIPS_GOT_HI16); 6610 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 6611 mips_gp_register); 6612 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6613 BFD_RELOC_MIPS_GOT_LO16, tempreg); 6614 if (breg != 0) 6615 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6616 tempreg, tempreg, breg); 6617 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); 6618 6619 relax_switch (); 6620 offset_expr.X_add_number = expr1.X_add_number; 6621 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6622 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 6623 if (breg != 0) 6624 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6625 tempreg, tempreg, breg); 6626 macro_build (&offset_expr, s, fmt, treg, 6627 BFD_RELOC_MIPS_GOT_OFST, tempreg); 6628 relax_end (); 6629 } 6630 else if (mips_pic == EMBEDDED_PIC) 6631 { 6632 /* If there is no base register, we want 6633 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) 6634 If there is a base register, we want 6635 addu $tempreg,$breg,$gp 6636 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) 6637 */ 6638 assert (offset_expr.X_op == O_symbol); 6639 if (breg == 0) 6640 { 6641 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, 6642 mips_gp_register); 6643 used_at = 0; 6644 } 6645 else 6646 { 6647 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6648 tempreg, breg, mips_gp_register); 6649 macro_build (&offset_expr, s, fmt, treg, 6650 BFD_RELOC_GPREL16, tempreg); 6651 } 6652 } 6653 else 6654 abort (); 6655 6656 if (! used_at) 6657 return; 6658 6659 break; 6660 6661 case M_LI: 6662 case M_LI_S: 6663 load_register (treg, &imm_expr, 0); 6664 return; 6665 6666 case M_DLI: 6667 load_register (treg, &imm_expr, 1); 6668 return; 6669 6670 case M_LI_SS: 6671 if (imm_expr.X_op == O_constant) 6672 { 6673 load_register (AT, &imm_expr, 0); 6674 macro_build (NULL, "mtc1", "t,G", AT, treg); 6675 break; 6676 } 6677 else 6678 { 6679 assert (offset_expr.X_op == O_symbol 6680 && strcmp (segment_name (S_GET_SEGMENT 6681 (offset_expr.X_add_symbol)), 6682 ".lit4") == 0 6683 && offset_expr.X_add_number == 0); 6684 macro_build (&offset_expr, "lwc1", "T,o(b)", treg, 6685 BFD_RELOC_MIPS_LITERAL, mips_gp_register); 6686 return; 6687 } 6688 6689 case M_LI_D: 6690 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits 6691 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high 6692 order 32 bits of the value and the low order 32 bits are either 6693 zero or in OFFSET_EXPR. */ 6694 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) 6695 { 6696 if (HAVE_64BIT_GPRS) 6697 load_register (treg, &imm_expr, 1); 6698 else 6699 { 6700 int hreg, lreg; 6701 6702 if (target_big_endian) 6703 { 6704 hreg = treg; 6705 lreg = treg + 1; 6706 } 6707 else 6708 { 6709 hreg = treg + 1; 6710 lreg = treg; 6711 } 6712 6713 if (hreg <= 31) 6714 load_register (hreg, &imm_expr, 0); 6715 if (lreg <= 31) 6716 { 6717 if (offset_expr.X_op == O_absent) 6718 move_register (lreg, 0); 6719 else 6720 { 6721 assert (offset_expr.X_op == O_constant); 6722 load_register (lreg, &offset_expr, 0); 6723 } 6724 } 6725 } 6726 return; 6727 } 6728 6729 /* We know that sym is in the .rdata section. First we get the 6730 upper 16 bits of the address. */ 6731 if (mips_pic == NO_PIC) 6732 { 6733 macro_build_lui (&offset_expr, AT); 6734 } 6735 else if (mips_pic == SVR4_PIC) 6736 { 6737 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 6738 BFD_RELOC_MIPS_GOT16, mips_gp_register); 6739 } 6740 else if (mips_pic == EMBEDDED_PIC) 6741 { 6742 /* For embedded PIC we pick up the entire address off $gp in 6743 a single instruction. */ 6744 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, 6745 mips_gp_register, BFD_RELOC_GPREL16); 6746 offset_expr.X_op = O_constant; 6747 offset_expr.X_add_number = 0; 6748 } 6749 else 6750 abort (); 6751 6752 /* Now we load the register(s). */ 6753 if (HAVE_64BIT_GPRS) 6754 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); 6755 else 6756 { 6757 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); 6758 if (treg != RA) 6759 { 6760 /* FIXME: How in the world do we deal with the possible 6761 overflow here? */ 6762 offset_expr.X_add_number += 4; 6763 macro_build (&offset_expr, "lw", "t,o(b)", 6764 treg + 1, BFD_RELOC_LO16, AT); 6765 } 6766 } 6767 break; 6768 6769 case M_LI_DD: 6770 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits 6771 wide, IMM_EXPR is the entire value and the GPRs are known to be 64 6772 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of 6773 the value and the low order 32 bits are either zero or in 6774 OFFSET_EXPR. */ 6775 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) 6776 { 6777 load_register (AT, &imm_expr, HAVE_64BIT_FPRS); 6778 if (HAVE_64BIT_FPRS) 6779 { 6780 assert (HAVE_64BIT_GPRS); 6781 macro_build (NULL, "dmtc1", "t,S", AT, treg); 6782 } 6783 else 6784 { 6785 macro_build (NULL, "mtc1", "t,G", AT, treg + 1); 6786 if (offset_expr.X_op == O_absent) 6787 macro_build (NULL, "mtc1", "t,G", 0, treg); 6788 else 6789 { 6790 assert (offset_expr.X_op == O_constant); 6791 load_register (AT, &offset_expr, 0); 6792 macro_build (NULL, "mtc1", "t,G", AT, treg); 6793 } 6794 } 6795 break; 6796 } 6797 6798 assert (offset_expr.X_op == O_symbol 6799 && offset_expr.X_add_number == 0); 6800 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); 6801 if (strcmp (s, ".lit8") == 0) 6802 { 6803 if (mips_opts.isa != ISA_MIPS1) 6804 { 6805 macro_build (&offset_expr, "ldc1", "T,o(b)", treg, 6806 BFD_RELOC_MIPS_LITERAL, mips_gp_register); 6807 return; 6808 } 6809 breg = mips_gp_register; 6810 r = BFD_RELOC_MIPS_LITERAL; 6811 goto dob; 6812 } 6813 else 6814 { 6815 assert (strcmp (s, RDATA_SECTION_NAME) == 0); 6816 if (mips_pic == SVR4_PIC) 6817 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 6818 BFD_RELOC_MIPS_GOT16, mips_gp_register); 6819 else 6820 { 6821 /* FIXME: This won't work for a 64 bit address. */ 6822 macro_build_lui (&offset_expr, AT); 6823 } 6824 6825 if (mips_opts.isa != ISA_MIPS1) 6826 { 6827 macro_build (&offset_expr, "ldc1", "T,o(b)", 6828 treg, BFD_RELOC_LO16, AT); 6829 break; 6830 } 6831 breg = AT; 6832 r = BFD_RELOC_LO16; 6833 goto dob; 6834 } 6835 6836 case M_L_DOB: 6837 if (mips_opts.arch == CPU_R4650) 6838 { 6839 as_bad (_("opcode not supported on this processor")); 6840 return; 6841 } 6842 /* Even on a big endian machine $fn comes before $fn+1. We have 6843 to adjust when loading from memory. */ 6844 r = BFD_RELOC_LO16; 6845 dob: 6846 assert (mips_opts.isa == ISA_MIPS1); 6847 macro_build (&offset_expr, "lwc1", "T,o(b)", 6848 target_big_endian ? treg + 1 : treg, r, breg); 6849 /* FIXME: A possible overflow which I don't know how to deal 6850 with. */ 6851 offset_expr.X_add_number += 4; 6852 macro_build (&offset_expr, "lwc1", "T,o(b)", 6853 target_big_endian ? treg : treg + 1, r, breg); 6854 6855 if (breg != AT) 6856 return; 6857 break; 6858 6859 case M_L_DAB: 6860 /* 6861 * The MIPS assembler seems to check for X_add_number not 6862 * being double aligned and generating: 6863 * lui at,%hi(foo+1) 6864 * addu at,at,v1 6865 * addiu at,at,%lo(foo+1) 6866 * lwc1 f2,0(at) 6867 * lwc1 f3,4(at) 6868 * But, the resulting address is the same after relocation so why 6869 * generate the extra instruction? 6870 */ 6871 if (mips_opts.arch == CPU_R4650) 6872 { 6873 as_bad (_("opcode not supported on this processor")); 6874 return; 6875 } 6876 /* Itbl support may require additional care here. */ 6877 coproc = 1; 6878 if (mips_opts.isa != ISA_MIPS1) 6879 { 6880 s = "ldc1"; 6881 goto ld; 6882 } 6883 6884 s = "lwc1"; 6885 fmt = "T,o(b)"; 6886 goto ldd_std; 6887 6888 case M_S_DAB: 6889 if (mips_opts.arch == CPU_R4650) 6890 { 6891 as_bad (_("opcode not supported on this processor")); 6892 return; 6893 } 6894 6895 if (mips_opts.isa != ISA_MIPS1) 6896 { 6897 s = "sdc1"; 6898 goto st; 6899 } 6900 6901 s = "swc1"; 6902 fmt = "T,o(b)"; 6903 /* Itbl support may require additional care here. */ 6904 coproc = 1; 6905 goto ldd_std; 6906 6907 case M_LD_AB: 6908 if (HAVE_64BIT_GPRS) 6909 { 6910 s = "ld"; 6911 goto ld; 6912 } 6913 6914 s = "lw"; 6915 fmt = "t,o(b)"; 6916 goto ldd_std; 6917 6918 case M_SD_AB: 6919 if (HAVE_64BIT_GPRS) 6920 { 6921 s = "sd"; 6922 goto st; 6923 } 6924 6925 s = "sw"; 6926 fmt = "t,o(b)"; 6927 6928 ldd_std: 6929 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) 6930 loads for the case of doing a pair of loads to simulate an 'ld'. 6931 This is not currently done by the compiler, and assembly coders 6932 writing embedded-pic code can cope. */ 6933 6934 if (offset_expr.X_op != O_symbol 6935 && offset_expr.X_op != O_constant) 6936 { 6937 as_bad (_("expression too complex")); 6938 offset_expr.X_op = O_constant; 6939 } 6940 6941 /* Even on a big endian machine $fn comes before $fn+1. We have 6942 to adjust when loading from memory. We set coproc if we must 6943 load $fn+1 first. */ 6944 /* Itbl support may require additional care here. */ 6945 if (! target_big_endian) 6946 coproc = 0; 6947 6948 if (mips_pic == NO_PIC 6949 || offset_expr.X_op == O_constant) 6950 { 6951 /* If this is a reference to a GP relative symbol, we want 6952 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) 6953 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) 6954 If we have a base register, we use this 6955 addu $at,$breg,$gp 6956 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) 6957 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) 6958 If this is not a GP relative symbol, we want 6959 lui $at,<sym> (BFD_RELOC_HI16_S) 6960 <op> $treg,<sym>($at) (BFD_RELOC_LO16) 6961 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) 6962 If there is a base register, we add it to $at after the 6963 lui instruction. If there is a constant, we always use 6964 the last case. */ 6965 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET 6966 || nopic_need_relax (offset_expr.X_add_symbol, 1)) 6967 used_at = 1; 6968 else 6969 { 6970 relax_start (offset_expr.X_add_symbol); 6971 if (breg == 0) 6972 { 6973 tempreg = mips_gp_register; 6974 used_at = 0; 6975 } 6976 else 6977 { 6978 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6979 AT, breg, mips_gp_register); 6980 tempreg = AT; 6981 used_at = 1; 6982 } 6983 6984 /* Itbl support may require additional care here. */ 6985 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 6986 BFD_RELOC_GPREL16, tempreg); 6987 offset_expr.X_add_number += 4; 6988 6989 /* Set mips_optimize to 2 to avoid inserting an 6990 undesired nop. */ 6991 hold_mips_optimize = mips_optimize; 6992 mips_optimize = 2; 6993 /* Itbl support may require additional care here. */ 6994 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 6995 BFD_RELOC_GPREL16, tempreg); 6996 mips_optimize = hold_mips_optimize; 6997 6998 relax_switch (); 6999 7000 /* We just generated two relocs. When tc_gen_reloc 7001 handles this case, it will skip the first reloc and 7002 handle the second. The second reloc already has an 7003 extra addend of 4, which we added above. We must 7004 subtract it out, and then subtract another 4 to make 7005 the first reloc come out right. The second reloc 7006 will come out right because we are going to add 4 to 7007 offset_expr when we build its instruction below. 7008 7009 If we have a symbol, then we don't want to include 7010 the offset, because it will wind up being included 7011 when we generate the reloc. */ 7012 7013 if (offset_expr.X_op == O_constant) 7014 offset_expr.X_add_number -= 8; 7015 else 7016 { 7017 offset_expr.X_add_number = -4; 7018 offset_expr.X_op = O_constant; 7019 } 7020 } 7021 macro_build_lui (&offset_expr, AT); 7022 if (breg != 0) 7023 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 7024 /* Itbl support may require additional care here. */ 7025 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 7026 BFD_RELOC_LO16, AT); 7027 /* FIXME: How do we handle overflow here? */ 7028 offset_expr.X_add_number += 4; 7029 /* Itbl support may require additional care here. */ 7030 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 7031 BFD_RELOC_LO16, AT); 7032 if (mips_relax.sequence) 7033 relax_end (); 7034 } 7035 else if (mips_pic == SVR4_PIC && ! mips_big_got) 7036 { 7037 /* If this is a reference to an external symbol, we want 7038 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 7039 nop 7040 <op> $treg,0($at) 7041 <op> $treg+1,4($at) 7042 Otherwise we want 7043 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 7044 nop 7045 <op> $treg,<sym>($at) (BFD_RELOC_LO16) 7046 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) 7047 If there is a base register we add it to $at before the 7048 lwc1 instructions. If there is a constant we include it 7049 in the lwc1 instructions. */ 7050 used_at = 1; 7051 expr1.X_add_number = offset_expr.X_add_number; 7052 if (expr1.X_add_number < -0x8000 7053 || expr1.X_add_number >= 0x8000 - 4) 7054 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 7055 load_got_offset (AT, &offset_expr); 7056 macro_build (NULL, "nop", ""); 7057 if (breg != 0) 7058 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 7059 7060 /* Set mips_optimize to 2 to avoid inserting an undesired 7061 nop. */ 7062 hold_mips_optimize = mips_optimize; 7063 mips_optimize = 2; 7064 7065 /* Itbl support may require additional care here. */ 7066 relax_start (offset_expr.X_add_symbol); 7067 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, 7068 BFD_RELOC_LO16, AT); 7069 expr1.X_add_number += 4; 7070 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, 7071 BFD_RELOC_LO16, AT); 7072 relax_switch (); 7073 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 7074 BFD_RELOC_LO16, AT); 7075 offset_expr.X_add_number += 4; 7076 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 7077 BFD_RELOC_LO16, AT); 7078 relax_end (); 7079 7080 mips_optimize = hold_mips_optimize; 7081 } 7082 else if (mips_pic == SVR4_PIC) 7083 { 7084 int gpdelay; 7085 7086 /* If this is a reference to an external symbol, we want 7087 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) 7088 addu $at,$at,$gp 7089 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) 7090 nop 7091 <op> $treg,0($at) 7092 <op> $treg+1,4($at) 7093 Otherwise we want 7094 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 7095 nop 7096 <op> $treg,<sym>($at) (BFD_RELOC_LO16) 7097 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) 7098 If there is a base register we add it to $at before the 7099 lwc1 instructions. If there is a constant we include it 7100 in the lwc1 instructions. */ 7101 used_at = 1; 7102 expr1.X_add_number = offset_expr.X_add_number; 7103 offset_expr.X_add_number = 0; 7104 if (expr1.X_add_number < -0x8000 7105 || expr1.X_add_number >= 0x8000 - 4) 7106 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 7107 gpdelay = reg_needs_delay (mips_gp_register); 7108 relax_start (offset_expr.X_add_symbol); 7109 macro_build (&offset_expr, "lui", "t,u", 7110 AT, BFD_RELOC_MIPS_GOT_HI16); 7111 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 7112 AT, AT, mips_gp_register); 7113 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 7114 AT, BFD_RELOC_MIPS_GOT_LO16, AT); 7115 macro_build (NULL, "nop", ""); 7116 if (breg != 0) 7117 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 7118 /* Itbl support may require additional care here. */ 7119 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, 7120 BFD_RELOC_LO16, AT); 7121 expr1.X_add_number += 4; 7122 7123 /* Set mips_optimize to 2 to avoid inserting an undesired 7124 nop. */ 7125 hold_mips_optimize = mips_optimize; 7126 mips_optimize = 2; 7127 /* Itbl support may require additional care here. */ 7128 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, 7129 BFD_RELOC_LO16, AT); 7130 mips_optimize = hold_mips_optimize; 7131 expr1.X_add_number -= 4; 7132 7133 relax_switch (); 7134 offset_expr.X_add_number = expr1.X_add_number; 7135 if (gpdelay) 7136 macro_build (NULL, "nop", ""); 7137 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 7138 BFD_RELOC_MIPS_GOT16, mips_gp_register); 7139 macro_build (NULL, "nop", ""); 7140 if (breg != 0) 7141 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 7142 /* Itbl support may require additional care here. */ 7143 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 7144 BFD_RELOC_LO16, AT); 7145 offset_expr.X_add_number += 4; 7146 7147 /* Set mips_optimize to 2 to avoid inserting an undesired 7148 nop. */ 7149 hold_mips_optimize = mips_optimize; 7150 mips_optimize = 2; 7151 /* Itbl support may require additional care here. */ 7152 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 7153 BFD_RELOC_LO16, AT); 7154 mips_optimize = hold_mips_optimize; 7155 relax_end (); 7156 } 7157 else if (mips_pic == EMBEDDED_PIC) 7158 { 7159 /* If there is no base register, we use 7160 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) 7161 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) 7162 If we have a base register, we use 7163 addu $at,$breg,$gp 7164 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) 7165 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) 7166 */ 7167 if (breg == 0) 7168 { 7169 tempreg = mips_gp_register; 7170 used_at = 0; 7171 } 7172 else 7173 { 7174 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 7175 AT, breg, mips_gp_register); 7176 tempreg = AT; 7177 used_at = 1; 7178 } 7179 7180 /* Itbl support may require additional care here. */ 7181 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 7182 BFD_RELOC_GPREL16, tempreg); 7183 offset_expr.X_add_number += 4; 7184 /* Itbl support may require additional care here. */ 7185 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 7186 BFD_RELOC_GPREL16, tempreg); 7187 } 7188 else 7189 abort (); 7190 7191 if (! used_at) 7192 return; 7193 7194 break; 7195 7196 case M_LD_OB: 7197 s = "lw"; 7198 goto sd_ob; 7199 case M_SD_OB: 7200 s = "sw"; 7201 sd_ob: 7202 assert (HAVE_32BIT_ADDRESSES); 7203 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); 7204 offset_expr.X_add_number += 4; 7205 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); 7206 return; 7207 7208 /* New code added to support COPZ instructions. 7209 This code builds table entries out of the macros in mip_opcodes. 7210 R4000 uses interlocks to handle coproc delays. 7211 Other chips (like the R3000) require nops to be inserted for delays. 7212 7213 FIXME: Currently, we require that the user handle delays. 7214 In order to fill delay slots for non-interlocked chips, 7215 we must have a way to specify delays based on the coprocessor. 7216 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. 7217 What are the side-effects of the cop instruction? 7218 What cache support might we have and what are its effects? 7219 Both coprocessor & memory require delays. how long??? 7220 What registers are read/set/modified? 7221 7222 If an itbl is provided to interpret cop instructions, 7223 this knowledge can be encoded in the itbl spec. */ 7224 7225 case M_COP0: 7226 s = "c0"; 7227 goto copz; 7228 case M_COP1: 7229 s = "c1"; 7230 goto copz; 7231 case M_COP2: 7232 s = "c2"; 7233 goto copz; 7234 case M_COP3: 7235 s = "c3"; 7236 copz: 7237 /* For now we just do C (same as Cz). The parameter will be 7238 stored in insn_opcode by mips_ip. */ 7239 macro_build (NULL, s, "C", ip->insn_opcode); 7240 return; 7241 7242 case M_MOVE: 7243 move_register (dreg, sreg); 7244 return; 7245 7246 #ifdef LOSING_COMPILER 7247 default: 7248 /* Try and see if this is a new itbl instruction. 7249 This code builds table entries out of the macros in mip_opcodes. 7250 FIXME: For now we just assemble the expression and pass it's 7251 value along as a 32-bit immediate. 7252 We may want to have the assembler assemble this value, 7253 so that we gain the assembler's knowledge of delay slots, 7254 symbols, etc. 7255 Would it be more efficient to use mask (id) here? */ 7256 if (itbl_have_entries 7257 && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) 7258 { 7259 s = ip->insn_mo->name; 7260 s2 = "cop3"; 7261 coproc = ITBL_DECODE_PNUM (immed_expr);; 7262 macro_build (&immed_expr, s, "C"); 7263 return; 7264 } 7265 macro2 (ip); 7266 return; 7267 } 7268 if (mips_opts.noat) 7269 as_warn (_("Macro used $at after \".set noat\"")); 7270 } 7271 7272 static void 7273 macro2 (struct mips_cl_insn *ip) 7274 { 7275 register int treg, sreg, dreg, breg; 7276 int tempreg; 7277 int mask; 7278 int used_at; 7279 expressionS expr1; 7280 const char *s; 7281 const char *s2; 7282 const char *fmt; 7283 int likely = 0; 7284 int dbl = 0; 7285 int coproc = 0; 7286 int lr = 0; 7287 int imm = 0; 7288 int off; 7289 offsetT maxnum; 7290 bfd_reloc_code_real_type r; 7291 7292 treg = (ip->insn_opcode >> 16) & 0x1f; 7293 dreg = (ip->insn_opcode >> 11) & 0x1f; 7294 sreg = breg = (ip->insn_opcode >> 21) & 0x1f; 7295 mask = ip->insn_mo->mask; 7296 7297 expr1.X_op = O_constant; 7298 expr1.X_op_symbol = NULL; 7299 expr1.X_add_symbol = NULL; 7300 expr1.X_add_number = 1; 7301 7302 switch (mask) 7303 { 7304 #endif /* LOSING_COMPILER */ 7305 7306 case M_DMUL: 7307 dbl = 1; 7308 case M_MUL: 7309 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); 7310 macro_build (NULL, "mflo", "d", dreg); 7311 return; 7312 7313 case M_DMUL_I: 7314 dbl = 1; 7315 case M_MUL_I: 7316 /* The MIPS assembler some times generates shifts and adds. I'm 7317 not trying to be that fancy. GCC should do this for us 7318 anyway. */ 7319 load_register (AT, &imm_expr, dbl); 7320 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); 7321 macro_build (NULL, "mflo", "d", dreg); 7322 break; 7323 7324 case M_DMULO_I: 7325 dbl = 1; 7326 case M_MULO_I: 7327 imm = 1; 7328 goto do_mulo; 7329 7330 case M_DMULO: 7331 dbl = 1; 7332 case M_MULO: 7333 do_mulo: 7334 mips_emit_delays (TRUE); 7335 ++mips_opts.noreorder; 7336 mips_any_noreorder = 1; 7337 if (imm) 7338 load_register (AT, &imm_expr, dbl); 7339 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); 7340 macro_build (NULL, "mflo", "d", dreg); 7341 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); 7342 macro_build (NULL, "mfhi", "d", AT); 7343 if (mips_trap) 7344 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); 7345 else 7346 { 7347 expr1.X_add_number = 8; 7348 macro_build (&expr1, "beq", "s,t,p", dreg, AT); 7349 macro_build (NULL, "nop", "", 0); 7350 macro_build (NULL, "break", "c", 6); 7351 } 7352 --mips_opts.noreorder; 7353 macro_build (NULL, "mflo", "d", dreg); 7354 break; 7355 7356 case M_DMULOU_I: 7357 dbl = 1; 7358 case M_MULOU_I: 7359 imm = 1; 7360 goto do_mulou; 7361 7362 case M_DMULOU: 7363 dbl = 1; 7364 case M_MULOU: 7365 do_mulou: 7366 mips_emit_delays (TRUE); 7367 ++mips_opts.noreorder; 7368 mips_any_noreorder = 1; 7369 if (imm) 7370 load_register (AT, &imm_expr, dbl); 7371 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", 7372 sreg, imm ? AT : treg); 7373 macro_build (NULL, "mfhi", "d", AT); 7374 macro_build (NULL, "mflo", "d", dreg); 7375 if (mips_trap) 7376 macro_build (NULL, "tne", "s,t,q", AT, 0, 6); 7377 else 7378 { 7379 expr1.X_add_number = 8; 7380 macro_build (&expr1, "beq", "s,t,p", AT, 0); 7381 macro_build (NULL, "nop", "", 0); 7382 macro_build (NULL, "break", "c", 6); 7383 } 7384 --mips_opts.noreorder; 7385 break; 7386 7387 case M_DROL: 7388 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7389 { 7390 if (dreg == sreg) 7391 { 7392 tempreg = AT; 7393 used_at = 1; 7394 } 7395 else 7396 { 7397 tempreg = dreg; 7398 used_at = 0; 7399 } 7400 macro_build (NULL, "dnegu", "d,w", tempreg, treg); 7401 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); 7402 if (used_at) 7403 break; 7404 return; 7405 } 7406 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); 7407 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); 7408 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); 7409 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7410 break; 7411 7412 case M_ROL: 7413 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7414 { 7415 if (dreg == sreg) 7416 { 7417 tempreg = AT; 7418 used_at = 1; 7419 } 7420 else 7421 { 7422 tempreg = dreg; 7423 used_at = 0; 7424 } 7425 macro_build (NULL, "negu", "d,w", tempreg, treg); 7426 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); 7427 if (used_at) 7428 break; 7429 return; 7430 } 7431 macro_build (NULL, "subu", "d,v,t", AT, 0, treg); 7432 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); 7433 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); 7434 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7435 break; 7436 7437 case M_DROL_I: 7438 { 7439 unsigned int rot; 7440 char *l, *r; 7441 7442 if (imm_expr.X_op != O_constant) 7443 as_bad (_("Improper rotate count")); 7444 rot = imm_expr.X_add_number & 0x3f; 7445 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7446 { 7447 rot = (64 - rot) & 0x3f; 7448 if (rot >= 32) 7449 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); 7450 else 7451 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); 7452 return; 7453 } 7454 if (rot == 0) 7455 { 7456 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); 7457 return; 7458 } 7459 l = (rot < 0x20) ? "dsll" : "dsll32"; 7460 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; 7461 rot &= 0x1f; 7462 macro_build (NULL, l, "d,w,<", AT, sreg, rot); 7463 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7464 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7465 } 7466 break; 7467 7468 case M_ROL_I: 7469 { 7470 unsigned int rot; 7471 7472 if (imm_expr.X_op != O_constant) 7473 as_bad (_("Improper rotate count")); 7474 rot = imm_expr.X_add_number & 0x1f; 7475 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7476 { 7477 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); 7478 return; 7479 } 7480 if (rot == 0) 7481 { 7482 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); 7483 return; 7484 } 7485 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); 7486 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7487 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7488 } 7489 break; 7490 7491 case M_DROR: 7492 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7493 { 7494 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); 7495 return; 7496 } 7497 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); 7498 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); 7499 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); 7500 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7501 break; 7502 7503 case M_ROR: 7504 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7505 { 7506 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); 7507 return; 7508 } 7509 macro_build (NULL, "subu", "d,v,t", AT, 0, treg); 7510 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); 7511 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); 7512 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7513 break; 7514 7515 case M_DROR_I: 7516 { 7517 unsigned int rot; 7518 char *l, *r; 7519 7520 if (imm_expr.X_op != O_constant) 7521 as_bad (_("Improper rotate count")); 7522 rot = imm_expr.X_add_number & 0x3f; 7523 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7524 { 7525 if (rot >= 32) 7526 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); 7527 else 7528 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); 7529 return; 7530 } 7531 if (rot == 0) 7532 { 7533 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); 7534 return; 7535 } 7536 r = (rot < 0x20) ? "dsrl" : "dsrl32"; 7537 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; 7538 rot &= 0x1f; 7539 macro_build (NULL, r, "d,w,<", AT, sreg, rot); 7540 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7541 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7542 } 7543 break; 7544 7545 case M_ROR_I: 7546 { 7547 unsigned int rot; 7548 7549 if (imm_expr.X_op != O_constant) 7550 as_bad (_("Improper rotate count")); 7551 rot = imm_expr.X_add_number & 0x1f; 7552 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7553 { 7554 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); 7555 return; 7556 } 7557 if (rot == 0) 7558 { 7559 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); 7560 return; 7561 } 7562 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); 7563 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7564 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7565 } 7566 break; 7567 7568 case M_S_DOB: 7569 if (mips_opts.arch == CPU_R4650) 7570 { 7571 as_bad (_("opcode not supported on this processor")); 7572 return; 7573 } 7574 assert (mips_opts.isa == ISA_MIPS1); 7575 /* Even on a big endian machine $fn comes before $fn+1. We have 7576 to adjust when storing to memory. */ 7577 macro_build (&offset_expr, "swc1", "T,o(b)", 7578 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); 7579 offset_expr.X_add_number += 4; 7580 macro_build (&offset_expr, "swc1", "T,o(b)", 7581 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); 7582 return; 7583 7584 case M_SEQ: 7585 if (sreg == 0) 7586 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); 7587 else if (treg == 0) 7588 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7589 else 7590 { 7591 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); 7592 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); 7593 } 7594 return; 7595 7596 case M_SEQ_I: 7597 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 7598 { 7599 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7600 return; 7601 } 7602 if (sreg == 0) 7603 { 7604 as_warn (_("Instruction %s: result is always false"), 7605 ip->insn_mo->name); 7606 move_register (dreg, 0); 7607 return; 7608 } 7609 if (imm_expr.X_op == O_constant 7610 && imm_expr.X_add_number >= 0 7611 && imm_expr.X_add_number < 0x10000) 7612 { 7613 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); 7614 used_at = 0; 7615 } 7616 else if (imm_expr.X_op == O_constant 7617 && imm_expr.X_add_number > -0x8000 7618 && imm_expr.X_add_number < 0) 7619 { 7620 imm_expr.X_add_number = -imm_expr.X_add_number; 7621 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", 7622 "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7623 used_at = 0; 7624 } 7625 else 7626 { 7627 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7628 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); 7629 used_at = 1; 7630 } 7631 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); 7632 if (used_at) 7633 break; 7634 return; 7635 7636 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ 7637 s = "slt"; 7638 goto sge; 7639 case M_SGEU: 7640 s = "sltu"; 7641 sge: 7642 macro_build (NULL, s, "d,v,t", dreg, sreg, treg); 7643 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7644 return; 7645 7646 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ 7647 case M_SGEU_I: 7648 if (imm_expr.X_op == O_constant 7649 && imm_expr.X_add_number >= -0x8000 7650 && imm_expr.X_add_number < 0x8000) 7651 { 7652 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", 7653 dreg, sreg, BFD_RELOC_LO16); 7654 used_at = 0; 7655 } 7656 else 7657 { 7658 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7659 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", 7660 dreg, sreg, AT); 7661 used_at = 1; 7662 } 7663 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7664 if (used_at) 7665 break; 7666 return; 7667 7668 case M_SGT: /* sreg > treg <==> treg < sreg */ 7669 s = "slt"; 7670 goto sgt; 7671 case M_SGTU: 7672 s = "sltu"; 7673 sgt: 7674 macro_build (NULL, s, "d,v,t", dreg, treg, sreg); 7675 return; 7676 7677 case M_SGT_I: /* sreg > I <==> I < sreg */ 7678 s = "slt"; 7679 goto sgti; 7680 case M_SGTU_I: 7681 s = "sltu"; 7682 sgti: 7683 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7684 macro_build (NULL, s, "d,v,t", dreg, AT, sreg); 7685 break; 7686 7687 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ 7688 s = "slt"; 7689 goto sle; 7690 case M_SLEU: 7691 s = "sltu"; 7692 sle: 7693 macro_build (NULL, s, "d,v,t", dreg, treg, sreg); 7694 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7695 return; 7696 7697 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ 7698 s = "slt"; 7699 goto slei; 7700 case M_SLEU_I: 7701 s = "sltu"; 7702 slei: 7703 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7704 macro_build (NULL, s, "d,v,t", dreg, AT, sreg); 7705 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7706 break; 7707 7708 case M_SLT_I: 7709 if (imm_expr.X_op == O_constant 7710 && imm_expr.X_add_number >= -0x8000 7711 && imm_expr.X_add_number < 0x8000) 7712 { 7713 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7714 return; 7715 } 7716 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7717 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); 7718 break; 7719 7720 case M_SLTU_I: 7721 if (imm_expr.X_op == O_constant 7722 && imm_expr.X_add_number >= -0x8000 7723 && imm_expr.X_add_number < 0x8000) 7724 { 7725 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, 7726 BFD_RELOC_LO16); 7727 return; 7728 } 7729 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7730 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); 7731 break; 7732 7733 case M_SNE: 7734 if (sreg == 0) 7735 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); 7736 else if (treg == 0) 7737 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); 7738 else 7739 { 7740 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); 7741 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); 7742 } 7743 return; 7744 7745 case M_SNE_I: 7746 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 7747 { 7748 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); 7749 return; 7750 } 7751 if (sreg == 0) 7752 { 7753 as_warn (_("Instruction %s: result is always true"), 7754 ip->insn_mo->name); 7755 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", 7756 dreg, 0, BFD_RELOC_LO16); 7757 return; 7758 } 7759 if (imm_expr.X_op == O_constant 7760 && imm_expr.X_add_number >= 0 7761 && imm_expr.X_add_number < 0x10000) 7762 { 7763 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); 7764 used_at = 0; 7765 } 7766 else if (imm_expr.X_op == O_constant 7767 && imm_expr.X_add_number > -0x8000 7768 && imm_expr.X_add_number < 0) 7769 { 7770 imm_expr.X_add_number = -imm_expr.X_add_number; 7771 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", 7772 "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7773 used_at = 0; 7774 } 7775 else 7776 { 7777 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7778 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); 7779 used_at = 1; 7780 } 7781 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); 7782 if (used_at) 7783 break; 7784 return; 7785 7786 case M_DSUB_I: 7787 dbl = 1; 7788 case M_SUB_I: 7789 if (imm_expr.X_op == O_constant 7790 && imm_expr.X_add_number > -0x8000 7791 && imm_expr.X_add_number <= 0x8000) 7792 { 7793 imm_expr.X_add_number = -imm_expr.X_add_number; 7794 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", 7795 dreg, sreg, BFD_RELOC_LO16); 7796 return; 7797 } 7798 load_register (AT, &imm_expr, dbl); 7799 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); 7800 break; 7801 7802 case M_DSUBU_I: 7803 dbl = 1; 7804 case M_SUBU_I: 7805 if (imm_expr.X_op == O_constant 7806 && imm_expr.X_add_number > -0x8000 7807 && imm_expr.X_add_number <= 0x8000) 7808 { 7809 imm_expr.X_add_number = -imm_expr.X_add_number; 7810 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", 7811 dreg, sreg, BFD_RELOC_LO16); 7812 return; 7813 } 7814 load_register (AT, &imm_expr, dbl); 7815 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); 7816 break; 7817 7818 case M_TEQ_I: 7819 s = "teq"; 7820 goto trap; 7821 case M_TGE_I: 7822 s = "tge"; 7823 goto trap; 7824 case M_TGEU_I: 7825 s = "tgeu"; 7826 goto trap; 7827 case M_TLT_I: 7828 s = "tlt"; 7829 goto trap; 7830 case M_TLTU_I: 7831 s = "tltu"; 7832 goto trap; 7833 case M_TNE_I: 7834 s = "tne"; 7835 trap: 7836 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7837 macro_build (NULL, s, "s,t", sreg, AT); 7838 break; 7839 7840 case M_TRUNCWS: 7841 case M_TRUNCWD: 7842 assert (mips_opts.isa == ISA_MIPS1); 7843 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ 7844 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ 7845 7846 /* 7847 * Is the double cfc1 instruction a bug in the mips assembler; 7848 * or is there a reason for it? 7849 */ 7850 mips_emit_delays (TRUE); 7851 ++mips_opts.noreorder; 7852 mips_any_noreorder = 1; 7853 macro_build (NULL, "cfc1", "t,G", treg, RA); 7854 macro_build (NULL, "cfc1", "t,G", treg, RA); 7855 macro_build (NULL, "nop", ""); 7856 expr1.X_add_number = 3; 7857 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); 7858 expr1.X_add_number = 2; 7859 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); 7860 macro_build (NULL, "ctc1", "t,G", AT, RA); 7861 macro_build (NULL, "nop", ""); 7862 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", 7863 dreg, sreg); 7864 macro_build (NULL, "ctc1", "t,G", treg, RA); 7865 macro_build (NULL, "nop", ""); 7866 --mips_opts.noreorder; 7867 break; 7868 7869 case M_ULH: 7870 s = "lb"; 7871 goto ulh; 7872 case M_ULHU: 7873 s = "lbu"; 7874 ulh: 7875 if (offset_expr.X_add_number >= 0x7fff) 7876 as_bad (_("operand overflow")); 7877 if (! target_big_endian) 7878 ++offset_expr.X_add_number; 7879 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); 7880 if (! target_big_endian) 7881 --offset_expr.X_add_number; 7882 else 7883 ++offset_expr.X_add_number; 7884 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); 7885 macro_build (NULL, "sll", "d,w,<", AT, AT, 8); 7886 macro_build (NULL, "or", "d,v,t", treg, treg, AT); 7887 break; 7888 7889 case M_ULD: 7890 s = "ldl"; 7891 s2 = "ldr"; 7892 off = 7; 7893 goto ulw; 7894 case M_ULW: 7895 s = "lwl"; 7896 s2 = "lwr"; 7897 off = 3; 7898 ulw: 7899 if (offset_expr.X_add_number >= 0x8000 - off) 7900 as_bad (_("operand overflow")); 7901 if (treg != breg) 7902 tempreg = treg; 7903 else 7904 tempreg = AT; 7905 if (! target_big_endian) 7906 offset_expr.X_add_number += off; 7907 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); 7908 if (! target_big_endian) 7909 offset_expr.X_add_number -= off; 7910 else 7911 offset_expr.X_add_number += off; 7912 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); 7913 7914 /* If necessary, move the result in tempreg the final destination. */ 7915 if (treg == tempreg) 7916 return; 7917 /* Protect second load's delay slot. */ 7918 if (!gpr_interlocks) 7919 macro_build (NULL, "nop", ""); 7920 move_register (treg, tempreg); 7921 break; 7922 7923 case M_ULD_A: 7924 s = "ldl"; 7925 s2 = "ldr"; 7926 off = 7; 7927 goto ulwa; 7928 case M_ULW_A: 7929 s = "lwl"; 7930 s2 = "lwr"; 7931 off = 3; 7932 ulwa: 7933 used_at = 1; 7934 load_address (AT, &offset_expr, &used_at); 7935 if (breg != 0) 7936 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 7937 if (! target_big_endian) 7938 expr1.X_add_number = off; 7939 else 7940 expr1.X_add_number = 0; 7941 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); 7942 if (! target_big_endian) 7943 expr1.X_add_number = 0; 7944 else 7945 expr1.X_add_number = off; 7946 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); 7947 break; 7948 7949 case M_ULH_A: 7950 case M_ULHU_A: 7951 used_at = 1; 7952 load_address (AT, &offset_expr, &used_at); 7953 if (breg != 0) 7954 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 7955 if (target_big_endian) 7956 expr1.X_add_number = 0; 7957 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", 7958 treg, BFD_RELOC_LO16, AT); 7959 if (target_big_endian) 7960 expr1.X_add_number = 1; 7961 else 7962 expr1.X_add_number = 0; 7963 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); 7964 macro_build (NULL, "sll", "d,w,<", treg, treg, 8); 7965 macro_build (NULL, "or", "d,v,t", treg, treg, AT); 7966 break; 7967 7968 case M_USH: 7969 if (offset_expr.X_add_number >= 0x7fff) 7970 as_bad (_("operand overflow")); 7971 if (target_big_endian) 7972 ++offset_expr.X_add_number; 7973 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); 7974 macro_build (NULL, "srl", "d,w,<", AT, treg, 8); 7975 if (target_big_endian) 7976 --offset_expr.X_add_number; 7977 else 7978 ++offset_expr.X_add_number; 7979 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); 7980 break; 7981 7982 case M_USD: 7983 s = "sdl"; 7984 s2 = "sdr"; 7985 off = 7; 7986 goto usw; 7987 case M_USW: 7988 s = "swl"; 7989 s2 = "swr"; 7990 off = 3; 7991 usw: 7992 if (offset_expr.X_add_number >= 0x8000 - off) 7993 as_bad (_("operand overflow")); 7994 if (! target_big_endian) 7995 offset_expr.X_add_number += off; 7996 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); 7997 if (! target_big_endian) 7998 offset_expr.X_add_number -= off; 7999 else 8000 offset_expr.X_add_number += off; 8001 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); 8002 return; 8003 8004 case M_USD_A: 8005 s = "sdl"; 8006 s2 = "sdr"; 8007 off = 7; 8008 goto uswa; 8009 case M_USW_A: 8010 s = "swl"; 8011 s2 = "swr"; 8012 off = 3; 8013 uswa: 8014 used_at = 1; 8015 load_address (AT, &offset_expr, &used_at); 8016 if (breg != 0) 8017 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 8018 if (! target_big_endian) 8019 expr1.X_add_number = off; 8020 else 8021 expr1.X_add_number = 0; 8022 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); 8023 if (! target_big_endian) 8024 expr1.X_add_number = 0; 8025 else 8026 expr1.X_add_number = off; 8027 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); 8028 break; 8029 8030 case M_USH_A: 8031 used_at = 1; 8032 load_address (AT, &offset_expr, &used_at); 8033 if (breg != 0) 8034 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 8035 if (! target_big_endian) 8036 expr1.X_add_number = 0; 8037 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); 8038 macro_build (NULL, "srl", "d,w,<", treg, treg, 8); 8039 if (! target_big_endian) 8040 expr1.X_add_number = 1; 8041 else 8042 expr1.X_add_number = 0; 8043 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); 8044 if (! target_big_endian) 8045 expr1.X_add_number = 0; 8046 else 8047 expr1.X_add_number = 1; 8048 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); 8049 macro_build (NULL, "sll", "d,w,<", treg, treg, 8); 8050 macro_build (NULL, "or", "d,v,t", treg, treg, AT); 8051 break; 8052 8053 default: 8054 /* FIXME: Check if this is one of the itbl macros, since they 8055 are added dynamically. */ 8056 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); 8057 break; 8058 } 8059 if (mips_opts.noat) 8060 as_warn (_("Macro used $at after \".set noat\"")); 8061 } 8062 8063 /* Implement macros in mips16 mode. */ 8064 8065 static void 8066 mips16_macro (struct mips_cl_insn *ip) 8067 { 8068 int mask; 8069 int xreg, yreg, zreg, tmp; 8070 expressionS expr1; 8071 int dbl; 8072 const char *s, *s2, *s3; 8073 8074 mask = ip->insn_mo->mask; 8075 8076 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 8077 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; 8078 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 8079 8080 expr1.X_op = O_constant; 8081 expr1.X_op_symbol = NULL; 8082 expr1.X_add_symbol = NULL; 8083 expr1.X_add_number = 1; 8084 8085 dbl = 0; 8086 8087 switch (mask) 8088 { 8089 default: 8090 internalError (); 8091 8092 case M_DDIV_3: 8093 dbl = 1; 8094 case M_DIV_3: 8095 s = "mflo"; 8096 goto do_div3; 8097 case M_DREM_3: 8098 dbl = 1; 8099 case M_REM_3: 8100 s = "mfhi"; 8101 do_div3: 8102 mips_emit_delays (TRUE); 8103 ++mips_opts.noreorder; 8104 mips_any_noreorder = 1; 8105 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); 8106 expr1.X_add_number = 2; 8107 macro_build (&expr1, "bnez", "x,p", yreg); 8108 macro_build (NULL, "break", "6", 7); 8109 8110 /* FIXME: The normal code checks for of -1 / -0x80000000 here, 8111 since that causes an overflow. We should do that as well, 8112 but I don't see how to do the comparisons without a temporary 8113 register. */ 8114 --mips_opts.noreorder; 8115 macro_build (NULL, s, "x", zreg); 8116 break; 8117 8118 case M_DIVU_3: 8119 s = "divu"; 8120 s2 = "mflo"; 8121 goto do_divu3; 8122 case M_REMU_3: 8123 s = "divu"; 8124 s2 = "mfhi"; 8125 goto do_divu3; 8126 case M_DDIVU_3: 8127 s = "ddivu"; 8128 s2 = "mflo"; 8129 goto do_divu3; 8130 case M_DREMU_3: 8131 s = "ddivu"; 8132 s2 = "mfhi"; 8133 do_divu3: 8134 mips_emit_delays (TRUE); 8135 ++mips_opts.noreorder; 8136 mips_any_noreorder = 1; 8137 macro_build (NULL, s, "0,x,y", xreg, yreg); 8138 expr1.X_add_number = 2; 8139 macro_build (&expr1, "bnez", "x,p", yreg); 8140 macro_build (NULL, "break", "6", 7); 8141 --mips_opts.noreorder; 8142 macro_build (NULL, s2, "x", zreg); 8143 break; 8144 8145 case M_DMUL: 8146 dbl = 1; 8147 case M_MUL: 8148 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); 8149 macro_build (NULL, "mflo", "x", zreg); 8150 return; 8151 8152 case M_DSUBU_I: 8153 dbl = 1; 8154 goto do_subu; 8155 case M_SUBU_I: 8156 do_subu: 8157 if (imm_expr.X_op != O_constant) 8158 as_bad (_("Unsupported large constant")); 8159 imm_expr.X_add_number = -imm_expr.X_add_number; 8160 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); 8161 break; 8162 8163 case M_SUBU_I_2: 8164 if (imm_expr.X_op != O_constant) 8165 as_bad (_("Unsupported large constant")); 8166 imm_expr.X_add_number = -imm_expr.X_add_number; 8167 macro_build (&imm_expr, "addiu", "x,k", xreg); 8168 break; 8169 8170 case M_DSUBU_I_2: 8171 if (imm_expr.X_op != O_constant) 8172 as_bad (_("Unsupported large constant")); 8173 imm_expr.X_add_number = -imm_expr.X_add_number; 8174 macro_build (&imm_expr, "daddiu", "y,j", yreg); 8175 break; 8176 8177 case M_BEQ: 8178 s = "cmp"; 8179 s2 = "bteqz"; 8180 goto do_branch; 8181 case M_BNE: 8182 s = "cmp"; 8183 s2 = "btnez"; 8184 goto do_branch; 8185 case M_BLT: 8186 s = "slt"; 8187 s2 = "btnez"; 8188 goto do_branch; 8189 case M_BLTU: 8190 s = "sltu"; 8191 s2 = "btnez"; 8192 goto do_branch; 8193 case M_BLE: 8194 s = "slt"; 8195 s2 = "bteqz"; 8196 goto do_reverse_branch; 8197 case M_BLEU: 8198 s = "sltu"; 8199 s2 = "bteqz"; 8200 goto do_reverse_branch; 8201 case M_BGE: 8202 s = "slt"; 8203 s2 = "bteqz"; 8204 goto do_branch; 8205 case M_BGEU: 8206 s = "sltu"; 8207 s2 = "bteqz"; 8208 goto do_branch; 8209 case M_BGT: 8210 s = "slt"; 8211 s2 = "btnez"; 8212 goto do_reverse_branch; 8213 case M_BGTU: 8214 s = "sltu"; 8215 s2 = "btnez"; 8216 8217 do_reverse_branch: 8218 tmp = xreg; 8219 xreg = yreg; 8220 yreg = tmp; 8221 8222 do_branch: 8223 macro_build (NULL, s, "x,y", xreg, yreg); 8224 macro_build (&offset_expr, s2, "p"); 8225 break; 8226 8227 case M_BEQ_I: 8228 s = "cmpi"; 8229 s2 = "bteqz"; 8230 s3 = "x,U"; 8231 goto do_branch_i; 8232 case M_BNE_I: 8233 s = "cmpi"; 8234 s2 = "btnez"; 8235 s3 = "x,U"; 8236 goto do_branch_i; 8237 case M_BLT_I: 8238 s = "slti"; 8239 s2 = "btnez"; 8240 s3 = "x,8"; 8241 goto do_branch_i; 8242 case M_BLTU_I: 8243 s = "sltiu"; 8244 s2 = "btnez"; 8245 s3 = "x,8"; 8246 goto do_branch_i; 8247 case M_BLE_I: 8248 s = "slti"; 8249 s2 = "btnez"; 8250 s3 = "x,8"; 8251 goto do_addone_branch_i; 8252 case M_BLEU_I: 8253 s = "sltiu"; 8254 s2 = "btnez"; 8255 s3 = "x,8"; 8256 goto do_addone_branch_i; 8257 case M_BGE_I: 8258 s = "slti"; 8259 s2 = "bteqz"; 8260 s3 = "x,8"; 8261 goto do_branch_i; 8262 case M_BGEU_I: 8263 s = "sltiu"; 8264 s2 = "bteqz"; 8265 s3 = "x,8"; 8266 goto do_branch_i; 8267 case M_BGT_I: 8268 s = "slti"; 8269 s2 = "bteqz"; 8270 s3 = "x,8"; 8271 goto do_addone_branch_i; 8272 case M_BGTU_I: 8273 s = "sltiu"; 8274 s2 = "bteqz"; 8275 s3 = "x,8"; 8276 8277 do_addone_branch_i: 8278 if (imm_expr.X_op != O_constant) 8279 as_bad (_("Unsupported large constant")); 8280 ++imm_expr.X_add_number; 8281 8282 do_branch_i: 8283 macro_build (&imm_expr, s, s3, xreg); 8284 macro_build (&offset_expr, s2, "p"); 8285 break; 8286 8287 case M_ABS: 8288 expr1.X_add_number = 0; 8289 macro_build (&expr1, "slti", "x,8", yreg); 8290 if (xreg != yreg) 8291 move_register (xreg, yreg); 8292 expr1.X_add_number = 2; 8293 macro_build (&expr1, "bteqz", "p"); 8294 macro_build (NULL, "neg", "x,w", xreg, xreg); 8295 } 8296 } 8297 8298 /* For consistency checking, verify that all bits are specified either 8299 by the match/mask part of the instruction definition, or by the 8300 operand list. */ 8301 static int 8302 validate_mips_insn (const struct mips_opcode *opc) 8303 { 8304 const char *p = opc->args; 8305 char c; 8306 unsigned long used_bits = opc->mask; 8307 8308 if ((used_bits & opc->match) != opc->match) 8309 { 8310 as_bad (_("internal: bad mips opcode (mask error): %s %s"), 8311 opc->name, opc->args); 8312 return 0; 8313 } 8314 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) 8315 while (*p) 8316 switch (c = *p++) 8317 { 8318 case ',': break; 8319 case '(': break; 8320 case ')': break; 8321 case '+': 8322 switch (c = *p++) 8323 { 8324 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 8325 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; 8326 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; 8327 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); 8328 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; 8329 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 8330 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; 8331 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; 8332 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; 8333 case 'I': break; 8334 default: 8335 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), 8336 c, opc->name, opc->args); 8337 return 0; 8338 } 8339 break; 8340 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 8341 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 8342 case 'A': break; 8343 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; 8344 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; 8345 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; 8346 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8347 case 'F': break; 8348 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 8349 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; 8350 case 'I': break; 8351 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; 8352 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 8353 case 'L': break; 8354 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; 8355 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; 8356 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; 8357 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); 8358 USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8359 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; 8360 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; 8361 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8362 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; 8363 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8364 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; 8365 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; 8366 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8367 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; 8368 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8369 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; 8370 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 8371 case 'f': break; 8372 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; 8373 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; 8374 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; 8375 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; 8376 case 'l': break; 8377 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; 8378 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; 8379 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; 8380 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8381 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8382 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8383 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; 8384 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8385 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8386 case 'x': break; 8387 case 'z': break; 8388 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; 8389 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); 8390 USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8391 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; 8392 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; 8393 case '[': break; 8394 case ']': break; 8395 default: 8396 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), 8397 c, opc->name, opc->args); 8398 return 0; 8399 } 8400 #undef USE_BITS 8401 if (used_bits != 0xffffffff) 8402 { 8403 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), 8404 ~used_bits & 0xffffffff, opc->name, opc->args); 8405 return 0; 8406 } 8407 return 1; 8408 } 8409 8410 /* This routine assembles an instruction into its binary format. As a 8411 side effect, it sets one of the global variables imm_reloc or 8412 offset_reloc to the type of relocation to do if one of the operands 8413 is an address expression. */ 8414 8415 static void 8416 mips_ip (char *str, struct mips_cl_insn *ip) 8417 { 8418 char *s; 8419 const char *args; 8420 char c = 0; 8421 struct mips_opcode *insn; 8422 char *argsStart; 8423 unsigned int regno; 8424 unsigned int lastregno = 0; 8425 unsigned int lastpos = 0; 8426 unsigned int limlo, limhi; 8427 char *s_reset; 8428 char save_c = 0; 8429 offsetT min_range, max_range; 8430 int argnum; 8431 unsigned int rtype; 8432 8433 insn_error = NULL; 8434 8435 /* If the instruction contains a '.', we first try to match an instruction 8436 including the '.'. Then we try again without the '.'. */ 8437 insn = NULL; 8438 for (s = str; *s != '\0' && !ISSPACE (*s); ++s) 8439 continue; 8440 8441 /* If we stopped on whitespace, then replace the whitespace with null for 8442 the call to hash_find. Save the character we replaced just in case we 8443 have to re-parse the instruction. */ 8444 if (ISSPACE (*s)) 8445 { 8446 save_c = *s; 8447 *s++ = '\0'; 8448 } 8449 8450 insn = (struct mips_opcode *) hash_find (op_hash, str); 8451 8452 /* If we didn't find the instruction in the opcode table, try again, but 8453 this time with just the instruction up to, but not including the 8454 first '.'. */ 8455 if (insn == NULL) 8456 { 8457 /* Restore the character we overwrite above (if any). */ 8458 if (save_c) 8459 *(--s) = save_c; 8460 8461 /* Scan up to the first '.' or whitespace. */ 8462 for (s = str; 8463 *s != '\0' && *s != '.' && !ISSPACE (*s); 8464 ++s) 8465 continue; 8466 8467 /* If we did not find a '.', then we can quit now. */ 8468 if (*s != '.') 8469 { 8470 insn_error = "unrecognized opcode"; 8471 return; 8472 } 8473 8474 /* Lookup the instruction in the hash table. */ 8475 *s++ = '\0'; 8476 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) 8477 { 8478 insn_error = "unrecognized opcode"; 8479 return; 8480 } 8481 } 8482 8483 argsStart = s; 8484 for (;;) 8485 { 8486 bfd_boolean ok; 8487 8488 assert (strcmp (insn->name, str) == 0); 8489 8490 if (OPCODE_IS_MEMBER (insn, 8491 (mips_opts.isa 8492 | (file_ase_mips16 ? INSN_MIPS16 : 0) 8493 | (mips_opts.ase_mdmx ? INSN_MDMX : 0) 8494 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), 8495 mips_opts.arch)) 8496 ok = TRUE; 8497 else 8498 ok = FALSE; 8499 8500 if (insn->pinfo != INSN_MACRO) 8501 { 8502 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) 8503 ok = FALSE; 8504 } 8505 8506 if (! ok) 8507 { 8508 if (insn + 1 < &mips_opcodes[NUMOPCODES] 8509 && strcmp (insn->name, insn[1].name) == 0) 8510 { 8511 ++insn; 8512 continue; 8513 } 8514 else 8515 { 8516 if (!insn_error) 8517 { 8518 static char buf[100]; 8519 sprintf (buf, 8520 _("opcode not supported on this processor: %s (%s)"), 8521 mips_cpu_info_from_arch (mips_opts.arch)->name, 8522 mips_cpu_info_from_isa (mips_opts.isa)->name); 8523 insn_error = buf; 8524 } 8525 if (save_c) 8526 *(--s) = save_c; 8527 return; 8528 } 8529 } 8530 8531 ip->insn_mo = insn; 8532 ip->insn_opcode = insn->match; 8533 insn_error = NULL; 8534 argnum = 1; 8535 for (args = insn->args;; ++args) 8536 { 8537 int is_mdmx; 8538 8539 s += strspn (s, " \t"); 8540 is_mdmx = 0; 8541 switch (*args) 8542 { 8543 case '\0': /* end of args */ 8544 if (*s == '\0') 8545 return; 8546 break; 8547 8548 case ',': 8549 if (*s++ == *args) 8550 continue; 8551 s--; 8552 switch (*++args) 8553 { 8554 case 'r': 8555 case 'v': 8556 ip->insn_opcode |= lastregno << OP_SH_RS; 8557 continue; 8558 8559 case 'w': 8560 ip->insn_opcode |= lastregno << OP_SH_RT; 8561 continue; 8562 8563 case 'W': 8564 ip->insn_opcode |= lastregno << OP_SH_FT; 8565 continue; 8566 8567 case 'V': 8568 ip->insn_opcode |= lastregno << OP_SH_FS; 8569 continue; 8570 } 8571 break; 8572 8573 case '(': 8574 /* Handle optional base register. 8575 Either the base register is omitted or 8576 we must have a left paren. */ 8577 /* This is dependent on the next operand specifier 8578 is a base register specification. */ 8579 assert (args[1] == 'b' || args[1] == '5' 8580 || args[1] == '-' || args[1] == '4'); 8581 if (*s == '\0') 8582 return; 8583 8584 case ')': /* these must match exactly */ 8585 case '[': 8586 case ']': 8587 if (*s++ == *args) 8588 continue; 8589 break; 8590 8591 case '+': /* Opcode extension character. */ 8592 switch (*++args) 8593 { 8594 case 'A': /* ins/ext position, becomes LSB. */ 8595 limlo = 0; 8596 limhi = 31; 8597 goto do_lsb; 8598 case 'E': 8599 limlo = 32; 8600 limhi = 63; 8601 goto do_lsb; 8602 do_lsb: 8603 my_getExpression (&imm_expr, s); 8604 check_absolute_expr (ip, &imm_expr); 8605 if ((unsigned long) imm_expr.X_add_number < limlo 8606 || (unsigned long) imm_expr.X_add_number > limhi) 8607 { 8608 as_bad (_("Improper position (%lu)"), 8609 (unsigned long) imm_expr.X_add_number); 8610 imm_expr.X_add_number = limlo; 8611 } 8612 lastpos = imm_expr.X_add_number; 8613 ip->insn_opcode |= (imm_expr.X_add_number 8614 & OP_MASK_SHAMT) << OP_SH_SHAMT; 8615 imm_expr.X_op = O_absent; 8616 s = expr_end; 8617 continue; 8618 8619 case 'B': /* ins size, becomes MSB. */ 8620 limlo = 1; 8621 limhi = 32; 8622 goto do_msb; 8623 case 'F': 8624 limlo = 33; 8625 limhi = 64; 8626 goto do_msb; 8627 do_msb: 8628 my_getExpression (&imm_expr, s); 8629 check_absolute_expr (ip, &imm_expr); 8630 /* Check for negative input so that small negative numbers 8631 will not succeed incorrectly. The checks against 8632 (pos+size) transitively check "size" itself, 8633 assuming that "pos" is reasonable. */ 8634 if ((long) imm_expr.X_add_number < 0 8635 || ((unsigned long) imm_expr.X_add_number 8636 + lastpos) < limlo 8637 || ((unsigned long) imm_expr.X_add_number 8638 + lastpos) > limhi) 8639 { 8640 as_bad (_("Improper insert size (%lu, position %lu)"), 8641 (unsigned long) imm_expr.X_add_number, 8642 (unsigned long) lastpos); 8643 imm_expr.X_add_number = limlo - lastpos; 8644 } 8645 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) 8646 & OP_MASK_INSMSB) << OP_SH_INSMSB; 8647 imm_expr.X_op = O_absent; 8648 s = expr_end; 8649 continue; 8650 8651 case 'C': /* ext size, becomes MSBD. */ 8652 limlo = 1; 8653 limhi = 32; 8654 goto do_msbd; 8655 case 'G': 8656 limlo = 33; 8657 limhi = 64; 8658 goto do_msbd; 8659 case 'H': 8660 limlo = 33; 8661 limhi = 64; 8662 goto do_msbd; 8663 do_msbd: 8664 my_getExpression (&imm_expr, s); 8665 check_absolute_expr (ip, &imm_expr); 8666 /* Check for negative input so that small negative numbers 8667 will not succeed incorrectly. The checks against 8668 (pos+size) transitively check "size" itself, 8669 assuming that "pos" is reasonable. */ 8670 if ((long) imm_expr.X_add_number < 0 8671 || ((unsigned long) imm_expr.X_add_number 8672 + lastpos) < limlo 8673 || ((unsigned long) imm_expr.X_add_number 8674 + lastpos) > limhi) 8675 { 8676 as_bad (_("Improper extract size (%lu, position %lu)"), 8677 (unsigned long) imm_expr.X_add_number, 8678 (unsigned long) lastpos); 8679 imm_expr.X_add_number = limlo - lastpos; 8680 } 8681 ip->insn_opcode |= ((imm_expr.X_add_number - 1) 8682 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; 8683 imm_expr.X_op = O_absent; 8684 s = expr_end; 8685 continue; 8686 8687 case 'D': 8688 /* +D is for disassembly only; never match. */ 8689 break; 8690 8691 case 'I': 8692 /* "+I" is like "I", except that imm2_expr is used. */ 8693 my_getExpression (&imm2_expr, s); 8694 if (imm2_expr.X_op != O_big 8695 && imm2_expr.X_op != O_constant) 8696 insn_error = _("absolute expression required"); 8697 normalize_constant_expr (&imm2_expr); 8698 s = expr_end; 8699 continue; 8700 8701 default: 8702 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), 8703 *args, insn->name, insn->args); 8704 /* Further processing is fruitless. */ 8705 return; 8706 } 8707 break; 8708 8709 case '<': /* must be at least one digit */ 8710 /* 8711 * According to the manual, if the shift amount is greater 8712 * than 31 or less than 0, then the shift amount should be 8713 * mod 32. In reality the mips assembler issues an error. 8714 * We issue a warning and mask out all but the low 5 bits. 8715 */ 8716 my_getExpression (&imm_expr, s); 8717 check_absolute_expr (ip, &imm_expr); 8718 if ((unsigned long) imm_expr.X_add_number > 31) 8719 { 8720 as_warn (_("Improper shift amount (%lu)"), 8721 (unsigned long) imm_expr.X_add_number); 8722 imm_expr.X_add_number &= OP_MASK_SHAMT; 8723 } 8724 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; 8725 imm_expr.X_op = O_absent; 8726 s = expr_end; 8727 continue; 8728 8729 case '>': /* shift amount minus 32 */ 8730 my_getExpression (&imm_expr, s); 8731 check_absolute_expr (ip, &imm_expr); 8732 if ((unsigned long) imm_expr.X_add_number < 32 8733 || (unsigned long) imm_expr.X_add_number > 63) 8734 break; 8735 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; 8736 imm_expr.X_op = O_absent; 8737 s = expr_end; 8738 continue; 8739 8740 case 'k': /* cache code */ 8741 case 'h': /* prefx code */ 8742 my_getExpression (&imm_expr, s); 8743 check_absolute_expr (ip, &imm_expr); 8744 if ((unsigned long) imm_expr.X_add_number > 31) 8745 { 8746 as_warn (_("Invalid value for `%s' (%lu)"), 8747 ip->insn_mo->name, 8748 (unsigned long) imm_expr.X_add_number); 8749 imm_expr.X_add_number &= 0x1f; 8750 } 8751 if (*args == 'k') 8752 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; 8753 else 8754 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; 8755 imm_expr.X_op = O_absent; 8756 s = expr_end; 8757 continue; 8758 8759 case 'c': /* break code */ 8760 my_getExpression (&imm_expr, s); 8761 check_absolute_expr (ip, &imm_expr); 8762 if ((unsigned long) imm_expr.X_add_number > 1023) 8763 { 8764 as_warn (_("Illegal break code (%lu)"), 8765 (unsigned long) imm_expr.X_add_number); 8766 imm_expr.X_add_number &= OP_MASK_CODE; 8767 } 8768 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; 8769 imm_expr.X_op = O_absent; 8770 s = expr_end; 8771 continue; 8772 8773 case 'q': /* lower break code */ 8774 my_getExpression (&imm_expr, s); 8775 check_absolute_expr (ip, &imm_expr); 8776 if ((unsigned long) imm_expr.X_add_number > 1023) 8777 { 8778 as_warn (_("Illegal lower break code (%lu)"), 8779 (unsigned long) imm_expr.X_add_number); 8780 imm_expr.X_add_number &= OP_MASK_CODE2; 8781 } 8782 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; 8783 imm_expr.X_op = O_absent; 8784 s = expr_end; 8785 continue; 8786 8787 case 'B': /* 20-bit syscall/break code. */ 8788 my_getExpression (&imm_expr, s); 8789 check_absolute_expr (ip, &imm_expr); 8790 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) 8791 as_warn (_("Illegal 20-bit code (%lu)"), 8792 (unsigned long) imm_expr.X_add_number); 8793 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; 8794 imm_expr.X_op = O_absent; 8795 s = expr_end; 8796 continue; 8797 8798 case 'C': /* Coprocessor code */ 8799 my_getExpression (&imm_expr, s); 8800 check_absolute_expr (ip, &imm_expr); 8801 if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) 8802 { 8803 as_warn (_("Coproccesor code > 25 bits (%lu)"), 8804 (unsigned long) imm_expr.X_add_number); 8805 imm_expr.X_add_number &= ((1 << 25) - 1); 8806 } 8807 ip->insn_opcode |= imm_expr.X_add_number; 8808 imm_expr.X_op = O_absent; 8809 s = expr_end; 8810 continue; 8811 8812 case 'J': /* 19-bit wait code. */ 8813 my_getExpression (&imm_expr, s); 8814 check_absolute_expr (ip, &imm_expr); 8815 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) 8816 as_warn (_("Illegal 19-bit code (%lu)"), 8817 (unsigned long) imm_expr.X_add_number); 8818 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; 8819 imm_expr.X_op = O_absent; 8820 s = expr_end; 8821 continue; 8822 8823 case 'P': /* Performance register */ 8824 my_getExpression (&imm_expr, s); 8825 check_absolute_expr (ip, &imm_expr); 8826 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) 8827 { 8828 as_warn (_("Invalid performance register (%lu)"), 8829 (unsigned long) imm_expr.X_add_number); 8830 imm_expr.X_add_number &= OP_MASK_PERFREG; 8831 } 8832 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); 8833 imm_expr.X_op = O_absent; 8834 s = expr_end; 8835 continue; 8836 8837 case 'G': /* Coprocessor destination register. */ 8838 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) 8839 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); 8840 else 8841 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); 8842 ip->insn_opcode |= regno << OP_SH_RD; 8843 if (ok) 8844 { 8845 lastregno = regno; 8846 continue; 8847 } 8848 else 8849 break; 8850 8851 case 'b': /* base register */ 8852 case 'd': /* destination register */ 8853 case 's': /* source register */ 8854 case 't': /* target register */ 8855 case 'r': /* both target and source */ 8856 case 'v': /* both dest and source */ 8857 case 'w': /* both dest and target */ 8858 case 'E': /* coprocessor target register */ 8859 case 'K': /* 'rdhwr' destination register */ 8860 case 'x': /* ignore register name */ 8861 case 'z': /* must be zero register */ 8862 case 'U': /* destination register (clo/clz). */ 8863 s_reset = s; 8864 if (*args == 'E' || *args == 'K') 8865 ok = reg_lookup (&s, RTYPE_NUM, ®no); 8866 else 8867 { 8868 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); 8869 if (regno == AT && ! mips_opts.noat) 8870 as_warn ("Used $at without \".set noat\""); 8871 } 8872 if (ok) 8873 { 8874 c = *args; 8875 if (*s == ' ') 8876 ++s; 8877 if (args[1] != *s) 8878 { 8879 if (c == 'r' || c == 'v' || c == 'w') 8880 { 8881 regno = lastregno; 8882 s = s_reset; 8883 ++args; 8884 } 8885 } 8886 /* 'z' only matches $0. */ 8887 if (c == 'z' && regno != 0) 8888 break; 8889 8890 /* Now that we have assembled one operand, we use the args string 8891 * to figure out where it goes in the instruction. */ 8892 switch (c) 8893 { 8894 case 'r': 8895 case 's': 8896 case 'v': 8897 case 'b': 8898 ip->insn_opcode |= regno << OP_SH_RS; 8899 break; 8900 case 'd': 8901 case 'G': 8902 case 'K': 8903 ip->insn_opcode |= regno << OP_SH_RD; 8904 break; 8905 case 'U': 8906 ip->insn_opcode |= regno << OP_SH_RD; 8907 ip->insn_opcode |= regno << OP_SH_RT; 8908 break; 8909 case 'w': 8910 case 't': 8911 case 'E': 8912 ip->insn_opcode |= regno << OP_SH_RT; 8913 break; 8914 case 'x': 8915 /* This case exists because on the r3000 trunc 8916 expands into a macro which requires a gp 8917 register. On the r6000 or r4000 it is 8918 assembled into a single instruction which 8919 ignores the register. Thus the insn version 8920 is MIPS_ISA2 and uses 'x', and the macro 8921 version is MIPS_ISA1 and uses 't'. */ 8922 break; 8923 case 'z': 8924 /* This case is for the div instruction, which 8925 acts differently if the destination argument 8926 is $0. This only matches $0, and is checked 8927 outside the switch. */ 8928 break; 8929 case 'D': 8930 /* Itbl operand; not yet implemented. FIXME ?? */ 8931 break; 8932 /* What about all other operands like 'i', which 8933 can be specified in the opcode table? */ 8934 } 8935 lastregno = regno; 8936 continue; 8937 } 8938 switch (*args++) 8939 { 8940 case 'r': 8941 case 'v': 8942 ip->insn_opcode |= lastregno << OP_SH_RS; 8943 continue; 8944 case 'w': 8945 ip->insn_opcode |= lastregno << OP_SH_RT; 8946 continue; 8947 } 8948 break; 8949 8950 case 'O': /* MDMX alignment immediate constant. */ 8951 my_getExpression (&imm_expr, s); 8952 check_absolute_expr (ip, &imm_expr); 8953 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) 8954 { 8955 as_warn ("Improper align amount (%ld), using low bits", 8956 (long) imm_expr.X_add_number); 8957 imm_expr.X_add_number &= OP_MASK_ALN; 8958 } 8959 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; 8960 imm_expr.X_op = O_absent; 8961 s = expr_end; 8962 continue; 8963 8964 case 'Q': /* MDMX vector, element sel, or const. */ 8965 if (s[0] != '$') 8966 { 8967 /* MDMX Immediate. */ 8968 my_getExpression (&imm_expr, s); 8969 check_absolute_expr (ip, &imm_expr); 8970 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) 8971 { 8972 as_warn (_("Invalid MDMX Immediate (%ld)"), 8973 (long) imm_expr.X_add_number); 8974 imm_expr.X_add_number &= OP_MASK_FT; 8975 } 8976 imm_expr.X_add_number &= OP_MASK_FT; 8977 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) 8978 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; 8979 else 8980 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; 8981 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; 8982 imm_expr.X_op = O_absent; 8983 s = expr_end; 8984 continue; 8985 } 8986 /* Not MDMX Immediate. Fall through. */ 8987 case 'X': /* MDMX destination register. */ 8988 case 'Y': /* MDMX source register. */ 8989 case 'Z': /* MDMX target register. */ 8990 is_mdmx = 1; 8991 case 'D': /* floating point destination register */ 8992 case 'S': /* floating point source register */ 8993 case 'T': /* floating point target register */ 8994 case 'R': /* floating point source register */ 8995 case 'V': 8996 case 'W': 8997 rtype = RTYPE_FPU; 8998 if (is_mdmx 8999 || (mips_opts.ase_mdmx 9000 && (ip->insn_mo->pinfo & FP_D) 9001 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY 9002 | INSN_COPROC_MEMORY_DELAY 9003 | INSN_LOAD_COPROC_DELAY 9004 | INSN_LOAD_MEMORY_DELAY 9005 | INSN_STORE_MEMORY)))) 9006 rtype |= RTYPE_VEC; 9007 s_reset = s; 9008 if (reg_lookup (&s, rtype, ®no)) 9009 { 9010 if ((regno & 1) != 0 9011 && HAVE_32BIT_FPRS 9012 && ! (strcmp (str, "mtc1") == 0 9013 || strcmp (str, "mfc1") == 0 9014 || strcmp (str, "lwc1") == 0 9015 || strcmp (str, "swc1") == 0 9016 || strcmp (str, "l.s") == 0 9017 || strcmp (str, "s.s") == 0)) 9018 as_warn (_("Float register should be even, was %d"), 9019 regno); 9020 9021 c = *args; 9022 if (*s == ' ') 9023 ++s; 9024 if (args[1] != *s) 9025 { 9026 if (c == 'V' || c == 'W') 9027 { 9028 regno = lastregno; 9029 s = s_reset; 9030 ++args; 9031 } 9032 } 9033 switch (c) 9034 { 9035 case 'D': 9036 case 'X': 9037 ip->insn_opcode |= regno << OP_SH_FD; 9038 break; 9039 case 'V': 9040 case 'S': 9041 case 'Y': 9042 ip->insn_opcode |= regno << OP_SH_FS; 9043 break; 9044 case 'Q': 9045 /* This is like 'Z', but also needs to fix the MDMX 9046 vector/scalar select bits. Note that the 9047 scalar immediate case is handled above. */ 9048 if (*s == '[') 9049 { 9050 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); 9051 int max_el = (is_qh ? 3 : 7); 9052 s++; 9053 my_getExpression(&imm_expr, s); 9054 check_absolute_expr (ip, &imm_expr); 9055 s = expr_end; 9056 if (imm_expr.X_add_number > max_el) 9057 as_bad(_("Bad element selector %ld"), 9058 (long) imm_expr.X_add_number); 9059 imm_expr.X_add_number &= max_el; 9060 ip->insn_opcode |= (imm_expr.X_add_number 9061 << (OP_SH_VSEL + 9062 (is_qh ? 2 : 1))); 9063 if (*s != ']') 9064 as_warn(_("Expecting ']' found '%s'"), s); 9065 else 9066 s++; 9067 } 9068 else 9069 { 9070 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) 9071 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH 9072 << OP_SH_VSEL); 9073 else 9074 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << 9075 OP_SH_VSEL); 9076 } 9077 /* Fall through */ 9078 case 'W': 9079 case 'T': 9080 case 'Z': 9081 ip->insn_opcode |= regno << OP_SH_FT; 9082 break; 9083 case 'R': 9084 ip->insn_opcode |= regno << OP_SH_FR; 9085 break; 9086 } 9087 lastregno = regno; 9088 continue; 9089 } 9090 9091 switch (*args++) 9092 { 9093 case 'V': 9094 ip->insn_opcode |= lastregno << OP_SH_FS; 9095 continue; 9096 case 'W': 9097 ip->insn_opcode |= lastregno << OP_SH_FT; 9098 continue; 9099 } 9100 break; 9101 9102 case 'I': 9103 my_getExpression (&imm_expr, s); 9104 if (imm_expr.X_op != O_big 9105 && imm_expr.X_op != O_constant) 9106 insn_error = _("absolute expression required"); 9107 normalize_constant_expr (&imm_expr); 9108 s = expr_end; 9109 continue; 9110 9111 case 'A': 9112 my_getExpression (&offset_expr, s); 9113 *imm_reloc = BFD_RELOC_32; 9114 s = expr_end; 9115 continue; 9116 9117 case 'F': 9118 case 'L': 9119 case 'f': 9120 case 'l': 9121 { 9122 int f64; 9123 int using_gprs; 9124 char *save_in; 9125 char *err; 9126 unsigned char temp[8]; 9127 int len; 9128 unsigned int length; 9129 segT seg; 9130 subsegT subseg; 9131 char *p; 9132 9133 /* These only appear as the last operand in an 9134 instruction, and every instruction that accepts 9135 them in any variant accepts them in all variants. 9136 This means we don't have to worry about backing out 9137 any changes if the instruction does not match. 9138 9139 The difference between them is the size of the 9140 floating point constant and where it goes. For 'F' 9141 and 'L' the constant is 64 bits; for 'f' and 'l' it 9142 is 32 bits. Where the constant is placed is based 9143 on how the MIPS assembler does things: 9144 F -- .rdata 9145 L -- .lit8 9146 f -- immediate value 9147 l -- .lit4 9148 9149 The .lit4 and .lit8 sections are only used if 9150 permitted by the -G argument. 9151 9152 When generating embedded PIC code, we use the 9153 .lit8 section but not the .lit4 section (we can do 9154 .lit4 inline easily; we need to put .lit8 9155 somewhere in the data segment, and using .lit8 9156 permits the linker to eventually combine identical 9157 .lit8 entries). 9158 9159 The code below needs to know whether the target register 9160 is 32 or 64 bits wide. It relies on the fact 'f' and 9161 'F' are used with GPR-based instructions and 'l' and 9162 'L' are used with FPR-based instructions. */ 9163 9164 f64 = *args == 'F' || *args == 'L'; 9165 using_gprs = *args == 'F' || *args == 'f'; 9166 9167 save_in = input_line_pointer; 9168 input_line_pointer = s; 9169 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); 9170 length = len; 9171 s = input_line_pointer; 9172 input_line_pointer = save_in; 9173 if (err != NULL && *err != '\0') 9174 { 9175 as_bad (_("Bad floating point constant: %s"), err); 9176 memset (temp, '\0', sizeof temp); 9177 length = f64 ? 8 : 4; 9178 } 9179 9180 assert (length == (unsigned) (f64 ? 8 : 4)); 9181 9182 if (*args == 'f' 9183 || (*args == 'l' 9184 && (! USE_GLOBAL_POINTER_OPT 9185 || mips_pic == EMBEDDED_PIC 9186 || g_switch_value < 4 9187 || (temp[0] == 0 && temp[1] == 0) 9188 || (temp[2] == 0 && temp[3] == 0)))) 9189 { 9190 imm_expr.X_op = O_constant; 9191 if (! target_big_endian) 9192 imm_expr.X_add_number = bfd_getl32 (temp); 9193 else 9194 imm_expr.X_add_number = bfd_getb32 (temp); 9195 } 9196 else if (length > 4 9197 && ! mips_disable_float_construction 9198 /* Constants can only be constructed in GPRs and 9199 copied to FPRs if the GPRs are at least as wide 9200 as the FPRs. Force the constant into memory if 9201 we are using 64-bit FPRs but the GPRs are only 9202 32 bits wide. */ 9203 && (using_gprs 9204 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) 9205 && ((temp[0] == 0 && temp[1] == 0) 9206 || (temp[2] == 0 && temp[3] == 0)) 9207 && ((temp[4] == 0 && temp[5] == 0) 9208 || (temp[6] == 0 && temp[7] == 0))) 9209 { 9210 /* The value is simple enough to load with a couple of 9211 instructions. If using 32-bit registers, set 9212 imm_expr to the high order 32 bits and offset_expr to 9213 the low order 32 bits. Otherwise, set imm_expr to 9214 the entire 64 bit constant. */ 9215 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) 9216 { 9217 imm_expr.X_op = O_constant; 9218 offset_expr.X_op = O_constant; 9219 if (! target_big_endian) 9220 { 9221 imm_expr.X_add_number = bfd_getl32 (temp + 4); 9222 offset_expr.X_add_number = bfd_getl32 (temp); 9223 } 9224 else 9225 { 9226 imm_expr.X_add_number = bfd_getb32 (temp); 9227 offset_expr.X_add_number = bfd_getb32 (temp + 4); 9228 } 9229 if (offset_expr.X_add_number == 0) 9230 offset_expr.X_op = O_absent; 9231 } 9232 else if (sizeof (imm_expr.X_add_number) > 4) 9233 { 9234 imm_expr.X_op = O_constant; 9235 if (! target_big_endian) 9236 imm_expr.X_add_number = bfd_getl64 (temp); 9237 else 9238 imm_expr.X_add_number = bfd_getb64 (temp); 9239 } 9240 else 9241 { 9242 imm_expr.X_op = O_big; 9243 imm_expr.X_add_number = 4; 9244 if (! target_big_endian) 9245 { 9246 generic_bignum[0] = bfd_getl16 (temp); 9247 generic_bignum[1] = bfd_getl16 (temp + 2); 9248 generic_bignum[2] = bfd_getl16 (temp + 4); 9249 generic_bignum[3] = bfd_getl16 (temp + 6); 9250 } 9251 else 9252 { 9253 generic_bignum[0] = bfd_getb16 (temp + 6); 9254 generic_bignum[1] = bfd_getb16 (temp + 4); 9255 generic_bignum[2] = bfd_getb16 (temp + 2); 9256 generic_bignum[3] = bfd_getb16 (temp); 9257 } 9258 } 9259 } 9260 else 9261 { 9262 const char *newname; 9263 segT new_seg; 9264 9265 /* Switch to the right section. */ 9266 seg = now_seg; 9267 subseg = now_subseg; 9268 switch (*args) 9269 { 9270 default: /* unused default case avoids warnings. */ 9271 case 'L': 9272 newname = RDATA_SECTION_NAME; 9273 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) 9274 || mips_pic == EMBEDDED_PIC) 9275 newname = ".lit8"; 9276 break; 9277 case 'F': 9278 if (mips_pic == EMBEDDED_PIC) 9279 newname = ".lit8"; 9280 else 9281 newname = RDATA_SECTION_NAME; 9282 break; 9283 case 'l': 9284 assert (!USE_GLOBAL_POINTER_OPT 9285 || g_switch_value >= 4); 9286 newname = ".lit4"; 9287 break; 9288 } 9289 new_seg = subseg_new (newname, (subsegT) 0); 9290 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 9291 bfd_set_section_flags (stdoutput, new_seg, 9292 (SEC_ALLOC 9293 | SEC_LOAD 9294 | SEC_READONLY 9295 | SEC_DATA)); 9296 frag_align (*args == 'l' ? 2 : 3, 0, 0); 9297 if (OUTPUT_FLAVOR == bfd_target_elf_flavour 9298 && strcmp (TARGET_OS, "elf") != 0) 9299 record_alignment (new_seg, 4); 9300 else 9301 record_alignment (new_seg, *args == 'l' ? 2 : 3); 9302 if (seg == now_seg) 9303 as_bad (_("Can't use floating point insn in this section")); 9304 9305 /* Set the argument to the current address in the 9306 section. */ 9307 offset_expr.X_op = O_symbol; 9308 offset_expr.X_add_symbol = 9309 symbol_new ("L0\001", now_seg, 9310 (valueT) frag_now_fix (), frag_now); 9311 offset_expr.X_add_number = 0; 9312 9313 /* Put the floating point number into the section. */ 9314 p = frag_more ((int) length); 9315 memcpy (p, temp, length); 9316 9317 /* Switch back to the original section. */ 9318 subseg_set (seg, subseg); 9319 } 9320 } 9321 continue; 9322 9323 case 'i': /* 16 bit unsigned immediate */ 9324 case 'j': /* 16 bit signed immediate */ 9325 *imm_reloc = BFD_RELOC_LO16; 9326 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) 9327 { 9328 int more; 9329 offsetT minval, maxval; 9330 9331 more = (insn + 1 < &mips_opcodes[NUMOPCODES] 9332 && strcmp (insn->name, insn[1].name) == 0); 9333 9334 /* If the expression was written as an unsigned number, 9335 only treat it as signed if there are no more 9336 alternatives. */ 9337 if (more 9338 && *args == 'j' 9339 && sizeof (imm_expr.X_add_number) <= 4 9340 && imm_expr.X_op == O_constant 9341 && imm_expr.X_add_number < 0 9342 && imm_expr.X_unsigned 9343 && HAVE_64BIT_GPRS) 9344 break; 9345 9346 /* For compatibility with older assemblers, we accept 9347 0x8000-0xffff as signed 16-bit numbers when only 9348 signed numbers are allowed. */ 9349 if (*args == 'i') 9350 minval = 0, maxval = 0xffff; 9351 else if (more) 9352 minval = -0x8000, maxval = 0x7fff; 9353 else 9354 minval = -0x8000, maxval = 0xffff; 9355 9356 if (imm_expr.X_op != O_constant 9357 || imm_expr.X_add_number < minval 9358 || imm_expr.X_add_number > maxval) 9359 { 9360 if (more) 9361 break; 9362 if (imm_expr.X_op == O_constant 9363 || imm_expr.X_op == O_big) 9364 as_bad (_("expression out of range")); 9365 } 9366 } 9367 s = expr_end; 9368 continue; 9369 9370 case 'o': /* 16 bit offset */ 9371 /* Check whether there is only a single bracketed expression 9372 left. If so, it must be the base register and the 9373 constant must be zero. */ 9374 if (*s == '(' && strchr (s + 1, '(') == 0) 9375 { 9376 offset_expr.X_op = O_constant; 9377 offset_expr.X_add_number = 0; 9378 continue; 9379 } 9380 9381 /* If this value won't fit into a 16 bit offset, then go 9382 find a macro that will generate the 32 bit offset 9383 code pattern. */ 9384 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 9385 && (offset_expr.X_op != O_constant 9386 || offset_expr.X_add_number >= 0x8000 9387 || offset_expr.X_add_number < -0x8000)) 9388 break; 9389 9390 s = expr_end; 9391 continue; 9392 9393 case 'p': /* pc relative offset */ 9394 *offset_reloc = BFD_RELOC_16_PCREL_S2; 9395 my_getExpression (&offset_expr, s); 9396 s = expr_end; 9397 continue; 9398 9399 case 'u': /* upper 16 bits */ 9400 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 9401 && imm_expr.X_op == O_constant 9402 && (imm_expr.X_add_number < 0 9403 || imm_expr.X_add_number >= 0x10000)) 9404 as_bad (_("lui expression not in range 0..65535")); 9405 s = expr_end; 9406 continue; 9407 9408 case 'a': /* 26 bit address */ 9409 my_getExpression (&offset_expr, s); 9410 s = expr_end; 9411 *offset_reloc = BFD_RELOC_MIPS_JMP; 9412 continue; 9413 9414 case 'N': /* 3 bit branch condition code */ 9415 case 'M': /* 3 bit compare condition code */ 9416 rtype = RTYPE_CCC; 9417 if (ip->insn_mo->pinfo & (FP_D| FP_S)) 9418 rtype |= RTYPE_FCC; 9419 if (!reg_lookup (&s, rtype, ®no)) 9420 break; 9421 if ((strcmp(str + strlen(str) - 3, ".ps") == 0 9422 || strcmp(str + strlen(str) - 5, "any2f") == 0 9423 || strcmp(str + strlen(str) - 5, "any2t") == 0) 9424 && (regno & 1) != 0) 9425 as_warn(_("Condition code register should be even for %s, was %d"), 9426 str, regno); 9427 if ((strcmp(str + strlen(str) - 5, "any4f") == 0 9428 || strcmp(str + strlen(str) - 5, "any4t") == 0) 9429 && (regno & 3) != 0) 9430 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), 9431 str, regno); 9432 if (*args == 'N') 9433 ip->insn_opcode |= regno << OP_SH_BCC; 9434 else 9435 ip->insn_opcode |= regno << OP_SH_CCC; 9436 continue; 9437 9438 case 'H': 9439 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) 9440 s += 2; 9441 if (ISDIGIT (*s)) 9442 { 9443 c = 0; 9444 do 9445 { 9446 c *= 10; 9447 c += *s - '0'; 9448 ++s; 9449 } 9450 while (ISDIGIT (*s)); 9451 } 9452 else 9453 c = 8; /* Invalid sel value. */ 9454 9455 if (c > 7) 9456 as_bad (_("invalid coprocessor sub-selection value (0-7)")); 9457 ip->insn_opcode |= c; 9458 continue; 9459 9460 case 'e': 9461 /* Must be at least one digit. */ 9462 my_getExpression (&imm_expr, s); 9463 check_absolute_expr (ip, &imm_expr); 9464 9465 if ((unsigned long) imm_expr.X_add_number 9466 > (unsigned long) OP_MASK_VECBYTE) 9467 { 9468 as_bad (_("bad byte vector index (%ld)"), 9469 (long) imm_expr.X_add_number); 9470 imm_expr.X_add_number = 0; 9471 } 9472 9473 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; 9474 imm_expr.X_op = O_absent; 9475 s = expr_end; 9476 continue; 9477 9478 case '%': 9479 my_getExpression (&imm_expr, s); 9480 check_absolute_expr (ip, &imm_expr); 9481 9482 if ((unsigned long) imm_expr.X_add_number 9483 > (unsigned long) OP_MASK_VECALIGN) 9484 { 9485 as_bad (_("bad byte vector index (%ld)"), 9486 (long) imm_expr.X_add_number); 9487 imm_expr.X_add_number = 0; 9488 } 9489 9490 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; 9491 imm_expr.X_op = O_absent; 9492 s = expr_end; 9493 continue; 9494 9495 default: 9496 as_bad (_("bad char = '%c'\n"), *args); 9497 internalError (); 9498 } 9499 break; 9500 } 9501 /* Args don't match. */ 9502 if (insn + 1 < &mips_opcodes[NUMOPCODES] && 9503 !strcmp (insn->name, insn[1].name)) 9504 { 9505 ++insn; 9506 s = argsStart; 9507 insn_error = _("illegal operands"); 9508 continue; 9509 } 9510 if (save_c) 9511 *(--s) = save_c; 9512 insn_error = _("illegal operands"); 9513 return; 9514 } 9515 } 9516 9517 /* This routine assembles an instruction into its binary format when 9518 assembling for the mips16. As a side effect, it sets one of the 9519 global variables imm_reloc or offset_reloc to the type of 9520 relocation to do if one of the operands is an address expression. 9521 It also sets mips16_small and mips16_ext if the user explicitly 9522 requested a small or extended instruction. */ 9523 9524 static void 9525 mips16_ip (char *str, struct mips_cl_insn *ip) 9526 { 9527 char *s; 9528 const char *args; 9529 struct mips_opcode *insn; 9530 char *argsstart; 9531 unsigned int regno; 9532 unsigned int lastregno = 0; 9533 char *s_reset; 9534 9535 insn_error = NULL; 9536 9537 mips16_small = FALSE; 9538 mips16_ext = FALSE; 9539 9540 for (s = str; ISLOWER (*s); ++s) 9541 ; 9542 switch (*s) 9543 { 9544 case '\0': 9545 break; 9546 9547 case ' ': 9548 *s++ = '\0'; 9549 break; 9550 9551 case '.': 9552 if (s[1] == 't' && s[2] == ' ') 9553 { 9554 *s = '\0'; 9555 mips16_small = TRUE; 9556 s += 3; 9557 break; 9558 } 9559 else if (s[1] == 'e' && s[2] == ' ') 9560 { 9561 *s = '\0'; 9562 mips16_ext = TRUE; 9563 s += 3; 9564 break; 9565 } 9566 /* Fall through. */ 9567 default: 9568 insn_error = _("unknown opcode"); 9569 return; 9570 } 9571 9572 if (mips_opts.noautoextend && ! mips16_ext) 9573 mips16_small = TRUE; 9574 9575 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) 9576 { 9577 insn_error = _("unrecognized opcode"); 9578 return; 9579 } 9580 9581 argsstart = s; 9582 for (;;) 9583 { 9584 assert (strcmp (insn->name, str) == 0); 9585 9586 ip->insn_mo = insn; 9587 ip->insn_opcode = insn->match; 9588 ip->use_extend = FALSE; 9589 imm_expr.X_op = O_absent; 9590 imm_reloc[0] = BFD_RELOC_UNUSED; 9591 imm_reloc[1] = BFD_RELOC_UNUSED; 9592 imm_reloc[2] = BFD_RELOC_UNUSED; 9593 imm2_expr.X_op = O_absent; 9594 offset_expr.X_op = O_absent; 9595 offset_reloc[0] = BFD_RELOC_UNUSED; 9596 offset_reloc[1] = BFD_RELOC_UNUSED; 9597 offset_reloc[2] = BFD_RELOC_UNUSED; 9598 for (args = insn->args; 1; ++args) 9599 { 9600 int c; 9601 9602 if (*s == ' ') 9603 ++s; 9604 9605 /* In this switch statement we call break if we did not find 9606 a match, continue if we did find a match, or return if we 9607 are done. */ 9608 9609 c = *args; 9610 switch (c) 9611 { 9612 case '\0': 9613 if (*s == '\0') 9614 { 9615 /* Stuff the immediate value in now, if we can. */ 9616 if (imm_expr.X_op == O_constant 9617 && *imm_reloc > BFD_RELOC_UNUSED 9618 && insn->pinfo != INSN_MACRO) 9619 { 9620 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, 9621 imm_expr.X_add_number, TRUE, mips16_small, 9622 mips16_ext, &ip->insn_opcode, 9623 &ip->use_extend, &ip->extend); 9624 imm_expr.X_op = O_absent; 9625 *imm_reloc = BFD_RELOC_UNUSED; 9626 } 9627 9628 return; 9629 } 9630 break; 9631 9632 case ',': 9633 if (*s++ == c) 9634 continue; 9635 s--; 9636 switch (*++args) 9637 { 9638 case 'v': 9639 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; 9640 continue; 9641 case 'w': 9642 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; 9643 continue; 9644 } 9645 break; 9646 9647 case '(': 9648 case ')': 9649 if (*s++ == c) 9650 continue; 9651 break; 9652 9653 case 'v': 9654 case 'w': 9655 if (s[0] != '$') 9656 { 9657 if (c == 'v') 9658 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; 9659 else 9660 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; 9661 ++args; 9662 continue; 9663 } 9664 /* Fall through. */ 9665 case 'x': 9666 case 'y': 9667 case 'z': 9668 case 'Z': 9669 case '0': 9670 case 'S': 9671 case 'R': 9672 case 'X': 9673 case 'Y': 9674 s_reset = s; 9675 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) 9676 { 9677 if (c == 'v' || c == 'w') 9678 { 9679 if (c == 'v') 9680 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; 9681 else 9682 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; 9683 ++args; 9684 continue; 9685 } 9686 break; 9687 } 9688 9689 if (*s == ' ') 9690 ++s; 9691 if (args[1] != *s) 9692 { 9693 if (c == 'v' || c == 'w') 9694 { 9695 regno = mips16_to_32_reg_map[lastregno]; 9696 s = s_reset; 9697 ++args; 9698 } 9699 } 9700 9701 switch (c) 9702 { 9703 case 'x': 9704 case 'y': 9705 case 'z': 9706 case 'v': 9707 case 'w': 9708 case 'Z': 9709 regno = mips32_to_16_reg_map[regno]; 9710 break; 9711 9712 case '0': 9713 if (regno != 0) 9714 regno = ILLEGAL_REG; 9715 break; 9716 9717 case 'S': 9718 if (regno != SP) 9719 regno = ILLEGAL_REG; 9720 break; 9721 9722 case 'R': 9723 if (regno != RA) 9724 regno = ILLEGAL_REG; 9725 break; 9726 9727 case 'X': 9728 case 'Y': 9729 if (regno == AT && ! mips_opts.noat) 9730 as_warn (_("used $at without \".set noat\"")); 9731 break; 9732 9733 default: 9734 internalError (); 9735 } 9736 9737 if (regno == ILLEGAL_REG) 9738 break; 9739 9740 switch (c) 9741 { 9742 case 'x': 9743 case 'v': 9744 ip->insn_opcode |= regno << MIPS16OP_SH_RX; 9745 break; 9746 case 'y': 9747 case 'w': 9748 ip->insn_opcode |= regno << MIPS16OP_SH_RY; 9749 break; 9750 case 'z': 9751 ip->insn_opcode |= regno << MIPS16OP_SH_RZ; 9752 break; 9753 case 'Z': 9754 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; 9755 case '0': 9756 case 'S': 9757 case 'R': 9758 break; 9759 case 'X': 9760 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; 9761 break; 9762 case 'Y': 9763 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); 9764 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; 9765 break; 9766 default: 9767 internalError (); 9768 } 9769 9770 lastregno = regno; 9771 continue; 9772 9773 case 'P': 9774 if (strncmp (s, "$pc", 3) == 0) 9775 { 9776 s += 3; 9777 continue; 9778 } 9779 break; 9780 9781 case '<': 9782 case '>': 9783 case '[': 9784 case ']': 9785 case '4': 9786 case '5': 9787 case 'H': 9788 case 'W': 9789 case 'D': 9790 case 'j': 9791 case '8': 9792 case 'V': 9793 case 'C': 9794 case 'U': 9795 case 'k': 9796 case 'K': 9797 if (s[0] == '%' 9798 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) 9799 { 9800 /* This is %gprel(SYMBOL). We need to read SYMBOL, 9801 and generate the appropriate reloc. If the text 9802 inside %gprel is not a symbol name with an 9803 optional offset, then we generate a normal reloc 9804 and will probably fail later. */ 9805 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); 9806 if (imm_expr.X_op == O_symbol) 9807 { 9808 mips16_ext = TRUE; 9809 *imm_reloc = BFD_RELOC_MIPS16_GPREL; 9810 s = expr_end; 9811 ip->use_extend = TRUE; 9812 ip->extend = 0; 9813 continue; 9814 } 9815 } 9816 else 9817 { 9818 /* Just pick up a normal expression. */ 9819 my_getExpression (&imm_expr, s); 9820 } 9821 9822 if (imm_expr.X_op == O_register) 9823 { 9824 /* What we thought was an expression turned out to 9825 be a register. */ 9826 9827 if (s[0] == '(' && args[1] == '(') 9828 { 9829 /* It looks like the expression was omitted 9830 before a register indirection, which means 9831 that the expression is implicitly zero. We 9832 still set up imm_expr, so that we handle 9833 explicit extensions correctly. */ 9834 imm_expr.X_op = O_constant; 9835 imm_expr.X_add_number = 0; 9836 *imm_reloc = (int) BFD_RELOC_UNUSED + c; 9837 continue; 9838 } 9839 9840 break; 9841 } 9842 9843 /* We need to relax this instruction. */ 9844 *imm_reloc = (int) BFD_RELOC_UNUSED + c; 9845 s = expr_end; 9846 continue; 9847 9848 case 'p': 9849 case 'q': 9850 case 'A': 9851 case 'B': 9852 case 'E': 9853 /* We use offset_reloc rather than imm_reloc for the PC 9854 relative operands. This lets macros with both 9855 immediate and address operands work correctly. */ 9856 my_getExpression (&offset_expr, s); 9857 9858 if (offset_expr.X_op == O_register) 9859 break; 9860 9861 /* We need to relax this instruction. */ 9862 *offset_reloc = (int) BFD_RELOC_UNUSED + c; 9863 s = expr_end; 9864 continue; 9865 9866 case '6': /* break code */ 9867 my_getExpression (&imm_expr, s); 9868 check_absolute_expr (ip, &imm_expr); 9869 if ((unsigned long) imm_expr.X_add_number > 63) 9870 { 9871 as_warn (_("Invalid value for `%s' (%lu)"), 9872 ip->insn_mo->name, 9873 (unsigned long) imm_expr.X_add_number); 9874 imm_expr.X_add_number &= 0x3f; 9875 } 9876 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; 9877 imm_expr.X_op = O_absent; 9878 s = expr_end; 9879 continue; 9880 9881 case 'a': /* 26 bit address */ 9882 my_getExpression (&offset_expr, s); 9883 s = expr_end; 9884 *offset_reloc = BFD_RELOC_MIPS16_JMP; 9885 ip->insn_opcode <<= 16; 9886 continue; 9887 9888 case 'l': /* register list for entry macro */ 9889 case 'L': /* register list for exit macro */ 9890 { 9891 int mask; 9892 9893 if (c == 'l') 9894 mask = 0; 9895 else 9896 mask = 7 << 3; 9897 while (*s != '\0') 9898 { 9899 unsigned int freg, reg1, reg2; 9900 9901 while (*s == ' ' || *s == ',') 9902 ++s; 9903 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) 9904 freg = 0; 9905 else if (reg_lookup (&s, RTYPE_FPU, ®1)) 9906 freg = 1; 9907 else 9908 { 9909 as_bad (_("can't parse register list")); 9910 break; 9911 } 9912 if (*s == ' ') 9913 ++s; 9914 if (*s != '-') 9915 reg2 = reg1; 9916 else 9917 { 9918 ++s; 9919 if (!reg_lookup (&s, freg ? RTYPE_FPU 9920 : (RTYPE_GP | RTYPE_NUM), ®2)) 9921 { 9922 as_bad (_("invalid register list")); 9923 break; 9924 } 9925 } 9926 if (freg && reg1 == 0 && reg2 == 0 && c == 'L') 9927 { 9928 mask &= ~ (7 << 3); 9929 mask |= 5 << 3; 9930 } 9931 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') 9932 { 9933 mask &= ~ (7 << 3); 9934 mask |= 6 << 3; 9935 } 9936 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') 9937 mask |= (reg2 - 3) << 3; 9938 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) 9939 mask |= (reg2 - 15) << 1; 9940 else if (reg1 == RA && reg2 == RA) 9941 mask |= 1; 9942 else 9943 { 9944 as_bad (_("invalid register list")); 9945 break; 9946 } 9947 } 9948 /* The mask is filled in in the opcode table for the 9949 benefit of the disassembler. We remove it before 9950 applying the actual mask. */ 9951 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); 9952 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; 9953 } 9954 continue; 9955 9956 case 'e': /* extend code */ 9957 my_getExpression (&imm_expr, s); 9958 check_absolute_expr (ip, &imm_expr); 9959 if ((unsigned long) imm_expr.X_add_number > 0x7ff) 9960 { 9961 as_warn (_("Invalid value for `%s' (%lu)"), 9962 ip->insn_mo->name, 9963 (unsigned long) imm_expr.X_add_number); 9964 imm_expr.X_add_number &= 0x7ff; 9965 } 9966 ip->insn_opcode |= imm_expr.X_add_number; 9967 imm_expr.X_op = O_absent; 9968 s = expr_end; 9969 continue; 9970 9971 default: 9972 internalError (); 9973 } 9974 break; 9975 } 9976 9977 /* Args don't match. */ 9978 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && 9979 strcmp (insn->name, insn[1].name) == 0) 9980 { 9981 ++insn; 9982 s = argsstart; 9983 continue; 9984 } 9985 9986 insn_error = _("illegal operands"); 9987 9988 return; 9989 } 9990 } 9991 9992 /* This structure holds information we know about a mips16 immediate 9993 argument type. */ 9994 9995 struct mips16_immed_operand 9996 { 9997 /* The type code used in the argument string in the opcode table. */ 9998 int type; 9999 /* The number of bits in the short form of the opcode. */ 10000 int nbits; 10001 /* The number of bits in the extended form of the opcode. */ 10002 int extbits; 10003 /* The amount by which the short form is shifted when it is used; 10004 for example, the sw instruction has a shift count of 2. */ 10005 int shift; 10006 /* The amount by which the short form is shifted when it is stored 10007 into the instruction code. */ 10008 int op_shift; 10009 /* Non-zero if the short form is unsigned. */ 10010 int unsp; 10011 /* Non-zero if the extended form is unsigned. */ 10012 int extu; 10013 /* Non-zero if the value is PC relative. */ 10014 int pcrel; 10015 }; 10016 10017 /* The mips16 immediate operand types. */ 10018 10019 static const struct mips16_immed_operand mips16_immed_operands[] = 10020 { 10021 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, 10022 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, 10023 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, 10024 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, 10025 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, 10026 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, 10027 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, 10028 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, 10029 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, 10030 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, 10031 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, 10032 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, 10033 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, 10034 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, 10035 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, 10036 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, 10037 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, 10038 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, 10039 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, 10040 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, 10041 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } 10042 }; 10043 10044 #define MIPS16_NUM_IMMED \ 10045 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) 10046 10047 /* Handle a mips16 instruction with an immediate value. This or's the 10048 small immediate value into *INSN. It sets *USE_EXTEND to indicate 10049 whether an extended value is needed; if one is needed, it sets 10050 *EXTEND to the value. The argument type is TYPE. The value is VAL. 10051 If SMALL is true, an unextended opcode was explicitly requested. 10052 If EXT is true, an extended opcode was explicitly requested. If 10053 WARN is true, warn if EXT does not match reality. */ 10054 10055 static void 10056 mips16_immed (char *file, unsigned int line, int type, offsetT val, 10057 bfd_boolean warn, bfd_boolean small, bfd_boolean ext, 10058 unsigned long *insn, bfd_boolean *use_extend, 10059 unsigned short *extend) 10060 { 10061 register const struct mips16_immed_operand *op; 10062 int mintiny, maxtiny; 10063 bfd_boolean needext; 10064 10065 op = mips16_immed_operands; 10066 while (op->type != type) 10067 { 10068 ++op; 10069 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); 10070 } 10071 10072 if (op->unsp) 10073 { 10074 if (type == '<' || type == '>' || type == '[' || type == ']') 10075 { 10076 mintiny = 1; 10077 maxtiny = 1 << op->nbits; 10078 } 10079 else 10080 { 10081 mintiny = 0; 10082 maxtiny = (1 << op->nbits) - 1; 10083 } 10084 } 10085 else 10086 { 10087 mintiny = - (1 << (op->nbits - 1)); 10088 maxtiny = (1 << (op->nbits - 1)) - 1; 10089 } 10090 10091 /* Branch offsets have an implicit 0 in the lowest bit. */ 10092 if (type == 'p' || type == 'q') 10093 val /= 2; 10094 10095 if ((val & ((1 << op->shift) - 1)) != 0 10096 || val < (mintiny << op->shift) 10097 || val > (maxtiny << op->shift)) 10098 needext = TRUE; 10099 else 10100 needext = FALSE; 10101 10102 if (warn && ext && ! needext) 10103 as_warn_where (file, line, 10104 _("extended operand requested but not required")); 10105 if (small && needext) 10106 as_bad_where (file, line, _("invalid unextended operand value")); 10107 10108 if (small || (! ext && ! needext)) 10109 { 10110 int insnval; 10111 10112 *use_extend = FALSE; 10113 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); 10114 insnval <<= op->op_shift; 10115 *insn |= insnval; 10116 } 10117 else 10118 { 10119 long minext, maxext; 10120 int extval; 10121 10122 if (op->extu) 10123 { 10124 minext = 0; 10125 maxext = (1 << op->extbits) - 1; 10126 } 10127 else 10128 { 10129 minext = - (1 << (op->extbits - 1)); 10130 maxext = (1 << (op->extbits - 1)) - 1; 10131 } 10132 if (val < minext || val > maxext) 10133 as_bad_where (file, line, 10134 _("operand value out of range for instruction")); 10135 10136 *use_extend = TRUE; 10137 if (op->extbits == 16) 10138 { 10139 extval = ((val >> 11) & 0x1f) | (val & 0x7e0); 10140 val &= 0x1f; 10141 } 10142 else if (op->extbits == 15) 10143 { 10144 extval = ((val >> 11) & 0xf) | (val & 0x7f0); 10145 val &= 0xf; 10146 } 10147 else 10148 { 10149 extval = ((val & 0x1f) << 6) | (val & 0x20); 10150 val = 0; 10151 } 10152 10153 *extend = (unsigned short) extval; 10154 *insn |= val; 10155 } 10156 } 10157 10158 static const struct percent_op_match 10159 { 10160 const char *str; 10161 bfd_reloc_code_real_type reloc; 10162 } percent_op[] = 10163 { 10164 {"%lo", BFD_RELOC_LO16}, 10165 #ifdef OBJ_ELF 10166 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, 10167 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, 10168 {"%call16", BFD_RELOC_MIPS_CALL16}, 10169 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, 10170 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, 10171 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, 10172 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, 10173 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, 10174 {"%got", BFD_RELOC_MIPS_GOT16}, 10175 {"%gp_rel", BFD_RELOC_GPREL16}, 10176 {"%half", BFD_RELOC_16}, 10177 {"%highest", BFD_RELOC_MIPS_HIGHEST}, 10178 {"%higher", BFD_RELOC_MIPS_HIGHER}, 10179 {"%neg", BFD_RELOC_MIPS_SUB}, 10180 #endif 10181 {"%hi", BFD_RELOC_HI16_S} 10182 }; 10183 10184 10185 /* Return true if *STR points to a relocation operator. When returning true, 10186 move *STR over the operator and store its relocation code in *RELOC. 10187 Leave both *STR and *RELOC alone when returning false. */ 10188 10189 static bfd_boolean 10190 parse_relocation (char **str, bfd_reloc_code_real_type *reloc) 10191 { 10192 size_t i; 10193 10194 for (i = 0; i < ARRAY_SIZE (percent_op); i++) 10195 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) 10196 { 10197 *str += strlen (percent_op[i].str); 10198 *reloc = percent_op[i].reloc; 10199 10200 /* Check whether the output BFD supports this relocation. 10201 If not, issue an error and fall back on something safe. */ 10202 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) 10203 { 10204 as_bad ("relocation %s isn't supported by the current ABI", 10205 percent_op[i].str); 10206 *reloc = BFD_RELOC_LO16; 10207 } 10208 return TRUE; 10209 } 10210 return FALSE; 10211 } 10212 10213 10214 /* Parse string STR as a 16-bit relocatable operand. Store the 10215 expression in *EP and the relocations in the array starting 10216 at RELOC. Return the number of relocation operators used. 10217 10218 On exit, EXPR_END points to the first character after the expression. 10219 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ 10220 10221 static size_t 10222 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 10223 char *str) 10224 { 10225 bfd_reloc_code_real_type reversed_reloc[3]; 10226 size_t reloc_index, i; 10227 int crux_depth, str_depth; 10228 char *crux; 10229 10230 /* Search for the start of the main expression, recoding relocations 10231 in REVERSED_RELOC. End the loop with CRUX pointing to the start 10232 of the main expression and with CRUX_DEPTH containing the number 10233 of open brackets at that point. */ 10234 reloc_index = -1; 10235 str_depth = 0; 10236 do 10237 { 10238 reloc_index++; 10239 crux = str; 10240 crux_depth = str_depth; 10241 10242 /* Skip over whitespace and brackets, keeping count of the number 10243 of brackets. */ 10244 while (*str == ' ' || *str == '\t' || *str == '(') 10245 if (*str++ == '(') 10246 str_depth++; 10247 } 10248 while (*str == '%' 10249 && reloc_index < (HAVE_NEWABI ? 3 : 1) 10250 && parse_relocation (&str, &reversed_reloc[reloc_index])); 10251 10252 my_getExpression (ep, crux); 10253 str = expr_end; 10254 10255 /* Match every open bracket. */ 10256 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) 10257 if (*str++ == ')') 10258 crux_depth--; 10259 10260 if (crux_depth > 0) 10261 as_bad ("unclosed '('"); 10262 10263 expr_end = str; 10264 10265 if (reloc_index == 0) 10266 reloc[0] = BFD_RELOC_LO16; 10267 else 10268 { 10269 prev_reloc_op_frag = frag_now; 10270 for (i = 0; i < reloc_index; i++) 10271 reloc[i] = reversed_reloc[reloc_index - 1 - i]; 10272 } 10273 10274 return reloc_index; 10275 } 10276 10277 static void 10278 my_getExpression (expressionS *ep, char *str) 10279 { 10280 char *save_in; 10281 valueT val; 10282 10283 save_in = input_line_pointer; 10284 input_line_pointer = str; 10285 expression (ep); 10286 expr_end = input_line_pointer; 10287 input_line_pointer = save_in; 10288 10289 /* If we are in mips16 mode, and this is an expression based on `.', 10290 then we bump the value of the symbol by 1 since that is how other 10291 text symbols are handled. We don't bother to handle complex 10292 expressions, just `.' plus or minus a constant. */ 10293 if (mips_opts.mips16 10294 && ep->X_op == O_symbol 10295 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 10296 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg 10297 && symbol_get_frag (ep->X_add_symbol) == frag_now 10298 && symbol_constant_p (ep->X_add_symbol) 10299 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) 10300 S_SET_VALUE (ep->X_add_symbol, val + 1); 10301 } 10302 10303 /* Turn a string in input_line_pointer into a floating point constant 10304 of type TYPE, and store the appropriate bytes in *LITP. The number 10305 of LITTLENUMS emitted is stored in *SIZEP. An error message is 10306 returned, or NULL on OK. */ 10307 10308 char * 10309 md_atof (int type, char *litP, int *sizeP) 10310 { 10311 int prec; 10312 LITTLENUM_TYPE words[4]; 10313 char *t; 10314 int i; 10315 10316 switch (type) 10317 { 10318 case 'f': 10319 prec = 2; 10320 break; 10321 10322 case 'd': 10323 prec = 4; 10324 break; 10325 10326 default: 10327 *sizeP = 0; 10328 return _("bad call to md_atof"); 10329 } 10330 10331 t = atof_ieee (input_line_pointer, type, words); 10332 if (t) 10333 input_line_pointer = t; 10334 10335 *sizeP = prec * 2; 10336 10337 if (! target_big_endian) 10338 { 10339 for (i = prec - 1; i >= 0; i--) 10340 { 10341 md_number_to_chars (litP, words[i], 2); 10342 litP += 2; 10343 } 10344 } 10345 else 10346 { 10347 for (i = 0; i < prec; i++) 10348 { 10349 md_number_to_chars (litP, words[i], 2); 10350 litP += 2; 10351 } 10352 } 10353 10354 return NULL; 10355 } 10356 10357 void 10358 md_number_to_chars (char *buf, valueT val, int n) 10359 { 10360 if (target_big_endian) 10361 number_to_chars_bigendian (buf, val, n); 10362 else 10363 number_to_chars_littleendian (buf, val, n); 10364 } 10365 10366 #ifdef OBJ_ELF 10367 static int support_64bit_objects(void) 10368 { 10369 const char **list, **l; 10370 int yes; 10371 10372 list = bfd_target_list (); 10373 for (l = list; *l != NULL; l++) 10374 #ifdef TE_TMIPS 10375 /* This is traditional mips */ 10376 if (strcmp (*l, "elf64-tradbigmips") == 0 10377 || strcmp (*l, "elf64-tradlittlemips") == 0) 10378 #else 10379 if (strcmp (*l, "elf64-bigmips") == 0 10380 || strcmp (*l, "elf64-littlemips") == 0) 10381 #endif 10382 break; 10383 yes = (*l != NULL); 10384 free (list); 10385 return yes; 10386 } 10387 #endif /* OBJ_ELF */ 10388 10389 const char *md_shortopts = "O::g::G:"; 10390 10391 struct option md_longopts[] = 10392 { 10393 /* Options which specify architecture. */ 10394 #define OPTION_ARCH_BASE (OPTION_MD_BASE) 10395 #define OPTION_MARCH (OPTION_ARCH_BASE + 0) 10396 {"march", required_argument, NULL, OPTION_MARCH}, 10397 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) 10398 {"mtune", required_argument, NULL, OPTION_MTUNE}, 10399 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) 10400 {"mips0", no_argument, NULL, OPTION_MIPS1}, 10401 {"mips1", no_argument, NULL, OPTION_MIPS1}, 10402 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) 10403 {"mips2", no_argument, NULL, OPTION_MIPS2}, 10404 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) 10405 {"mips3", no_argument, NULL, OPTION_MIPS3}, 10406 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) 10407 {"mips4", no_argument, NULL, OPTION_MIPS4}, 10408 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) 10409 {"mips5", no_argument, NULL, OPTION_MIPS5}, 10410 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) 10411 {"mips32", no_argument, NULL, OPTION_MIPS32}, 10412 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) 10413 {"mips64", no_argument, NULL, OPTION_MIPS64}, 10414 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) 10415 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, 10416 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) 10417 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, 10418 10419 /* Options which specify Application Specific Extensions (ASEs). */ 10420 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) 10421 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) 10422 {"mips16", no_argument, NULL, OPTION_MIPS16}, 10423 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) 10424 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, 10425 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) 10426 {"mips3d", no_argument, NULL, OPTION_MIPS3D}, 10427 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) 10428 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, 10429 #define OPTION_MDMX (OPTION_ASE_BASE + 4) 10430 {"mdmx", no_argument, NULL, OPTION_MDMX}, 10431 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) 10432 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, 10433 10434 /* Old-style architecture options. Don't add more of these. */ 10435 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) 10436 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) 10437 {"m4650", no_argument, NULL, OPTION_M4650}, 10438 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) 10439 {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, 10440 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) 10441 {"m4010", no_argument, NULL, OPTION_M4010}, 10442 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) 10443 {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, 10444 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) 10445 {"m4100", no_argument, NULL, OPTION_M4100}, 10446 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) 10447 {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, 10448 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) 10449 {"m3900", no_argument, NULL, OPTION_M3900}, 10450 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) 10451 {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, 10452 10453 /* Options which enable bug fixes. */ 10454 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) 10455 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) 10456 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, 10457 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) 10458 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 10459 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 10460 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) 10461 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) 10462 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, 10463 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, 10464 #define OPTION_FIX_LOONGSON2F_BTB (OPTION_FIX_BASE + 4) 10465 #define OPTION_NO_FIX_LOONGSON2F_BTB (OPTION_FIX_BASE + 5) 10466 {"mfix-loongson2f-btb", no_argument, NULL, OPTION_FIX_LOONGSON2F_BTB}, 10467 {"mno-fix-loongson2f-btb", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_BTB}, 10468 10469 /* Miscellaneous options. */ 10470 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) 10471 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0) 10472 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, 10473 #define OPTION_TRAP (OPTION_MISC_BASE + 1) 10474 {"trap", no_argument, NULL, OPTION_TRAP}, 10475 {"no-break", no_argument, NULL, OPTION_TRAP}, 10476 #define OPTION_BREAK (OPTION_MISC_BASE + 2) 10477 {"break", no_argument, NULL, OPTION_BREAK}, 10478 {"no-trap", no_argument, NULL, OPTION_BREAK}, 10479 #define OPTION_EB (OPTION_MISC_BASE + 3) 10480 {"EB", no_argument, NULL, OPTION_EB}, 10481 #define OPTION_EL (OPTION_MISC_BASE + 4) 10482 {"EL", no_argument, NULL, OPTION_EL}, 10483 #define OPTION_FP32 (OPTION_MISC_BASE + 5) 10484 {"mfp32", no_argument, NULL, OPTION_FP32}, 10485 #define OPTION_GP32 (OPTION_MISC_BASE + 6) 10486 {"mgp32", no_argument, NULL, OPTION_GP32}, 10487 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) 10488 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, 10489 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8) 10490 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, 10491 #define OPTION_FP64 (OPTION_MISC_BASE + 9) 10492 {"mfp64", no_argument, NULL, OPTION_FP64}, 10493 #define OPTION_GP64 (OPTION_MISC_BASE + 10) 10494 {"mgp64", no_argument, NULL, OPTION_GP64}, 10495 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11) 10496 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12) 10497 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, 10498 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, 10499 10500 /* ELF-specific options. */ 10501 #ifdef OBJ_ELF 10502 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13) 10503 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) 10504 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, 10505 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, 10506 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) 10507 {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, 10508 #define OPTION_XGOT (OPTION_ELF_BASE + 2) 10509 {"xgot", no_argument, NULL, OPTION_XGOT}, 10510 #define OPTION_MABI (OPTION_ELF_BASE + 3) 10511 {"mabi", required_argument, NULL, OPTION_MABI}, 10512 #define OPTION_32 (OPTION_ELF_BASE + 4) 10513 {"32", no_argument, NULL, OPTION_32}, 10514 #define OPTION_N32 (OPTION_ELF_BASE + 5) 10515 {"n32", no_argument, NULL, OPTION_N32}, 10516 #define OPTION_64 (OPTION_ELF_BASE + 6) 10517 {"64", no_argument, NULL, OPTION_64}, 10518 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) 10519 {"mdebug", no_argument, NULL, OPTION_MDEBUG}, 10520 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) 10521 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, 10522 #define OPTION_PDR (OPTION_ELF_BASE + 9) 10523 {"mpdr", no_argument, NULL, OPTION_PDR}, 10524 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) 10525 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, 10526 #endif /* OBJ_ELF */ 10527 10528 {NULL, no_argument, NULL, 0} 10529 }; 10530 size_t md_longopts_size = sizeof (md_longopts); 10531 10532 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to 10533 NEW_VALUE. Warn if another value was already specified. Note: 10534 we have to defer parsing the -march and -mtune arguments in order 10535 to handle 'from-abi' correctly, since the ABI might be specified 10536 in a later argument. */ 10537 10538 static void 10539 mips_set_option_string (const char **string_ptr, const char *new_value) 10540 { 10541 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) 10542 as_warn (_("A different %s was already specified, is now %s"), 10543 string_ptr == &mips_arch_string ? "-march" : "-mtune", 10544 new_value); 10545 10546 *string_ptr = new_value; 10547 } 10548 10549 int 10550 md_parse_option (int c, char *arg) 10551 { 10552 switch (c) 10553 { 10554 case OPTION_CONSTRUCT_FLOATS: 10555 mips_disable_float_construction = 0; 10556 break; 10557 10558 case OPTION_NO_CONSTRUCT_FLOATS: 10559 mips_disable_float_construction = 1; 10560 break; 10561 10562 case OPTION_TRAP: 10563 mips_trap = 1; 10564 break; 10565 10566 case OPTION_BREAK: 10567 mips_trap = 0; 10568 break; 10569 10570 case OPTION_EB: 10571 target_big_endian = 1; 10572 break; 10573 10574 case OPTION_EL: 10575 target_big_endian = 0; 10576 break; 10577 10578 case 'O': 10579 if (arg && arg[1] == '0') 10580 mips_optimize = 1; 10581 else 10582 mips_optimize = 2; 10583 break; 10584 10585 case 'g': 10586 if (arg == NULL) 10587 mips_debug = 2; 10588 else 10589 mips_debug = atoi (arg); 10590 /* When the MIPS assembler sees -g or -g2, it does not do 10591 optimizations which limit full symbolic debugging. We take 10592 that to be equivalent to -O0. */ 10593 if (mips_debug == 2) 10594 mips_optimize = 1; 10595 break; 10596 10597 case OPTION_MIPS1: 10598 file_mips_isa = ISA_MIPS1; 10599 break; 10600 10601 case OPTION_MIPS2: 10602 file_mips_isa = ISA_MIPS2; 10603 break; 10604 10605 case OPTION_MIPS3: 10606 file_mips_isa = ISA_MIPS3; 10607 break; 10608 10609 case OPTION_MIPS4: 10610 file_mips_isa = ISA_MIPS4; 10611 break; 10612 10613 case OPTION_MIPS5: 10614 file_mips_isa = ISA_MIPS5; 10615 break; 10616 10617 case OPTION_MIPS32: 10618 file_mips_isa = ISA_MIPS32; 10619 break; 10620 10621 case OPTION_MIPS32R2: 10622 file_mips_isa = ISA_MIPS32R2; 10623 break; 10624 10625 case OPTION_MIPS64R2: 10626 file_mips_isa = ISA_MIPS64R2; 10627 break; 10628 10629 case OPTION_MIPS64: 10630 file_mips_isa = ISA_MIPS64; 10631 break; 10632 10633 case OPTION_MTUNE: 10634 mips_set_option_string (&mips_tune_string, arg); 10635 break; 10636 10637 case OPTION_MARCH: 10638 mips_set_option_string (&mips_arch_string, arg); 10639 break; 10640 10641 case OPTION_M4650: 10642 mips_set_option_string (&mips_arch_string, "4650"); 10643 mips_set_option_string (&mips_tune_string, "4650"); 10644 break; 10645 10646 case OPTION_NO_M4650: 10647 break; 10648 10649 case OPTION_M4010: 10650 mips_set_option_string (&mips_arch_string, "4010"); 10651 mips_set_option_string (&mips_tune_string, "4010"); 10652 break; 10653 10654 case OPTION_NO_M4010: 10655 break; 10656 10657 case OPTION_M4100: 10658 mips_set_option_string (&mips_arch_string, "4100"); 10659 mips_set_option_string (&mips_tune_string, "4100"); 10660 break; 10661 10662 case OPTION_NO_M4100: 10663 break; 10664 10665 case OPTION_M3900: 10666 mips_set_option_string (&mips_arch_string, "3900"); 10667 mips_set_option_string (&mips_tune_string, "3900"); 10668 break; 10669 10670 case OPTION_NO_M3900: 10671 break; 10672 10673 case OPTION_MDMX: 10674 mips_opts.ase_mdmx = 1; 10675 break; 10676 10677 case OPTION_NO_MDMX: 10678 mips_opts.ase_mdmx = 0; 10679 break; 10680 10681 case OPTION_MIPS16: 10682 mips_opts.mips16 = 1; 10683 mips_no_prev_insn (FALSE); 10684 break; 10685 10686 case OPTION_NO_MIPS16: 10687 mips_opts.mips16 = 0; 10688 mips_no_prev_insn (FALSE); 10689 break; 10690 10691 case OPTION_MIPS3D: 10692 mips_opts.ase_mips3d = 1; 10693 break; 10694 10695 case OPTION_NO_MIPS3D: 10696 mips_opts.ase_mips3d = 0; 10697 break; 10698 10699 case OPTION_MEMBEDDED_PIC: 10700 mips_pic = EMBEDDED_PIC; 10701 if (USE_GLOBAL_POINTER_OPT && g_switch_seen) 10702 { 10703 as_bad (_("-G may not be used with embedded PIC code")); 10704 return 0; 10705 } 10706 g_switch_value = 0x7fffffff; 10707 break; 10708 10709 case OPTION_FIX_VR4120: 10710 mips_fix_vr4120 = 1; 10711 break; 10712 10713 case OPTION_NO_FIX_VR4120: 10714 mips_fix_vr4120 = 0; 10715 break; 10716 10717 case OPTION_FIX_LOONGSON2F_BTB: 10718 mips_fix_loongson2f_btb = 1; 10719 break; 10720 10721 case OPTION_NO_FIX_LOONGSON2F_BTB: 10722 mips_fix_loongson2f_btb = 0; 10723 break; 10724 10725 case OPTION_RELAX_BRANCH: 10726 mips_relax_branch = 1; 10727 break; 10728 10729 case OPTION_NO_RELAX_BRANCH: 10730 mips_relax_branch = 0; 10731 break; 10732 10733 #ifdef OBJ_ELF 10734 /* When generating ELF code, we permit -KPIC and -call_shared to 10735 select SVR4_PIC, and -non_shared to select no PIC. This is 10736 intended to be compatible with Irix 5. */ 10737 case OPTION_CALL_SHARED: 10738 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10739 { 10740 as_bad (_("-call_shared is supported only for ELF format")); 10741 return 0; 10742 } 10743 mips_pic = SVR4_PIC; 10744 mips_abicalls = TRUE; 10745 if (g_switch_seen && g_switch_value != 0) 10746 { 10747 as_bad (_("-G may not be used with SVR4 PIC code")); 10748 return 0; 10749 } 10750 g_switch_value = 0; 10751 break; 10752 10753 case OPTION_NON_SHARED: 10754 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10755 { 10756 as_bad (_("-non_shared is supported only for ELF format")); 10757 return 0; 10758 } 10759 mips_pic = NO_PIC; 10760 mips_abicalls = FALSE; 10761 break; 10762 10763 /* The -xgot option tells the assembler to use 32 offsets when 10764 accessing the got in SVR4_PIC mode. It is for Irix 10765 compatibility. */ 10766 case OPTION_XGOT: 10767 mips_big_got = 1; 10768 break; 10769 #endif /* OBJ_ELF */ 10770 10771 case 'G': 10772 if (! USE_GLOBAL_POINTER_OPT) 10773 { 10774 as_bad (_("-G is not supported for this configuration")); 10775 return 0; 10776 } 10777 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) 10778 { 10779 as_bad (_("-G may not be used with SVR4 or embedded PIC code")); 10780 return 0; 10781 } 10782 else 10783 g_switch_value = atoi (arg); 10784 g_switch_seen = 1; 10785 break; 10786 10787 #ifdef OBJ_ELF 10788 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 10789 and -mabi=64. */ 10790 case OPTION_32: 10791 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10792 { 10793 as_bad (_("-32 is supported for ELF format only")); 10794 return 0; 10795 } 10796 mips_abi = O32_ABI; 10797 break; 10798 10799 case OPTION_N32: 10800 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10801 { 10802 as_bad (_("-n32 is supported for ELF format only")); 10803 return 0; 10804 } 10805 mips_abi = N32_ABI; 10806 break; 10807 10808 case OPTION_64: 10809 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10810 { 10811 as_bad (_("-64 is supported for ELF format only")); 10812 return 0; 10813 } 10814 mips_abi = N64_ABI; 10815 if (! support_64bit_objects()) 10816 as_fatal (_("No compiled in support for 64 bit object file format")); 10817 break; 10818 #endif /* OBJ_ELF */ 10819 10820 case OPTION_GP32: 10821 file_mips_gp32 = 1; 10822 break; 10823 10824 case OPTION_GP64: 10825 file_mips_gp32 = 0; 10826 break; 10827 10828 case OPTION_FP32: 10829 file_mips_fp32 = 1; 10830 break; 10831 10832 case OPTION_FP64: 10833 file_mips_fp32 = 0; 10834 break; 10835 10836 #ifdef OBJ_ELF 10837 case OPTION_MABI: 10838 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10839 { 10840 as_bad (_("-mabi is supported for ELF format only")); 10841 return 0; 10842 } 10843 if (strcmp (arg, "32") == 0) 10844 mips_abi = O32_ABI; 10845 else if (strcmp (arg, "o64") == 0) 10846 mips_abi = O64_ABI; 10847 else if (strcmp (arg, "n32") == 0) 10848 mips_abi = N32_ABI; 10849 else if (strcmp (arg, "64") == 0) 10850 { 10851 mips_abi = N64_ABI; 10852 if (! support_64bit_objects()) 10853 as_fatal (_("No compiled in support for 64 bit object file " 10854 "format")); 10855 } 10856 else if (strcmp (arg, "eabi") == 0) 10857 mips_abi = EABI_ABI; 10858 else 10859 { 10860 as_fatal (_("invalid abi -mabi=%s"), arg); 10861 return 0; 10862 } 10863 break; 10864 #endif /* OBJ_ELF */ 10865 10866 case OPTION_M7000_HILO_FIX: 10867 mips_7000_hilo_fix = TRUE; 10868 break; 10869 10870 case OPTION_MNO_7000_HILO_FIX: 10871 mips_7000_hilo_fix = FALSE; 10872 break; 10873 10874 #ifdef OBJ_ELF 10875 case OPTION_MDEBUG: 10876 mips_flag_mdebug = TRUE; 10877 break; 10878 10879 case OPTION_NO_MDEBUG: 10880 mips_flag_mdebug = FALSE; 10881 break; 10882 10883 case OPTION_PDR: 10884 mips_flag_pdr = TRUE; 10885 break; 10886 10887 case OPTION_NO_PDR: 10888 mips_flag_pdr = FALSE; 10889 break; 10890 #endif /* OBJ_ELF */ 10891 10892 default: 10893 return 0; 10894 } 10895 10896 return 1; 10897 } 10898 10899 /* Set up globals to generate code for the ISA or processor 10900 described by INFO. */ 10901 10902 static void 10903 mips_set_architecture (const struct mips_cpu_info *info) 10904 { 10905 if (info != 0) 10906 { 10907 file_mips_arch = info->cpu; 10908 mips_opts.arch = info->cpu; 10909 mips_opts.isa = info->isa; 10910 } 10911 } 10912 10913 10914 /* Likewise for tuning. */ 10915 10916 static void 10917 mips_set_tune (const struct mips_cpu_info *info) 10918 { 10919 if (info != 0) 10920 mips_tune = info->cpu; 10921 } 10922 10923 10924 void 10925 mips_after_parse_args (void) 10926 { 10927 const struct mips_cpu_info *arch_info = 0; 10928 const struct mips_cpu_info *tune_info = 0; 10929 10930 /* GP relative stuff not working for PE */ 10931 if (strncmp (TARGET_OS, "pe", 2) == 0 10932 && g_switch_value != 0) 10933 { 10934 if (g_switch_seen) 10935 as_bad (_("-G not supported in this configuration.")); 10936 g_switch_value = 0; 10937 } 10938 10939 if (mips_abi == NO_ABI) 10940 mips_abi = MIPS_DEFAULT_ABI; 10941 10942 /* The following code determines the architecture and register size. 10943 Similar code was added to GCC 3.3 (see override_options() in 10944 config/mips/mips.c). The GAS and GCC code should be kept in sync 10945 as much as possible. */ 10946 10947 if (mips_arch_string != 0) 10948 arch_info = mips_parse_cpu ("-march", mips_arch_string); 10949 10950 if (file_mips_isa != ISA_UNKNOWN) 10951 { 10952 /* Handle -mipsN. At this point, file_mips_isa contains the 10953 ISA level specified by -mipsN, while arch_info->isa contains 10954 the -march selection (if any). */ 10955 if (arch_info != 0) 10956 { 10957 /* -march takes precedence over -mipsN, since it is more descriptive. 10958 There's no harm in specifying both as long as the ISA levels 10959 are the same. */ 10960 if (file_mips_isa != arch_info->isa) 10961 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), 10962 mips_cpu_info_from_isa (file_mips_isa)->name, 10963 mips_cpu_info_from_isa (arch_info->isa)->name); 10964 } 10965 else 10966 arch_info = mips_cpu_info_from_isa (file_mips_isa); 10967 } 10968 10969 if (arch_info == 0) 10970 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); 10971 10972 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) 10973 as_bad ("-march=%s is not compatible with the selected ABI", 10974 arch_info->name); 10975 10976 mips_set_architecture (arch_info); 10977 10978 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ 10979 if (mips_tune_string != 0) 10980 tune_info = mips_parse_cpu ("-mtune", mips_tune_string); 10981 10982 if (tune_info == 0) 10983 mips_set_tune (arch_info); 10984 else 10985 mips_set_tune (tune_info); 10986 10987 if (file_mips_gp32 >= 0) 10988 { 10989 /* The user specified the size of the integer registers. Make sure 10990 it agrees with the ABI and ISA. */ 10991 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) 10992 as_bad (_("-mgp64 used with a 32-bit processor")); 10993 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) 10994 as_bad (_("-mgp32 used with a 64-bit ABI")); 10995 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) 10996 as_bad (_("-mgp64 used with a 32-bit ABI")); 10997 } 10998 else 10999 { 11000 /* Infer the integer register size from the ABI and processor. 11001 Restrict ourselves to 32-bit registers if that's all the 11002 processor has, or if the ABI cannot handle 64-bit registers. */ 11003 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) 11004 || !ISA_HAS_64BIT_REGS (mips_opts.isa)); 11005 } 11006 11007 /* ??? GAS treats single-float processors as though they had 64-bit 11008 float registers (although it complains when double-precision 11009 instructions are used). As things stand, saying they have 32-bit 11010 registers would lead to spurious "register must be even" messages. 11011 So here we assume float registers are always the same size as 11012 integer ones, unless the user says otherwise. */ 11013 if (file_mips_fp32 < 0) 11014 file_mips_fp32 = file_mips_gp32; 11015 11016 /* End of GCC-shared inference code. */ 11017 11018 /* This flag is set when we have a 64-bit capable CPU but use only 11019 32-bit wide registers. Note that EABI does not use it. */ 11020 if (ISA_HAS_64BIT_REGS (mips_opts.isa) 11021 && ((mips_abi == NO_ABI && file_mips_gp32 == 1) 11022 || mips_abi == O32_ABI)) 11023 mips_32bitmode = 1; 11024 11025 if (mips_opts.isa == ISA_MIPS1 && mips_trap) 11026 as_bad (_("trap exception not supported at ISA 1")); 11027 11028 /* If the selected architecture includes support for ASEs, enable 11029 generation of code for them. */ 11030 if (mips_opts.mips16 == -1) 11031 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; 11032 if (mips_opts.ase_mips3d == -1) 11033 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; 11034 if (mips_opts.ase_mdmx == -1) 11035 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; 11036 11037 file_mips_isa = mips_opts.isa; 11038 file_ase_mips16 = mips_opts.mips16; 11039 file_ase_mips3d = mips_opts.ase_mips3d; 11040 file_ase_mdmx = mips_opts.ase_mdmx; 11041 mips_opts.gp32 = file_mips_gp32; 11042 mips_opts.fp32 = file_mips_fp32; 11043 11044 if (mips_flag_mdebug < 0) 11045 { 11046 #ifdef OBJ_MAYBE_ECOFF 11047 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) 11048 mips_flag_mdebug = 1; 11049 else 11050 #endif /* OBJ_MAYBE_ECOFF */ 11051 mips_flag_mdebug = 0; 11052 } 11053 } 11054 11055 void 11056 mips_init_after_args (void) 11057 { 11058 /* initialize opcodes */ 11059 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; 11060 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; 11061 } 11062 11063 long 11064 md_pcrel_from (fixS *fixP) 11065 { 11066 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 11067 switch (fixP->fx_r_type) 11068 { 11069 case BFD_RELOC_16_PCREL_S2: 11070 case BFD_RELOC_MIPS_JMP: 11071 /* Return the address of the delay slot. */ 11072 return addr + 4; 11073 default: 11074 return addr; 11075 } 11076 } 11077 11078 /* This is called before the symbol table is processed. In order to 11079 work with gcc when using mips-tfile, we must keep all local labels. 11080 However, in other cases, we want to discard them. If we were 11081 called with -g, but we didn't see any debugging information, it may 11082 mean that gcc is smuggling debugging information through to 11083 mips-tfile, in which case we must generate all local labels. */ 11084 11085 void 11086 mips_frob_file_before_adjust (void) 11087 { 11088 #ifndef NO_ECOFF_DEBUGGING 11089 if (ECOFF_DEBUGGING 11090 && mips_debug != 0 11091 && ! ecoff_debugging_seen) 11092 flag_keep_locals = 1; 11093 #endif 11094 } 11095 11096 /* Sort any unmatched HI16_S relocs so that they immediately precede 11097 the corresponding LO reloc. This is called before md_apply_fix3 and 11098 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by 11099 explicit use of the %hi modifier. */ 11100 11101 void 11102 mips_frob_file (void) 11103 { 11104 struct mips_hi_fixup *l; 11105 11106 for (l = mips_hi_fixup_list; l != NULL; l = l->next) 11107 { 11108 segment_info_type *seginfo; 11109 int pass; 11110 11111 assert (reloc_needs_lo_p (l->fixp->fx_r_type)); 11112 11113 /* If a GOT16 relocation turns out to be against a global symbol, 11114 there isn't supposed to be a matching LO. */ 11115 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 11116 && !pic_need_relax (l->fixp->fx_addsy, l->seg)) 11117 continue; 11118 11119 /* Check quickly whether the next fixup happens to be a matching %lo. */ 11120 if (fixup_has_matching_lo_p (l->fixp)) 11121 continue; 11122 11123 /* Look through the fixups for this segment for a matching %lo. 11124 When we find one, move the %hi just in front of it. We do 11125 this in two passes. In the first pass, we try to find a 11126 unique %lo. In the second pass, we permit multiple %hi 11127 relocs for a single %lo (this is a GNU extension). */ 11128 seginfo = seg_info (l->seg); 11129 for (pass = 0; pass < 2; pass++) 11130 { 11131 fixS *f, *prev; 11132 11133 prev = NULL; 11134 for (f = seginfo->fix_root; f != NULL; f = f->fx_next) 11135 { 11136 /* Check whether this is a %lo fixup which matches l->fixp. */ 11137 if (f->fx_r_type == BFD_RELOC_LO16 11138 && f->fx_addsy == l->fixp->fx_addsy 11139 && f->fx_offset == l->fixp->fx_offset 11140 && (pass == 1 11141 || prev == NULL 11142 || !reloc_needs_lo_p (prev->fx_r_type) 11143 || !fixup_has_matching_lo_p (prev))) 11144 { 11145 fixS **pf; 11146 11147 /* Move l->fixp before f. */ 11148 for (pf = &seginfo->fix_root; 11149 *pf != l->fixp; 11150 pf = &(*pf)->fx_next) 11151 assert (*pf != NULL); 11152 11153 *pf = l->fixp->fx_next; 11154 11155 l->fixp->fx_next = f; 11156 if (prev == NULL) 11157 seginfo->fix_root = l->fixp; 11158 else 11159 prev->fx_next = l->fixp; 11160 11161 break; 11162 } 11163 11164 prev = f; 11165 } 11166 11167 if (f != NULL) 11168 break; 11169 11170 #if 0 /* GCC code motion plus incomplete dead code elimination 11171 can leave a %hi without a %lo. */ 11172 if (pass == 1) 11173 as_warn_where (l->fixp->fx_file, l->fixp->fx_line, 11174 _("Unmatched %%hi reloc")); 11175 #endif 11176 } 11177 } 11178 } 11179 11180 /* When generating embedded PIC code we need to use a special 11181 relocation to represent the difference of two symbols in the .text 11182 section (switch tables use a difference of this sort). See 11183 include/coff/mips.h for details. This macro checks whether this 11184 fixup requires the special reloc. */ 11185 #define SWITCH_TABLE(fixp) \ 11186 ((fixp)->fx_r_type == BFD_RELOC_32 \ 11187 && OUTPUT_FLAVOR != bfd_target_elf_flavour \ 11188 && (fixp)->fx_addsy != NULL \ 11189 && (fixp)->fx_subsy != NULL \ 11190 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ 11191 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) 11192 11193 /* When generating embedded PIC code we must keep all PC relative 11194 relocations, in case the linker has to relax a call. We also need 11195 to keep relocations for switch table entries. 11196 11197 We may have combined relocations without symbols in the N32/N64 ABI. 11198 We have to prevent gas from dropping them. */ 11199 11200 int 11201 mips_force_relocation (fixS *fixp) 11202 { 11203 if (generic_force_reloc (fixp)) 11204 return 1; 11205 11206 if (HAVE_NEWABI 11207 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr 11208 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB 11209 || fixp->fx_r_type == BFD_RELOC_HI16_S 11210 || fixp->fx_r_type == BFD_RELOC_LO16)) 11211 return 1; 11212 11213 return (mips_pic == EMBEDDED_PIC 11214 && (fixp->fx_pcrel 11215 || SWITCH_TABLE (fixp) 11216 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S 11217 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); 11218 } 11219 11220 /* This hook is called before a fix is simplified. We don't really 11221 decide whether to skip a fix here. Rather, we turn global symbols 11222 used as branch targets into local symbols, such that they undergo 11223 simplification. We can only do this if the symbol is defined and 11224 it is in the same section as the branch. If this doesn't hold, we 11225 emit a better error message than just saying the relocation is not 11226 valid for the selected object format. 11227 11228 FIXP is the fix-up we're going to try to simplify, SEG is the 11229 segment in which the fix up occurs. The return value should be 11230 non-zero to indicate the fix-up is valid for further 11231 simplifications. */ 11232 11233 int 11234 mips_validate_fix (struct fix *fixP, asection *seg) 11235 { 11236 /* There's a lot of discussion on whether it should be possible to 11237 use R_MIPS_PC16 to represent branch relocations. The outcome 11238 seems to be that it can, but gas/bfd are very broken in creating 11239 RELA relocations for this, so for now we only accept branches to 11240 symbols in the same section. Anything else is of dubious value, 11241 since there's no guarantee that at link time the symbol would be 11242 in range. Even for branches to local symbols this is arguably 11243 wrong, since it we assume the symbol is not going to be 11244 overridden, which should be possible per ELF library semantics, 11245 but then, there isn't a dynamic relocation that could be used to 11246 this effect, and the target would likely be out of range as well. 11247 11248 Unfortunately, it seems that there is too much code out there 11249 that relies on branches to symbols that are global to be resolved 11250 as if they were local, like the IRIX tools do, so we do it as 11251 well, but with a warning so that people are reminded to fix their 11252 code. If we ever get back to using R_MIPS_PC16 for branch 11253 targets, this entire block should go away (and probably the 11254 whole function). */ 11255 11256 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 11257 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour 11258 || OUTPUT_FLAVOR == bfd_target_elf_flavour) 11259 && mips_pic != EMBEDDED_PIC) 11260 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) 11261 && fixP->fx_addsy) 11262 { 11263 if (! S_IS_DEFINED (fixP->fx_addsy)) 11264 { 11265 as_bad_where (fixP->fx_file, fixP->fx_line, 11266 _("Cannot branch to undefined symbol.")); 11267 /* Avoid any further errors about this fixup. */ 11268 fixP->fx_done = 1; 11269 } 11270 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) 11271 { 11272 as_bad_where (fixP->fx_file, fixP->fx_line, 11273 _("Cannot branch to symbol in another section.")); 11274 fixP->fx_done = 1; 11275 } 11276 else if (S_IS_EXTERNAL (fixP->fx_addsy)) 11277 { 11278 symbolS *sym = fixP->fx_addsy; 11279 11280 if (mips_pic == SVR4_PIC) 11281 as_warn_where (fixP->fx_file, fixP->fx_line, 11282 _("Pretending global symbol used as branch target is local.")); 11283 11284 fixP->fx_addsy = symbol_create (S_GET_NAME (sym), 11285 S_GET_SEGMENT (sym), 11286 S_GET_VALUE (sym), 11287 symbol_get_frag (sym)); 11288 copy_symbol_attributes (fixP->fx_addsy, sym); 11289 S_CLEAR_EXTERNAL (fixP->fx_addsy); 11290 assert (symbol_resolved_p (sym)); 11291 symbol_mark_resolved (fixP->fx_addsy); 11292 } 11293 } 11294 11295 return 1; 11296 } 11297 11298 /* Apply a fixup to the object file. */ 11299 11300 void 11301 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 11302 { 11303 bfd_byte *buf; 11304 long insn; 11305 static int previous_fx_r_type = 0; 11306 reloc_howto_type *howto; 11307 11308 /* We ignore generic BFD relocations we don't know about. */ 11309 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); 11310 if (! howto) 11311 return; 11312 11313 assert (fixP->fx_size == 4 11314 || fixP->fx_r_type == BFD_RELOC_16 11315 || fixP->fx_r_type == BFD_RELOC_64 11316 || fixP->fx_r_type == BFD_RELOC_CTOR 11317 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB 11318 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 11319 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); 11320 11321 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); 11322 11323 /* We are not done if this is a composite relocation to set up gp. */ 11324 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel 11325 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB 11326 || (fixP->fx_r_type == BFD_RELOC_64 11327 && (previous_fx_r_type == BFD_RELOC_GPREL32 11328 || previous_fx_r_type == BFD_RELOC_GPREL16)) 11329 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB 11330 && (fixP->fx_r_type == BFD_RELOC_HI16_S 11331 || fixP->fx_r_type == BFD_RELOC_LO16)))) 11332 fixP->fx_done = 1; 11333 previous_fx_r_type = fixP->fx_r_type; 11334 11335 switch (fixP->fx_r_type) 11336 { 11337 case BFD_RELOC_MIPS_JMP: 11338 case BFD_RELOC_MIPS_SHIFT5: 11339 case BFD_RELOC_MIPS_SHIFT6: 11340 case BFD_RELOC_MIPS_GOT_DISP: 11341 case BFD_RELOC_MIPS_GOT_PAGE: 11342 case BFD_RELOC_MIPS_GOT_OFST: 11343 case BFD_RELOC_MIPS_SUB: 11344 case BFD_RELOC_MIPS_INSERT_A: 11345 case BFD_RELOC_MIPS_INSERT_B: 11346 case BFD_RELOC_MIPS_DELETE: 11347 case BFD_RELOC_MIPS_HIGHEST: 11348 case BFD_RELOC_MIPS_HIGHER: 11349 case BFD_RELOC_MIPS_SCN_DISP: 11350 case BFD_RELOC_MIPS_REL16: 11351 case BFD_RELOC_MIPS_RELGOT: 11352 case BFD_RELOC_MIPS_JALR: 11353 case BFD_RELOC_HI16: 11354 case BFD_RELOC_HI16_S: 11355 case BFD_RELOC_GPREL16: 11356 case BFD_RELOC_MIPS_LITERAL: 11357 case BFD_RELOC_MIPS_CALL16: 11358 case BFD_RELOC_MIPS_GOT16: 11359 case BFD_RELOC_GPREL32: 11360 case BFD_RELOC_MIPS_GOT_HI16: 11361 case BFD_RELOC_MIPS_GOT_LO16: 11362 case BFD_RELOC_MIPS_CALL_HI16: 11363 case BFD_RELOC_MIPS_CALL_LO16: 11364 case BFD_RELOC_MIPS16_GPREL: 11365 if (fixP->fx_pcrel) 11366 as_bad_where (fixP->fx_file, fixP->fx_line, 11367 _("Invalid PC relative reloc")); 11368 /* Nothing needed to do. The value comes from the reloc entry */ 11369 break; 11370 11371 case BFD_RELOC_MIPS16_JMP: 11372 /* We currently always generate a reloc against a symbol, which 11373 means that we don't want an addend even if the symbol is 11374 defined. */ 11375 *valP = 0; 11376 break; 11377 11378 case BFD_RELOC_PCREL_HI16_S: 11379 /* The addend for this is tricky if it is internal, so we just 11380 do everything here rather than in bfd_install_relocation. */ 11381 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) 11382 break; 11383 if (fixP->fx_addsy 11384 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) 11385 { 11386 /* For an external symbol adjust by the address to make it 11387 pcrel_offset. We use the address of the RELLO reloc 11388 which follows this one. */ 11389 *valP += (fixP->fx_next->fx_frag->fr_address 11390 + fixP->fx_next->fx_where); 11391 } 11392 *valP = ((*valP + 0x8000) >> 16) & 0xffff; 11393 if (target_big_endian) 11394 buf += 2; 11395 md_number_to_chars (buf, *valP, 2); 11396 break; 11397 11398 case BFD_RELOC_PCREL_LO16: 11399 /* The addend for this is tricky if it is internal, so we just 11400 do everything here rather than in bfd_install_relocation. */ 11401 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) 11402 break; 11403 if (fixP->fx_addsy 11404 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) 11405 *valP += fixP->fx_frag->fr_address + fixP->fx_where; 11406 if (target_big_endian) 11407 buf += 2; 11408 md_number_to_chars (buf, *valP, 2); 11409 break; 11410 11411 case BFD_RELOC_64: 11412 /* This is handled like BFD_RELOC_32, but we output a sign 11413 extended value if we are only 32 bits. */ 11414 if (fixP->fx_done 11415 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) 11416 { 11417 if (8 <= sizeof (valueT)) 11418 md_number_to_chars (buf, *valP, 8); 11419 else 11420 { 11421 valueT hiv; 11422 11423 if ((*valP & 0x80000000) != 0) 11424 hiv = 0xffffffff; 11425 else 11426 hiv = 0; 11427 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), 11428 *valP, 4); 11429 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), 11430 hiv, 4); 11431 } 11432 } 11433 break; 11434 11435 case BFD_RELOC_RVA: 11436 case BFD_RELOC_32: 11437 /* If we are deleting this reloc entry, we must fill in the 11438 value now. This can happen if we have a .word which is not 11439 resolved when it appears but is later defined. We also need 11440 to fill in the value if this is an embedded PIC switch table 11441 entry. */ 11442 if (fixP->fx_done 11443 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) 11444 md_number_to_chars (buf, *valP, 4); 11445 break; 11446 11447 case BFD_RELOC_16: 11448 /* If we are deleting this reloc entry, we must fill in the 11449 value now. */ 11450 assert (fixP->fx_size == 2); 11451 if (fixP->fx_done) 11452 md_number_to_chars (buf, *valP, 2); 11453 break; 11454 11455 case BFD_RELOC_LO16: 11456 /* When handling an embedded PIC switch statement, we can wind 11457 up deleting a LO16 reloc. See the 'o' case in mips_ip. */ 11458 if (fixP->fx_done) 11459 { 11460 if (*valP + 0x8000 > 0xffff) 11461 as_bad_where (fixP->fx_file, fixP->fx_line, 11462 _("relocation overflow")); 11463 if (target_big_endian) 11464 buf += 2; 11465 md_number_to_chars (buf, *valP, 2); 11466 } 11467 break; 11468 11469 case BFD_RELOC_16_PCREL_S2: 11470 if ((*valP & 0x3) != 0) 11471 as_bad_where (fixP->fx_file, fixP->fx_line, 11472 _("Branch to odd address (%lx)"), (long) *valP); 11473 11474 /* 11475 * We need to save the bits in the instruction since fixup_segment() 11476 * might be deleting the relocation entry (i.e., a branch within 11477 * the current segment). 11478 */ 11479 if (! fixP->fx_done) 11480 break; 11481 11482 /* update old instruction data */ 11483 if (target_big_endian) 11484 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; 11485 else 11486 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 11487 11488 if (*valP + 0x20000 <= 0x3ffff) 11489 { 11490 insn |= (*valP >> 2) & 0xffff; 11491 md_number_to_chars (buf, insn, 4); 11492 } 11493 else if (mips_pic == NO_PIC 11494 && fixP->fx_done 11495 && fixP->fx_frag->fr_address >= text_section->vma 11496 && (fixP->fx_frag->fr_address 11497 < text_section->vma + text_section->_raw_size) 11498 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 11499 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ 11500 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 11501 { 11502 /* The branch offset is too large. If this is an 11503 unconditional branch, and we are not generating PIC code, 11504 we can convert it to an absolute jump instruction. */ 11505 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ 11506 insn = 0x0c000000; /* jal */ 11507 else 11508 insn = 0x08000000; /* j */ 11509 fixP->fx_r_type = BFD_RELOC_MIPS_JMP; 11510 fixP->fx_done = 0; 11511 fixP->fx_addsy = section_symbol (text_section); 11512 *valP += md_pcrel_from (fixP); 11513 md_number_to_chars (buf, insn, 4); 11514 } 11515 else 11516 { 11517 /* If we got here, we have branch-relaxation disabled, 11518 and there's nothing we can do to fix this instruction 11519 without turning it into a longer sequence. */ 11520 as_bad_where (fixP->fx_file, fixP->fx_line, 11521 _("Branch out of range")); 11522 } 11523 break; 11524 11525 case BFD_RELOC_VTABLE_INHERIT: 11526 fixP->fx_done = 0; 11527 if (fixP->fx_addsy 11528 && !S_IS_DEFINED (fixP->fx_addsy) 11529 && !S_IS_WEAK (fixP->fx_addsy)) 11530 S_SET_WEAK (fixP->fx_addsy); 11531 break; 11532 11533 case BFD_RELOC_VTABLE_ENTRY: 11534 fixP->fx_done = 0; 11535 break; 11536 11537 default: 11538 internalError (); 11539 } 11540 11541 /* Remember value for tc_gen_reloc. */ 11542 fixP->fx_addnumber = *valP; 11543 } 11544 11545 #if 0 11546 void 11547 printInsn (unsigned long oc) 11548 { 11549 const struct mips_opcode *p; 11550 int treg, sreg, dreg, shamt; 11551 short imm; 11552 const char *args; 11553 int i; 11554 11555 for (i = 0; i < NUMOPCODES; ++i) 11556 { 11557 p = &mips_opcodes[i]; 11558 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) 11559 { 11560 printf ("%08lx %s\t", oc, p->name); 11561 treg = (oc >> 16) & 0x1f; 11562 sreg = (oc >> 21) & 0x1f; 11563 dreg = (oc >> 11) & 0x1f; 11564 shamt = (oc >> 6) & 0x1f; 11565 imm = oc; 11566 for (args = p->args;; ++args) 11567 { 11568 switch (*args) 11569 { 11570 case '\0': 11571 printf ("\n"); 11572 break; 11573 11574 case ',': 11575 case '(': 11576 case ')': 11577 printf ("%c", *args); 11578 continue; 11579 11580 case 'r': 11581 assert (treg == sreg); 11582 printf ("$%d,$%d", treg, sreg); 11583 continue; 11584 11585 case 'd': 11586 case 'G': 11587 printf ("$%d", dreg); 11588 continue; 11589 11590 case 't': 11591 case 'E': 11592 printf ("$%d", treg); 11593 continue; 11594 11595 case 'k': 11596 printf ("0x%x", treg); 11597 continue; 11598 11599 case 'b': 11600 case 's': 11601 printf ("$%d", sreg); 11602 continue; 11603 11604 case 'a': 11605 printf ("0x%08lx", oc & 0x1ffffff); 11606 continue; 11607 11608 case 'i': 11609 case 'j': 11610 case 'o': 11611 case 'u': 11612 printf ("%d", imm); 11613 continue; 11614 11615 case '<': 11616 case '>': 11617 printf ("$%d", shamt); 11618 continue; 11619 11620 default: 11621 internalError (); 11622 } 11623 break; 11624 } 11625 return; 11626 } 11627 } 11628 printf (_("%08lx UNDEFINED\n"), oc); 11629 } 11630 #endif 11631 11632 static symbolS * 11633 get_symbol (void) 11634 { 11635 int c; 11636 char *name; 11637 symbolS *p; 11638 11639 name = input_line_pointer; 11640 c = get_symbol_end (); 11641 p = (symbolS *) symbol_find_or_make (name); 11642 *input_line_pointer = c; 11643 return p; 11644 } 11645 11646 /* Align the current frag to a given power of two. The MIPS assembler 11647 also automatically adjusts any preceding label. */ 11648 11649 static void 11650 mips_align (int to, int fill, symbolS *label) 11651 { 11652 mips_emit_delays (FALSE); 11653 frag_align (to, fill, 0); 11654 record_alignment (now_seg, to); 11655 if (label != NULL) 11656 { 11657 assert (S_GET_SEGMENT (label) == now_seg); 11658 symbol_set_frag (label, frag_now); 11659 S_SET_VALUE (label, (valueT) frag_now_fix ()); 11660 } 11661 } 11662 11663 /* Align to a given power of two. .align 0 turns off the automatic 11664 alignment used by the data creating pseudo-ops. */ 11665 11666 static void 11667 s_align (int x ATTRIBUTE_UNUSED) 11668 { 11669 register int temp; 11670 register long temp_fill; 11671 long max_alignment = 15; 11672 11673 /* 11674 11675 o Note that the assembler pulls down any immediately preceding label 11676 to the aligned address. 11677 o It's not documented but auto alignment is reinstated by 11678 a .align pseudo instruction. 11679 o Note also that after auto alignment is turned off the mips assembler 11680 issues an error on attempt to assemble an improperly aligned data item. 11681 We don't. 11682 11683 */ 11684 11685 temp = get_absolute_expression (); 11686 if (temp > max_alignment) 11687 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); 11688 else if (temp < 0) 11689 { 11690 as_warn (_("Alignment negative: 0 assumed.")); 11691 temp = 0; 11692 } 11693 if (*input_line_pointer == ',') 11694 { 11695 ++input_line_pointer; 11696 temp_fill = get_absolute_expression (); 11697 } 11698 else 11699 temp_fill = 0; 11700 if (temp) 11701 { 11702 auto_align = 1; 11703 mips_align (temp, (int) temp_fill, 11704 insn_labels != NULL ? insn_labels->label : NULL); 11705 } 11706 else 11707 { 11708 auto_align = 0; 11709 } 11710 11711 demand_empty_rest_of_line (); 11712 } 11713 11714 void 11715 mips_flush_pending_output (void) 11716 { 11717 mips_emit_delays (FALSE); 11718 mips_clear_insn_labels (); 11719 } 11720 11721 static void 11722 s_change_sec (int sec) 11723 { 11724 segT seg; 11725 11726 /* When generating embedded PIC code, we only use the .text, .lit8, 11727 .sdata and .sbss sections. We change the .data and .rdata 11728 pseudo-ops to use .sdata. */ 11729 if (mips_pic == EMBEDDED_PIC 11730 && (sec == 'd' || sec == 'r')) 11731 sec = 's'; 11732 11733 #ifdef OBJ_ELF 11734 /* The ELF backend needs to know that we are changing sections, so 11735 that .previous works correctly. We could do something like check 11736 for an obj_section_change_hook macro, but that might be confusing 11737 as it would not be appropriate to use it in the section changing 11738 functions in read.c, since obj-elf.c intercepts those. FIXME: 11739 This should be cleaner, somehow. */ 11740 obj_elf_section_change_hook (); 11741 #endif 11742 11743 mips_emit_delays (FALSE); 11744 switch (sec) 11745 { 11746 case 't': 11747 s_text (0); 11748 break; 11749 case 'd': 11750 s_data (0); 11751 break; 11752 case 'b': 11753 subseg_set (bss_section, (subsegT) get_absolute_expression ()); 11754 demand_empty_rest_of_line (); 11755 break; 11756 11757 case 'r': 11758 if (USE_GLOBAL_POINTER_OPT) 11759 { 11760 seg = subseg_new (RDATA_SECTION_NAME, 11761 (subsegT) get_absolute_expression ()); 11762 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 11763 { 11764 bfd_set_section_flags (stdoutput, seg, 11765 (SEC_ALLOC 11766 | SEC_LOAD 11767 | SEC_READONLY 11768 | SEC_RELOC 11769 | SEC_DATA)); 11770 if (strcmp (TARGET_OS, "elf") != 0) 11771 record_alignment (seg, 4); 11772 } 11773 demand_empty_rest_of_line (); 11774 } 11775 else 11776 { 11777 as_bad (_("No read only data section in this object file format")); 11778 demand_empty_rest_of_line (); 11779 return; 11780 } 11781 break; 11782 11783 case 's': 11784 if (USE_GLOBAL_POINTER_OPT) 11785 { 11786 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); 11787 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 11788 { 11789 bfd_set_section_flags (stdoutput, seg, 11790 SEC_ALLOC | SEC_LOAD | SEC_RELOC 11791 | SEC_DATA); 11792 if (strcmp (TARGET_OS, "elf") != 0) 11793 record_alignment (seg, 4); 11794 } 11795 demand_empty_rest_of_line (); 11796 break; 11797 } 11798 else 11799 { 11800 as_bad (_("Global pointers not supported; recompile -G 0")); 11801 demand_empty_rest_of_line (); 11802 return; 11803 } 11804 } 11805 11806 auto_align = 1; 11807 } 11808 11809 void 11810 s_change_section (int ignore ATTRIBUTE_UNUSED) 11811 { 11812 #ifdef OBJ_ELF 11813 char *section_name; 11814 char c; 11815 char next_c = 0; 11816 int section_type; 11817 int section_flag; 11818 int section_entry_size; 11819 int section_alignment; 11820 11821 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 11822 return; 11823 11824 section_name = input_line_pointer; 11825 c = get_symbol_end (); 11826 if (c) 11827 next_c = *(input_line_pointer + 1); 11828 11829 /* Do we have .section Name<,"flags">? */ 11830 if (c != ',' || (c == ',' && next_c == '"')) 11831 { 11832 /* just after name is now '\0'. */ 11833 *input_line_pointer = c; 11834 input_line_pointer = section_name; 11835 obj_elf_section (ignore); 11836 return; 11837 } 11838 input_line_pointer++; 11839 11840 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ 11841 if (c == ',') 11842 section_type = get_absolute_expression (); 11843 else 11844 section_type = 0; 11845 if (*input_line_pointer++ == ',') 11846 section_flag = get_absolute_expression (); 11847 else 11848 section_flag = 0; 11849 if (*input_line_pointer++ == ',') 11850 section_entry_size = get_absolute_expression (); 11851 else 11852 section_entry_size = 0; 11853 if (*input_line_pointer++ == ',') 11854 section_alignment = get_absolute_expression (); 11855 else 11856 section_alignment = 0; 11857 11858 section_name = xstrdup (section_name); 11859 11860 /* When using the generic form of .section (as implemented by obj-elf.c), 11861 there's no way to set the section type to SHT_MIPS_DWARF. Users have 11862 traditionally had to fall back on the more common @progbits instead. 11863 11864 There's nothing really harmful in this, since bfd will correct 11865 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it 11866 means that, for backwards compatibiltiy, the special_section entries 11867 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. 11868 11869 Even so, we shouldn't force users of the MIPS .section syntax to 11870 incorrectly label the sections as SHT_PROGBITS. The best compromise 11871 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the 11872 generic type-checking code. */ 11873 if (section_type == SHT_MIPS_DWARF) 11874 section_type = SHT_PROGBITS; 11875 11876 obj_elf_change_section (section_name, section_type, section_flag, 11877 section_entry_size, 0, 0, 0); 11878 11879 if (now_seg->name != section_name) 11880 free (section_name); 11881 #endif /* OBJ_ELF */ 11882 } 11883 11884 void 11885 mips_enable_auto_align (void) 11886 { 11887 auto_align = 1; 11888 } 11889 11890 static void 11891 s_cons (int log_size) 11892 { 11893 symbolS *label; 11894 11895 label = insn_labels != NULL ? insn_labels->label : NULL; 11896 mips_emit_delays (FALSE); 11897 if (log_size > 0 && auto_align) 11898 mips_align (log_size, 0, label); 11899 mips_clear_insn_labels (); 11900 cons (1 << log_size); 11901 } 11902 11903 static void 11904 s_float_cons (int type) 11905 { 11906 symbolS *label; 11907 11908 label = insn_labels != NULL ? insn_labels->label : NULL; 11909 11910 mips_emit_delays (FALSE); 11911 11912 if (auto_align) 11913 { 11914 if (type == 'd') 11915 mips_align (3, 0, label); 11916 else 11917 mips_align (2, 0, label); 11918 } 11919 11920 mips_clear_insn_labels (); 11921 11922 float_cons (type); 11923 } 11924 11925 /* Handle .globl. We need to override it because on Irix 5 you are 11926 permitted to say 11927 .globl foo .text 11928 where foo is an undefined symbol, to mean that foo should be 11929 considered to be the address of a function. */ 11930 11931 static void 11932 s_mips_globl (int x ATTRIBUTE_UNUSED) 11933 { 11934 char *name; 11935 int c; 11936 symbolS *symbolP; 11937 flagword flag; 11938 11939 name = input_line_pointer; 11940 c = get_symbol_end (); 11941 symbolP = symbol_find_or_make (name); 11942 *input_line_pointer = c; 11943 SKIP_WHITESPACE (); 11944 11945 /* On Irix 5, every global symbol that is not explicitly labelled as 11946 being a function is apparently labelled as being an object. */ 11947 flag = BSF_OBJECT; 11948 11949 if (! is_end_of_line[(unsigned char) *input_line_pointer]) 11950 { 11951 char *secname; 11952 asection *sec; 11953 11954 secname = input_line_pointer; 11955 c = get_symbol_end (); 11956 sec = bfd_get_section_by_name (stdoutput, secname); 11957 if (sec == NULL) 11958 as_bad (_("%s: no such section"), secname); 11959 *input_line_pointer = c; 11960 11961 if (sec != NULL && (sec->flags & SEC_CODE) != 0) 11962 flag = BSF_FUNCTION; 11963 } 11964 11965 symbol_get_bfdsym (symbolP)->flags |= flag; 11966 11967 S_SET_EXTERNAL (symbolP); 11968 demand_empty_rest_of_line (); 11969 } 11970 11971 static void 11972 s_option (int x ATTRIBUTE_UNUSED) 11973 { 11974 char *opt; 11975 char c; 11976 11977 opt = input_line_pointer; 11978 c = get_symbol_end (); 11979 11980 if (*opt == 'O') 11981 { 11982 /* FIXME: What does this mean? */ 11983 } 11984 else if (strncmp (opt, "pic", 3) == 0) 11985 { 11986 int i; 11987 11988 i = atoi (opt + 3); 11989 if (i == 0) 11990 mips_pic = NO_PIC; 11991 else if (i == 2) 11992 { 11993 mips_pic = SVR4_PIC; 11994 mips_abicalls = TRUE; 11995 } 11996 else 11997 as_bad (_(".option pic%d not supported"), i); 11998 11999 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) 12000 { 12001 if (g_switch_seen && g_switch_value != 0) 12002 as_warn (_("-G may not be used with SVR4 PIC code")); 12003 g_switch_value = 0; 12004 bfd_set_gp_size (stdoutput, 0); 12005 } 12006 } 12007 else 12008 as_warn (_("Unrecognized option \"%s\""), opt); 12009 12010 *input_line_pointer = c; 12011 demand_empty_rest_of_line (); 12012 } 12013 12014 /* This structure is used to hold a stack of .set values. */ 12015 12016 struct mips_option_stack 12017 { 12018 struct mips_option_stack *next; 12019 struct mips_set_options options; 12020 }; 12021 12022 static struct mips_option_stack *mips_opts_stack; 12023 12024 /* Handle the .set pseudo-op. */ 12025 12026 static void 12027 s_mipsset (int x ATTRIBUTE_UNUSED) 12028 { 12029 char *name = input_line_pointer, ch; 12030 12031 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 12032 ++input_line_pointer; 12033 ch = *input_line_pointer; 12034 *input_line_pointer = '\0'; 12035 12036 if (strcmp (name, "reorder") == 0) 12037 { 12038 if (mips_opts.noreorder && prev_nop_frag != NULL) 12039 { 12040 /* If we still have pending nops, we can discard them. The 12041 usual nop handling will insert any that are still 12042 needed. */ 12043 prev_nop_frag->fr_fix -= (prev_nop_frag_holds 12044 * (mips_opts.mips16 ? 2 : 4)); 12045 prev_nop_frag = NULL; 12046 } 12047 mips_opts.noreorder = 0; 12048 } 12049 else if (strcmp (name, "noreorder") == 0) 12050 { 12051 mips_emit_delays (TRUE); 12052 mips_opts.noreorder = 1; 12053 mips_any_noreorder = 1; 12054 } 12055 else if (strcmp (name, "at") == 0) 12056 { 12057 mips_opts.noat = 0; 12058 } 12059 else if (strcmp (name, "noat") == 0) 12060 { 12061 mips_opts.noat = 1; 12062 } 12063 else if (strcmp (name, "macro") == 0) 12064 { 12065 mips_opts.warn_about_macros = 0; 12066 } 12067 else if (strcmp (name, "nomacro") == 0) 12068 { 12069 if (mips_opts.noreorder == 0) 12070 as_bad (_("`noreorder' must be set before `nomacro'")); 12071 mips_opts.warn_about_macros = 1; 12072 } 12073 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) 12074 { 12075 mips_opts.nomove = 0; 12076 } 12077 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) 12078 { 12079 mips_opts.nomove = 1; 12080 } 12081 else if (strcmp (name, "bopt") == 0) 12082 { 12083 mips_opts.nobopt = 0; 12084 } 12085 else if (strcmp (name, "nobopt") == 0) 12086 { 12087 mips_opts.nobopt = 1; 12088 } 12089 else if (strcmp (name, "mips16") == 0 12090 || strcmp (name, "MIPS-16") == 0) 12091 mips_opts.mips16 = 1; 12092 else if (strcmp (name, "nomips16") == 0 12093 || strcmp (name, "noMIPS-16") == 0) 12094 mips_opts.mips16 = 0; 12095 else if (strcmp (name, "mips3d") == 0) 12096 mips_opts.ase_mips3d = 1; 12097 else if (strcmp (name, "nomips3d") == 0) 12098 mips_opts.ase_mips3d = 0; 12099 else if (strcmp (name, "mdmx") == 0) 12100 mips_opts.ase_mdmx = 1; 12101 else if (strcmp (name, "nomdmx") == 0) 12102 mips_opts.ase_mdmx = 0; 12103 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) 12104 { 12105 int reset = 0; 12106 12107 /* Permit the user to change the ISA and architecture on the fly. 12108 Needless to say, misuse can cause serious problems. */ 12109 if (strcmp (name, "mips0") == 0) 12110 { 12111 reset = 1; 12112 mips_opts.isa = file_mips_isa; 12113 } 12114 else if (strcmp (name, "mips1") == 0) 12115 mips_opts.isa = ISA_MIPS1; 12116 else if (strcmp (name, "mips2") == 0) 12117 mips_opts.isa = ISA_MIPS2; 12118 else if (strcmp (name, "mips3") == 0) 12119 mips_opts.isa = ISA_MIPS3; 12120 else if (strcmp (name, "mips4") == 0) 12121 mips_opts.isa = ISA_MIPS4; 12122 else if (strcmp (name, "mips5") == 0) 12123 mips_opts.isa = ISA_MIPS5; 12124 else if (strcmp (name, "mips32") == 0) 12125 mips_opts.isa = ISA_MIPS32; 12126 else if (strcmp (name, "mips32r2") == 0) 12127 mips_opts.isa = ISA_MIPS32R2; 12128 else if (strcmp (name, "mips64") == 0) 12129 mips_opts.isa = ISA_MIPS64; 12130 else if (strcmp (name, "mips64r2") == 0) 12131 mips_opts.isa = ISA_MIPS64R2; 12132 else if (strcmp (name, "arch=default") == 0) 12133 { 12134 reset = 1; 12135 mips_opts.arch = file_mips_arch; 12136 mips_opts.isa = file_mips_isa; 12137 } 12138 else if (strncmp (name, "arch=", 5) == 0) 12139 { 12140 const struct mips_cpu_info *p; 12141 12142 p = mips_parse_cpu("internal use", name + 5); 12143 if (!p) 12144 as_bad (_("unknown architecture %s"), name + 5); 12145 else 12146 { 12147 mips_opts.arch = p->cpu; 12148 mips_opts.isa = p->isa; 12149 } 12150 } 12151 else 12152 as_bad (_("unknown ISA level %s"), name + 4); 12153 12154 switch (mips_opts.isa) 12155 { 12156 case 0: 12157 break; 12158 case ISA_MIPS1: 12159 case ISA_MIPS2: 12160 case ISA_MIPS32: 12161 case ISA_MIPS32R2: 12162 mips_opts.gp32 = 1; 12163 mips_opts.fp32 = 1; 12164 break; 12165 case ISA_MIPS3: 12166 case ISA_MIPS4: 12167 case ISA_MIPS5: 12168 case ISA_MIPS64: 12169 case ISA_MIPS64R2: 12170 mips_opts.gp32 = 0; 12171 mips_opts.fp32 = 0; 12172 break; 12173 default: 12174 as_bad (_("unknown ISA level %s"), name + 4); 12175 break; 12176 } 12177 if (reset) 12178 { 12179 mips_opts.gp32 = file_mips_gp32; 12180 mips_opts.fp32 = file_mips_fp32; 12181 } 12182 } 12183 else if (strcmp (name, "autoextend") == 0) 12184 mips_opts.noautoextend = 0; 12185 else if (strcmp (name, "noautoextend") == 0) 12186 mips_opts.noautoextend = 1; 12187 else if (strcmp (name, "push") == 0) 12188 { 12189 struct mips_option_stack *s; 12190 12191 s = (struct mips_option_stack *) xmalloc (sizeof *s); 12192 s->next = mips_opts_stack; 12193 s->options = mips_opts; 12194 mips_opts_stack = s; 12195 } 12196 else if (strcmp (name, "pop") == 0) 12197 { 12198 struct mips_option_stack *s; 12199 12200 s = mips_opts_stack; 12201 if (s == NULL) 12202 as_bad (_(".set pop with no .set push")); 12203 else 12204 { 12205 /* If we're changing the reorder mode we need to handle 12206 delay slots correctly. */ 12207 if (s->options.noreorder && ! mips_opts.noreorder) 12208 mips_emit_delays (TRUE); 12209 else if (! s->options.noreorder && mips_opts.noreorder) 12210 { 12211 if (prev_nop_frag != NULL) 12212 { 12213 prev_nop_frag->fr_fix -= (prev_nop_frag_holds 12214 * (mips_opts.mips16 ? 2 : 4)); 12215 prev_nop_frag = NULL; 12216 } 12217 } 12218 12219 mips_opts = s->options; 12220 mips_opts_stack = s->next; 12221 free (s); 12222 } 12223 } 12224 else 12225 { 12226 as_warn (_("Tried to set unrecognized symbol: %s\n"), name); 12227 } 12228 *input_line_pointer = ch; 12229 demand_empty_rest_of_line (); 12230 } 12231 12232 /* Handle the .abicalls pseudo-op. I believe this is equivalent to 12233 .option pic2. It means to generate SVR4 PIC calls. */ 12234 12235 static void 12236 s_abicalls (int ignore ATTRIBUTE_UNUSED) 12237 { 12238 mips_pic = SVR4_PIC; 12239 mips_abicalls = TRUE; 12240 if (USE_GLOBAL_POINTER_OPT) 12241 { 12242 if (g_switch_seen && g_switch_value != 0) 12243 as_warn (_("-G may not be used with SVR4 PIC code")); 12244 g_switch_value = 0; 12245 } 12246 bfd_set_gp_size (stdoutput, 0); 12247 demand_empty_rest_of_line (); 12248 } 12249 12250 /* Handle the .cpload pseudo-op. This is used when generating SVR4 12251 PIC code. It sets the $gp register for the function based on the 12252 function address, which is in the register named in the argument. 12253 This uses a relocation against _gp_disp, which is handled specially 12254 by the linker. The result is: 12255 lui $gp,%hi(_gp_disp) 12256 addiu $gp,$gp,%lo(_gp_disp) 12257 addu $gp,$gp,.cpload argument 12258 The .cpload argument is normally $25 == $t9. */ 12259 12260 static void 12261 s_cpload (int ignore ATTRIBUTE_UNUSED) 12262 { 12263 expressionS ex; 12264 12265 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 12266 .cpload is ignored. */ 12267 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 12268 { 12269 s_ignore (0); 12270 return; 12271 } 12272 12273 /* .cpload should be in a .set noreorder section. */ 12274 if (mips_opts.noreorder == 0) 12275 as_warn (_(".cpload not in noreorder section")); 12276 12277 ex.X_op = O_symbol; 12278 ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); 12279 ex.X_op_symbol = NULL; 12280 ex.X_add_number = 0; 12281 12282 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 12283 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 12284 12285 macro_start (); 12286 macro_build_lui (&ex, mips_gp_register); 12287 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 12288 mips_gp_register, BFD_RELOC_LO16); 12289 macro_build (NULL, "addu", "d,v,t", mips_gp_register, 12290 mips_gp_register, tc_get_register (0)); 12291 macro_end (); 12292 12293 demand_empty_rest_of_line (); 12294 } 12295 12296 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: 12297 .cpsetup $reg1, offset|$reg2, label 12298 12299 If offset is given, this results in: 12300 sd $gp, offset($sp) 12301 lui $gp, %hi(%neg(%gp_rel(label))) 12302 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 12303 daddu $gp, $gp, $reg1 12304 12305 If $reg2 is given, this results in: 12306 daddu $reg2, $gp, $0 12307 lui $gp, %hi(%neg(%gp_rel(label))) 12308 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 12309 daddu $gp, $gp, $reg1 12310 $reg1 is normally $25 == $t9. */ 12311 static void 12312 s_cpsetup (int ignore ATTRIBUTE_UNUSED) 12313 { 12314 expressionS ex_off; 12315 expressionS ex_sym; 12316 int reg1; 12317 char *f; 12318 12319 /* If we are not generating SVR4 PIC code, .cpsetup is ignored. 12320 We also need NewABI support. */ 12321 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 12322 { 12323 s_ignore (0); 12324 return; 12325 } 12326 12327 reg1 = tc_get_register (0); 12328 SKIP_WHITESPACE (); 12329 if (*input_line_pointer != ',') 12330 { 12331 as_bad (_("missing argument separator ',' for .cpsetup")); 12332 return; 12333 } 12334 else 12335 ++input_line_pointer; 12336 SKIP_WHITESPACE (); 12337 if (*input_line_pointer == '$') 12338 { 12339 mips_cpreturn_register = tc_get_register (0); 12340 mips_cpreturn_offset = -1; 12341 } 12342 else 12343 { 12344 mips_cpreturn_offset = get_absolute_expression (); 12345 mips_cpreturn_register = -1; 12346 } 12347 SKIP_WHITESPACE (); 12348 if (*input_line_pointer != ',') 12349 { 12350 as_bad (_("missing argument separator ',' for .cpsetup")); 12351 return; 12352 } 12353 else 12354 ++input_line_pointer; 12355 SKIP_WHITESPACE (); 12356 expression (&ex_sym); 12357 12358 macro_start (); 12359 if (mips_cpreturn_register == -1) 12360 { 12361 ex_off.X_op = O_constant; 12362 ex_off.X_add_symbol = NULL; 12363 ex_off.X_op_symbol = NULL; 12364 ex_off.X_add_number = mips_cpreturn_offset; 12365 12366 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, 12367 BFD_RELOC_LO16, SP); 12368 } 12369 else 12370 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, 12371 mips_gp_register, 0); 12372 12373 /* Ensure there's room for the next two instructions, so that `f' 12374 doesn't end up with an address in the wrong frag. */ 12375 frag_grow (8); 12376 f = frag_more (0); 12377 macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16); 12378 fix_new (frag_now, f - frag_now->fr_literal, 12379 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); 12380 fix_new (frag_now, f - frag_now->fr_literal, 12381 4, NULL, 0, 0, BFD_RELOC_HI16_S); 12382 12383 f = frag_more (0); 12384 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, 12385 mips_gp_register, BFD_RELOC_GPREL16); 12386 fix_new (frag_now, f - frag_now->fr_literal, 12387 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); 12388 fix_new (frag_now, f - frag_now->fr_literal, 12389 4, NULL, 0, 0, BFD_RELOC_LO16); 12390 12391 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, 12392 mips_gp_register, reg1); 12393 macro_end (); 12394 12395 demand_empty_rest_of_line (); 12396 } 12397 12398 static void 12399 s_cplocal (int ignore ATTRIBUTE_UNUSED) 12400 { 12401 /* If we are not generating SVR4 PIC code, or if this is not NewABI code, 12402 .cplocal is ignored. */ 12403 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 12404 { 12405 s_ignore (0); 12406 return; 12407 } 12408 12409 mips_gp_register = tc_get_register (0); 12410 demand_empty_rest_of_line (); 12411 } 12412 12413 /* Handle the .cprestore pseudo-op. This stores $gp into a given 12414 offset from $sp. The offset is remembered, and after making a PIC 12415 call $gp is restored from that location. */ 12416 12417 static void 12418 s_cprestore (int ignore ATTRIBUTE_UNUSED) 12419 { 12420 expressionS ex; 12421 12422 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 12423 .cprestore is ignored. */ 12424 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 12425 { 12426 s_ignore (0); 12427 return; 12428 } 12429 12430 mips_cprestore_offset = get_absolute_expression (); 12431 mips_cprestore_valid = 1; 12432 12433 ex.X_op = O_constant; 12434 ex.X_add_symbol = NULL; 12435 ex.X_op_symbol = NULL; 12436 ex.X_add_number = mips_cprestore_offset; 12437 12438 macro_start (); 12439 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, 12440 SP, HAVE_64BIT_ADDRESSES); 12441 macro_end (); 12442 12443 demand_empty_rest_of_line (); 12444 } 12445 12446 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset 12447 was given in the preceding .cpsetup, it results in: 12448 ld $gp, offset($sp) 12449 12450 If a register $reg2 was given there, it results in: 12451 daddu $gp, $reg2, $0 12452 */ 12453 static void 12454 s_cpreturn (int ignore ATTRIBUTE_UNUSED) 12455 { 12456 expressionS ex; 12457 12458 /* If we are not generating SVR4 PIC code, .cpreturn is ignored. 12459 We also need NewABI support. */ 12460 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 12461 { 12462 s_ignore (0); 12463 return; 12464 } 12465 12466 macro_start (); 12467 if (mips_cpreturn_register == -1) 12468 { 12469 ex.X_op = O_constant; 12470 ex.X_add_symbol = NULL; 12471 ex.X_op_symbol = NULL; 12472 ex.X_add_number = mips_cpreturn_offset; 12473 12474 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); 12475 } 12476 else 12477 macro_build (NULL, "daddu", "d,v,t", mips_gp_register, 12478 mips_cpreturn_register, 0); 12479 macro_end (); 12480 12481 demand_empty_rest_of_line (); 12482 } 12483 12484 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC 12485 code. It sets the offset to use in gp_rel relocations. */ 12486 12487 static void 12488 s_gpvalue (int ignore ATTRIBUTE_UNUSED) 12489 { 12490 /* If we are not generating SVR4 PIC code, .gpvalue is ignored. 12491 We also need NewABI support. */ 12492 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 12493 { 12494 s_ignore (0); 12495 return; 12496 } 12497 12498 mips_gprel_offset = get_absolute_expression (); 12499 12500 demand_empty_rest_of_line (); 12501 } 12502 12503 /* Handle the .gpword pseudo-op. This is used when generating PIC 12504 code. It generates a 32 bit GP relative reloc. */ 12505 12506 static void 12507 s_gpword (int ignore ATTRIBUTE_UNUSED) 12508 { 12509 symbolS *label; 12510 expressionS ex; 12511 char *p; 12512 12513 /* When not generating PIC code, this is treated as .word. */ 12514 if (mips_pic != SVR4_PIC) 12515 { 12516 s_cons (2); 12517 return; 12518 } 12519 12520 label = insn_labels != NULL ? insn_labels->label : NULL; 12521 mips_emit_delays (TRUE); 12522 if (auto_align) 12523 mips_align (2, 0, label); 12524 mips_clear_insn_labels (); 12525 12526 expression (&ex); 12527 12528 if (ex.X_op != O_symbol || ex.X_add_number != 0) 12529 { 12530 as_bad (_("Unsupported use of .gpword")); 12531 ignore_rest_of_line (); 12532 } 12533 12534 p = frag_more (4); 12535 md_number_to_chars (p, 0, 4); 12536 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 12537 BFD_RELOC_GPREL32); 12538 12539 demand_empty_rest_of_line (); 12540 } 12541 12542 static void 12543 s_gpdword (int ignore ATTRIBUTE_UNUSED) 12544 { 12545 symbolS *label; 12546 expressionS ex; 12547 char *p; 12548 12549 /* When not generating PIC code, this is treated as .dword. */ 12550 if (mips_pic != SVR4_PIC) 12551 { 12552 s_cons (3); 12553 return; 12554 } 12555 12556 label = insn_labels != NULL ? insn_labels->label : NULL; 12557 mips_emit_delays (TRUE); 12558 if (auto_align) 12559 mips_align (3, 0, label); 12560 mips_clear_insn_labels (); 12561 12562 expression (&ex); 12563 12564 if (ex.X_op != O_symbol || ex.X_add_number != 0) 12565 { 12566 as_bad (_("Unsupported use of .gpdword")); 12567 ignore_rest_of_line (); 12568 } 12569 12570 p = frag_more (8); 12571 md_number_to_chars (p, 0, 8); 12572 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 12573 BFD_RELOC_GPREL32); 12574 12575 /* GPREL32 composed with 64 gives a 64-bit GP offset. */ 12576 ex.X_op = O_absent; 12577 ex.X_add_symbol = 0; 12578 ex.X_add_number = 0; 12579 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, 12580 BFD_RELOC_64); 12581 12582 demand_empty_rest_of_line (); 12583 } 12584 12585 /* Handle the .cpadd pseudo-op. This is used when dealing with switch 12586 tables in SVR4 PIC code. */ 12587 12588 static void 12589 s_cpadd (int ignore ATTRIBUTE_UNUSED) 12590 { 12591 int reg; 12592 12593 /* This is ignored when not generating SVR4 PIC code. */ 12594 if (mips_pic != SVR4_PIC) 12595 { 12596 s_ignore (0); 12597 return; 12598 } 12599 12600 /* Add $gp to the register named as an argument. */ 12601 macro_start (); 12602 reg = tc_get_register (0); 12603 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); 12604 macro_end (); 12605 12606 demand_empty_rest_of_line (); 12607 } 12608 12609 /* Handle the .insn pseudo-op. This marks instruction labels in 12610 mips16 mode. This permits the linker to handle them specially, 12611 such as generating jalx instructions when needed. We also make 12612 them odd for the duration of the assembly, in order to generate the 12613 right sort of code. We will make them even in the adjust_symtab 12614 routine, while leaving them marked. This is convenient for the 12615 debugger and the disassembler. The linker knows to make them odd 12616 again. */ 12617 12618 static void 12619 s_insn (int ignore ATTRIBUTE_UNUSED) 12620 { 12621 mips16_mark_labels (); 12622 12623 demand_empty_rest_of_line (); 12624 } 12625 12626 /* Handle a .stabn directive. We need these in order to mark a label 12627 as being a mips16 text label correctly. Sometimes the compiler 12628 will emit a label, followed by a .stabn, and then switch sections. 12629 If the label and .stabn are in mips16 mode, then the label is 12630 really a mips16 text label. */ 12631 12632 static void 12633 s_mips_stab (int type) 12634 { 12635 if (type == 'n') 12636 mips16_mark_labels (); 12637 12638 s_stab (type); 12639 } 12640 12641 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. 12642 */ 12643 12644 static void 12645 s_mips_weakext (int ignore ATTRIBUTE_UNUSED) 12646 { 12647 char *name; 12648 int c; 12649 symbolS *symbolP; 12650 expressionS exp; 12651 12652 name = input_line_pointer; 12653 c = get_symbol_end (); 12654 symbolP = symbol_find_or_make (name); 12655 S_SET_WEAK (symbolP); 12656 *input_line_pointer = c; 12657 12658 SKIP_WHITESPACE (); 12659 12660 if (! is_end_of_line[(unsigned char) *input_line_pointer]) 12661 { 12662 if (S_IS_DEFINED (symbolP)) 12663 { 12664 as_bad ("ignoring attempt to redefine symbol %s", 12665 S_GET_NAME (symbolP)); 12666 ignore_rest_of_line (); 12667 return; 12668 } 12669 12670 if (*input_line_pointer == ',') 12671 { 12672 ++input_line_pointer; 12673 SKIP_WHITESPACE (); 12674 } 12675 12676 expression (&exp); 12677 if (exp.X_op != O_symbol) 12678 { 12679 as_bad ("bad .weakext directive"); 12680 ignore_rest_of_line (); 12681 return; 12682 } 12683 symbol_set_value_expression (symbolP, &exp); 12684 } 12685 12686 demand_empty_rest_of_line (); 12687 } 12688 12689 /* Parse a register string into a number. Called from the ECOFF code 12690 to parse .frame. The argument is non-zero if this is the frame 12691 register, so that we can record it in mips_frame_reg. */ 12692 12693 int 12694 tc_get_register (int frame) 12695 { 12696 unsigned int reg; 12697 12698 SKIP_WHITESPACE (); 12699 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) 12700 reg = 0; 12701 if (frame) 12702 { 12703 mips_frame_reg = reg != 0 ? reg : SP; 12704 mips_frame_reg_valid = 1; 12705 mips_cprestore_valid = 0; 12706 } 12707 return reg; 12708 } 12709 12710 valueT 12711 md_section_align (asection *seg, valueT addr) 12712 { 12713 int align = bfd_get_section_alignment (stdoutput, seg); 12714 12715 #ifdef OBJ_ELF 12716 /* We don't need to align ELF sections to the full alignment. 12717 However, Irix 5 may prefer that we align them at least to a 16 12718 byte boundary. We don't bother to align the sections if we are 12719 targeted for an embedded system. */ 12720 if (strcmp (TARGET_OS, "elf") == 0) 12721 return addr; 12722 if (align > 4) 12723 align = 4; 12724 #endif 12725 12726 return ((addr + (1 << align) - 1) & (-1 << align)); 12727 } 12728 12729 /* Utility routine, called from above as well. If called while the 12730 input file is still being read, it's only an approximation. (For 12731 example, a symbol may later become defined which appeared to be 12732 undefined earlier.) */ 12733 12734 static int 12735 nopic_need_relax (symbolS *sym, int before_relaxing) 12736 { 12737 if (sym == 0) 12738 return 0; 12739 12740 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) 12741 { 12742 const char *symname; 12743 int change; 12744 12745 /* Find out whether this symbol can be referenced off the $gp 12746 register. It can be if it is smaller than the -G size or if 12747 it is in the .sdata or .sbss section. Certain symbols can 12748 not be referenced off the $gp, although it appears as though 12749 they can. */ 12750 symname = S_GET_NAME (sym); 12751 if (symname != (const char *) NULL 12752 && (strcmp (symname, "eprol") == 0 12753 || strcmp (symname, "etext") == 0 12754 || strcmp (symname, "_gp") == 0 12755 || strcmp (symname, "edata") == 0 12756 || strcmp (symname, "_fbss") == 0 12757 || strcmp (symname, "_fdata") == 0 12758 || strcmp (symname, "_ftext") == 0 12759 || strcmp (symname, "end") == 0 12760 || strcmp (symname, "_gp_disp") == 0)) 12761 change = 1; 12762 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) 12763 && (0 12764 #ifndef NO_ECOFF_DEBUGGING 12765 || (symbol_get_obj (sym)->ecoff_extern_size != 0 12766 && (symbol_get_obj (sym)->ecoff_extern_size 12767 <= g_switch_value)) 12768 #endif 12769 /* We must defer this decision until after the whole 12770 file has been read, since there might be a .extern 12771 after the first use of this symbol. */ 12772 || (before_relaxing 12773 #ifndef NO_ECOFF_DEBUGGING 12774 && symbol_get_obj (sym)->ecoff_extern_size == 0 12775 #endif 12776 && S_GET_VALUE (sym) == 0) 12777 || (S_GET_VALUE (sym) != 0 12778 && S_GET_VALUE (sym) <= g_switch_value))) 12779 change = 0; 12780 else 12781 { 12782 const char *segname; 12783 12784 segname = segment_name (S_GET_SEGMENT (sym)); 12785 assert (strcmp (segname, ".lit8") != 0 12786 && strcmp (segname, ".lit4") != 0); 12787 change = (strcmp (segname, ".sdata") != 0 12788 && strcmp (segname, ".sbss") != 0 12789 && strncmp (segname, ".sdata.", 7) != 0 12790 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); 12791 } 12792 return change; 12793 } 12794 else 12795 /* We are not optimizing for the $gp register. */ 12796 return 1; 12797 } 12798 12799 12800 /* Return true if the given symbol should be considered local for SVR4 PIC. */ 12801 12802 static bfd_boolean 12803 pic_need_relax (symbolS *sym, asection *segtype) 12804 { 12805 asection *symsec; 12806 bfd_boolean linkonce; 12807 12808 /* Handle the case of a symbol equated to another symbol. */ 12809 while (symbol_equated_reloc_p (sym)) 12810 { 12811 symbolS *n; 12812 12813 /* It's possible to get a loop here in a badly written 12814 program. */ 12815 n = symbol_get_value_expression (sym)->X_add_symbol; 12816 if (n == sym) 12817 break; 12818 sym = n; 12819 } 12820 12821 symsec = S_GET_SEGMENT (sym); 12822 12823 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ 12824 linkonce = FALSE; 12825 if (symsec != segtype && ! S_IS_LOCAL (sym)) 12826 { 12827 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) 12828 != 0) 12829 linkonce = TRUE; 12830 12831 /* The GNU toolchain uses an extension for ELF: a section 12832 beginning with the magic string .gnu.linkonce is a linkonce 12833 section. */ 12834 if (strncmp (segment_name (symsec), ".gnu.linkonce", 12835 sizeof ".gnu.linkonce" - 1) == 0) 12836 linkonce = TRUE; 12837 } 12838 12839 /* This must duplicate the test in adjust_reloc_syms. */ 12840 return (symsec != &bfd_und_section 12841 && symsec != &bfd_abs_section 12842 && ! bfd_is_com_section (symsec) 12843 && !linkonce 12844 #ifdef OBJ_ELF 12845 /* A global or weak symbol is treated as external. */ 12846 && (OUTPUT_FLAVOR != bfd_target_elf_flavour 12847 || (! S_IS_WEAK (sym) 12848 && (! S_IS_EXTERNAL (sym) 12849 || mips_pic == EMBEDDED_PIC))) 12850 #endif 12851 ); 12852 } 12853 12854 12855 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an 12856 extended opcode. SEC is the section the frag is in. */ 12857 12858 static int 12859 mips16_extended_frag (fragS *fragp, asection *sec, long stretch) 12860 { 12861 int type; 12862 register const struct mips16_immed_operand *op; 12863 offsetT val; 12864 int mintiny, maxtiny; 12865 segT symsec; 12866 fragS *sym_frag; 12867 12868 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 12869 return 0; 12870 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 12871 return 1; 12872 12873 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 12874 op = mips16_immed_operands; 12875 while (op->type != type) 12876 { 12877 ++op; 12878 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); 12879 } 12880 12881 if (op->unsp) 12882 { 12883 if (type == '<' || type == '>' || type == '[' || type == ']') 12884 { 12885 mintiny = 1; 12886 maxtiny = 1 << op->nbits; 12887 } 12888 else 12889 { 12890 mintiny = 0; 12891 maxtiny = (1 << op->nbits) - 1; 12892 } 12893 } 12894 else 12895 { 12896 mintiny = - (1 << (op->nbits - 1)); 12897 maxtiny = (1 << (op->nbits - 1)) - 1; 12898 } 12899 12900 sym_frag = symbol_get_frag (fragp->fr_symbol); 12901 val = S_GET_VALUE (fragp->fr_symbol); 12902 symsec = S_GET_SEGMENT (fragp->fr_symbol); 12903 12904 if (op->pcrel) 12905 { 12906 addressT addr; 12907 12908 /* We won't have the section when we are called from 12909 mips_relax_frag. However, we will always have been called 12910 from md_estimate_size_before_relax first. If this is a 12911 branch to a different section, we mark it as such. If SEC is 12912 NULL, and the frag is not marked, then it must be a branch to 12913 the same section. */ 12914 if (sec == NULL) 12915 { 12916 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) 12917 return 1; 12918 } 12919 else 12920 { 12921 /* Must have been called from md_estimate_size_before_relax. */ 12922 if (symsec != sec) 12923 { 12924 fragp->fr_subtype = 12925 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 12926 12927 /* FIXME: We should support this, and let the linker 12928 catch branches and loads that are out of range. */ 12929 as_bad_where (fragp->fr_file, fragp->fr_line, 12930 _("unsupported PC relative reference to different section")); 12931 12932 return 1; 12933 } 12934 if (fragp != sym_frag && sym_frag->fr_address == 0) 12935 /* Assume non-extended on the first relaxation pass. 12936 The address we have calculated will be bogus if this is 12937 a forward branch to another frag, as the forward frag 12938 will have fr_address == 0. */ 12939 return 0; 12940 } 12941 12942 /* In this case, we know for sure that the symbol fragment is in 12943 the same section. If the relax_marker of the symbol fragment 12944 differs from the relax_marker of this fragment, we have not 12945 yet adjusted the symbol fragment fr_address. We want to add 12946 in STRETCH in order to get a better estimate of the address. 12947 This particularly matters because of the shift bits. */ 12948 if (stretch != 0 12949 && sym_frag->relax_marker != fragp->relax_marker) 12950 { 12951 fragS *f; 12952 12953 /* Adjust stretch for any alignment frag. Note that if have 12954 been expanding the earlier code, the symbol may be 12955 defined in what appears to be an earlier frag. FIXME: 12956 This doesn't handle the fr_subtype field, which specifies 12957 a maximum number of bytes to skip when doing an 12958 alignment. */ 12959 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) 12960 { 12961 if (f->fr_type == rs_align || f->fr_type == rs_align_code) 12962 { 12963 if (stretch < 0) 12964 stretch = - ((- stretch) 12965 & ~ ((1 << (int) f->fr_offset) - 1)); 12966 else 12967 stretch &= ~ ((1 << (int) f->fr_offset) - 1); 12968 if (stretch == 0) 12969 break; 12970 } 12971 } 12972 if (f != NULL) 12973 val += stretch; 12974 } 12975 12976 addr = fragp->fr_address + fragp->fr_fix; 12977 12978 /* The base address rules are complicated. The base address of 12979 a branch is the following instruction. The base address of a 12980 PC relative load or add is the instruction itself, but if it 12981 is in a delay slot (in which case it can not be extended) use 12982 the address of the instruction whose delay slot it is in. */ 12983 if (type == 'p' || type == 'q') 12984 { 12985 addr += 2; 12986 12987 /* If we are currently assuming that this frag should be 12988 extended, then, the current address is two bytes 12989 higher. */ 12990 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 12991 addr += 2; 12992 12993 /* Ignore the low bit in the target, since it will be set 12994 for a text label. */ 12995 if ((val & 1) != 0) 12996 --val; 12997 } 12998 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 12999 addr -= 4; 13000 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 13001 addr -= 2; 13002 13003 val -= addr & ~ ((1 << op->shift) - 1); 13004 13005 /* Branch offsets have an implicit 0 in the lowest bit. */ 13006 if (type == 'p' || type == 'q') 13007 val /= 2; 13008 13009 /* If any of the shifted bits are set, we must use an extended 13010 opcode. If the address depends on the size of this 13011 instruction, this can lead to a loop, so we arrange to always 13012 use an extended opcode. We only check this when we are in 13013 the main relaxation loop, when SEC is NULL. */ 13014 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) 13015 { 13016 fragp->fr_subtype = 13017 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 13018 return 1; 13019 } 13020 13021 /* If we are about to mark a frag as extended because the value 13022 is precisely maxtiny + 1, then there is a chance of an 13023 infinite loop as in the following code: 13024 la $4,foo 13025 .skip 1020 13026 .align 2 13027 foo: 13028 In this case when the la is extended, foo is 0x3fc bytes 13029 away, so the la can be shrunk, but then foo is 0x400 away, so 13030 the la must be extended. To avoid this loop, we mark the 13031 frag as extended if it was small, and is about to become 13032 extended with a value of maxtiny + 1. */ 13033 if (val == ((maxtiny + 1) << op->shift) 13034 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) 13035 && sec == NULL) 13036 { 13037 fragp->fr_subtype = 13038 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 13039 return 1; 13040 } 13041 } 13042 else if (symsec != absolute_section && sec != NULL) 13043 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); 13044 13045 if ((val & ((1 << op->shift) - 1)) != 0 13046 || val < (mintiny << op->shift) 13047 || val > (maxtiny << op->shift)) 13048 return 1; 13049 else 13050 return 0; 13051 } 13052 13053 /* Compute the length of a branch sequence, and adjust the 13054 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the 13055 worst-case length is computed, with UPDATE being used to indicate 13056 whether an unconditional (-1), branch-likely (+1) or regular (0) 13057 branch is to be computed. */ 13058 static int 13059 relaxed_branch_length (fragS *fragp, asection *sec, int update) 13060 { 13061 bfd_boolean toofar; 13062 int length; 13063 13064 if (fragp 13065 && S_IS_DEFINED (fragp->fr_symbol) 13066 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 13067 { 13068 addressT addr; 13069 offsetT val; 13070 13071 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 13072 13073 addr = fragp->fr_address + fragp->fr_fix + 4; 13074 13075 val -= addr; 13076 13077 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); 13078 } 13079 else if (fragp) 13080 /* If the symbol is not defined or it's in a different segment, 13081 assume the user knows what's going on and emit a short 13082 branch. */ 13083 toofar = FALSE; 13084 else 13085 toofar = TRUE; 13086 13087 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 13088 fragp->fr_subtype 13089 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), 13090 RELAX_BRANCH_LIKELY (fragp->fr_subtype), 13091 RELAX_BRANCH_LINK (fragp->fr_subtype), 13092 toofar); 13093 13094 length = 4; 13095 if (toofar) 13096 { 13097 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) 13098 length += 8; 13099 13100 if (mips_pic != NO_PIC) 13101 { 13102 /* Additional space for PIC loading of target address. */ 13103 length += 8; 13104 if (mips_opts.isa == ISA_MIPS1) 13105 /* Additional space for $at-stabilizing nop. */ 13106 length += 4; 13107 } 13108 13109 /* If branch is conditional. */ 13110 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) 13111 length += 8; 13112 } 13113 13114 return length; 13115 } 13116 13117 /* Estimate the size of a frag before relaxing. Unless this is the 13118 mips16, we are not really relaxing here, and the final size is 13119 encoded in the subtype information. For the mips16, we have to 13120 decide whether we are using an extended opcode or not. */ 13121 13122 int 13123 md_estimate_size_before_relax (fragS *fragp, asection *segtype) 13124 { 13125 int change; 13126 13127 if (RELAX_BRANCH_P (fragp->fr_subtype)) 13128 { 13129 13130 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); 13131 13132 return fragp->fr_var; 13133 } 13134 13135 if (RELAX_MIPS16_P (fragp->fr_subtype)) 13136 /* We don't want to modify the EXTENDED bit here; it might get us 13137 into infinite loops. We change it only in mips_relax_frag(). */ 13138 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); 13139 13140 if (mips_pic == NO_PIC) 13141 change = nopic_need_relax (fragp->fr_symbol, 0); 13142 else if (mips_pic == SVR4_PIC) 13143 change = pic_need_relax (fragp->fr_symbol, segtype); 13144 else 13145 abort (); 13146 13147 if (change) 13148 { 13149 fragp->fr_subtype |= RELAX_USE_SECOND; 13150 return -RELAX_FIRST (fragp->fr_subtype); 13151 } 13152 else 13153 return -RELAX_SECOND (fragp->fr_subtype); 13154 } 13155 13156 /* This is called to see whether a reloc against a defined symbol 13157 should be converted into a reloc against a section. Don't adjust 13158 MIPS16 jump relocations, so we don't have to worry about the format 13159 of the offset in the .o file. Don't adjust relocations against 13160 mips16 symbols, so that the linker can find them if it needs to set 13161 up a stub. */ 13162 13163 int 13164 mips_fix_adjustable (fixS *fixp) 13165 { 13166 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) 13167 return 0; 13168 13169 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 13170 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 13171 return 0; 13172 13173 if (fixp->fx_addsy == NULL) 13174 return 1; 13175 13176 #ifdef OBJ_ELF 13177 if (OUTPUT_FLAVOR == bfd_target_elf_flavour 13178 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 13179 && fixp->fx_subsy == NULL) 13180 return 0; 13181 #endif 13182 13183 return 1; 13184 } 13185 13186 /* Translate internal representation of relocation info to BFD target 13187 format. */ 13188 13189 arelent ** 13190 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 13191 { 13192 static arelent *retval[4]; 13193 arelent *reloc; 13194 bfd_reloc_code_real_type code; 13195 13196 memset (retval, 0, sizeof(retval)); 13197 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); 13198 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 13199 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 13200 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 13201 13202 if (mips_pic == EMBEDDED_PIC 13203 && SWITCH_TABLE (fixp)) 13204 { 13205 /* For a switch table entry we use a special reloc. The addend 13206 is actually the difference between the reloc address and the 13207 subtrahend. */ 13208 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); 13209 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) 13210 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); 13211 fixp->fx_r_type = BFD_RELOC_GPREL32; 13212 } 13213 else if (fixp->fx_pcrel) 13214 { 13215 bfd_vma pcrel_address; 13216 13217 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high 13218 high-part relocs is the address of the low-part reloc. */ 13219 if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) 13220 { 13221 assert (fixp->fx_next != NULL 13222 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); 13223 pcrel_address = (fixp->fx_next->fx_where 13224 + fixp->fx_next->fx_frag->fr_address); 13225 } 13226 else 13227 pcrel_address = reloc->address; 13228 13229 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 13230 { 13231 /* At this point, fx_addnumber is "symbol offset - pcrel_address". 13232 Relocations want only the symbol offset. */ 13233 reloc->addend = fixp->fx_addnumber + pcrel_address; 13234 } 13235 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16 13236 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) 13237 { 13238 /* We use a special addend for an internal RELLO or RELHI reloc. */ 13239 if (symbol_section_p (fixp->fx_addsy)) 13240 reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy); 13241 else 13242 reloc->addend = fixp->fx_addnumber + pcrel_address; 13243 } 13244 else 13245 { 13246 if (OUTPUT_FLAVOR != bfd_target_aout_flavour) 13247 /* A gruesome hack which is a result of the gruesome gas reloc 13248 handling. */ 13249 reloc->addend = pcrel_address; 13250 else 13251 reloc->addend = -pcrel_address; 13252 } 13253 } 13254 else 13255 reloc->addend = fixp->fx_addnumber; 13256 13257 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable 13258 entry to be used in the relocation's section offset. */ 13259 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 13260 { 13261 reloc->address = reloc->addend; 13262 reloc->addend = 0; 13263 } 13264 13265 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that 13266 fixup_segment converted a non-PC relative reloc into a PC 13267 relative reloc. In such a case, we need to convert the reloc 13268 code. */ 13269 code = fixp->fx_r_type; 13270 if (fixp->fx_pcrel) 13271 { 13272 switch (code) 13273 { 13274 case BFD_RELOC_8: 13275 code = BFD_RELOC_8_PCREL; 13276 break; 13277 case BFD_RELOC_16: 13278 code = BFD_RELOC_16_PCREL; 13279 break; 13280 case BFD_RELOC_32: 13281 code = BFD_RELOC_32_PCREL; 13282 break; 13283 case BFD_RELOC_64: 13284 code = BFD_RELOC_64_PCREL; 13285 break; 13286 case BFD_RELOC_8_PCREL: 13287 case BFD_RELOC_16_PCREL: 13288 case BFD_RELOC_32_PCREL: 13289 case BFD_RELOC_64_PCREL: 13290 case BFD_RELOC_16_PCREL_S2: 13291 case BFD_RELOC_PCREL_HI16_S: 13292 case BFD_RELOC_PCREL_LO16: 13293 break; 13294 default: 13295 as_bad_where (fixp->fx_file, fixp->fx_line, 13296 _("Cannot make %s relocation PC relative"), 13297 bfd_get_reloc_code_name (code)); 13298 } 13299 } 13300 13301 /* To support a PC relative reloc when generating embedded PIC code 13302 for ECOFF, we use a Cygnus extension. We check for that here to 13303 make sure that we don't let such a reloc escape normally. */ 13304 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour 13305 || OUTPUT_FLAVOR == bfd_target_elf_flavour) 13306 && code == BFD_RELOC_16_PCREL_S2 13307 && mips_pic != EMBEDDED_PIC) 13308 reloc->howto = NULL; 13309 else 13310 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 13311 13312 if (reloc->howto == NULL) 13313 { 13314 as_bad_where (fixp->fx_file, fixp->fx_line, 13315 _("Can not represent %s relocation in this object file format"), 13316 bfd_get_reloc_code_name (code)); 13317 retval[0] = NULL; 13318 } 13319 13320 return retval; 13321 } 13322 13323 /* Relax a machine dependent frag. This returns the amount by which 13324 the current size of the frag should change. */ 13325 13326 int 13327 mips_relax_frag (asection *sec, fragS *fragp, long stretch) 13328 { 13329 if (RELAX_BRANCH_P (fragp->fr_subtype)) 13330 { 13331 offsetT old_var = fragp->fr_var; 13332 13333 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); 13334 13335 return fragp->fr_var - old_var; 13336 } 13337 13338 if (! RELAX_MIPS16_P (fragp->fr_subtype)) 13339 return 0; 13340 13341 if (mips16_extended_frag (fragp, NULL, stretch)) 13342 { 13343 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 13344 return 0; 13345 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); 13346 return 2; 13347 } 13348 else 13349 { 13350 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 13351 return 0; 13352 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); 13353 return -2; 13354 } 13355 13356 return 0; 13357 } 13358 13359 /* Convert a machine dependent frag. */ 13360 13361 void 13362 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) 13363 { 13364 if (RELAX_BRANCH_P (fragp->fr_subtype)) 13365 { 13366 bfd_byte *buf; 13367 unsigned long insn; 13368 expressionS exp; 13369 fixS *fixp; 13370 13371 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; 13372 13373 if (target_big_endian) 13374 insn = bfd_getb32 (buf); 13375 else 13376 insn = bfd_getl32 (buf); 13377 13378 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 13379 { 13380 /* We generate a fixup instead of applying it right now 13381 because, if there are linker relaxations, we're going to 13382 need the relocations. */ 13383 exp.X_op = O_symbol; 13384 exp.X_add_symbol = fragp->fr_symbol; 13385 exp.X_add_number = fragp->fr_offset; 13386 13387 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 13388 4, &exp, 1, 13389 BFD_RELOC_16_PCREL_S2); 13390 fixp->fx_file = fragp->fr_file; 13391 fixp->fx_line = fragp->fr_line; 13392 13393 md_number_to_chars (buf, insn, 4); 13394 buf += 4; 13395 } 13396 else 13397 { 13398 int i; 13399 13400 as_warn_where (fragp->fr_file, fragp->fr_line, 13401 _("relaxed out-of-range branch into a jump")); 13402 13403 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) 13404 goto uncond; 13405 13406 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 13407 { 13408 /* Reverse the branch. */ 13409 switch ((insn >> 28) & 0xf) 13410 { 13411 case 4: 13412 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can 13413 have the condition reversed by tweaking a single 13414 bit, and their opcodes all have 0x4???????. */ 13415 assert ((insn & 0xf1000000) == 0x41000000); 13416 insn ^= 0x00010000; 13417 break; 13418 13419 case 0: 13420 /* bltz 0x04000000 bgez 0x04010000 13421 bltzal 0x04100000 bgezal 0x04110000 */ 13422 assert ((insn & 0xfc0e0000) == 0x04000000); 13423 insn ^= 0x00010000; 13424 break; 13425 13426 case 1: 13427 /* beq 0x10000000 bne 0x14000000 13428 blez 0x18000000 bgtz 0x1c000000 */ 13429 insn ^= 0x04000000; 13430 break; 13431 13432 default: 13433 abort (); 13434 } 13435 } 13436 13437 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 13438 { 13439 /* Clear the and-link bit. */ 13440 assert ((insn & 0xfc1c0000) == 0x04100000); 13441 13442 /* bltzal 0x04100000 bgezal 0x04110000 13443 bltzall 0x04120000 bgezall 0x04130000 */ 13444 insn &= ~0x00100000; 13445 } 13446 13447 /* Branch over the branch (if the branch was likely) or the 13448 full jump (not likely case). Compute the offset from the 13449 current instruction to branch to. */ 13450 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 13451 i = 16; 13452 else 13453 { 13454 /* How many bytes in instructions we've already emitted? */ 13455 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; 13456 /* How many bytes in instructions from here to the end? */ 13457 i = fragp->fr_var - i; 13458 } 13459 /* Convert to instruction count. */ 13460 i >>= 2; 13461 /* Branch counts from the next instruction. */ 13462 i--; 13463 insn |= i; 13464 /* Branch over the jump. */ 13465 md_number_to_chars (buf, insn, 4); 13466 buf += 4; 13467 13468 /* Nop */ 13469 md_number_to_chars (buf, 0, 4); 13470 buf += 4; 13471 13472 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 13473 { 13474 /* beql $0, $0, 2f */ 13475 insn = 0x50000000; 13476 /* Compute the PC offset from the current instruction to 13477 the end of the variable frag. */ 13478 /* How many bytes in instructions we've already emitted? */ 13479 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; 13480 /* How many bytes in instructions from here to the end? */ 13481 i = fragp->fr_var - i; 13482 /* Convert to instruction count. */ 13483 i >>= 2; 13484 /* Don't decrement i, because we want to branch over the 13485 delay slot. */ 13486 13487 insn |= i; 13488 md_number_to_chars (buf, insn, 4); 13489 buf += 4; 13490 13491 md_number_to_chars (buf, 0, 4); 13492 buf += 4; 13493 } 13494 13495 uncond: 13496 if (mips_pic == NO_PIC) 13497 { 13498 /* j or jal. */ 13499 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) 13500 ? 0x0c000000 : 0x08000000); 13501 exp.X_op = O_symbol; 13502 exp.X_add_symbol = fragp->fr_symbol; 13503 exp.X_add_number = fragp->fr_offset; 13504 13505 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 13506 4, &exp, 0, BFD_RELOC_MIPS_JMP); 13507 fixp->fx_file = fragp->fr_file; 13508 fixp->fx_line = fragp->fr_line; 13509 13510 md_number_to_chars (buf, insn, 4); 13511 buf += 4; 13512 } 13513 else 13514 { 13515 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ 13516 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; 13517 exp.X_op = O_symbol; 13518 exp.X_add_symbol = fragp->fr_symbol; 13519 exp.X_add_number = fragp->fr_offset; 13520 13521 if (fragp->fr_offset) 13522 { 13523 exp.X_add_symbol = make_expr_symbol (&exp); 13524 exp.X_add_number = 0; 13525 } 13526 13527 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 13528 4, &exp, 0, BFD_RELOC_MIPS_GOT16); 13529 fixp->fx_file = fragp->fr_file; 13530 fixp->fx_line = fragp->fr_line; 13531 13532 md_number_to_chars (buf, insn, 4); 13533 buf += 4; 13534 13535 if (mips_opts.isa == ISA_MIPS1) 13536 { 13537 /* nop */ 13538 md_number_to_chars (buf, 0, 4); 13539 buf += 4; 13540 } 13541 13542 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ 13543 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; 13544 13545 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 13546 4, &exp, 0, BFD_RELOC_LO16); 13547 fixp->fx_file = fragp->fr_file; 13548 fixp->fx_line = fragp->fr_line; 13549 13550 md_number_to_chars (buf, insn, 4); 13551 buf += 4; 13552 13553 /* j(al)r $at. */ 13554 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 13555 insn = 0x0020f809; 13556 else 13557 insn = 0x00200008; 13558 13559 md_number_to_chars (buf, insn, 4); 13560 buf += 4; 13561 } 13562 } 13563 13564 assert (buf == (bfd_byte *)fragp->fr_literal 13565 + fragp->fr_fix + fragp->fr_var); 13566 13567 fragp->fr_fix += fragp->fr_var; 13568 13569 return; 13570 } 13571 13572 if (RELAX_MIPS16_P (fragp->fr_subtype)) 13573 { 13574 int type; 13575 register const struct mips16_immed_operand *op; 13576 bfd_boolean small, ext; 13577 offsetT val; 13578 bfd_byte *buf; 13579 unsigned long insn; 13580 bfd_boolean use_extend; 13581 unsigned short extend; 13582 13583 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 13584 op = mips16_immed_operands; 13585 while (op->type != type) 13586 ++op; 13587 13588 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 13589 { 13590 small = FALSE; 13591 ext = TRUE; 13592 } 13593 else 13594 { 13595 small = TRUE; 13596 ext = FALSE; 13597 } 13598 13599 resolve_symbol_value (fragp->fr_symbol); 13600 val = S_GET_VALUE (fragp->fr_symbol); 13601 if (op->pcrel) 13602 { 13603 addressT addr; 13604 13605 addr = fragp->fr_address + fragp->fr_fix; 13606 13607 /* The rules for the base address of a PC relative reloc are 13608 complicated; see mips16_extended_frag. */ 13609 if (type == 'p' || type == 'q') 13610 { 13611 addr += 2; 13612 if (ext) 13613 addr += 2; 13614 /* Ignore the low bit in the target, since it will be 13615 set for a text label. */ 13616 if ((val & 1) != 0) 13617 --val; 13618 } 13619 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 13620 addr -= 4; 13621 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 13622 addr -= 2; 13623 13624 addr &= ~ (addressT) ((1 << op->shift) - 1); 13625 val -= addr; 13626 13627 /* Make sure the section winds up with the alignment we have 13628 assumed. */ 13629 if (op->shift > 0) 13630 record_alignment (asec, op->shift); 13631 } 13632 13633 if (ext 13634 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) 13635 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) 13636 as_warn_where (fragp->fr_file, fragp->fr_line, 13637 _("extended instruction in delay slot")); 13638 13639 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); 13640 13641 if (target_big_endian) 13642 insn = bfd_getb16 (buf); 13643 else 13644 insn = bfd_getl16 (buf); 13645 13646 mips16_immed (fragp->fr_file, fragp->fr_line, type, val, 13647 RELAX_MIPS16_USER_EXT (fragp->fr_subtype), 13648 small, ext, &insn, &use_extend, &extend); 13649 13650 if (use_extend) 13651 { 13652 md_number_to_chars (buf, 0xf000 | extend, 2); 13653 fragp->fr_fix += 2; 13654 buf += 2; 13655 } 13656 13657 md_number_to_chars (buf, insn, 2); 13658 fragp->fr_fix += 2; 13659 buf += 2; 13660 } 13661 else 13662 { 13663 int first, second; 13664 fixS *fixp; 13665 13666 first = RELAX_FIRST (fragp->fr_subtype); 13667 second = RELAX_SECOND (fragp->fr_subtype); 13668 fixp = (fixS *) fragp->fr_opcode; 13669 13670 /* Possibly emit a warning if we've chosen the longer option. */ 13671 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) 13672 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) 13673 { 13674 const char *msg = macro_warning (fragp->fr_subtype); 13675 if (msg != 0) 13676 as_warn_where (fragp->fr_file, fragp->fr_line, msg); 13677 } 13678 13679 /* Go through all the fixups for the first sequence. Disable them 13680 (by marking them as done) if we're going to use the second 13681 sequence instead. */ 13682 while (fixp 13683 && fixp->fx_frag == fragp 13684 && fixp->fx_where < fragp->fr_fix - second) 13685 { 13686 if (fragp->fr_subtype & RELAX_USE_SECOND) 13687 fixp->fx_done = 1; 13688 fixp = fixp->fx_next; 13689 } 13690 13691 /* Go through the fixups for the second sequence. Disable them if 13692 we're going to use the first sequence, otherwise adjust their 13693 addresses to account for the relaxation. */ 13694 while (fixp && fixp->fx_frag == fragp) 13695 { 13696 if (fragp->fr_subtype & RELAX_USE_SECOND) 13697 fixp->fx_where -= first; 13698 else 13699 fixp->fx_done = 1; 13700 fixp = fixp->fx_next; 13701 } 13702 13703 /* Now modify the frag contents. */ 13704 if (fragp->fr_subtype & RELAX_USE_SECOND) 13705 { 13706 char *start; 13707 13708 start = fragp->fr_literal + fragp->fr_fix - first - second; 13709 memmove (start, start + first, second); 13710 fragp->fr_fix -= first; 13711 } 13712 else 13713 fragp->fr_fix -= second; 13714 } 13715 } 13716 13717 #ifdef OBJ_ELF 13718 13719 /* This function is called after the relocs have been generated. 13720 We've been storing mips16 text labels as odd. Here we convert them 13721 back to even for the convenience of the debugger. */ 13722 13723 void 13724 mips_frob_file_after_relocs (void) 13725 { 13726 asymbol **syms; 13727 unsigned int count, i; 13728 13729 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 13730 return; 13731 13732 syms = bfd_get_outsymbols (stdoutput); 13733 count = bfd_get_symcount (stdoutput); 13734 for (i = 0; i < count; i++, syms++) 13735 { 13736 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 13737 && ((*syms)->value & 1) != 0) 13738 { 13739 (*syms)->value &= ~1; 13740 /* If the symbol has an odd size, it was probably computed 13741 incorrectly, so adjust that as well. */ 13742 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) 13743 ++elf_symbol (*syms)->internal_elf_sym.st_size; 13744 } 13745 } 13746 } 13747 13748 #endif 13749 13750 /* This function is called whenever a label is defined. It is used 13751 when handling branch delays; if a branch has a label, we assume we 13752 can not move it. */ 13753 13754 void 13755 mips_define_label (symbolS *sym) 13756 { 13757 struct insn_label_list *l; 13758 13759 if (free_insn_labels == NULL) 13760 l = (struct insn_label_list *) xmalloc (sizeof *l); 13761 else 13762 { 13763 l = free_insn_labels; 13764 free_insn_labels = l->next; 13765 } 13766 13767 l->label = sym; 13768 l->next = insn_labels; 13769 insn_labels = l; 13770 } 13771 13772 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 13773 13774 /* Some special processing for a MIPS ELF file. */ 13775 13776 void 13777 mips_elf_final_processing (void) 13778 { 13779 /* Write out the register information. */ 13780 if (mips_abi != N64_ABI) 13781 { 13782 Elf32_RegInfo s; 13783 13784 s.ri_gprmask = mips_gprmask; 13785 s.ri_cprmask[0] = mips_cprmask[0]; 13786 s.ri_cprmask[1] = mips_cprmask[1]; 13787 s.ri_cprmask[2] = mips_cprmask[2]; 13788 s.ri_cprmask[3] = mips_cprmask[3]; 13789 /* The gp_value field is set by the MIPS ELF backend. */ 13790 13791 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, 13792 ((Elf32_External_RegInfo *) 13793 mips_regmask_frag)); 13794 } 13795 else 13796 { 13797 Elf64_Internal_RegInfo s; 13798 13799 s.ri_gprmask = mips_gprmask; 13800 s.ri_pad = 0; 13801 s.ri_cprmask[0] = mips_cprmask[0]; 13802 s.ri_cprmask[1] = mips_cprmask[1]; 13803 s.ri_cprmask[2] = mips_cprmask[2]; 13804 s.ri_cprmask[3] = mips_cprmask[3]; 13805 /* The gp_value field is set by the MIPS ELF backend. */ 13806 13807 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, 13808 ((Elf64_External_RegInfo *) 13809 mips_regmask_frag)); 13810 } 13811 13812 /* Set the MIPS ELF flag bits. FIXME: There should probably be some 13813 sort of BFD interface for this. */ 13814 if (mips_any_noreorder) 13815 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; 13816 if (mips_pic != NO_PIC) 13817 { 13818 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; 13819 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 13820 } 13821 if (mips_abicalls) 13822 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 13823 13824 /* Set MIPS ELF flags for ASEs. */ 13825 if (file_ase_mips16) 13826 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; 13827 #if 0 /* XXX FIXME */ 13828 if (file_ase_mips3d) 13829 elf_elfheader (stdoutput)->e_flags |= ???; 13830 #endif 13831 if (file_ase_mdmx) 13832 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; 13833 13834 /* Set the MIPS ELF ABI flags. */ 13835 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) 13836 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; 13837 else if (mips_abi == O64_ABI) 13838 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; 13839 else if (mips_abi == EABI_ABI) 13840 { 13841 if (!file_mips_gp32) 13842 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; 13843 else 13844 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; 13845 } 13846 else if (mips_abi == N32_ABI) 13847 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; 13848 13849 /* Nothing to do for N64_ABI. */ 13850 13851 if (mips_32bitmode) 13852 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; 13853 } 13854 13855 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ 13856 13857 typedef struct proc { 13858 symbolS *isym; 13859 unsigned long reg_mask; 13860 unsigned long reg_offset; 13861 unsigned long fpreg_mask; 13862 unsigned long fpreg_offset; 13863 unsigned long frame_offset; 13864 unsigned long frame_reg; 13865 unsigned long pc_reg; 13866 } procS; 13867 13868 static procS cur_proc; 13869 static procS *cur_proc_ptr; 13870 static int numprocs; 13871 13872 /* Fill in an rs_align_code fragment. */ 13873 13874 void 13875 mips_handle_align (fragS *fragp) 13876 { 13877 if (fragp->fr_type != rs_align_code) 13878 return; 13879 13880 if (mips_opts.mips16) 13881 { 13882 static const unsigned char be_nop[] = { 0x65, 0x00 }; 13883 static const unsigned char le_nop[] = { 0x00, 0x65 }; 13884 13885 int bytes; 13886 char *p; 13887 13888 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 13889 p = fragp->fr_literal + fragp->fr_fix; 13890 13891 if (bytes & 1) 13892 { 13893 *p++ = 0; 13894 fragp->fr_fix++; 13895 } 13896 13897 memcpy (p, (target_big_endian ? be_nop : le_nop), 2); 13898 fragp->fr_var = 2; 13899 } 13900 13901 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ 13902 } 13903 13904 static void 13905 md_obj_begin (void) 13906 { 13907 } 13908 13909 static void 13910 md_obj_end (void) 13911 { 13912 /* check for premature end, nesting errors, etc */ 13913 if (cur_proc_ptr) 13914 as_warn (_("missing .end at end of assembly")); 13915 } 13916 13917 static long 13918 get_number (void) 13919 { 13920 int negative = 0; 13921 long val = 0; 13922 13923 if (*input_line_pointer == '-') 13924 { 13925 ++input_line_pointer; 13926 negative = 1; 13927 } 13928 if (!ISDIGIT (*input_line_pointer)) 13929 as_bad (_("expected simple number")); 13930 if (input_line_pointer[0] == '0') 13931 { 13932 if (input_line_pointer[1] == 'x') 13933 { 13934 input_line_pointer += 2; 13935 while (ISXDIGIT (*input_line_pointer)) 13936 { 13937 val <<= 4; 13938 val |= hex_value (*input_line_pointer++); 13939 } 13940 return negative ? -val : val; 13941 } 13942 else 13943 { 13944 ++input_line_pointer; 13945 while (ISDIGIT (*input_line_pointer)) 13946 { 13947 val <<= 3; 13948 val |= *input_line_pointer++ - '0'; 13949 } 13950 return negative ? -val : val; 13951 } 13952 } 13953 if (!ISDIGIT (*input_line_pointer)) 13954 { 13955 printf (_(" *input_line_pointer == '%c' 0x%02x\n"), 13956 *input_line_pointer, *input_line_pointer); 13957 as_warn (_("invalid number")); 13958 return -1; 13959 } 13960 while (ISDIGIT (*input_line_pointer)) 13961 { 13962 val *= 10; 13963 val += *input_line_pointer++ - '0'; 13964 } 13965 return negative ? -val : val; 13966 } 13967 13968 /* The .file directive; just like the usual .file directive, but there 13969 is an initial number which is the ECOFF file index. In the non-ECOFF 13970 case .file implies DWARF-2. */ 13971 13972 static void 13973 s_mips_file (int x ATTRIBUTE_UNUSED) 13974 { 13975 static int first_file_directive = 0; 13976 13977 if (ECOFF_DEBUGGING) 13978 { 13979 get_number (); 13980 s_app_file (0); 13981 } 13982 else 13983 { 13984 char *filename; 13985 13986 filename = dwarf2_directive_file (0); 13987 13988 /* Versions of GCC up to 3.1 start files with a ".file" 13989 directive even for stabs output. Make sure that this 13990 ".file" is handled. Note that you need a version of GCC 13991 after 3.1 in order to support DWARF-2 on MIPS. */ 13992 if (filename != NULL && ! first_file_directive) 13993 { 13994 (void) new_logical_line (filename, -1); 13995 s_app_file_string (filename); 13996 } 13997 first_file_directive = 1; 13998 } 13999 } 14000 14001 /* The .loc directive, implying DWARF-2. */ 14002 14003 static void 14004 s_mips_loc (int x ATTRIBUTE_UNUSED) 14005 { 14006 if (!ECOFF_DEBUGGING) 14007 dwarf2_directive_loc (0); 14008 } 14009 14010 /* The .end directive. */ 14011 14012 static void 14013 s_mips_end (int x ATTRIBUTE_UNUSED) 14014 { 14015 symbolS *p; 14016 14017 /* Following functions need their own .frame and .cprestore directives. */ 14018 mips_frame_reg_valid = 0; 14019 mips_cprestore_valid = 0; 14020 14021 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 14022 { 14023 p = get_symbol (); 14024 demand_empty_rest_of_line (); 14025 } 14026 else 14027 p = NULL; 14028 14029 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 14030 as_warn (_(".end not in text section")); 14031 14032 if (!cur_proc_ptr) 14033 { 14034 as_warn (_(".end directive without a preceding .ent directive.")); 14035 demand_empty_rest_of_line (); 14036 return; 14037 } 14038 14039 if (p != NULL) 14040 { 14041 assert (S_GET_NAME (p)); 14042 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) 14043 as_warn (_(".end symbol does not match .ent symbol.")); 14044 14045 if (debug_type == DEBUG_STABS) 14046 stabs_generate_asm_endfunc (S_GET_NAME (p), 14047 S_GET_NAME (p)); 14048 } 14049 else 14050 as_warn (_(".end directive missing or unknown symbol")); 14051 14052 #ifdef OBJ_ELF 14053 /* Generate a .pdr section. */ 14054 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING 14055 && mips_flag_pdr) 14056 { 14057 segT saved_seg = now_seg; 14058 subsegT saved_subseg = now_subseg; 14059 valueT dot; 14060 expressionS exp; 14061 char *fragp; 14062 14063 dot = frag_now_fix (); 14064 14065 #ifdef md_flush_pending_output 14066 md_flush_pending_output (); 14067 #endif 14068 14069 assert (pdr_seg); 14070 subseg_set (pdr_seg, 0); 14071 14072 /* Write the symbol. */ 14073 exp.X_op = O_symbol; 14074 exp.X_add_symbol = p; 14075 exp.X_add_number = 0; 14076 emit_expr (&exp, 4); 14077 14078 fragp = frag_more (7 * 4); 14079 14080 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); 14081 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); 14082 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); 14083 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); 14084 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); 14085 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); 14086 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); 14087 14088 subseg_set (saved_seg, saved_subseg); 14089 } 14090 #endif /* OBJ_ELF */ 14091 14092 cur_proc_ptr = NULL; 14093 } 14094 14095 /* The .aent and .ent directives. */ 14096 14097 static void 14098 s_mips_ent (int aent) 14099 { 14100 symbolS *symbolP; 14101 14102 symbolP = get_symbol (); 14103 if (*input_line_pointer == ',') 14104 ++input_line_pointer; 14105 SKIP_WHITESPACE (); 14106 if (ISDIGIT (*input_line_pointer) 14107 || *input_line_pointer == '-') 14108 get_number (); 14109 14110 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 14111 as_warn (_(".ent or .aent not in text section.")); 14112 14113 if (!aent && cur_proc_ptr) 14114 as_warn (_("missing .end")); 14115 14116 if (!aent) 14117 { 14118 /* This function needs its own .frame and .cprestore directives. */ 14119 mips_frame_reg_valid = 0; 14120 mips_cprestore_valid = 0; 14121 14122 cur_proc_ptr = &cur_proc; 14123 memset (cur_proc_ptr, '\0', sizeof (procS)); 14124 14125 cur_proc_ptr->isym = symbolP; 14126 14127 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; 14128 14129 ++numprocs; 14130 14131 if (debug_type == DEBUG_STABS) 14132 stabs_generate_asm_func (S_GET_NAME (symbolP), 14133 S_GET_NAME (symbolP)); 14134 } 14135 14136 demand_empty_rest_of_line (); 14137 } 14138 14139 /* The .frame directive. If the mdebug section is present (IRIX 5 native) 14140 then ecoff.c (ecoff_directive_frame) is used. For embedded targets, 14141 s_mips_frame is used so that we can set the PDR information correctly. 14142 We can't use the ecoff routines because they make reference to the ecoff 14143 symbol table (in the mdebug section). */ 14144 14145 static void 14146 s_mips_frame (int ignore ATTRIBUTE_UNUSED) 14147 { 14148 #ifdef OBJ_ELF 14149 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) 14150 { 14151 long val; 14152 14153 if (cur_proc_ptr == (procS *) NULL) 14154 { 14155 as_warn (_(".frame outside of .ent")); 14156 demand_empty_rest_of_line (); 14157 return; 14158 } 14159 14160 cur_proc_ptr->frame_reg = tc_get_register (1); 14161 14162 SKIP_WHITESPACE (); 14163 if (*input_line_pointer++ != ',' 14164 || get_absolute_expression_and_terminator (&val) != ',') 14165 { 14166 as_warn (_("Bad .frame directive")); 14167 --input_line_pointer; 14168 demand_empty_rest_of_line (); 14169 return; 14170 } 14171 14172 cur_proc_ptr->frame_offset = val; 14173 cur_proc_ptr->pc_reg = tc_get_register (0); 14174 14175 demand_empty_rest_of_line (); 14176 } 14177 else 14178 #endif /* OBJ_ELF */ 14179 s_ignore (ignore); 14180 } 14181 14182 /* The .fmask and .mask directives. If the mdebug section is present 14183 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For 14184 embedded targets, s_mips_mask is used so that we can set the PDR 14185 information correctly. We can't use the ecoff routines because they 14186 make reference to the ecoff symbol table (in the mdebug section). */ 14187 14188 static void 14189 s_mips_mask (int reg_type) 14190 { 14191 #ifdef OBJ_ELF 14192 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) 14193 { 14194 long mask, off; 14195 14196 if (cur_proc_ptr == (procS *) NULL) 14197 { 14198 as_warn (_(".mask/.fmask outside of .ent")); 14199 demand_empty_rest_of_line (); 14200 return; 14201 } 14202 14203 if (get_absolute_expression_and_terminator (&mask) != ',') 14204 { 14205 as_warn (_("Bad .mask/.fmask directive")); 14206 --input_line_pointer; 14207 demand_empty_rest_of_line (); 14208 return; 14209 } 14210 14211 off = get_absolute_expression (); 14212 14213 if (reg_type == 'F') 14214 { 14215 cur_proc_ptr->fpreg_mask = mask; 14216 cur_proc_ptr->fpreg_offset = off; 14217 } 14218 else 14219 { 14220 cur_proc_ptr->reg_mask = mask; 14221 cur_proc_ptr->reg_offset = off; 14222 } 14223 14224 demand_empty_rest_of_line (); 14225 } 14226 else 14227 #endif /* OBJ_ELF */ 14228 s_ignore (reg_type); 14229 } 14230 14231 /* The .loc directive. */ 14232 14233 #if 0 14234 static void 14235 s_loc (int x) 14236 { 14237 symbolS *symbolP; 14238 int lineno; 14239 int addroff; 14240 14241 assert (now_seg == text_section); 14242 14243 lineno = get_number (); 14244 addroff = frag_now_fix (); 14245 14246 symbolP = symbol_new ("", N_SLINE, addroff, frag_now); 14247 S_SET_TYPE (symbolP, N_SLINE); 14248 S_SET_OTHER (symbolP, 0); 14249 S_SET_DESC (symbolP, lineno); 14250 symbolP->sy_segment = now_seg; 14251 } 14252 #endif 14253 14254 /* A table describing all the processors gas knows about. Names are 14255 matched in the order listed. 14256 14257 To ease comparison, please keep this table in the same order as 14258 gcc's mips_cpu_info_table[]. */ 14259 static const struct mips_cpu_info mips_cpu_info_table[] = 14260 { 14261 /* Entries for generic ISAs */ 14262 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, 14263 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, 14264 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, 14265 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, 14266 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, 14267 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, 14268 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, 14269 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, 14270 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, 14271 14272 /* MIPS I */ 14273 { "r3000", 0, ISA_MIPS1, CPU_R3000 }, 14274 { "r2000", 0, ISA_MIPS1, CPU_R3000 }, 14275 { "r3900", 0, ISA_MIPS1, CPU_R3900 }, 14276 14277 /* MIPS II */ 14278 { "r6000", 0, ISA_MIPS2, CPU_R6000 }, 14279 14280 /* MIPS III */ 14281 { "r4000", 0, ISA_MIPS3, CPU_R4000 }, 14282 { "r4010", 0, ISA_MIPS2, CPU_R4010 }, 14283 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, 14284 { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, 14285 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, 14286 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, 14287 { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, 14288 { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, 14289 { "r4400", 0, ISA_MIPS3, CPU_R4400 }, 14290 { "r4600", 0, ISA_MIPS3, CPU_R4600 }, 14291 { "orion", 0, ISA_MIPS3, CPU_R4600 }, 14292 { "r4650", 0, ISA_MIPS3, CPU_R4650 }, 14293 14294 /* Loongson 2F */ 14295 /* First step to getting full Loongson opcode support. 14296 Not just a MIPS III, not quite anything else. */ 14297 /* XXX: Not yet, keep commented out for now 14298 { "loongson2f", 0, ISA_L2F, CPU_L2F }, 14299 */ 14300 14301 /* MIPS IV */ 14302 { "r8000", 0, ISA_MIPS4, CPU_R8000 }, 14303 { "r10000", 0, ISA_MIPS4, CPU_R10000 }, 14304 { "r12000", 0, ISA_MIPS4, CPU_R12000 }, 14305 { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, 14306 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, 14307 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, 14308 { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, 14309 { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, 14310 { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, 14311 { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, 14312 { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, 14313 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, 14314 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 }, 14315 14316 /* MIPS 32 */ 14317 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, 14318 { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, 14319 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, 14320 14321 /* MIPS 64 */ 14322 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, 14323 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, 14324 14325 /* Broadcom SB-1 CPU core */ 14326 { "sb1", 0, ISA_MIPS64, CPU_SB1 }, 14327 14328 /* End marker */ 14329 { NULL, 0, 0, 0 } 14330 }; 14331 14332 14333 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL 14334 with a final "000" replaced by "k". Ignore case. 14335 14336 Note: this function is shared between GCC and GAS. */ 14337 14338 static bfd_boolean 14339 mips_strict_matching_cpu_name_p (const char *canonical, const char *given) 14340 { 14341 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) 14342 given++, canonical++; 14343 14344 return ((*given == 0 && *canonical == 0) 14345 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); 14346 } 14347 14348 14349 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied 14350 CPU name. We've traditionally allowed a lot of variation here. 14351 14352 Note: this function is shared between GCC and GAS. */ 14353 14354 static bfd_boolean 14355 mips_matching_cpu_name_p (const char *canonical, const char *given) 14356 { 14357 /* First see if the name matches exactly, or with a final "000" 14358 turned into "k". */ 14359 if (mips_strict_matching_cpu_name_p (canonical, given)) 14360 return TRUE; 14361 14362 /* If not, try comparing based on numerical designation alone. 14363 See if GIVEN is an unadorned number, or 'r' followed by a number. */ 14364 if (TOLOWER (*given) == 'r') 14365 given++; 14366 if (!ISDIGIT (*given)) 14367 return FALSE; 14368 14369 /* Skip over some well-known prefixes in the canonical name, 14370 hoping to find a number there too. */ 14371 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') 14372 canonical += 2; 14373 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') 14374 canonical += 2; 14375 else if (TOLOWER (canonical[0]) == 'r') 14376 canonical += 1; 14377 14378 return mips_strict_matching_cpu_name_p (canonical, given); 14379 } 14380 14381 14382 /* Parse an option that takes the name of a processor as its argument. 14383 OPTION is the name of the option and CPU_STRING is the argument. 14384 Return the corresponding processor enumeration if the CPU_STRING is 14385 recognized, otherwise report an error and return null. 14386 14387 A similar function exists in GCC. */ 14388 14389 static const struct mips_cpu_info * 14390 mips_parse_cpu (const char *option, const char *cpu_string) 14391 { 14392 const struct mips_cpu_info *p; 14393 14394 /* 'from-abi' selects the most compatible architecture for the given 14395 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the 14396 EABIs, we have to decide whether we're using the 32-bit or 64-bit 14397 version. Look first at the -mgp options, if given, otherwise base 14398 the choice on MIPS_DEFAULT_64BIT. 14399 14400 Treat NO_ABI like the EABIs. One reason to do this is that the 14401 plain 'mips' and 'mips64' configs have 'from-abi' as their default 14402 architecture. This code picks MIPS I for 'mips' and MIPS III for 14403 'mips64', just as we did in the days before 'from-abi'. */ 14404 if (strcasecmp (cpu_string, "from-abi") == 0) 14405 { 14406 if (ABI_NEEDS_32BIT_REGS (mips_abi)) 14407 return mips_cpu_info_from_isa (ISA_MIPS1); 14408 14409 if (ABI_NEEDS_64BIT_REGS (mips_abi)) 14410 return mips_cpu_info_from_isa (ISA_MIPS3); 14411 14412 if (file_mips_gp32 >= 0) 14413 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); 14414 14415 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT 14416 ? ISA_MIPS3 14417 : ISA_MIPS1); 14418 } 14419 14420 /* 'default' has traditionally been a no-op. Probably not very useful. */ 14421 if (strcasecmp (cpu_string, "default") == 0) 14422 return 0; 14423 14424 for (p = mips_cpu_info_table; p->name != 0; p++) 14425 if (mips_matching_cpu_name_p (p->name, cpu_string)) 14426 return p; 14427 14428 as_bad ("Bad value (%s) for %s", cpu_string, option); 14429 return 0; 14430 } 14431 14432 /* Return the canonical processor information for ISA (a member of the 14433 ISA_MIPS* enumeration). */ 14434 14435 static const struct mips_cpu_info * 14436 mips_cpu_info_from_isa (int isa) 14437 { 14438 int i; 14439 14440 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 14441 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) 14442 && isa == mips_cpu_info_table[i].isa) 14443 return (&mips_cpu_info_table[i]); 14444 14445 return NULL; 14446 } 14447 14448 static const struct mips_cpu_info * 14449 mips_cpu_info_from_arch (int arch) 14450 { 14451 int i; 14452 14453 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 14454 if (arch == mips_cpu_info_table[i].cpu) 14455 return (&mips_cpu_info_table[i]); 14456 14457 return NULL; 14458 } 14459 14460 static void 14461 show (FILE *stream, const char *string, int *col_p, int *first_p) 14462 { 14463 if (*first_p) 14464 { 14465 fprintf (stream, "%24s", ""); 14466 *col_p = 24; 14467 } 14468 else 14469 { 14470 fprintf (stream, ", "); 14471 *col_p += 2; 14472 } 14473 14474 if (*col_p + strlen (string) > 72) 14475 { 14476 fprintf (stream, "\n%24s", ""); 14477 *col_p = 24; 14478 } 14479 14480 fprintf (stream, "%s", string); 14481 *col_p += strlen (string); 14482 14483 *first_p = 0; 14484 } 14485 14486 void 14487 md_show_usage (FILE *stream) 14488 { 14489 int column, first; 14490 size_t i; 14491 14492 fprintf (stream, _("\ 14493 MIPS options:\n\ 14494 -membedded-pic generate embedded position independent code\n\ 14495 -EB generate big endian output\n\ 14496 -EL generate little endian output\n\ 14497 -g, -g2 do not remove unneeded NOPs or swap branches\n\ 14498 -G NUM allow referencing objects up to NUM bytes\n\ 14499 implicitly with the gp register [default 8]\n")); 14500 fprintf (stream, _("\ 14501 -mips1 generate MIPS ISA I instructions\n\ 14502 -mips2 generate MIPS ISA II instructions\n\ 14503 -mips3 generate MIPS ISA III instructions\n\ 14504 -mips4 generate MIPS ISA IV instructions\n\ 14505 -mips5 generate MIPS ISA V instructions\n\ 14506 -mips32 generate MIPS32 ISA instructions\n\ 14507 -mips32r2 generate MIPS32 release 2 ISA instructions\n\ 14508 -mips64 generate MIPS64 ISA instructions\n\ 14509 -mips64r2 generate MIPS64 release 2 ISA instructions\n\ 14510 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); 14511 14512 first = 1; 14513 14514 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 14515 show (stream, mips_cpu_info_table[i].name, &column, &first); 14516 show (stream, "from-abi", &column, &first); 14517 fputc ('\n', stream); 14518 14519 fprintf (stream, _("\ 14520 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ 14521 -no-mCPU don't generate code specific to CPU.\n\ 14522 For -mCPU and -no-mCPU, CPU must be one of:\n")); 14523 14524 first = 1; 14525 14526 show (stream, "3900", &column, &first); 14527 show (stream, "4010", &column, &first); 14528 show (stream, "4100", &column, &first); 14529 show (stream, "4650", &column, &first); 14530 fputc ('\n', stream); 14531 14532 fprintf (stream, _("\ 14533 -mips16 generate mips16 instructions\n\ 14534 -no-mips16 do not generate mips16 instructions\n")); 14535 fprintf (stream, _("\ 14536 -mfix-vr4120 work around certain VR4120 errata\n\ 14537 -mfix-loongson2f-btb work around Loongson2F BTB errata\n\ 14538 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ 14539 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ 14540 -O0 remove unneeded NOPs, do not swap branches\n\ 14541 -O remove unneeded NOPs and swap branches\n\ 14542 --[no-]construct-floats [dis]allow floating point values to be constructed\n\ 14543 --trap, --no-break trap exception on div by 0 and mult overflow\n\ 14544 --break, --no-trap break exception on div by 0 and mult overflow\n")); 14545 #ifdef OBJ_ELF 14546 fprintf (stream, _("\ 14547 -KPIC, -call_shared generate SVR4 position independent code\n\ 14548 -non_shared do not generate position independent code\n\ 14549 -xgot assume a 32 bit GOT\n\ 14550 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ 14551 -mabi=ABI create ABI conformant object file for:\n")); 14552 14553 first = 1; 14554 14555 show (stream, "32", &column, &first); 14556 show (stream, "o64", &column, &first); 14557 show (stream, "n32", &column, &first); 14558 show (stream, "64", &column, &first); 14559 show (stream, "eabi", &column, &first); 14560 14561 fputc ('\n', stream); 14562 14563 fprintf (stream, _("\ 14564 -32 create o32 ABI object file (default)\n\ 14565 -n32 create n32 ABI object file\n\ 14566 -64 create 64 ABI object file\n")); 14567 #endif 14568 } 14569 14570 enum dwarf2_format 14571 mips_dwarf2_format (void) 14572 { 14573 if (mips_abi == N64_ABI) 14574 { 14575 #ifdef TE_IRIX 14576 return dwarf2_format_64bit_irix; 14577 #else 14578 return dwarf2_format_64bit; 14579 #endif 14580 } 14581 else 14582 return dwarf2_format_32bit; 14583 } 14584 14585 int 14586 mips_dwarf2_addr_size (void) 14587 { 14588 if (mips_abi == N64_ABI) 14589 return 8; 14590 else 14591 return 4; 14592 } 14593 14594 /* Standard calling conventions leave the CFA at SP on entry. */ 14595 void 14596 mips_cfi_frame_initial_instructions (void) 14597 { 14598 cfi_add_CFA_def_cfa_register (SP); 14599 } 14600 14601 int 14602 tc_mips_regname_to_dw2regnum (char *regname) 14603 { 14604 unsigned int regnum = -1; 14605 unsigned int reg; 14606 14607 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) 14608 regnum = reg; 14609 14610 return regnum; 14611 } 14612