1*cf2f2c56Smiod@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003 25f210c2aSfgsch@c Free Software Foundation, Inc. 3f7cc78ecSespie@c This is part of the GAS manual. 4f7cc78ecSespie@c For copying conditions, see the file as.texinfo. 5f7cc78ecSespie 6f7cc78ecSespie@ifset GENERIC 7f7cc78ecSespie@page 8f7cc78ecSespie@node ARM-Dependent 9f7cc78ecSespie@chapter ARM Dependent Features 10f7cc78ecSespie@end ifset 11f7cc78ecSespie 12f7cc78ecSespie@ifclear GENERIC 13f7cc78ecSespie@node Machine Dependencies 14f7cc78ecSespie@chapter ARM Dependent Features 15f7cc78ecSespie@end ifclear 16f7cc78ecSespie 17f7cc78ecSespie@cindex ARM support 18f7cc78ecSespie@cindex Thumb support 19f7cc78ecSespie@menu 20f7cc78ecSespie* ARM Options:: Options 21f7cc78ecSespie* ARM Syntax:: Syntax 22f7cc78ecSespie* ARM Floating Point:: Floating Point 23f7cc78ecSespie* ARM Directives:: ARM Machine Directives 24f7cc78ecSespie* ARM Opcodes:: Opcodes 25*cf2f2c56Smiod* ARM Mapping Symbols:: Mapping Symbols 26f7cc78ecSespie@end menu 27f7cc78ecSespie 28f7cc78ecSespie@node ARM Options 29f7cc78ecSespie@section Options 30f7cc78ecSespie@cindex ARM options (none) 31f7cc78ecSespie@cindex options for ARM (none) 32f7cc78ecSespie 33f7cc78ecSespie@table @code 34f7cc78ecSespie 35d2201f2fSdrahn@cindex @code{-mcpu=} command line option, ARM 36d2201f2fSdrahn@item -mcpu=@var{processor}[+@var{extension}@dots{}] 37f7cc78ecSespieThis option specifies the target processor. The assembler will issue an 38f7cc78ecSespieerror message if an attempt is made to assemble an instruction which 39d2201f2fSdrahnwill not execute on the target processor. The following processor names are 40d2201f2fSdrahnrecognized: 41d2201f2fSdrahn@code{arm1}, 42d2201f2fSdrahn@code{arm2}, 43d2201f2fSdrahn@code{arm250}, 44d2201f2fSdrahn@code{arm3}, 45d2201f2fSdrahn@code{arm6}, 46d2201f2fSdrahn@code{arm60}, 47d2201f2fSdrahn@code{arm600}, 48d2201f2fSdrahn@code{arm610}, 49d2201f2fSdrahn@code{arm620}, 50d2201f2fSdrahn@code{arm7}, 51d2201f2fSdrahn@code{arm7m}, 52d2201f2fSdrahn@code{arm7d}, 53d2201f2fSdrahn@code{arm7dm}, 54d2201f2fSdrahn@code{arm7di}, 55d2201f2fSdrahn@code{arm7dmi}, 56d2201f2fSdrahn@code{arm70}, 57d2201f2fSdrahn@code{arm700}, 58d2201f2fSdrahn@code{arm700i}, 59d2201f2fSdrahn@code{arm710}, 60d2201f2fSdrahn@code{arm710t}, 61d2201f2fSdrahn@code{arm720}, 62d2201f2fSdrahn@code{arm720t}, 63d2201f2fSdrahn@code{arm740t}, 64d2201f2fSdrahn@code{arm710c}, 65d2201f2fSdrahn@code{arm7100}, 66d2201f2fSdrahn@code{arm7500}, 67d2201f2fSdrahn@code{arm7500fe}, 68d2201f2fSdrahn@code{arm7t}, 69d2201f2fSdrahn@code{arm7tdmi}, 70d2201f2fSdrahn@code{arm8}, 71d2201f2fSdrahn@code{arm810}, 72d2201f2fSdrahn@code{strongarm}, 73d2201f2fSdrahn@code{strongarm1}, 74d2201f2fSdrahn@code{strongarm110}, 75d2201f2fSdrahn@code{strongarm1100}, 76d2201f2fSdrahn@code{strongarm1110}, 77d2201f2fSdrahn@code{arm9}, 78d2201f2fSdrahn@code{arm920}, 79d2201f2fSdrahn@code{arm920t}, 80d2201f2fSdrahn@code{arm922t}, 81d2201f2fSdrahn@code{arm940t}, 82d2201f2fSdrahn@code{arm9tdmi}, 83d2201f2fSdrahn@code{arm9e}, 84*cf2f2c56Smiod@code{arm926e}, 85*cf2f2c56Smiod@code{arm926ejs}, 86d2201f2fSdrahn@code{arm946e-r0}, 87d2201f2fSdrahn@code{arm946e}, 88d2201f2fSdrahn@code{arm966e-r0}, 89d2201f2fSdrahn@code{arm966e}, 90d2201f2fSdrahn@code{arm10t}, 91d2201f2fSdrahn@code{arm10e}, 92d2201f2fSdrahn@code{arm1020}, 93d2201f2fSdrahn@code{arm1020t}, 94d2201f2fSdrahn@code{arm1020e}, 95*cf2f2c56Smiod@code{arm1026ejs}, 96*cf2f2c56Smiod@code{arm1136js}, 97*cf2f2c56Smiod@code{arm1136jfs}, 98d2201f2fSdrahn@code{ep9312} (ARM920 with Cirrus Maverick coprocessor), 99d2201f2fSdrahn@code{i80200} (Intel XScale processor) 100d2201f2fSdrahn@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) 101d2201f2fSdrahnand 102d2201f2fSdrahn@code{xscale}. 103d2201f2fSdrahnThe special name @code{all} may be used to allow the 104d2201f2fSdrahnassembler to accept instructions valid for any ARM processor. 105f7cc78ecSespie 106d2201f2fSdrahnIn addition to the basic instruction set, the assembler can be told to 107d2201f2fSdrahnaccept various extension mnemonics that extend the processor using the 108d2201f2fSdrahnco-processor instruction space. For example, @code{-mcpu=arm920+maverick} 109d2201f2fSdrahnis equivalent to specifying @code{-mcpu=ep9312}. The following extensions 110d2201f2fSdrahnare currently supported: 111d2201f2fSdrahn@code{+maverick} 112d2201f2fSdrahn@code{+iwmmxt} 113d2201f2fSdrahnand 114d2201f2fSdrahn@code{+xscale}. 115d2201f2fSdrahn 116d2201f2fSdrahn@cindex @code{-march=} command line option, ARM 117d2201f2fSdrahn@item -march=@var{architecture}[+@var{extension}@dots{}] 118f7cc78ecSespieThis option specifies the target architecture. The assembler will issue 119f7cc78ecSespiean error message if an attempt is made to assemble an instruction which 120d2201f2fSdrahnwill not execute on the target architecture. The following architecture 121d2201f2fSdrahnnames are recognized: 122d2201f2fSdrahn@code{armv1}, 123d2201f2fSdrahn@code{armv2}, 124d2201f2fSdrahn@code{armv2a}, 125d2201f2fSdrahn@code{armv2s}, 126d2201f2fSdrahn@code{armv3}, 127d2201f2fSdrahn@code{armv3m}, 128d2201f2fSdrahn@code{armv4}, 129d2201f2fSdrahn@code{armv4xm}, 130d2201f2fSdrahn@code{armv4t}, 131d2201f2fSdrahn@code{armv4txm}, 132d2201f2fSdrahn@code{armv5}, 133d2201f2fSdrahn@code{armv5t}, 134d2201f2fSdrahn@code{armv5txm}, 135d2201f2fSdrahn@code{armv5te}, 136*cf2f2c56Smiod@code{armv5texp}, 137*cf2f2c56Smiod@code{armv6}, 138*cf2f2c56Smiod@code{armv6j}, 139d2201f2fSdrahn@code{iwmmxt} 140d2201f2fSdrahnand 141d2201f2fSdrahn@code{xscale}. 142d2201f2fSdrahnIf both @code{-mcpu} and 143d2201f2fSdrahn@code{-march} are specified, the assembler will use 144d2201f2fSdrahnthe setting for @code{-mcpu}. 145d2201f2fSdrahn 146d2201f2fSdrahnThe architecture option can be extended with the same instruction set 147d2201f2fSdrahnextension options as the @code{-mcpu} option. 148d2201f2fSdrahn 149d2201f2fSdrahn@cindex @code{-mfpu=} command line option, ARM 150d2201f2fSdrahn@item -mfpu=@var{floating-point-format} 151d2201f2fSdrahn 152d2201f2fSdrahnThis option specifies the floating point format to assemble for. The 153d2201f2fSdrahnassembler will issue an error message if an attempt is made to assemble 154d2201f2fSdrahnan instruction which will not execute on the target floating point unit. 155d2201f2fSdrahnThe following format options are recognized: 156d2201f2fSdrahn@code{softfpa}, 157d2201f2fSdrahn@code{fpe}, 158d2201f2fSdrahn@code{fpe2}, 159d2201f2fSdrahn@code{fpe3}, 160d2201f2fSdrahn@code{fpa}, 161d2201f2fSdrahn@code{fpa10}, 162d2201f2fSdrahn@code{fpa11}, 163d2201f2fSdrahn@code{arm7500fe}, 164d2201f2fSdrahn@code{softvfp}, 165d2201f2fSdrahn@code{softvfp+vfp}, 166d2201f2fSdrahn@code{vfp}, 167d2201f2fSdrahn@code{vfp10}, 168d2201f2fSdrahn@code{vfp10-r0}, 169d2201f2fSdrahn@code{vfp9}, 170d2201f2fSdrahn@code{vfpxd}, 171*cf2f2c56Smiod@code{arm1020t}, 172*cf2f2c56Smiod@code{arm1020e}, 173*cf2f2c56Smiod@code{arm1136jfs} 174d2201f2fSdrahnand 175*cf2f2c56Smiod@code{maverick}. 176d2201f2fSdrahn 177d2201f2fSdrahnIn addition to determining which instructions are assembled, this option 178d2201f2fSdrahnalso affects the way in which the @code{.double} assembler directive behaves 179d2201f2fSdrahnwhen assembling little-endian code. 180d2201f2fSdrahn 181d2201f2fSdrahnThe default is dependent on the processor selected. For Architecture 5 or 182d2201f2fSdrahnlater, the default is to assembler for VFP instructions; for earlier 183d2201f2fSdrahnarchitectures the default is to assemble for FPA instructions. 184f7cc78ecSespie 185f7cc78ecSespie@cindex @code{-mthumb} command line option, ARM 186f7cc78ecSespie@item -mthumb 187d2201f2fSdrahnThis option specifies that the assembler should start assembling Thumb 188d2201f2fSdrahninstructions; that is, it should behave as though the file starts with a 189d2201f2fSdrahn@code{.code 16} directive. 190f7cc78ecSespie 191f7cc78ecSespie@cindex @code{-mthumb-interwork} command line option, ARM 192f7cc78ecSespie@item -mthumb-interwork 193f7cc78ecSespieThis option specifies that the output generated by the assembler should 194f7cc78ecSespiebe marked as supporting interworking. 195f7cc78ecSespie 196f7cc78ecSespie@cindex @code{-mapcs} command line option, ARM 1975f210c2aSfgsch@item -mapcs @code{[26|32]} 198f7cc78ecSespieThis option specifies that the output generated by the assembler should 199f7cc78ecSespiebe marked as supporting the indicated version of the Arm Procedure. 200f7cc78ecSespieCalling Standard. 201f7cc78ecSespie 2025f210c2aSfgsch@cindex @code{-matpcs} command line option, ARM 2035f210c2aSfgsch@item -matpcs 2045f210c2aSfgschThis option specifies that the output generated by the assembler should 2055f210c2aSfgschbe marked as supporting the Arm/Thumb Procedure Calling Standard. If 2065f210c2aSfgschenabled this option will cause the assembler to create an empty 2075f210c2aSfgschdebugging section in the object file called .arm.atpcs. Debuggers can 2085f210c2aSfgschuse this to determine the ABI being used by. 2095f210c2aSfgsch 210f7cc78ecSespie@cindex @code{-mapcs-float} command line option, ARM 211f7cc78ecSespie@item -mapcs-float 212*cf2f2c56SmiodThis indicates the floating point variant of the APCS should be 213f7cc78ecSespieused. In this variant floating point arguments are passed in FP 214f7cc78ecSespieregisters rather than integer registers. 215f7cc78ecSespie 216f7cc78ecSespie@cindex @code{-mapcs-reentrant} command line option, ARM 217f7cc78ecSespie@item -mapcs-reentrant 218f7cc78ecSespieThis indicates that the reentrant variant of the APCS should be used. 219f7cc78ecSespieThis variant supports position independent code. 220f7cc78ecSespie 221*cf2f2c56Smiod@cindex @code{-mfloat-abi=} command line option, ARM 222*cf2f2c56Smiod@item -mfloat-abi=@var{abi} 223*cf2f2c56SmiodThis option specifies that the output generated by the assembler should be 224*cf2f2c56Smiodmarked as using specified floating point ABI. 225*cf2f2c56SmiodThe following values are recognized: 226*cf2f2c56Smiod@code{soft}, 227*cf2f2c56Smiod@code{softfp} 228*cf2f2c56Smiodand 229*cf2f2c56Smiod@code{hard}. 230*cf2f2c56Smiod 231f7cc78ecSespie@cindex @code{-EB} command line option, ARM 232f7cc78ecSespie@item -EB 233f7cc78ecSespieThis option specifies that the output generated by the assembler should 234f7cc78ecSespiebe marked as being encoded for a big-endian processor. 235f7cc78ecSespie 236f7cc78ecSespie@cindex @code{-EL} command line option, ARM 237f7cc78ecSespie@item -EL 238f7cc78ecSespieThis option specifies that the output generated by the assembler should 239f7cc78ecSespiebe marked as being encoded for a little-endian processor. 240f7cc78ecSespie 241f7cc78ecSespie@cindex @code{-k} command line option, ARM 242f7cc78ecSespie@cindex PIC code generation for ARM 243f7cc78ecSespie@item -k 2445f210c2aSfgschThis option specifies that the output of the assembler should be marked 2455f210c2aSfgschas position-independent code (PIC). 246f7cc78ecSespie 247f7cc78ecSespie@cindex @code{-moabi} command line option, ARM 248f7cc78ecSespie@item -moabi 249f7cc78ecSespieThis indicates that the code should be assembled using the old ARM ELF 250f7cc78ecSespieconventions, based on a beta release release of the ARM-ELF 251f7cc78ecSespiespecifications, rather than the default conventions which are based on 252f7cc78ecSespiethe final release of the ARM-ELF specifications. 253f7cc78ecSespie 254f7cc78ecSespie@end table 255f7cc78ecSespie 256f7cc78ecSespie 257f7cc78ecSespie@node ARM Syntax 258f7cc78ecSespie@section Syntax 259f7cc78ecSespie@menu 260f7cc78ecSespie* ARM-Chars:: Special Characters 261f7cc78ecSespie* ARM-Regs:: Register Names 262f7cc78ecSespie@end menu 263f7cc78ecSespie 264f7cc78ecSespie@node ARM-Chars 265f7cc78ecSespie@subsection Special Characters 266f7cc78ecSespie 267f7cc78ecSespie@cindex line comment character, ARM 268f7cc78ecSespie@cindex ARM line comment character 269f7cc78ecSespieThe presence of a @samp{@@} on a line indicates the start of a comment 270f7cc78ecSespiethat extends to the end of the current line. If a @samp{#} appears as 271f7cc78ecSespiethe first character of a line, the whole line is treated as a comment. 272f7cc78ecSespie 273f7cc78ecSespie@cindex line separator, ARM 274f7cc78ecSespie@cindex statement separator, ARM 275f7cc78ecSespie@cindex ARM line separator 2765f210c2aSfgschThe @samp{;} character can be used instead of a newline to separate 2775f210c2aSfgschstatements. 278f7cc78ecSespie 279f7cc78ecSespie@cindex immediate character, ARM 280f7cc78ecSespie@cindex ARM immediate character 281f7cc78ecSespieEither @samp{#} or @samp{$} can be used to indicate immediate operands. 282f7cc78ecSespie 283f7cc78ecSespie@cindex identifiers, ARM 284f7cc78ecSespie@cindex ARM identifiers 285f7cc78ecSespie*TODO* Explain about /data modifier on symbols. 286f7cc78ecSespie 287f7cc78ecSespie@node ARM-Regs 288f7cc78ecSespie@subsection Register Names 289f7cc78ecSespie 290f7cc78ecSespie@cindex ARM register names 291f7cc78ecSespie@cindex register names, ARM 292f7cc78ecSespie*TODO* Explain about ARM register naming, and the predefined names. 293f7cc78ecSespie 294f7cc78ecSespie@node ARM Floating Point 295f7cc78ecSespie@section Floating Point 296f7cc78ecSespie 297f7cc78ecSespie@cindex floating point, ARM (@sc{ieee}) 298f7cc78ecSespie@cindex ARM floating point (@sc{ieee}) 299f7cc78ecSespieThe ARM family uses @sc{ieee} floating-point numbers. 300f7cc78ecSespie 301f7cc78ecSespie 302f7cc78ecSespie 303f7cc78ecSespie@node ARM Directives 304f7cc78ecSespie@section ARM Machine Directives 305f7cc78ecSespie 306f7cc78ecSespie@cindex machine directives, ARM 307f7cc78ecSespie@cindex ARM machine directives 308f7cc78ecSespie@table @code 309f7cc78ecSespie 310f7cc78ecSespie@cindex @code{align} directive, ARM 311f7cc78ecSespie@item .align @var{expression} [, @var{expression}] 312f7cc78ecSespieThis is the generic @var{.align} directive. For the ARM however if the 313f7cc78ecSespiefirst argument is zero (ie no alignment is needed) the assembler will 314f7cc78ecSespiebehave as if the argument had been 2 (ie pad to the next four byte 315d2201f2fSdrahnboundary). This is for compatibility with ARM's own assembler. 316f7cc78ecSespie 317f7cc78ecSespie@cindex @code{req} directive, ARM 318f7cc78ecSespie@item @var{name} .req @var{register name} 319f7cc78ecSespieThis creates an alias for @var{register name} called @var{name}. For 320f7cc78ecSespieexample: 321f7cc78ecSespie 322f7cc78ecSespie@smallexample 323f7cc78ecSespie foo .req r0 324f7cc78ecSespie@end smallexample 325f7cc78ecSespie 326*cf2f2c56Smiod@cindex @code{unreq} directive, ARM 327*cf2f2c56Smiod@item .unreq @var{alias-name} 328*cf2f2c56SmiodThis undefines a register alias which was previously defined using the 329*cf2f2c56Smiod@code{req} directive. For example: 330*cf2f2c56Smiod 331*cf2f2c56Smiod@smallexample 332*cf2f2c56Smiod foo .req r0 333*cf2f2c56Smiod .unreq foo 334*cf2f2c56Smiod@end smallexample 335*cf2f2c56Smiod 336*cf2f2c56SmiodAn error occurs if the name is undefined. Note - this pseudo op can 337*cf2f2c56Smiodbe used to delete builtin in register name aliases (eg 'r0'). This 338*cf2f2c56Smiodshould only be done if it is really necessary. 339*cf2f2c56Smiod 340f7cc78ecSespie@cindex @code{code} directive, ARM 3415f210c2aSfgsch@item .code @code{[16|32]} 342f7cc78ecSespieThis directive selects the instruction set being generated. The value 16 343f7cc78ecSespieselects Thumb, with the value 32 selecting ARM. 344f7cc78ecSespie 345f7cc78ecSespie@cindex @code{thumb} directive, ARM 346f7cc78ecSespie@item .thumb 347f7cc78ecSespieThis performs the same action as @var{.code 16}. 348f7cc78ecSespie 349f7cc78ecSespie@cindex @code{arm} directive, ARM 350f7cc78ecSespie@item .arm 351f7cc78ecSespieThis performs the same action as @var{.code 32}. 352f7cc78ecSespie 353f7cc78ecSespie@cindex @code{force_thumb} directive, ARM 354f7cc78ecSespie@item .force_thumb 355f7cc78ecSespieThis directive forces the selection of Thumb instructions, even if the 356f7cc78ecSespietarget processor does not support those instructions 357f7cc78ecSespie 358f7cc78ecSespie@cindex @code{thumb_func} directive, ARM 359f7cc78ecSespie@item .thumb_func 360f7cc78ecSespieThis directive specifies that the following symbol is the name of a 361f7cc78ecSespieThumb encoded function. This information is necessary in order to allow 362f7cc78ecSespiethe assembler and linker to generate correct code for interworking 363f7cc78ecSespiebetween Arm and Thumb instructions and should be used even if 3645f210c2aSfgschinterworking is not going to be performed. The presence of this 3655f210c2aSfgschdirective also implies @code{.thumb} 366f7cc78ecSespie 367f7cc78ecSespie@cindex @code{thumb_set} directive, ARM 368f7cc78ecSespie@item .thumb_set 369f7cc78ecSespieThis performs the equivalent of a @code{.set} directive in that it 370f7cc78ecSespiecreates a symbol which is an alias for another symbol (possibly not yet 371f7cc78ecSespiedefined). This directive also has the added property in that it marks 372f7cc78ecSespiethe aliased symbol as being a thumb function entry point, in the same 373f7cc78ecSespieway that the @code{.thumb_func} directive does. 374f7cc78ecSespie 375f7cc78ecSespie@cindex @code{.ltorg} directive, ARM 376f7cc78ecSespie@item .ltorg 377f7cc78ecSespieThis directive causes the current contents of the literal pool to be 378f7cc78ecSespiedumped into the current section (which is assumed to be the .text 379f7cc78ecSespiesection) at the current location (aligned to a word boundary). 380d2201f2fSdrahn@code{GAS} maintains a separate literal pool for each section and each 381d2201f2fSdrahnsub-section. The @code{.ltorg} directive will only affect the literal 382d2201f2fSdrahnpool of the current section and sub-section. At the end of assembly 383d2201f2fSdrahnall remaining, un-empty literal pools will automatically be dumped. 384d2201f2fSdrahn 385d2201f2fSdrahnNote - older versions of @code{GAS} would dump the current literal 386d2201f2fSdrahnpool any time a section change occurred. This is no longer done, since 387d2201f2fSdrahnit prevents accurate control of the placement of literal pools. 388f7cc78ecSespie 389f7cc78ecSespie@cindex @code{.pool} directive, ARM 390f7cc78ecSespie@item .pool 391f7cc78ecSespieThis is a synonym for .ltorg. 392f7cc78ecSespie 393f7cc78ecSespie@end table 394f7cc78ecSespie 395f7cc78ecSespie@node ARM Opcodes 396f7cc78ecSespie@section Opcodes 397f7cc78ecSespie 398f7cc78ecSespie@cindex ARM opcodes 399f7cc78ecSespie@cindex opcodes for ARM 400f7cc78ecSespie@code{@value{AS}} implements all the standard ARM opcodes. It also 401f7cc78ecSespieimplements several pseudo opcodes, including several synthetic load 402f7cc78ecSespieinstructions. 403f7cc78ecSespie 404f7cc78ecSespie@table @code 405f7cc78ecSespie 406f7cc78ecSespie@cindex @code{NOP} pseudo op, ARM 407f7cc78ecSespie@item NOP 408f7cc78ecSespie@smallexample 409f7cc78ecSespie nop 410f7cc78ecSespie@end smallexample 411f7cc78ecSespie 412f7cc78ecSespieThis pseudo op will always evaluate to a legal ARM instruction that does 413f7cc78ecSespienothing. Currently it will evaluate to MOV r0, r0. 414f7cc78ecSespie 415f7cc78ecSespie@cindex @code{LDR reg,=<label>} pseudo op, ARM 416f7cc78ecSespie@item LDR 417f7cc78ecSespie@smallexample 418f7cc78ecSespie ldr <register> , = <expression> 419f7cc78ecSespie@end smallexample 420f7cc78ecSespie 421f7cc78ecSespieIf expression evaluates to a numeric constant then a MOV or MVN 422f7cc78ecSespieinstruction will be used in place of the LDR instruction, if the 423f7cc78ecSespieconstant can be generated by either of these instructions. Otherwise 424f7cc78ecSespiethe constant will be placed into the nearest literal pool (if it not 425f7cc78ecSespiealready there) and a PC relative LDR instruction will be generated. 426f7cc78ecSespie 427f7cc78ecSespie@cindex @code{ADR reg,<label>} pseudo op, ARM 428f7cc78ecSespie@item ADR 429f7cc78ecSespie@smallexample 430f7cc78ecSespie adr <register> <label> 431f7cc78ecSespie@end smallexample 432f7cc78ecSespie 433f7cc78ecSespieThis instruction will load the address of @var{label} into the indicated 434f7cc78ecSespieregister. The instruction will evaluate to a PC relative ADD or SUB 435f7cc78ecSespieinstruction depending upon where the label is located. If the label is 436f7cc78ecSespieout of range, or if it is not defined in the same file (and section) as 437f7cc78ecSespiethe ADR instruction, then an error will be generated. This instruction 438f7cc78ecSespiewill not make use of the literal pool. 439f7cc78ecSespie 440f7cc78ecSespie@cindex @code{ADRL reg,<label>} pseudo op, ARM 441f7cc78ecSespie@item ADRL 442f7cc78ecSespie@smallexample 443f7cc78ecSespie adrl <register> <label> 444f7cc78ecSespie@end smallexample 445f7cc78ecSespie 446f7cc78ecSespieThis instruction will load the address of @var{label} into the indicated 4475f210c2aSfgschregister. The instruction will evaluate to one or two PC relative ADD 448f7cc78ecSespieor SUB instructions depending upon where the label is located. If a 449f7cc78ecSespiesecond instruction is not needed a NOP instruction will be generated in 450f7cc78ecSespieits place, so that this instruction is always 8 bytes long. 451f7cc78ecSespie 452f7cc78ecSespieIf the label is out of range, or if it is not defined in the same file 453f7cc78ecSespie(and section) as the ADRL instruction, then an error will be generated. 454f7cc78ecSespieThis instruction will not make use of the literal pool. 455f7cc78ecSespie 456f7cc78ecSespie@end table 457f7cc78ecSespie 458f7cc78ecSespieFor information on the ARM or Thumb instruction sets, see @cite{ARM 459f7cc78ecSespieSoftware Development Toolkit Reference Manual}, Advanced RISC Machines 460f7cc78ecSespieLtd. 461f7cc78ecSespie 462*cf2f2c56Smiod@node ARM Mapping Symbols 463*cf2f2c56Smiod@section Mapping Symbols 464*cf2f2c56Smiod 465*cf2f2c56SmiodThe ARM ELF specification requires that special symbols be inserted 466*cf2f2c56Smiodinto object files to mark certain features: 467*cf2f2c56Smiod 468*cf2f2c56Smiod@table @code 469*cf2f2c56Smiod 470*cf2f2c56Smiod@cindex @code{$a} 471*cf2f2c56Smiod@item $a 472*cf2f2c56SmiodAt the start of a region of code containing ARM instructions. 473*cf2f2c56Smiod 474*cf2f2c56Smiod@cindex @code{$t} 475*cf2f2c56Smiod@item $t 476*cf2f2c56SmiodAt the start of a region of code containing THUMB instructions. 477*cf2f2c56Smiod 478*cf2f2c56Smiod@cindex @code{$d} 479*cf2f2c56Smiod@item $d 480*cf2f2c56SmiodAt the start of a region of data. 481*cf2f2c56Smiod 482*cf2f2c56Smiod@end table 483*cf2f2c56Smiod 484*cf2f2c56SmiodThe assembler will automatically insert these symbols for you - there 485*cf2f2c56Smiodis no need to code them yourself. Support for tagging symbols ($b, 486*cf2f2c56Smiod$f, $p and $m) which is also mentioned in the current ARM ELF 487*cf2f2c56Smiodspecification is not implemented. This is because they have been 488*cf2f2c56Smioddropped from the new EABI and so tools cannot rely upon their 489*cf2f2c56Smiodpresence. 490*cf2f2c56Smiod 491