1@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003 2@c Free Software Foundation, Inc. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5 6@ifset GENERIC 7@page 8@node ARM-Dependent 9@chapter ARM Dependent Features 10@end ifset 11 12@ifclear GENERIC 13@node Machine Dependencies 14@chapter ARM Dependent Features 15@end ifclear 16 17@cindex ARM support 18@cindex Thumb support 19@menu 20* ARM Options:: Options 21* ARM Syntax:: Syntax 22* ARM Floating Point:: Floating Point 23* ARM Directives:: ARM Machine Directives 24* ARM Opcodes:: Opcodes 25* ARM Mapping Symbols:: Mapping Symbols 26@end menu 27 28@node ARM Options 29@section Options 30@cindex ARM options (none) 31@cindex options for ARM (none) 32 33@table @code 34 35@cindex @code{-mcpu=} command line option, ARM 36@item -mcpu=@var{processor}[+@var{extension}@dots{}] 37This option specifies the target processor. The assembler will issue an 38error message if an attempt is made to assemble an instruction which 39will not execute on the target processor. The following processor names are 40recognized: 41@code{arm1}, 42@code{arm2}, 43@code{arm250}, 44@code{arm3}, 45@code{arm6}, 46@code{arm60}, 47@code{arm600}, 48@code{arm610}, 49@code{arm620}, 50@code{arm7}, 51@code{arm7m}, 52@code{arm7d}, 53@code{arm7dm}, 54@code{arm7di}, 55@code{arm7dmi}, 56@code{arm70}, 57@code{arm700}, 58@code{arm700i}, 59@code{arm710}, 60@code{arm710t}, 61@code{arm720}, 62@code{arm720t}, 63@code{arm740t}, 64@code{arm710c}, 65@code{arm7100}, 66@code{arm7500}, 67@code{arm7500fe}, 68@code{arm7t}, 69@code{arm7tdmi}, 70@code{arm8}, 71@code{arm810}, 72@code{strongarm}, 73@code{strongarm1}, 74@code{strongarm110}, 75@code{strongarm1100}, 76@code{strongarm1110}, 77@code{arm9}, 78@code{arm920}, 79@code{arm920t}, 80@code{arm922t}, 81@code{arm940t}, 82@code{arm9tdmi}, 83@code{arm9e}, 84@code{arm926e}, 85@code{arm926ejs}, 86@code{arm946e-r0}, 87@code{arm946e}, 88@code{arm966e-r0}, 89@code{arm966e}, 90@code{arm10t}, 91@code{arm10e}, 92@code{arm1020}, 93@code{arm1020t}, 94@code{arm1020e}, 95@code{arm1026ejs}, 96@code{arm1136js}, 97@code{arm1136jfs}, 98@code{ep9312} (ARM920 with Cirrus Maverick coprocessor), 99@code{i80200} (Intel XScale processor) 100@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) 101and 102@code{xscale}. 103The special name @code{all} may be used to allow the 104assembler to accept instructions valid for any ARM processor. 105 106In addition to the basic instruction set, the assembler can be told to 107accept various extension mnemonics that extend the processor using the 108co-processor instruction space. For example, @code{-mcpu=arm920+maverick} 109is equivalent to specifying @code{-mcpu=ep9312}. The following extensions 110are currently supported: 111@code{+maverick} 112@code{+iwmmxt} 113and 114@code{+xscale}. 115 116@cindex @code{-march=} command line option, ARM 117@item -march=@var{architecture}[+@var{extension}@dots{}] 118This option specifies the target architecture. The assembler will issue 119an error message if an attempt is made to assemble an instruction which 120will not execute on the target architecture. The following architecture 121names are recognized: 122@code{armv1}, 123@code{armv2}, 124@code{armv2a}, 125@code{armv2s}, 126@code{armv3}, 127@code{armv3m}, 128@code{armv4}, 129@code{armv4xm}, 130@code{armv4t}, 131@code{armv4txm}, 132@code{armv5}, 133@code{armv5t}, 134@code{armv5txm}, 135@code{armv5te}, 136@code{armv5texp}, 137@code{armv6}, 138@code{armv6j}, 139@code{iwmmxt} 140and 141@code{xscale}. 142If both @code{-mcpu} and 143@code{-march} are specified, the assembler will use 144the setting for @code{-mcpu}. 145 146The architecture option can be extended with the same instruction set 147extension options as the @code{-mcpu} option. 148 149@cindex @code{-mfpu=} command line option, ARM 150@item -mfpu=@var{floating-point-format} 151 152This option specifies the floating point format to assemble for. The 153assembler will issue an error message if an attempt is made to assemble 154an instruction which will not execute on the target floating point unit. 155The following format options are recognized: 156@code{softfpa}, 157@code{fpe}, 158@code{fpe2}, 159@code{fpe3}, 160@code{fpa}, 161@code{fpa10}, 162@code{fpa11}, 163@code{arm7500fe}, 164@code{softvfp}, 165@code{softvfp+vfp}, 166@code{vfp}, 167@code{vfp10}, 168@code{vfp10-r0}, 169@code{vfp9}, 170@code{vfpxd}, 171@code{arm1020t}, 172@code{arm1020e}, 173@code{arm1136jfs} 174and 175@code{maverick}. 176 177In addition to determining which instructions are assembled, this option 178also affects the way in which the @code{.double} assembler directive behaves 179when assembling little-endian code. 180 181The default is dependent on the processor selected. For Architecture 5 or 182later, the default is to assembler for VFP instructions; for earlier 183architectures the default is to assemble for FPA instructions. 184 185@cindex @code{-mthumb} command line option, ARM 186@item -mthumb 187This option specifies that the assembler should start assembling Thumb 188instructions; that is, it should behave as though the file starts with a 189@code{.code 16} directive. 190 191@cindex @code{-mthumb-interwork} command line option, ARM 192@item -mthumb-interwork 193This option specifies that the output generated by the assembler should 194be marked as supporting interworking. 195 196@cindex @code{-mapcs} command line option, ARM 197@item -mapcs @code{[26|32]} 198This option specifies that the output generated by the assembler should 199be marked as supporting the indicated version of the Arm Procedure. 200Calling Standard. 201 202@cindex @code{-matpcs} command line option, ARM 203@item -matpcs 204This option specifies that the output generated by the assembler should 205be marked as supporting the Arm/Thumb Procedure Calling Standard. If 206enabled this option will cause the assembler to create an empty 207debugging section in the object file called .arm.atpcs. Debuggers can 208use this to determine the ABI being used by. 209 210@cindex @code{-mapcs-float} command line option, ARM 211@item -mapcs-float 212This indicates the floating point variant of the APCS should be 213used. In this variant floating point arguments are passed in FP 214registers rather than integer registers. 215 216@cindex @code{-mapcs-reentrant} command line option, ARM 217@item -mapcs-reentrant 218This indicates that the reentrant variant of the APCS should be used. 219This variant supports position independent code. 220 221@cindex @code{-mfloat-abi=} command line option, ARM 222@item -mfloat-abi=@var{abi} 223This option specifies that the output generated by the assembler should be 224marked as using specified floating point ABI. 225The following values are recognized: 226@code{soft}, 227@code{softfp} 228and 229@code{hard}. 230 231@cindex @code{-EB} command line option, ARM 232@item -EB 233This option specifies that the output generated by the assembler should 234be marked as being encoded for a big-endian processor. 235 236@cindex @code{-EL} command line option, ARM 237@item -EL 238This option specifies that the output generated by the assembler should 239be marked as being encoded for a little-endian processor. 240 241@cindex @code{-k} command line option, ARM 242@cindex PIC code generation for ARM 243@item -k 244This option specifies that the output of the assembler should be marked 245as position-independent code (PIC). 246 247@cindex @code{-moabi} command line option, ARM 248@item -moabi 249This indicates that the code should be assembled using the old ARM ELF 250conventions, based on a beta release release of the ARM-ELF 251specifications, rather than the default conventions which are based on 252the final release of the ARM-ELF specifications. 253 254@end table 255 256 257@node ARM Syntax 258@section Syntax 259@menu 260* ARM-Chars:: Special Characters 261* ARM-Regs:: Register Names 262@end menu 263 264@node ARM-Chars 265@subsection Special Characters 266 267@cindex line comment character, ARM 268@cindex ARM line comment character 269The presence of a @samp{@@} on a line indicates the start of a comment 270that extends to the end of the current line. If a @samp{#} appears as 271the first character of a line, the whole line is treated as a comment. 272 273@cindex line separator, ARM 274@cindex statement separator, ARM 275@cindex ARM line separator 276The @samp{;} character can be used instead of a newline to separate 277statements. 278 279@cindex immediate character, ARM 280@cindex ARM immediate character 281Either @samp{#} or @samp{$} can be used to indicate immediate operands. 282 283@cindex identifiers, ARM 284@cindex ARM identifiers 285*TODO* Explain about /data modifier on symbols. 286 287@node ARM-Regs 288@subsection Register Names 289 290@cindex ARM register names 291@cindex register names, ARM 292*TODO* Explain about ARM register naming, and the predefined names. 293 294@node ARM Floating Point 295@section Floating Point 296 297@cindex floating point, ARM (@sc{ieee}) 298@cindex ARM floating point (@sc{ieee}) 299The ARM family uses @sc{ieee} floating-point numbers. 300 301 302 303@node ARM Directives 304@section ARM Machine Directives 305 306@cindex machine directives, ARM 307@cindex ARM machine directives 308@table @code 309 310@cindex @code{align} directive, ARM 311@item .align @var{expression} [, @var{expression}] 312This is the generic @var{.align} directive. For the ARM however if the 313first argument is zero (ie no alignment is needed) the assembler will 314behave as if the argument had been 2 (ie pad to the next four byte 315boundary). This is for compatibility with ARM's own assembler. 316 317@cindex @code{req} directive, ARM 318@item @var{name} .req @var{register name} 319This creates an alias for @var{register name} called @var{name}. For 320example: 321 322@smallexample 323 foo .req r0 324@end smallexample 325 326@cindex @code{unreq} directive, ARM 327@item .unreq @var{alias-name} 328This undefines a register alias which was previously defined using the 329@code{req} directive. For example: 330 331@smallexample 332 foo .req r0 333 .unreq foo 334@end smallexample 335 336An error occurs if the name is undefined. Note - this pseudo op can 337be used to delete builtin in register name aliases (eg 'r0'). This 338should only be done if it is really necessary. 339 340@cindex @code{code} directive, ARM 341@item .code @code{[16|32]} 342This directive selects the instruction set being generated. The value 16 343selects Thumb, with the value 32 selecting ARM. 344 345@cindex @code{thumb} directive, ARM 346@item .thumb 347This performs the same action as @var{.code 16}. 348 349@cindex @code{arm} directive, ARM 350@item .arm 351This performs the same action as @var{.code 32}. 352 353@cindex @code{force_thumb} directive, ARM 354@item .force_thumb 355This directive forces the selection of Thumb instructions, even if the 356target processor does not support those instructions 357 358@cindex @code{thumb_func} directive, ARM 359@item .thumb_func 360This directive specifies that the following symbol is the name of a 361Thumb encoded function. This information is necessary in order to allow 362the assembler and linker to generate correct code for interworking 363between Arm and Thumb instructions and should be used even if 364interworking is not going to be performed. The presence of this 365directive also implies @code{.thumb} 366 367@cindex @code{thumb_set} directive, ARM 368@item .thumb_set 369This performs the equivalent of a @code{.set} directive in that it 370creates a symbol which is an alias for another symbol (possibly not yet 371defined). This directive also has the added property in that it marks 372the aliased symbol as being a thumb function entry point, in the same 373way that the @code{.thumb_func} directive does. 374 375@cindex @code{.ltorg} directive, ARM 376@item .ltorg 377This directive causes the current contents of the literal pool to be 378dumped into the current section (which is assumed to be the .text 379section) at the current location (aligned to a word boundary). 380@code{GAS} maintains a separate literal pool for each section and each 381sub-section. The @code{.ltorg} directive will only affect the literal 382pool of the current section and sub-section. At the end of assembly 383all remaining, un-empty literal pools will automatically be dumped. 384 385Note - older versions of @code{GAS} would dump the current literal 386pool any time a section change occurred. This is no longer done, since 387it prevents accurate control of the placement of literal pools. 388 389@cindex @code{.pool} directive, ARM 390@item .pool 391This is a synonym for .ltorg. 392 393@end table 394 395@node ARM Opcodes 396@section Opcodes 397 398@cindex ARM opcodes 399@cindex opcodes for ARM 400@code{@value{AS}} implements all the standard ARM opcodes. It also 401implements several pseudo opcodes, including several synthetic load 402instructions. 403 404@table @code 405 406@cindex @code{NOP} pseudo op, ARM 407@item NOP 408@smallexample 409 nop 410@end smallexample 411 412This pseudo op will always evaluate to a legal ARM instruction that does 413nothing. Currently it will evaluate to MOV r0, r0. 414 415@cindex @code{LDR reg,=<label>} pseudo op, ARM 416@item LDR 417@smallexample 418 ldr <register> , = <expression> 419@end smallexample 420 421If expression evaluates to a numeric constant then a MOV or MVN 422instruction will be used in place of the LDR instruction, if the 423constant can be generated by either of these instructions. Otherwise 424the constant will be placed into the nearest literal pool (if it not 425already there) and a PC relative LDR instruction will be generated. 426 427@cindex @code{ADR reg,<label>} pseudo op, ARM 428@item ADR 429@smallexample 430 adr <register> <label> 431@end smallexample 432 433This instruction will load the address of @var{label} into the indicated 434register. The instruction will evaluate to a PC relative ADD or SUB 435instruction depending upon where the label is located. If the label is 436out of range, or if it is not defined in the same file (and section) as 437the ADR instruction, then an error will be generated. This instruction 438will not make use of the literal pool. 439 440@cindex @code{ADRL reg,<label>} pseudo op, ARM 441@item ADRL 442@smallexample 443 adrl <register> <label> 444@end smallexample 445 446This instruction will load the address of @var{label} into the indicated 447register. The instruction will evaluate to one or two PC relative ADD 448or SUB instructions depending upon where the label is located. If a 449second instruction is not needed a NOP instruction will be generated in 450its place, so that this instruction is always 8 bytes long. 451 452If the label is out of range, or if it is not defined in the same file 453(and section) as the ADRL instruction, then an error will be generated. 454This instruction will not make use of the literal pool. 455 456@end table 457 458For information on the ARM or Thumb instruction sets, see @cite{ARM 459Software Development Toolkit Reference Manual}, Advanced RISC Machines 460Ltd. 461 462@node ARM Mapping Symbols 463@section Mapping Symbols 464 465The ARM ELF specification requires that special symbols be inserted 466into object files to mark certain features: 467 468@table @code 469 470@cindex @code{$a} 471@item $a 472At the start of a region of code containing ARM instructions. 473 474@cindex @code{$t} 475@item $t 476At the start of a region of code containing THUMB instructions. 477 478@cindex @code{$d} 479@item $d 480At the start of a region of data. 481 482@end table 483 484The assembler will automatically insert these symbols for you - there 485is no need to code them yourself. Support for tagging symbols ($b, 486$f, $p and $m) which is also mentioned in the current ARM ELF 487specification is not implemented. This is because they have been 488dropped from the new EABI and so tools cannot rely upon their 489presence. 490 491