1@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2003 2@c Free Software Foundation, Inc. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5@ifset GENERIC 6@page 7@node M32R-Dependent 8@chapter M32R Dependent Features 9@end ifset 10@ifclear GENERIC 11@node Machine Dependencies 12@chapter M32R Dependent Features 13@end ifclear 14 15@cindex M32R support 16@menu 17* M32R-Opts:: M32R Options 18* M32R-Directives:: M32R Directives 19* M32R-Warnings:: M32R Warnings 20@end menu 21 22@node M32R-Opts 23@section M32R Options 24 25@cindex options, M32R 26@cindex M32R options 27 28The Renease M32R version of @code{@value{AS}} has a few machine 29dependent options: 30 31@table @code 32 33@item -m32rx 34@cindex @samp{-m32rx} option, M32RX 35@cindex architecture options, M32RX 36@cindex M32R architecture options 37@code{@value{AS}} can assemble code for several different members of the 38Renesas M32R family. Normally the default is to assemble code for 39the M32R microprocessor. This option may be used to change the default 40to the M32RX microprocessor, which adds some more instructions to the 41basic M32R instruction set, and some additional parameters to some of 42the original instructions. 43 44@item -m32r2 45@cindex @samp{-m32rx} option, M32R2 46@cindex architecture options, M32R2 47@cindex M32R architecture options 48This option changes the target processor to the the M32R2 49microprocessor. 50 51@item -m32r 52@cindex @samp{-m32r} option, M32R 53@cindex architecture options, M32R 54@cindex M32R architecture options 55This option can be used to restore the assembler's default behaviour of 56assembling for the M32R microprocessor. This can be useful if the 57default has been changed by a previous command line option. 58 59@item -little 60@cindex @code{-little} option, M32R 61This option tells the assembler to produce little-endian code and 62data. The default is dependent upon how the toolchain was 63configured. 64 65@item -EL 66@cindex @code{-EL} option, M32R 67This is a synonum for @emph{-little}. 68 69@item -big 70@cindex @code{-big} option, M32R 71This option tells the assembler to produce big-endian code and 72data. 73 74@item -EB 75@cindex @code{-EB} option, M32R 76This is a synonum for @emph{-big}. 77 78@item -KPIC 79@cindex @code{-KPIC} option, M32R 80@cindex PIC code generation for M32R 81This option specifies that the output of the assembler should be 82marked as position-independent code (PIC). 83 84@item -parallel 85@cindex @code{-parallel} option, M32RX 86This option tells the assembler to attempts to combine two sequential 87instructions into a single, parallel instruction, where it is legal to 88do so. 89 90@item -no-parallel 91@cindex @code{-no-parallel} option, M32RX 92This option disables a previously enabled @emph{-parallel} option. 93 94@item -O 95@cindex @code{-O} option, M32RX 96This option tells the assembler to attempt to optimize the 97instructions that it produces. This includes filling delay slots and 98converting sequential instructions into parallel ones. This option 99implies @emph{-parallel}. 100 101@item -warn-explicit-parallel-conflicts 102@cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX 103Instructs @code{@value{AS}} to produce warning messages when 104questionable parallel instructions are encountered. This option is 105enabled by default, but @code{@value{GCC}} disables it when it invokes 106@code{@value{AS}} directly. Questionable instructions are those whoes 107behaviour would be different if they were executed sequentially. For 108example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a 109different result from @samp{mv r1, r2 \n mv r3, r1} since the former 110moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 111and r3. 112 113@item -Wp 114@cindex @samp{-Wp} option, M32RX 115This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts} 116option. 117 118@item -no-warn-explicit-parallel-conflicts 119@cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX 120Instructs @code{@value{AS}} not to produce warning messages when 121questionable parallel instructions are encountered. 122 123@item -Wnp 124@cindex @samp{-Wnp} option, M32RX 125This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts} 126option. 127 128@item -ignore-parallel-conflicts 129@cindex @samp{-ignore-parallel-conflicts} option, M32RX 130This option tells the assembler's to stop checking parallel 131instructions for contraint violations. This ability is provided for 132hardware vendors testing chip designs and should not be used under 133normal circumstances. 134 135@item -no-ignore-parallel-conflicts 136@cindex @samp{-no-ignore-parallel-conflicts} option, M32RX 137This option restores the assembler's default behaviour of checking 138parallel instructions to detect constraint violations. 139 140@item -Ip 141@cindex @samp{-Ip} option, M32RX 142This is a shorter synonym for the @emph{-ignore-parallel-conflicts} 143option. 144 145@item -nIp 146@cindex @samp{-nIp} option, M32RX 147This is a shorter synonym for the @emph{-no-ignore-parallel-conflicts} 148option. 149 150@item -warn-unmatched-high 151@cindex @samp{-warn-unmatched-high} option, M32R 152This option tells the assembler to produce a warning message if a 153@code{.high} pseudo op is encountered without a mathcing @code{.low} 154pseudo op. The presence of such an unmatches pseudo op usually 155indicates a programming error. 156 157@item -no-warn-unmatched-high 158@cindex @samp{-no-warn-unmatched-high} option, M32R 159Disables a previously enabled @emph{-warn-unmatched-high} option. 160 161@item -Wuh 162@cindex @samp{-Wuh} option, M32RX 163This is a shorter synonym for the @emph{-warn-unmatched-high} option. 164 165@item -Wnuh 166@cindex @samp{-Wnuh} option, M32RX 167This is a shorter synonym for the @emph{-no-warn-unmatched-high} option. 168 169@end table 170 171@node M32R-Directives 172@section M32R Directives 173@cindex directives, M32R 174@cindex M32R directives 175 176The Renease M32R version of @code{@value{AS}} has a few architecture 177specific directives: 178 179@table @code 180 181@cindex @code{low} directive, M32R 182@item low @var{expression} 183The @code{low} directive computes the value of its expression and 184places the lower 16-bits of the result into the immediate-field of the 185instruction. For example: 186 187@smallexample 188 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 189 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred 190@end smallexample 191 192@item high @var{expression} 193@cindex @code{high} directive, M32R 194The @code{high} directive computes the value of its expression and 195places the upper 16-bits of the result into the immediate-field of the 196instruction. For example: 197 198@smallexample 199 seth r0, #high(0x12345678) ; compute r0 = 0x12340000 200 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred 201@end smallexample 202 203@item shigh @var{expression} 204@cindex @code{shigh} directive, M32R 205The @code{shigh} directive is very similar to the @code{high} 206directive. It also computes the value of its expression and places 207the upper 16-bits of the result into the immediate-field of the 208instruction. The difference is that @code{shigh} also checks to see 209if the lower 16-bits could be interpreted as a signed number, and if 210so it assumes that a borrow will occur from the upper-16 bits. To 211compensate for this the @code{shigh} directive pre-biases the upper 21216 bit value by adding one to it. For example: 213 214For example: 215 216@smallexample 217 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 218 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 219@end smallexample 220 221In the second example the lower 16-bits are 0x8000. If these are 222treated as a signed value and sign extended to 32-bits then the value 223becomes 0xffff8000. If this value is then added to 0x00010000 then 224the result is 0x00008000. 225 226This behaviour is to allow for the different semantics of the 227@code{or3} and @code{add3} instructions. The @code{or3} instruction 228treats its 16-bit immediate argument as unsigned whereas the 229@code{add3} treats its 16-bit immediate as a signed value. So for 230example: 231 232@smallexample 233 seth r0, #shigh(0x00008000) 234 add3 r0, r0, #low(0x00008000) 235@end smallexample 236 237Produces the correct result in r0, whereas: 238 239@smallexample 240 seth r0, #shigh(0x00008000) 241 or3 r0, r0, #low(0x00008000) 242@end smallexample 243 244Stores 0xffff8000 into r0. 245 246Note - the @code{shigh} directive does not know where in the assembly 247source code the lower 16-bits of the value are going set, so it cannot 248check to make sure that an @code{or3} instruction is being used rather 249than an @code{add3} instruction. It is up to the programmer to make 250sure that correct directives are used. 251 252@cindex @code{.m32r} directive, M32R 253@item .m32r 254The directive performs a similar thing as the @emph{-m32r} command 255line option. It tells the assembler to only accept M32R instructions 256from now on. An instructions from later M32R architectures are 257refused. 258 259@cindex @code{.m32rx} directive, M32RX 260@item .m32rx 261The directive performs a similar thing as the @emph{-m32rx} command 262line option. It tells the assembler to start accepting the extra 263instructions in the M32RX ISA as well as the ordinary M32R ISA. 264 265@cindex @code{.m32r2} directive, M32R2 266@item .m32r2 267The directive performs a similar thing as the @emph{-m32r2} command 268line option. It tells the assembler to start accepting the extra 269instructions in the M32R2 ISA as well as the ordinary M32R ISA. 270 271@cindex @code{.little} directive, M32RX 272@item .little 273The directive performs a similar thing as the @emph{-little} command 274line option. It tells the assembler to start producing little-endian 275code and data. This option should be used with care as producing 276mixed-endian binary files is frought with danger. 277 278@cindex @code{.big} directive, M32RX 279@item .big 280The directive performs a similar thing as the @emph{-big} command 281line option. It tells the assembler to start producing big-endian 282code and data. This option should be used with care as producing 283mixed-endian binary files is frought with danger. 284 285@end table 286 287@node M32R-Warnings 288@section M32R Warnings 289 290@cindex warnings, M32R 291@cindex M32R warnings 292 293There are several warning and error messages that can be produced by 294@code{@value{AS}} which are specific to the M32R: 295 296@table @code 297 298@item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ? 299This message is only produced if warnings for explicit parallel 300conflicts have been enabled. It indicates that the assembler has 301encountered a parallel instruction in which the destination register of 302the left hand instruction is used as an input register in the right hand 303instruction. For example in this code fragment 304@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the 305move instruction and the input to the neg instruction. 306 307@item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ? 308This message is only produced if warnings for explicit parallel 309conflicts have been enabled. It indicates that the assembler has 310encountered a parallel instruction in which the destination register of 311the right hand instruction is used as an input register in the left hand 312instruction. For example in this code fragment 313@samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the 314neg instruction and the input to the move instruction. 315 316@item instruction @samp{...} is for the M32RX only 317This message is produced when the assembler encounters an instruction 318which is only supported by the M32Rx processor, and the @samp{-m32rx} 319command line flag has not been specified to allow assembly of such 320instructions. 321 322@item unknown instruction @samp{...} 323This message is produced when the assembler encounters an instruction 324which it does not recognise. 325 326@item only the NOP instruction can be issued in parallel on the m32r 327This message is produced when the assembler encounters a parallel 328instruction which does not involve a NOP instruction and the 329@samp{-m32rx} command line flag has not been specified. Only the M32Rx 330processor is able to execute two instructions in parallel. 331 332@item instruction @samp{...} cannot be executed in parallel. 333This message is produced when the assembler encounters a parallel 334instruction which is made up of one or two instructions which cannot be 335executed in parallel. 336 337@item Instructions share the same execution pipeline 338This message is produced when the assembler encounters a parallel 339instruction whoes components both use the same execution pipeline. 340 341@item Instructions write to the same destination register. 342This message is produced when the assembler encounters a parallel 343instruction where both components attempt to modify the same register. 344For example these code fragments will produce this message: 345@samp{mv r1, r2 || neg r1, r3} 346@samp{jl r0 || mv r14, r1} 347@samp{st r2, @@-r1 || mv r1, r3} 348@samp{mv r1, r2 || ld r0, @@r1+} 349@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit) 350 351@end table 352