1@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2@c 2002, 2003, 2004 3@c Free Software Foundation, Inc. 4@c This is part of the GAS manual. 5@c For copying conditions, see the file as.texinfo. 6@ifset GENERIC 7@page 8@node MIPS-Dependent 9@chapter MIPS Dependent Features 10@end ifset 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter MIPS Dependent Features 14@end ifclear 15 16@cindex MIPS processor 17@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several 18different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, 19and MIPS64. For information about the @sc{mips} instruction set, see 20@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). 21For an overview of @sc{mips} assembly conventions, see ``Appendix D: 22Assembly Language Programming'' in the same work. 23 24@menu 25* MIPS Opts:: Assembler options 26* MIPS Object:: ECOFF object code 27* MIPS Stabs:: Directives for debugging information 28* MIPS ISA:: Directives to override the ISA level 29* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 30* MIPS insn:: Directive to mark data as an instruction 31* MIPS option stack:: Directives to save and restore options 32* MIPS ASE instruction generation overrides:: Directives to control 33 generation of MIPS ASE instructions 34@end menu 35 36@node MIPS Opts 37@section Assembler options 38 39The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these 40special options: 41 42@table @code 43@cindex @code{-G} option (MIPS) 44@item -G @var{num} 45This option sets the largest size of an object that can be referenced 46implicitly with the @code{gp} register. It is only accepted for targets 47that use @sc{ecoff} format. The default value is 8. 48 49@cindex @code{-EB} option (MIPS) 50@cindex @code{-EL} option (MIPS) 51@cindex MIPS big-endian output 52@cindex MIPS little-endian output 53@cindex big-endian output, MIPS 54@cindex little-endian output, MIPS 55@item -EB 56@itemx -EL 57Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or 58little-endian output at run time (unlike the other @sc{gnu} development 59tools, which must be configured for one or the other). Use @samp{-EB} 60to select big-endian output, and @samp{-EL} for little-endian. 61 62@cindex MIPS architecture options 63@item -mips1 64@itemx -mips2 65@itemx -mips3 66@itemx -mips4 67@itemx -mips5 68@itemx -mips32 69@itemx -mips32r2 70@itemx -mips64 71@itemx -mips64r2 72Generate code for a particular MIPS Instruction Set Architecture level. 73@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, 74@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the 75@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and 76@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, 77@samp{-mips64}, and @samp{-mips64r2} 78correspond to generic 79@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, 80and @sc{MIPS64 Release 2} 81ISA processors, respectively. You can also switch 82instruction sets during the assembly; see @ref{MIPS ISA, Directives to 83override the ISA level}. 84 85@item -mgp32 86@itemx -mfp32 87Some macros have different expansions for 32-bit and 64-bit registers. 88The register sizes are normally inferred from the ISA and ABI, but these 89flags force a certain group of registers to be treated as 32 bits wide at 90all times. @samp{-mgp32} controls the size of general-purpose registers 91and @samp{-mfp32} controls the size of floating-point registers. 92 93On some MIPS variants there is a 32-bit mode flag; when this flag is 94set, 64-bit instructions generate a trap. Also, some 32-bit OSes only 95save the 32-bit registers on a context switch, so it is essential never 96to use the 64-bit registers. 97 98@item -mgp64 99Assume that 64-bit general purpose registers are available. This is 100provided in the interests of symmetry with -gp32. 101 102@item -mips16 103@itemx -no-mips16 104Generate code for the MIPS 16 processor. This is equivalent to putting 105@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16} 106turns off this option. 107 108@item -mips3d 109@itemx -no-mips3d 110Generate code for the MIPS-3D Application Specific Extension. 111This tells the assembler to accept MIPS-3D instructions. 112@samp{-no-mips3d} turns off this option. 113 114@item -mdmx 115@itemx -no-mdmx 116Generate code for the MDMX Application Specific Extension. 117This tells the assembler to accept MDMX instructions. 118@samp{-no-mdmx} turns off this option. 119 120@item -mfix7000 121@itemx -mno-fix7000 122Cause nops to be inserted if the read of the destination register 123of an mfhi or mflo instruction occurs in the following two instructions. 124 125@item -mfix-vr4120 126@itemx -no-mfix-vr4120 127Insert nops to work around certain VR4120 errata. This option is 128intended to be used on GCC-generated code: it is not designed to catch 129all problems in hand-written assembler code. 130 131@item -mfix-loongson2f-btb 132@itemx -mno-fix-loongson2f-btb 133Clear the Branch Target Buffer before any jump through a register. This 134option is intended to be used on kernel code for the Loongson 2F processor 135only; userland code compiled with this option will fault, and kernel code 136compiled with this option run on another processor than Loongson 2F will 137yield unpredictable results. 138 139@item -m4010 140@itemx -no-m4010 141Generate code for the LSI @sc{r4010} chip. This tells the assembler to 142accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, 143etc.), and to not schedule @samp{nop} instructions around accesses to 144the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this 145option. 146 147@item -m4650 148@itemx -no-m4650 149Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept 150the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} 151instructions around accesses to the @samp{HI} and @samp{LO} registers. 152@samp{-no-m4650} turns off this option. 153 154@itemx -m3900 155@itemx -no-m3900 156@itemx -m4100 157@itemx -no-m4100 158For each option @samp{-m@var{nnnn}}, generate code for the MIPS 159@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions 160specific to that chip, and to schedule for that chip's hazards. 161 162@item -march=@var{cpu} 163Generate code for a particular MIPS cpu. It is exactly equivalent to 164@samp{-m@var{cpu}}, except that there are more value of @var{cpu} 165understood. Valid @var{cpu} value are: 166 167@quotation 1682000, 1693000, 1703900, 1714000, 1724010, 1734100, 1744111, 175vr4120, 176vr4130, 177vr4181, 1784300, 1794400, 1804600, 1814650, 1825000, 183rm5200, 184rm5230, 185rm5231, 186rm5261, 187rm5721, 188vr5400, 189vr5500, 1906000, 191rm7000, 1928000, 193rm9000, 19410000, 19512000, 196mips32-4k, 197sb1 198@end quotation 199 200@item -mtune=@var{cpu} 201Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are 202identical to @samp{-march=@var{cpu}}. 203 204@item -mabi=@var{abi} 205Record which ABI the source code uses. The recognized arguments 206are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. 207 208@cindex @code{-nocpp} ignored (MIPS) 209@item -nocpp 210This option is ignored. It is accepted for command-line compatibility with 211other assemblers, which use it to turn off C style preprocessing. With 212@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the 213@sc{gnu} assembler itself never runs the C preprocessor. 214 215@item --construct-floats 216@itemx --no-construct-floats 217@cindex --construct-floats 218@cindex --no-construct-floats 219The @code{--no-construct-floats} option disables the construction of 220double width floating point constants by loading the two halves of the 221value into the two single width floating point registers that make up 222the double width register. This feature is useful if the processor 223support the FR bit in its status register, and this bit is known (by 224the programmer) to be set. This bit prevents the aliasing of the double 225width register by the single width registers. 226 227By default @code{--construct-floats} is selected, allowing construction 228of these floating point constants. 229 230@item --trap 231@itemx --no-break 232@c FIXME! (1) reflect these options (next item too) in option summaries; 233@c (2) stop teasing, say _which_ instructions expanded _how_. 234@code{@value{AS}} automatically macro expands certain division and 235multiplication instructions to check for overflow and division by zero. This 236option causes @code{@value{AS}} to generate code to take a trap exception 237rather than a break exception when an error is detected. The trap instructions 238are only supported at Instruction Set Architecture level 2 and higher. 239 240@item --break 241@itemx --no-trap 242Generate code to take a break exception rather than a trap exception when an 243error is detected. This is the default. 244 245@item -mpdr 246@itemx -mno-pdr 247Control generation of @code{.pdr} sections. Off by default on IRIX, on 248elsewhere. 249@end table 250 251@node MIPS Object 252@section MIPS ECOFF object code 253 254@cindex ECOFF sections 255@cindex MIPS ECOFF sections 256Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections 257besides the usual @code{.text}, @code{.data} and @code{.bss}. The 258additional sections are @code{.rdata}, used for read-only data, 259@code{.sdata}, used for small data, and @code{.sbss}, used for small 260common objects. 261 262@cindex small objects, MIPS ECOFF 263@cindex @code{gp} register, MIPS 264When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) 265register to form the address of a ``small object''. Any object in the 266@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. 267For external objects, or for objects in the @code{.bss} section, you can use 268the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via 269@code{$gp}; the default value is 8, meaning that a reference to any object 270eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to 271@code{@value{AS}} prevents it from using the @code{$gp} register on the basis 272of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} 273or @code{sbss} in any case). The size of an object in the @code{.bss} section 274is set by the @code{.comm} or @code{.lcomm} directive that defines it. The 275size of an external object may be set with the @code{.extern} directive. For 276example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes 277in length, whie leaving @code{sym} otherwise undefined. 278 279Using small @sc{ecoff} objects requires linker support, and assumes that the 280@code{$gp} register is correctly initialized (normally done automatically by 281the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the 282@code{$gp} register. 283 284@node MIPS Stabs 285@section Directives for debugging information 286 287@cindex MIPS debugging directives 288@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for 289generating debugging information which are not support by traditional @sc{mips} 290assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, 291@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, 292@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information 293generated by the three @code{.stab} directives can only be read by @sc{gdb}, 294not by traditional @sc{mips} debuggers (this enhancement is required to fully 295support C++ debugging). These directives are primarily used by compilers, not 296assembly language programmers! 297 298@node MIPS ISA 299@section Directives to override the ISA level 300 301@cindex MIPS ISA override 302@kindex @code{.set mips@var{n}} 303@sc{gnu} @code{@value{AS}} supports an additional directive to change 304the @sc{mips} Instruction Set Architecture level on the fly: @code{.set 305mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 306or 64r2. 307The values other than 0 make the assembler accept instructions 308for the corresponding @sc{isa} level, from that point on in the 309assembly. @code{.set mips@var{n}} affects not only which instructions 310are permitted, but also how certain macros are expanded. @code{.set 311mips0} restores the @sc{isa} level to its original level: either the 312level you selected with command line options, or the default for your 313configuration. You can use this feature to permit specific @sc{r4000} 314instructions while assembling in 32 bit mode. Use this directive with 315care! 316 317The directive @samp{.set mips16} puts the assembler into MIPS 16 mode, 318in which it will assemble instructions for the MIPS 16 processor. Use 319@samp{.set nomips16} to return to normal 32 bit mode. 320 321Traditional @sc{mips} assemblers do not support this directive. 322 323@node MIPS autoextend 324@section Directives for extending MIPS 16 bit instructions 325 326@kindex @code{.set autoextend} 327@kindex @code{.set noautoextend} 328By default, MIPS 16 instructions are automatically extended to 32 bits 329when necessary. The directive @samp{.set noautoextend} will turn this 330off. When @samp{.set noautoextend} is in effect, any 32 bit instruction 331must be explicitly extended with the @samp{.e} modifier (e.g., 332@samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used 333to once again automatically extend instructions when necessary. 334 335This directive is only meaningful when in MIPS 16 mode. Traditional 336@sc{mips} assemblers do not support this directive. 337 338@node MIPS insn 339@section Directive to mark data as an instruction 340 341@kindex @code{.insn} 342The @code{.insn} directive tells @code{@value{AS}} that the following 343data is actually instructions. This makes a difference in MIPS 16 mode: 344when loading the address of a label which precedes instructions, 345@code{@value{AS}} automatically adds 1 to the value, so that jumping to 346the loaded address will do the right thing. 347 348@node MIPS option stack 349@section Directives to save and restore options 350 351@cindex MIPS option stack 352@kindex @code{.set push} 353@kindex @code{.set pop} 354The directives @code{.set push} and @code{.set pop} may be used to save 355and restore the current settings for all the options which are 356controlled by @code{.set}. The @code{.set push} directive saves the 357current settings on a stack. The @code{.set pop} directive pops the 358stack and restores the settings. 359 360These directives can be useful inside an macro which must change an 361option such as the ISA level or instruction reordering but does not want 362to change the state of the code which invoked the macro. 363 364Traditional @sc{mips} assemblers do not support these directives. 365 366@node MIPS ASE instruction generation overrides 367@section Directives to control generation of MIPS ASE instructions 368 369@cindex MIPS MIPS-3D instruction generation override 370@kindex @code{.set mips3d} 371@kindex @code{.set nomips3d} 372The directive @code{.set mips3d} makes the assembler accept instructions 373from the MIPS-3D Application Specific Extension from that point on 374in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D 375instructions from being accepted. 376 377@cindex MIPS MDMX instruction generation override 378@kindex @code{.set mdmx} 379@kindex @code{.set nomdmx} 380The directive @code{.set mdmx} makes the assembler accept instructions 381from the MDMX Application Specific Extension from that point on 382in the assembly. The @code{.set nomdmx} directive prevents MDMX 383instructions from being accepted. 384 385Traditional @sc{mips} assemblers do not support these directives. 386