1 /* opcode/i386.h -- Intel 80386 opcode table 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 21 22 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived 23 ix86 Unix assemblers, generate floating point instructions with 24 reversed source and destination registers in certain cases. 25 Unfortunately, gcc and possibly many other programs use this 26 reversed syntax, so we're stuck with it. 27 28 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but 29 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than 30 the expected st(3) = st(3) - st 31 32 This happens with all the non-commutative arithmetic floating point 33 operations with two register operands, where the source register is 34 %st, and destination register is %st(i). See FloatDR below. 35 36 The affected opcode map is dceX, dcfX, deeX, defX. */ 37 38 #ifndef SYSV386_COMPAT 39 /* Set non-zero for broken, compatible instructions. Set to zero for 40 non-broken opcodes at your peril. gcc generates SystemV/386 41 compatible instructions. */ 42 #define SYSV386_COMPAT 1 43 #endif 44 #ifndef OLDGCC_COMPAT 45 /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could 46 generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands 47 reversed. */ 48 #define OLDGCC_COMPAT SYSV386_COMPAT 49 #endif 50 51 static const template i386_optab[] = { 52 53 #define X None 54 #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) 55 #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) 56 #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) 57 #define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf) 58 #define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) 59 #define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf) 60 #define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf) 61 #define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf) 62 #define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf) 63 #define wlq_Suf (No_bSuf|No_sSuf|No_xSuf) 64 #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf) 65 #define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf) 66 #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf) 67 #define sldx_Suf (No_bSuf|No_wSuf|No_qSuf) 68 #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf) 69 #define bwlq_Suf (No_sSuf|No_xSuf) 70 #define FP (NoSuf|IgnoreSize) 71 #define l_FP (l_Suf|IgnoreSize) 72 #define x_FP (x_Suf|IgnoreSize) 73 #define sl_FP (sl_Suf|IgnoreSize) 74 #if SYSV386_COMPAT 75 /* Someone forgot that the FloatR bit reverses the operation when not 76 equal to the FloatD bit. ie. Changing only FloatD results in the 77 destination being swapped *and* the direction being reversed. */ 78 #define FloatDR FloatD 79 #else 80 #define FloatDR (FloatD|FloatR) 81 #endif 82 83 /* Move instructions. */ 84 #define MOV_AX_DISP32 0xa0 85 /* In the 64bit mode the short form mov immediate is redefined to have 86 64bit displacement value. */ 87 { "mov", 2, 0xa0, X, CpuNo64,bwlq_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, 88 { "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 89 /* In the 64bit mode the short form mov immediate is redefined to have 90 64bit displacement value. */ 91 { "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } }, 92 { "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } }, 93 { "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, 94 /* The segment register moves accept WordReg so that a segment register 95 can be copied to a 32 bit register, and vice versa, without using a 96 size prefix. When moving to a 32 bit register, the upper 16 bits 97 are set to an implementation defined value (on the Pentium Pro, 98 the implementation defined value is zero). */ 99 { "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } }, 100 { "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } }, 101 { "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } }, 102 { "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } }, 103 /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit 104 mode they are 64bit.*/ 105 { "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} }, 106 { "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, 107 { "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, 108 { "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, 109 { "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, 110 { "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, 111 { "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, 112 113 /* Move with sign extend. */ 114 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid 115 conflict with the "movs" string move instruction. */ 116 {"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, 117 {"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, 118 {"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} }, 119 {"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, 120 {"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} }, 121 {"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, 122 /* Intel Syntax next 5 insns */ 123 {"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, 124 {"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} }, 125 {"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, 126 {"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, 127 {"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, 128 129 /* Move with zero extend. */ 130 {"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, 131 {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, 132 /* These instructions are not particulary usefull, since the zero extend 133 32->64 is implicit, but we can encode them. */ 134 {"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, 135 {"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, 136 /* Intel Syntax next 4 insns */ 137 {"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, 138 {"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} }, 139 /* These instructions are not particulary usefull, since the zero extend 140 32->64 is implicit, but we can encode them. */ 141 {"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, 142 {"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, 143 144 /* Push instructions. */ 145 {"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, 146 {"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, 147 {"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, 148 {"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, 149 {"push", 1, 0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, 150 {"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, 151 /* In 64bit mode, the operand size is implicitly 64bit. */ 152 {"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } }, 153 {"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } }, 154 {"push", 1, 0x6a, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, 155 {"push", 1, 0x68, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} }, 156 {"push", 1, 0x06, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, 157 {"push", 1, 0x0fa0, X, Cpu386|Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, 158 159 {"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, 160 161 /* Pop instructions. */ 162 {"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, 163 {"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, 164 #define POP_SEG_SHORT 0x07 165 {"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, 166 {"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, 167 /* In 64bit mode, the operand size is implicitly 64bit. */ 168 {"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } }, 169 {"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } }, 170 {"pop", 1, 0x07, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, 171 {"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, 172 173 {"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, 174 175 /* Exchange instructions. 176 xchg commutes: we allow both operand orders. 177 178 In the 64bit code, xchg eax, eax is reused for new nop instruction. 179 */ 180 {"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } }, 181 {"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } }, 182 {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, 183 {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, 184 185 /* In/out from ports. */ 186 {"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } }, 187 {"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, 188 {"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, 189 {"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, 190 {"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } }, 191 {"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, 192 {"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, 193 {"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, 194 195 /* Load effective address. */ 196 {"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } }, 197 198 /* Load segment registers from memory. */ 199 {"lds", 2, 0xc5, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, 200 {"les", 2, 0xc4, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, 201 {"lfs", 2, 0x0fb4, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, 202 {"lgs", 2, 0x0fb5, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, 203 {"lss", 2, 0x0fb2, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, 204 205 /* Flags register instructions. */ 206 {"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} }, 207 {"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} }, 208 {"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} }, 209 {"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} }, 210 {"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} }, 211 {"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} }, 212 {"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} }, 213 {"pushf", 0, 0x9c, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, 214 {"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, 215 {"popf", 0, 0x9d, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, 216 {"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, 217 {"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, 218 {"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, 219 {"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} }, 220 221 /* Arithmetic. */ 222 {"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 223 {"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 224 {"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 225 {"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 226 227 {"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} }, 228 {"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 229 230 {"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 231 {"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 232 {"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 233 {"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 234 235 {"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} }, 236 {"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 237 238 {"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 239 {"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 240 {"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 241 {"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 242 243 {"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 244 {"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 245 {"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 246 {"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 247 248 {"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, 249 {"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, 250 {"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 251 {"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 252 253 {"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 254 {"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 255 {"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 256 {"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 257 258 {"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 259 {"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 260 {"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 261 {"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 262 263 {"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 264 {"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 265 {"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 266 {"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 267 268 /* clr with 1 operand is really xor with 2 operands. */ 269 {"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, 270 271 {"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 272 {"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 273 {"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, 274 {"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, 275 276 {"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 277 {"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 278 279 {"aaa", 0, 0x37, X, 0, NoSuf, { 0, 0, 0} }, 280 {"aas", 0, 0x3f, X, 0, NoSuf, { 0, 0, 0} }, 281 {"daa", 0, 0x27, X, 0, NoSuf, { 0, 0, 0} }, 282 {"das", 0, 0x2f, X, 0, NoSuf, { 0, 0, 0} }, 283 {"aad", 0, 0xd50a, X, 0, NoSuf, { 0, 0, 0} }, 284 {"aad", 1, 0xd5, X, 0, NoSuf, { Imm8S, 0, 0} }, 285 {"aam", 0, 0xd40a, X, 0, NoSuf, { 0, 0, 0} }, 286 {"aam", 1, 0xd4, X, 0, NoSuf, { Imm8S, 0, 0} }, 287 288 /* Conversion insns. */ 289 /* Intel naming */ 290 {"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, 291 {"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, 292 {"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, 293 {"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, 294 {"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, 295 {"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, 296 /* AT&T naming */ 297 {"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, 298 {"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, 299 {"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, 300 {"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, 301 {"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, 302 {"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, 303 304 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are 305 expanding 64-bit multiplies, and *cannot* be selected to accomplish 306 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) 307 These multiplies can only be selected with single operand forms. */ 308 {"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 309 {"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 310 {"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 311 {"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, 312 {"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} }, 313 /* imul with 2 operands mimics imul with 3 by putting the register in 314 both i.rm.reg & i.rm.regmem fields. regKludge enables this 315 transformation. */ 316 {"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, 317 {"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} }, 318 319 {"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 320 {"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, 321 {"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 322 {"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, 323 324 {"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 325 {"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 326 {"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 327 {"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 328 329 {"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 330 {"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 331 {"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 332 {"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 333 334 {"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 335 {"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 336 {"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 337 {"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 338 339 {"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 340 {"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 341 {"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 342 {"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 343 344 {"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 345 {"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 346 {"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 347 {"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 348 349 {"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 350 {"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 351 {"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 352 {"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 353 354 {"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 355 {"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 356 {"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 357 {"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 358 359 {"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 360 {"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 361 {"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 362 {"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 363 364 {"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, 365 {"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, 366 {"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 367 368 {"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, 369 {"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, 370 {"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 371 372 /* Control transfer instructions. */ 373 {"call", 1, 0xe8, X, 0, wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, 374 {"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, 375 {"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64,{ WordReg|WordMem|JumpAbsolute, 0, 0} }, 376 /* Intel Syntax */ 377 {"call", 2, 0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, 378 /* Intel Syntax */ 379 {"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} }, 380 {"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, 381 {"lcall", 1, 0xff, 3, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} }, 382 {"lcall", 1, 0xff, 3, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64,{ WordMem|JumpAbsolute, 0, 0} }, 383 384 #define JUMP_PC_RELATIVE 0xeb 385 {"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 386 {"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, 387 {"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { WordReg|WordMem|JumpAbsolute, 0, 0} }, 388 /* Intel Syntax */ 389 {"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, 390 /* Intel Syntax */ 391 {"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} }, 392 {"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, 393 {"ljmp", 1, 0xff, 5, CpuNo64, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, 394 {"ljmp", 1, 0xff, 5, Cpu64, q_Suf|Modrm|NoRex64, { WordMem|JumpAbsolute, 0, 0} }, 395 396 {"ret", 0, 0xc3, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, 397 {"ret", 1, 0xc2, X, CpuNo64,wlq_Suf|DefaultSize, { Imm16, 0, 0} }, 398 {"ret", 0, 0xc3, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, 399 {"ret", 1, 0xc2, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} }, 400 {"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, 401 {"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} }, 402 {"enter", 2, 0xc8, X, Cpu186, wlq_Suf|DefaultSize, { Imm16, Imm8, 0} }, 403 {"leave", 0, 0xc9, X, Cpu186, wlq_Suf|DefaultSize, { 0, 0, 0} }, 404 405 /* Conditional jumps. */ 406 {"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 407 {"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 408 {"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 409 {"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 410 {"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 411 {"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 412 {"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 413 {"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 414 {"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 415 {"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 416 {"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 417 {"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 418 {"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 419 {"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 420 {"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 421 {"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 422 {"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 423 {"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 424 {"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 425 {"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 426 {"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 427 {"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 428 {"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 429 {"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 430 {"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 431 {"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 432 {"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 433 {"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 434 {"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 435 {"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, 436 437 /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ 438 {"jcxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} }, 439 {"jecxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, 440 {"jecxz", 1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, 441 {"jrcxz", 1, 0xe3, X, Cpu64, NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} }, 442 443 /* The loop instructions also use the address size prefix to select 444 %cx rather than %ecx for the loop count, so the `w' form of these 445 instructions emit an address size prefix rather than a data size 446 prefix. */ 447 {"loop", 1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, 448 {"loop", 1, 0xe2, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, 449 {"loopz", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, 450 {"loopz", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, 451 {"loope", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, 452 {"loope", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, 453 {"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, 454 {"loopnz", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, 455 {"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, 456 {"loopne", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, 457 458 /* Set byte on flag instructions. */ 459 {"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 460 {"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 461 {"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 462 {"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 463 {"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 464 {"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 465 {"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 466 {"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 467 {"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 468 {"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 469 {"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 470 {"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 471 {"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 472 {"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 473 {"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 474 {"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 475 {"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 476 {"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 477 {"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 478 {"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 479 {"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 480 {"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 481 {"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 482 {"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 483 {"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 484 {"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 485 {"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 486 {"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 487 {"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 488 {"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 489 490 /* String manipulation. */ 491 {"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 492 {"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, 493 {"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 494 {"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, 495 {"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, 496 {"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, 497 {"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, 498 {"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, 499 {"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 500 {"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, 501 {"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, 502 {"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 503 {"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, 504 {"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, 505 {"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 506 {"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, 507 {"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 508 {"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, 509 {"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 510 {"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 511 {"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, 512 {"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 513 {"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 514 {"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, 515 {"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 516 {"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 517 {"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, 518 {"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, 519 {"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 520 {"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, 521 {"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} }, 522 {"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} }, 523 524 /* Bit manipulation. */ 525 {"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 526 {"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 527 {"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 528 {"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 529 {"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 530 {"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 531 {"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 532 {"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 533 {"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 534 {"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 535 536 /* Interrupts & op. sys insns. */ 537 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special 538 int 3 insn. */ 539 #define INT_OPCODE 0xcd 540 #define INT3_OPCODE 0xcc 541 {"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} }, 542 {"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} }, 543 {"into", 0, 0xce, X, 0, NoSuf, { 0, 0, 0} }, 544 {"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, 545 /* i386sl, i486sl, later 486, and Pentium. */ 546 {"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} }, 547 548 {"bound", 2, 0x62, X, Cpu186, wlq_Suf|Modrm, { WordReg, WordMem, 0} }, 549 550 {"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} }, 551 /* nop is actually 'xchgl %eax, %eax'. */ 552 {"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} }, 553 554 /* Protection control. */ 555 {"arpl", 2, 0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, 556 {"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 557 {"lgdt", 1, 0x0f01, 2, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, 558 {"lidt", 1, 0x0f01, 3, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, 559 {"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 560 {"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 561 {"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 562 {"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 563 564 {"sgdt", 1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, 565 {"sidt", 1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, 566 {"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, 567 {"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, 568 {"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, 569 {"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, 570 {"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, 571 {"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, 572 573 {"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 574 {"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 575 576 /* Floating point instructions. */ 577 578 /* load */ 579 {"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 580 {"fld", 1, 0xd9, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 581 {"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, 582 /* Intel Syntax */ 583 {"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} }, 584 {"fild", 1, 0xdf, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 585 /* Intel Syntax */ 586 {"fildd", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, 587 {"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, 588 {"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, 589 {"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, 590 {"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} }, 591 592 /* store (no pop) */ 593 {"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 594 {"fst", 1, 0xd9, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 595 {"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, 596 {"fist", 1, 0xdf, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 597 598 /* store (with pop) */ 599 {"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 600 {"fstp", 1, 0xd9, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 601 {"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, 602 /* Intel Syntax */ 603 {"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} }, 604 {"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 605 /* Intel Syntax */ 606 {"fistpd", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, 607 {"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, 608 {"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, 609 {"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, 610 {"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} }, 611 612 /* exchange %st<n> with %st0 */ 613 {"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 614 /* alias for fxch %st(1) */ 615 {"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} }, 616 617 /* comparison (without pop) */ 618 {"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 619 /* alias for fcom %st(1) */ 620 {"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} }, 621 {"fcom", 1, 0xd8, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 622 {"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, 623 {"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 624 625 /* comparison (with pop) */ 626 {"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 627 /* alias for fcomp %st(1) */ 628 {"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} }, 629 {"fcomp", 1, 0xd8, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 630 {"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, 631 {"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 632 {"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} }, 633 634 /* unordered comparison (with pop) */ 635 {"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, 636 /* alias for fucom %st(1) */ 637 {"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} }, 638 {"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, 639 /* alias for fucomp %st(1) */ 640 {"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} }, 641 {"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} }, 642 643 {"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} }, 644 {"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} }, 645 646 /* load constants into %st0 */ 647 {"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} }, 648 {"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} }, 649 {"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} }, 650 {"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} }, 651 {"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} }, 652 {"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} }, 653 {"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} }, 654 655 /* arithmetic */ 656 657 /* add */ 658 {"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 659 /* alias for fadd %st(i), %st */ 660 {"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 661 #if SYSV386_COMPAT 662 /* alias for faddp */ 663 {"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} }, 664 #endif 665 {"fadd", 1, 0xd8, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 666 {"fiadd", 1, 0xde, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 667 668 {"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 669 {"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 670 /* alias for faddp %st, %st(1) */ 671 {"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} }, 672 {"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 673 674 /* subtract */ 675 {"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 676 {"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 677 #if SYSV386_COMPAT 678 /* alias for fsubp */ 679 {"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} }, 680 #endif 681 {"fsub", 1, 0xd8, 4, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 682 {"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 683 684 #if SYSV386_COMPAT 685 {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 686 {"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 687 {"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, 688 #if OLDGCC_COMPAT 689 {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 690 #endif 691 #else 692 {"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 693 {"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 694 {"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, 695 #endif 696 697 /* subtract reverse */ 698 {"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 699 {"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 700 #if SYSV386_COMPAT 701 /* alias for fsubrp */ 702 {"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} }, 703 #endif 704 {"fsubr", 1, 0xd8, 5, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 705 {"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 706 707 #if SYSV386_COMPAT 708 {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 709 {"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 710 {"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, 711 #if OLDGCC_COMPAT 712 {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 713 #endif 714 #else 715 {"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 716 {"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 717 {"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, 718 #endif 719 720 /* multiply */ 721 {"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 722 {"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 723 #if SYSV386_COMPAT 724 /* alias for fmulp */ 725 {"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} }, 726 #endif 727 {"fmul", 1, 0xd8, 1, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 728 {"fimul", 1, 0xde, 1, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 729 730 {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 731 {"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 732 {"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} }, 733 {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 734 735 /* divide */ 736 {"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 737 {"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 738 #if SYSV386_COMPAT 739 /* alias for fdivp */ 740 {"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} }, 741 #endif 742 {"fdiv", 1, 0xd8, 6, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 743 {"fidiv", 1, 0xde, 6, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 744 745 #if SYSV386_COMPAT 746 {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 747 {"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 748 {"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, 749 #if OLDGCC_COMPAT 750 {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 751 #endif 752 #else 753 {"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 754 {"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 755 {"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, 756 #endif 757 758 /* divide reverse */ 759 {"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 760 {"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 761 #if SYSV386_COMPAT 762 /* alias for fdivrp */ 763 {"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} }, 764 #endif 765 {"fdivr", 1, 0xd8, 7, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 766 {"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 767 768 #if SYSV386_COMPAT 769 {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 770 {"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 771 {"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, 772 #if OLDGCC_COMPAT 773 {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 774 #endif 775 #else 776 {"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 777 {"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 778 {"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, 779 #endif 780 781 {"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} }, 782 {"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} }, 783 {"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} }, 784 {"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} }, 785 {"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} }, 786 {"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} }, 787 {"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} }, 788 {"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} }, 789 {"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} }, 790 {"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} }, 791 {"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} }, 792 {"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} }, 793 {"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} }, 794 {"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} }, 795 {"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} }, 796 {"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} }, 797 {"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} }, 798 {"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} }, 799 800 /* processor control */ 801 {"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} }, 802 {"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} }, 803 {"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} }, 804 {"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, 805 {"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, 806 {"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} }, 807 {"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, 808 {"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} }, 809 {"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} }, 810 {"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, 811 {"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} }, 812 {"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} }, 813 {"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} }, 814 /* Short forms of fldenv, fstenv use data size prefix. */ 815 {"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, 816 {"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, 817 {"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, 818 {"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, 819 {"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, 820 {"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, 821 822 {"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, 823 /* P6:free st(i), pop st */ 824 {"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 825 {"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} }, 826 #define FWAIT_OPCODE 0x9b 827 {"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} }, 828 829 /* Opcode prefixes; we allow them as separate insns too. */ 830 831 #define ADDR_PREFIX_OPCODE 0x67 832 {"addr16", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 833 {"addr32", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 834 {"aword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 835 {"adword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 836 #define DATA_PREFIX_OPCODE 0x66 837 {"data16", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 838 {"data32", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 839 {"word", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 840 {"dword", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 841 #define LOCK_PREFIX_OPCODE 0xf0 842 {"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 843 {"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 844 #define CS_PREFIX_OPCODE 0x2e 845 {"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 846 #define DS_PREFIX_OPCODE 0x3e 847 {"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 848 #define ES_PREFIX_OPCODE 0x26 849 {"es", 0, 0x26, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 850 #define FS_PREFIX_OPCODE 0x64 851 {"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, 852 #define GS_PREFIX_OPCODE 0x65 853 {"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, 854 #define SS_PREFIX_OPCODE 0x36 855 {"ss", 0, 0x36, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 856 #define REPNE_PREFIX_OPCODE 0xf2 857 #define REPE_PREFIX_OPCODE 0xf3 858 {"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 859 {"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 860 {"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 861 {"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 862 {"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, 863 {"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 864 {"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 865 {"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 866 {"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 867 {"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 868 {"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 869 {"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 870 {"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 871 {"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 872 {"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 873 {"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 874 {"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 875 {"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 876 {"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 877 {"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 878 {"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, 879 880 /* 486 extensions. */ 881 882 {"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } }, 883 {"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, 884 {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, 885 {"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} }, 886 {"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} }, 887 {"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} }, 888 889 /* 586 and late 486 extensions. */ 890 {"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} }, 891 892 /* Pentium extensions. */ 893 {"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} }, 894 {"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} }, 895 {"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} }, 896 {"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} }, 897 898 /* Pentium II/Pentium Pro extensions. */ 899 {"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} }, 900 {"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} }, 901 {"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, 902 {"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, 903 {"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, 904 /* official undefined instr. */ 905 {"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, 906 /* alias for ud2 */ 907 {"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, 908 /* 2nd. official undefined instr. */ 909 {"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} }, 910 911 /* VIA C3 extensions */ 912 {"xstore-rng",0, 0x0fa7, 0xc0, Cpu686, ImmExt|NoSuf|IsString, { 0, 0, 0} }, 913 {"xcrypt-ecb",0, 0x0fa7, 0xc8, Cpu686, ImmExt|NoSuf|IsString, { 0, 0, 0} }, 914 {"xcrypt-cbc",0, 0x0fa7, 0xd0, Cpu686, ImmExt|NoSuf|IsString, { 0, 0, 0} }, 915 {"xcrypt-ctr",0, 0x0fa7, 0xd8, Cpu686, ImmExt|NoSuf|IsString, { 0, 0, 0} }, 916 {"xcrypt-cfb",0, 0x0fa7, 0xe0, Cpu686, ImmExt|NoSuf|IsString, { 0, 0, 0} }, 917 {"xcrypt-ofb",0, 0x0fa7, 0xe8, Cpu686, ImmExt|NoSuf|IsString, { 0, 0, 0} }, 918 919 {"montmul",0, 0x0fa6, 0xc0, Cpu686, ImmExt|NoSuf|IsString, { 0, 0, 0} }, 920 {"xsha1",0, 0x0fa6, 0xc8, Cpu686, ImmExt|NoSuf|IsString, { 0, 0, 0} }, 921 {"xsha256",0, 0x0fa6, 0xd0, Cpu686, ImmExt|NoSuf|IsString, { 0, 0, 0} }, 922 923 924 {"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 925 {"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 926 {"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 927 {"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 928 {"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 929 {"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 930 {"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 931 {"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 932 {"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 933 {"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 934 {"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 935 {"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 936 {"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 937 {"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 938 {"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 939 {"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 940 {"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 941 {"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 942 {"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 943 {"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 944 {"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 945 {"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 946 {"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 947 {"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 948 {"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 949 {"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 950 {"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 951 {"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 952 953 {"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 954 {"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 955 {"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 956 {"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 957 {"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 958 {"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 959 {"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 960 {"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 961 {"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 962 {"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 963 {"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 964 {"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 965 966 {"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 967 {"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, 968 {"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 969 {"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 970 {"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, 971 {"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 972 {"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 973 {"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 974 {"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, 975 {"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 976 {"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 977 {"fucomip", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, 978 {"fucomip", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 979 {"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 980 {"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, 981 {"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, 982 983 /* Pentium4 extensions. */ 984 985 {"movnti", 2, 0x0fc3, X, CpuP4, FP|Modrm, { WordReg, WordMem, 0 } }, 986 {"clflush", 1, 0x0fae, 7, CpuP4, FP|Modrm, { ByteMem, 0, 0 } }, 987 {"lfence", 0, 0x0fae, 0xe8, CpuP4, FP|ImmExt, { 0, 0, 0 } }, 988 {"mfence", 0, 0x0fae, 0xf0, CpuP4, FP|ImmExt, { 0, 0, 0 } }, 989 {"pause", 0, 0xf390, X, CpuP4, FP, { 0, 0, 0 } }, 990 991 /* MMX/SSE2 instructions. */ 992 993 {"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } }, 994 /* These really shouldn't allow for Reg64 (movq is the right mnemonic for 995 copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's 996 spec). AMD's spec, having been in existence for much longer, failed to 997 recognize that and specified movd for 32- and 64-bit operations. */ 998 {"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } }, 999 {"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } }, 1000 {"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg32|Reg64|LLongMem, RegXMM, 0 } }, 1001 {"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg32|Reg64|LLongMem, 0 } }, 1002 /* In the 64bit mode the short form mov immediate is redefined to have 1003 64bit displacement value. */ 1004 {"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm|NoRex64, { RegMMX|LongMem, RegMMX, 0 } }, 1005 {"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm|NoRex64, { RegMMX, RegMMX|LongMem, 0 } }, 1006 {"movq", 2, 0xf30f7e,X,CpuSSE2,FP|Modrm|NoRex64, { RegXMM|LLongMem, RegXMM, 0 } }, 1007 {"movq", 2, 0x660fd6,X,CpuSSE2,FP|Modrm|NoRex64, { RegXMM, RegXMM|LLongMem, 0 } }, 1008 {"movq", 2, 0x0f6e, X, Cpu64, FP|Modrm, { Reg64|LLongMem, RegMMX, 0 } }, 1009 {"movq", 2, 0x0f7e, X, Cpu64, FP|Modrm, { RegMMX, Reg64|LLongMem, 0 } }, 1010 {"movq", 2, 0x660f6e,X,Cpu64, FP|Modrm, { Reg64|LLongMem, RegXMM, 0 } }, 1011 {"movq", 2, 0x660f7e,X,Cpu64, FP|Modrm, { RegXMM, Reg64|LLongMem, 0 } }, 1012 {"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } }, 1013 {"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } }, 1014 {"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, 1015 /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit 1016 mode they are 64bit.*/ 1017 {"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} }, 1018 {"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} }, 1019 {"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1020 {"packssdw", 2, 0x660f6b,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1021 {"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1022 {"packsswb", 2, 0x660f63,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1023 {"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1024 {"packuswb", 2, 0x660f67,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1025 {"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1026 {"paddb", 2, 0x660ffc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1027 {"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1028 {"paddw", 2, 0x660ffd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1029 {"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1030 {"paddd", 2, 0x660ffe,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1031 {"paddq", 2, 0x0fd4, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1032 {"paddq", 2, 0x660fd4,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1033 {"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1034 {"paddsb", 2, 0x660fec,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1035 {"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1036 {"paddsw", 2, 0x660fed,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1037 {"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1038 {"paddusb", 2, 0x660fdc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1039 {"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1040 {"paddusw", 2, 0x660fdd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1041 {"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1042 {"pand", 2, 0x660fdb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1043 {"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1044 {"pandn", 2, 0x660fdf,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1045 {"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1046 {"pcmpeqb", 2, 0x660f74,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1047 {"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1048 {"pcmpeqw", 2, 0x660f75,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1049 {"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1050 {"pcmpeqd", 2, 0x660f76,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1051 {"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1052 {"pcmpgtb", 2, 0x660f64,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1053 {"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1054 {"pcmpgtw", 2, 0x660f65,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1055 {"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1056 {"pcmpgtd", 2, 0x660f66,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1057 {"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1058 {"pmaddwd", 2, 0x660ff5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1059 {"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1060 {"pmulhw", 2, 0x660fe5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1061 {"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1062 {"pmullw", 2, 0x660fd5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1063 {"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1064 {"por", 2, 0x660feb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1065 {"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1066 {"psllw", 2, 0x660ff1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1067 {"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, 1068 {"psllw", 2, 0x660f71,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, 1069 {"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1070 {"pslld", 2, 0x660ff2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1071 {"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, 1072 {"pslld", 2, 0x660f72,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, 1073 {"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1074 {"psllq", 2, 0x660ff3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1075 {"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, 1076 {"psllq", 2, 0x660f73,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, 1077 {"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1078 {"psraw", 2, 0x660fe1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1079 {"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, 1080 {"psraw", 2, 0x660f71,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, 1081 {"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1082 {"psrad", 2, 0x660fe2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1083 {"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, 1084 {"psrad", 2, 0x660f72,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, 1085 {"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1086 {"psrlw", 2, 0x660fd1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1087 {"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, 1088 {"psrlw", 2, 0x660f71,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, 1089 {"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1090 {"psrld", 2, 0x660fd2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1091 {"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, 1092 {"psrld", 2, 0x660f72,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, 1093 {"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1094 {"psrlq", 2, 0x660fd3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1095 {"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, 1096 {"psrlq", 2, 0x660f73,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, 1097 {"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1098 {"psubb", 2, 0x660ff8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1099 {"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1100 {"psubw", 2, 0x660ff9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1101 {"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1102 {"psubd", 2, 0x660ffa,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1103 {"psubq", 2, 0x0ffb, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1104 {"psubq", 2, 0x660ffb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1105 {"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1106 {"psubsb", 2, 0x660fe8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1107 {"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1108 {"psubsw", 2, 0x660fe9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1109 {"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1110 {"psubusb", 2, 0x660fd8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1111 {"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1112 {"psubusw", 2, 0x660fd9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1113 {"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1114 {"punpckhbw",2, 0x660f68,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1115 {"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1116 {"punpckhwd",2, 0x660f69,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1117 {"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1118 {"punpckhdq",2, 0x660f6a,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1119 {"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1120 {"punpcklbw",2, 0x660f60,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1121 {"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1122 {"punpcklwd",2, 0x660f61,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1123 {"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1124 {"punpckldq",2, 0x660f62,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1125 {"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1126 {"pxor", 2, 0x660fef,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1127 1128 /* PIII Katmai New Instructions / SIMD instructions. */ 1129 1130 {"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1131 {"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1132 {"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1133 {"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1134 {"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 1135 {"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 1136 {"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 1137 {"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 1138 {"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 1139 {"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 1140 {"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 1141 {"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 1142 {"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 1143 {"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 1144 {"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 1145 {"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 1146 {"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 1147 {"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 1148 {"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 1149 {"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 1150 {"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 1151 {"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, 1152 {"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1153 {"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, 1154 {"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, 1155 {"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, 1156 {"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, 1157 {"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, 1158 {"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } }, 1159 {"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1160 {"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1161 {"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, 1162 {"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, 1163 {"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1164 {"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1165 {"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1166 {"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1167 {"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1168 {"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 1169 {"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, 1170 {"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, 1171 {"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, 1172 {"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, 1173 {"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, 1174 {"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, 1175 {"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, 1176 {"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, 1177 {"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } }, 1178 {"movntdq", 2, 0x660fe7, X, CpuSSE2,FP|Modrm, { RegXMM, LLongMem, 0 } }, 1179 {"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1180 {"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, 1181 {"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1182 {"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 1183 {"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1184 {"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1185 {"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1186 {"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1187 {"pavgb", 2, 0x660fe0, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1188 {"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1189 {"pavgw", 2, 0x660fe3, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1190 {"pextrw", 3, 0x0fc5, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } }, 1191 {"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } }, 1192 {"pinsrw", 3, 0x0fc4, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } }, 1193 {"pinsrw", 3, 0x660fc4, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } }, 1194 {"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1195 {"pmaxsw", 2, 0x660fee, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1196 {"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1197 {"pmaxub", 2, 0x660fde, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1198 {"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1199 {"pminsw", 2, 0x660fea, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1200 {"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1201 {"pminub", 2, 0x660fda, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1202 {"pmovmskb", 2, 0x0fd7, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } }, 1203 {"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, 1204 {"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1205 {"pmulhuw", 2, 0x660fe4, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1206 {"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, 1207 {"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, 1208 {"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, 1209 {"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, 1210 {"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1211 {"psadbw", 2, 0x660ff6, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1212 {"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, 1213 {"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1214 {"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1215 {"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1216 {"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1217 {"sfence", 0, 0x0fae, 0xf8, CpuSSE, FP|ImmExt, { 0, 0, 0 } }, 1218 {"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 1219 {"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1220 {"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1221 {"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, 1222 {"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1223 {"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1224 {"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1225 {"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1226 {"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1227 {"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1228 1229 /* SSE-2 instructions. */ 1230 1231 {"addpd", 2, 0x660f58, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1232 {"addsd", 2, 0xf20f58, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1233 {"andnpd", 2, 0x660f55, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1234 {"andpd", 2, 0x660f54, X, CpuSSE2, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1235 {"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 1236 {"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 1237 {"cmplepd", 2, 0x660fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 1238 {"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 1239 {"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 1240 {"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 1241 {"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 1242 {"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 1243 {"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 1244 {"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 1245 {"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 1246 {"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 1247 {"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 1248 {"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 1249 {"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, 1250 {"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, 1251 {"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 1252 /* Intel mode string compare. */ 1253 {"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, 1254 {"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, 1255 {"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, 1256 {"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1257 {"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, 1258 {"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, 1259 {"divpd", 2, 0x660f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1260 {"divsd", 2, 0xf20f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1261 {"maxpd", 2, 0x660f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1262 {"maxsd", 2, 0xf20f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1263 {"minpd", 2, 0x660f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1264 {"minsd", 2, 0xf20f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1265 {"movapd", 2, 0x660f28, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1266 {"movapd", 2, 0x660f29, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 1267 {"movhpd", 2, 0x660f16, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, 1268 {"movhpd", 2, 0x660f17, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, 1269 {"movlpd", 2, 0x660f12, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, 1270 {"movlpd", 2, 0x660f13, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, 1271 {"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, 1272 {"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, 1273 /* Intel mode string move. */ 1274 {"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, 1275 {"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, 1276 {"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1277 {"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, 1278 {"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1279 {"movupd", 2, 0x660f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 1280 {"mulpd", 2, 0x660f59, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1281 {"mulsd", 2, 0xf20f59, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1282 {"orpd", 2, 0x660f56, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1283 {"shufpd", 3, 0x660fc6, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 1284 {"sqrtpd", 2, 0x660f51, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1285 {"sqrtsd", 2, 0xf20f51, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1286 {"subpd", 2, 0x660f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1287 {"subsd", 2, 0xf20f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1288 {"ucomisd", 2, 0x660f2e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1289 {"unpckhpd", 2, 0x660f15, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1290 {"unpcklpd", 2, 0x660f14, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1291 {"xorpd", 2, 0x660f57, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1292 {"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1293 {"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1294 {"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1295 {"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, 1296 {"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1297 {"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1298 {"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1299 {"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } }, 1300 {"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1301 {"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1302 {"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, 1303 {"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, 1304 {"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1305 {"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1306 {"maskmovdqu",2, 0x660ff7, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, 1307 {"movdqa", 2, 0x660f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1308 {"movdqa", 2, 0x660f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 1309 {"movdqu", 2, 0xf30f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1310 {"movdqu", 2, 0xf30f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 1311 {"movdq2q", 2, 0xf20fd6, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegMMX, 0 } }, 1312 {"movq2dq", 2, 0xf30fd6, X, CpuSSE2, FP|Modrm, { RegMMX|InvMem, RegXMM, 0 } }, 1313 {"pmuludq", 2, 0x0ff4, X, CpuSSE2, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 1314 {"pmuludq", 2, 0x660ff4, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, 1315 {"pshufd", 3, 0x660f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 1316 {"pshufhw", 3, 0xf30f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 1317 {"pshuflw", 3, 0xf20f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 1318 {"pslldq", 2, 0x660f73, 7, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } }, 1319 {"psrldq", 2, 0x660f73, 3, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } }, 1320 {"punpckhqdq",2, 0x660f6d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1321 {"punpcklqdq",2, 0x660f6c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1322 1323 /* Prescott New Instructions. */ 1324 1325 {"addsubpd", 2, 0x660fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1326 {"addsubps", 2, 0xf20fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1327 {"cmpxchg16b",1, 0x0fc7, 1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} }, 1328 {"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 1329 /* Intel Syntax */ 1330 {"fisttpd", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, 1331 {"fisttpq", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, 1332 {"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, 1333 {"haddpd", 2, 0x660f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1334 {"haddps", 2, 0xf20f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1335 {"hsubpd", 2, 0x660f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1336 {"hsubps", 2, 0xf20f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1337 {"lddqu", 2, 0xf20ff0, X, CpuPNI, FP|Modrm, { LLongMem, RegXMM, 0 } }, 1338 {"monitor", 0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { 0, 0, 0} }, 1339 /* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */ 1340 {"monitor", 3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { Reg32, Reg32, Reg32} }, 1341 {"movddup", 2, 0xf20f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1342 {"movshdup", 2, 0xf30f16, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1343 {"movsldup", 2, 0xf30f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1344 {"mwait", 0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { 0, 0, 0} }, 1345 /* Need to ensure only "mwait %eax,%ecx" is accepted. */ 1346 {"mwait", 2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { Reg32, Reg32, 0} }, 1347 1348 /* AMD 3DNow! instructions. */ 1349 1350 {"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, 1351 {"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, 1352 {"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } }, 1353 {"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1354 {"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1355 {"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1356 {"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1357 {"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1358 {"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1359 {"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1360 {"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1361 {"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1362 {"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1363 {"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1364 {"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1365 {"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1366 {"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1367 {"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1368 {"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1369 {"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1370 {"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1371 {"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1372 {"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1373 {"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1374 {"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1375 {"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1376 {"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1377 1378 /* AMD extensions. */ 1379 {"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} }, 1380 {"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} }, 1381 {"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} }, 1382 {"rdtscp", 0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt, { 0, 0, 0} }, 1383 1384 /* VIA PadLock extensions. */ 1385 {"xstorerng", 0, 0x0fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, 1386 {"xcryptecb", 0, 0xf30fa7c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, 1387 {"xcryptcbc", 0, 0xf30fa7d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, 1388 {"xcryptcfb", 0, 0xf30fa7e0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, 1389 {"xcryptofb", 0, 0xf30fa7e8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, 1390 /* alias for xstorerng */ 1391 {"xstore", 0, 0x0fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, 1392 1393 /* Supplemental Streaming SIMD Extensions 3 extensions. */ 1394 {"pshufb", 2, 0x660f3800, X, CpuSSSE3, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1395 1396 /* Intel AES extensions */ 1397 {"aesdec", 2, 0x660f38de, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1398 {"aesdeclast", 2, 0x660f38df, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1399 {"aesenc", 2, 0x660f38dc, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1400 {"aesenclast", 2, 0x660f38dd, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1401 {"aesimc", 2, 0x660f38db, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { RegXMM|LLongMem, RegXMM } }, 1402 {"aeskeygenassist", 3, 0x660f3adf, X, CpuAES, FP|Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM|LLongMem, RegXMM } }, 1403 1404 /* Intel Carry-less Multiplication extensions */ 1405 {"pclmulqdq", 3, 0x660f3a44, X, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM|LLongMem, RegXMM } }, 1406 {"pclmullqlqdq", 2, 0x660f3a44, 0x0, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem, RegXMM } }, 1407 {"pclmulhqlqdq", 2, 0x660f3a44, 0x1, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem, RegXMM } }, 1408 {"pclmullqhqdq", 2, 0x660f3a44, 0x10, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem, RegXMM } }, 1409 {"pclmulhqhqdq", 2, 0x660f3a44, 0x11, CpuPCLMUL, FP|Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem, RegXMM } }, 1410 1411 /* Intel Random Number Generator extensions */ 1412 {"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } }, 1413 1414 /* Intel Supervisor Mode Access Prevention extensions */ 1415 {"clac", 0, 0x0f01, 0xca, CpuSMAP, NoSuf|ImmExt, { 0, 0, 0 } }, 1416 {"stac", 0, 0x0f01, 0xcb, CpuSMAP, NoSuf|ImmExt, { 0, 0, 0 } }, 1417 1418 /* Intel XSAVE extensions */ 1419 {"xgetbv", 0, 0x0f01, 0xd0, CpuXSAVE, NoSuf|ImmExt, { 0, 0, 0 } }, 1420 {"xsetbv", 0, 0x0f01, 0xd1, CpuXSAVE, NoSuf|ImmExt, { 0, 0, 0 } }, 1421 {"xsave", 1, 0x0fae, 4, CpuXSAVE, NoSuf|Modrm, { LLongMem, 0, 0 } }, 1422 {"xrstor", 1, 0x0fae, 5, CpuXSAVE, NoSuf|Modrm, { LLongMem, 0, 0 } }, 1423 {"xsaveopt", 1, 0x0fae, 6, CpuXSAVE, NoSuf|Modrm, { LLongMem, 0, 0 } }, 1424 1425 /* Intel VMX extensions */ 1426 {"invept", 2, 0x660f3880, X, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, 1427 {"invept", 2, 0x660f3880, X, CpuVMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, 1428 {"invvpid", 2, 0x660f3881, X, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, 1429 {"invvpid", 2, 0x660f3881, X, CpuVMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, 1430 {"vmcall", 0, 0xf01, 0xc1, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1431 {"vmclear", 1, 0x660fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, 1432 {"vmlaunch", 0, 0xf01, 0xc2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1433 {"vmresume", 0, 0xf01, 0xc3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1434 {"vmptrld", 1, 0xfc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, 1435 {"vmptrst", 1, 0xfc7, 0x7, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, 1436 {"vmread", 2, 0xf78, None, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, 1437 {"vmread", 2, 0xf78, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg64, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, 1438 {"vmwrite", 2, 0xf79, None, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, 1439 {"vmwrite", 2, 0xf79, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, 1440 {"vmxoff", 0, 0xf01, 0xc4, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1441 {"vmxon", 1, 0xf30fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, 1442 1443 /* AMD SVM extensions */ 1444 {"clgi", 0, 0xf01, 0xdd, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1445 {"invlpga", 0, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1446 {"invlpga", 2, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, 1447 {"stgi", 0, 0xf01, 0xdc, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1448 {"vmload", 0, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1449 {"vmload", 1, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, 1450 {"vmmcall", 0, 0xf01, 0xd9, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1451 {"vmrun", 0, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1452 {"vmrun", 1, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, 1453 {"vmsave", 0, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0, 0, 0 } }, 1454 {"vmsave", 1, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, 1455 1456 /* sentinel */ 1457 {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } 1458 }; 1459 #undef X 1460 #undef NoSuf 1461 #undef b_Suf 1462 #undef w_Suf 1463 #undef l_Suf 1464 #undef q_Suf 1465 #undef x_Suf 1466 #undef bw_Suf 1467 #undef bl_Suf 1468 #undef wl_Suf 1469 #undef wlq_Suf 1470 #undef sl_Suf 1471 #undef bwl_Suf 1472 #undef bwlq_Suf 1473 #undef FP 1474 #undef l_FP 1475 #undef x_FP 1476 #undef sl_FP 1477 1478 #define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */ 1479 1480 1481 /* 386 register table. */ 1482 1483 static const reg_entry i386_regtab[] = { 1484 /* make %st first as we test for it */ 1485 {"st", FloatReg|FloatAcc, 0, 0}, 1486 /* 8 bit regs */ 1487 #define REGNAM_AL 1 /* Entry in i386_regtab. */ 1488 {"al", Reg8|Acc, 0, 0}, 1489 {"cl", Reg8|ShiftCount, 0, 1}, 1490 {"dl", Reg8, 0, 2}, 1491 {"bl", Reg8, 0, 3}, 1492 {"ah", Reg8, 0, 4}, 1493 {"ch", Reg8, 0, 5}, 1494 {"dh", Reg8, 0, 6}, 1495 {"bh", Reg8, 0, 7}, 1496 {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */ 1497 {"cxl", Reg8, RegRex64, 1}, 1498 {"dxl", Reg8, RegRex64, 2}, 1499 {"bxl", Reg8, RegRex64, 3}, 1500 {"spl", Reg8, RegRex64, 4}, 1501 {"bpl", Reg8, RegRex64, 5}, 1502 {"sil", Reg8, RegRex64, 6}, 1503 {"dil", Reg8, RegRex64, 7}, 1504 {"r8b", Reg8, RegRex64|RegRex, 0}, 1505 {"r9b", Reg8, RegRex64|RegRex, 1}, 1506 {"r10b", Reg8, RegRex64|RegRex, 2}, 1507 {"r11b", Reg8, RegRex64|RegRex, 3}, 1508 {"r12b", Reg8, RegRex64|RegRex, 4}, 1509 {"r13b", Reg8, RegRex64|RegRex, 5}, 1510 {"r14b", Reg8, RegRex64|RegRex, 6}, 1511 {"r15b", Reg8, RegRex64|RegRex, 7}, 1512 /* 16 bit regs */ 1513 #define REGNAM_AX 25 1514 {"ax", Reg16|Acc, 0, 0}, 1515 {"cx", Reg16, 0, 1}, 1516 {"dx", Reg16|InOutPortReg, 0, 2}, 1517 {"bx", Reg16|BaseIndex, 0, 3}, 1518 {"sp", Reg16, 0, 4}, 1519 {"bp", Reg16|BaseIndex, 0, 5}, 1520 {"si", Reg16|BaseIndex, 0, 6}, 1521 {"di", Reg16|BaseIndex, 0, 7}, 1522 {"r8w", Reg16, RegRex, 0}, 1523 {"r9w", Reg16, RegRex, 1}, 1524 {"r10w", Reg16, RegRex, 2}, 1525 {"r11w", Reg16, RegRex, 3}, 1526 {"r12w", Reg16, RegRex, 4}, 1527 {"r13w", Reg16, RegRex, 5}, 1528 {"r14w", Reg16, RegRex, 6}, 1529 {"r15w", Reg16, RegRex, 7}, 1530 /* 32 bit regs */ 1531 #define REGNAM_EAX 41 1532 {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot */ 1533 {"ecx", Reg32|BaseIndex, 0, 1}, 1534 {"edx", Reg32|BaseIndex, 0, 2}, 1535 {"ebx", Reg32|BaseIndex, 0, 3}, 1536 {"esp", Reg32, 0, 4}, 1537 {"ebp", Reg32|BaseIndex, 0, 5}, 1538 {"esi", Reg32|BaseIndex, 0, 6}, 1539 {"edi", Reg32|BaseIndex, 0, 7}, 1540 {"r8d", Reg32|BaseIndex, RegRex, 0}, 1541 {"r9d", Reg32|BaseIndex, RegRex, 1}, 1542 {"r10d", Reg32|BaseIndex, RegRex, 2}, 1543 {"r11d", Reg32|BaseIndex, RegRex, 3}, 1544 {"r12d", Reg32|BaseIndex, RegRex, 4}, 1545 {"r13d", Reg32|BaseIndex, RegRex, 5}, 1546 {"r14d", Reg32|BaseIndex, RegRex, 6}, 1547 {"r15d", Reg32|BaseIndex, RegRex, 7}, 1548 {"rax", Reg64|BaseIndex|Acc, 0, 0}, 1549 {"rcx", Reg64|BaseIndex, 0, 1}, 1550 {"rdx", Reg64|BaseIndex, 0, 2}, 1551 {"rbx", Reg64|BaseIndex, 0, 3}, 1552 {"rsp", Reg64, 0, 4}, 1553 {"rbp", Reg64|BaseIndex, 0, 5}, 1554 {"rsi", Reg64|BaseIndex, 0, 6}, 1555 {"rdi", Reg64|BaseIndex, 0, 7}, 1556 {"r8", Reg64|BaseIndex, RegRex, 0}, 1557 {"r9", Reg64|BaseIndex, RegRex, 1}, 1558 {"r10", Reg64|BaseIndex, RegRex, 2}, 1559 {"r11", Reg64|BaseIndex, RegRex, 3}, 1560 {"r12", Reg64|BaseIndex, RegRex, 4}, 1561 {"r13", Reg64|BaseIndex, RegRex, 5}, 1562 {"r14", Reg64|BaseIndex, RegRex, 6}, 1563 {"r15", Reg64|BaseIndex, RegRex, 7}, 1564 /* segment registers */ 1565 {"es", SReg2, 0, 0}, 1566 {"cs", SReg2, 0, 1}, 1567 {"ss", SReg2, 0, 2}, 1568 {"ds", SReg2, 0, 3}, 1569 {"fs", SReg3, 0, 4}, 1570 {"gs", SReg3, 0, 5}, 1571 /* control registers */ 1572 {"cr0", Control, 0, 0}, 1573 {"cr1", Control, 0, 1}, 1574 {"cr2", Control, 0, 2}, 1575 {"cr3", Control, 0, 3}, 1576 {"cr4", Control, 0, 4}, 1577 {"cr5", Control, 0, 5}, 1578 {"cr6", Control, 0, 6}, 1579 {"cr7", Control, 0, 7}, 1580 {"cr8", Control, RegRex, 0}, 1581 {"cr9", Control, RegRex, 1}, 1582 {"cr10", Control, RegRex, 2}, 1583 {"cr11", Control, RegRex, 3}, 1584 {"cr12", Control, RegRex, 4}, 1585 {"cr13", Control, RegRex, 5}, 1586 {"cr14", Control, RegRex, 6}, 1587 {"cr15", Control, RegRex, 7}, 1588 /* debug registers */ 1589 {"db0", Debug, 0, 0}, 1590 {"db1", Debug, 0, 1}, 1591 {"db2", Debug, 0, 2}, 1592 {"db3", Debug, 0, 3}, 1593 {"db4", Debug, 0, 4}, 1594 {"db5", Debug, 0, 5}, 1595 {"db6", Debug, 0, 6}, 1596 {"db7", Debug, 0, 7}, 1597 {"db8", Debug, RegRex, 0}, 1598 {"db9", Debug, RegRex, 1}, 1599 {"db10", Debug, RegRex, 2}, 1600 {"db11", Debug, RegRex, 3}, 1601 {"db12", Debug, RegRex, 4}, 1602 {"db13", Debug, RegRex, 5}, 1603 {"db14", Debug, RegRex, 6}, 1604 {"db15", Debug, RegRex, 7}, 1605 {"dr0", Debug, 0, 0}, 1606 {"dr1", Debug, 0, 1}, 1607 {"dr2", Debug, 0, 2}, 1608 {"dr3", Debug, 0, 3}, 1609 {"dr4", Debug, 0, 4}, 1610 {"dr5", Debug, 0, 5}, 1611 {"dr6", Debug, 0, 6}, 1612 {"dr7", Debug, 0, 7}, 1613 {"dr8", Debug, RegRex, 0}, 1614 {"dr9", Debug, RegRex, 1}, 1615 {"dr10", Debug, RegRex, 2}, 1616 {"dr11", Debug, RegRex, 3}, 1617 {"dr12", Debug, RegRex, 4}, 1618 {"dr13", Debug, RegRex, 5}, 1619 {"dr14", Debug, RegRex, 6}, 1620 {"dr15", Debug, RegRex, 7}, 1621 /* test registers */ 1622 {"tr0", Test, 0, 0}, 1623 {"tr1", Test, 0, 1}, 1624 {"tr2", Test, 0, 2}, 1625 {"tr3", Test, 0, 3}, 1626 {"tr4", Test, 0, 4}, 1627 {"tr5", Test, 0, 5}, 1628 {"tr6", Test, 0, 6}, 1629 {"tr7", Test, 0, 7}, 1630 /* mmx and simd registers */ 1631 {"mm0", RegMMX, 0, 0}, 1632 {"mm1", RegMMX, 0, 1}, 1633 {"mm2", RegMMX, 0, 2}, 1634 {"mm3", RegMMX, 0, 3}, 1635 {"mm4", RegMMX, 0, 4}, 1636 {"mm5", RegMMX, 0, 5}, 1637 {"mm6", RegMMX, 0, 6}, 1638 {"mm7", RegMMX, 0, 7}, 1639 {"xmm0", RegXMM, 0, 0}, 1640 {"xmm1", RegXMM, 0, 1}, 1641 {"xmm2", RegXMM, 0, 2}, 1642 {"xmm3", RegXMM, 0, 3}, 1643 {"xmm4", RegXMM, 0, 4}, 1644 {"xmm5", RegXMM, 0, 5}, 1645 {"xmm6", RegXMM, 0, 6}, 1646 {"xmm7", RegXMM, 0, 7}, 1647 {"xmm8", RegXMM, RegRex, 0}, 1648 {"xmm9", RegXMM, RegRex, 1}, 1649 {"xmm10", RegXMM, RegRex, 2}, 1650 {"xmm11", RegXMM, RegRex, 3}, 1651 {"xmm12", RegXMM, RegRex, 4}, 1652 {"xmm13", RegXMM, RegRex, 5}, 1653 {"xmm14", RegXMM, RegRex, 6}, 1654 {"xmm15", RegXMM, RegRex, 7}, 1655 /* no type will make this register rejected for all purposes except 1656 for addressing. This saves creating one extra type for RIP. */ 1657 {"rip", BaseIndex, 0, 0} 1658 }; 1659 1660 static const reg_entry i386_float_regtab[] = { 1661 {"st(0)", FloatReg|FloatAcc, 0, 0}, 1662 {"st(1)", FloatReg, 0, 1}, 1663 {"st(2)", FloatReg, 0, 2}, 1664 {"st(3)", FloatReg, 0, 3}, 1665 {"st(4)", FloatReg, 0, 4}, 1666 {"st(5)", FloatReg, 0, 5}, 1667 {"st(6)", FloatReg, 0, 6}, 1668 {"st(7)", FloatReg, 0, 7} 1669 }; 1670 1671 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ 1672 1673 /* segment stuff */ 1674 static const seg_entry cs = { "cs", 0x2e }; 1675 static const seg_entry ds = { "ds", 0x3e }; 1676 static const seg_entry ss = { "ss", 0x36 }; 1677 static const seg_entry es = { "es", 0x26 }; 1678 static const seg_entry fs = { "fs", 0x64 }; 1679 static const seg_entry gs = { "gs", 0x65 }; 1680 1681 /* end of opcode/i386.h */ 1682