1 /* Opcode table for the ARM. 2 3 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003 4 Free Software Foundation, Inc. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 19 20 21 struct arm_opcode { 22 unsigned long value, mask; /* recognise instruction if (op&mask)==value */ 23 char *assembler; /* how to disassemble this instruction */ 24 }; 25 26 struct thumb_opcode 27 { 28 unsigned short value, mask; /* recognise instruction if (op&mask)==value */ 29 char * assembler; /* how to disassemble this instruction */ 30 }; 31 32 /* format of the assembler string : 33 34 %% % 35 %<bitfield>d print the bitfield in decimal 36 %<bitfield>x print the bitfield in hex 37 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 38 %<bitfield>w print the bitfield plus one in decimal 39 %<bitfield>r print as an ARM register 40 %<bitfield>f print a floating point constant if >7 else a 41 floating point register 42 %<code>y print a single precision VFP reg. 43 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 44 %<code>z print a double precision VFP reg 45 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 46 %c print condition code (always bits 28-31) 47 %P print floating point precision in arithmetic insn 48 %Q print floating point precision in ldf/stf insn 49 %R print floating point rounding mode 50 %<bitnum>'c print specified char iff bit is one 51 %<bitnum>`c print specified char iff bit is zero 52 %<bitnum>?ab print a if bit is one else print b 53 %p print 'p' iff bits 12-15 are 15 54 %t print 't' iff bit 21 set and bit 24 clear 55 %o print operand2 (immediate or register + shift) 56 %a print address for ldr/str instruction 57 %s print address for ldr/str halfword/signextend instruction 58 %b print branch destination 59 %B print arm BLX(1) destination 60 %A print address for ldc/stc/ldf/stf instruction 61 %m print register mask for ldm/stm instruction 62 %C print the PSR sub type. 63 %F print the COUNT field of a LFM/SFM instruction. 64 IWMMXT specific format options: 65 %<bitfield>g print as an iWMMXt 64-bit register 66 %<bitfield>G print as an iWMMXt general purpose or control register 67 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 68 %Z print the Immediate of a WSHUFH instruction. 69 %L print as an iWMMXt N/M width field. 70 %l like 'A' except use byte offsets for 'B' & 'H' versions 71 Thumb specific format options: 72 %D print Thumb register (bits 0..2 as high number if bit 7 set) 73 %S print Thumb register (bits 3..5 as high number if bit 6 set) 74 %<bitfield>I print bitfield as a signed decimal 75 (top bit of range being the sign bit) 76 %M print Thumb register mask 77 %N print Thumb register mask (with LR) 78 %O print Thumb register mask (with PC) 79 %T print Thumb condition code (always bits 8-11) 80 %I print cirrus signed shift immediate: bits 0..3|4..6 81 %<bitfield>B print Thumb branch destination (signed displacement) 82 %<bitfield>W print (bitfield * 4) as a decimal 83 %<bitfield>H print (bitfield * 2) as a decimal 84 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 85 */ 86 87 /* Note: There is a partial ordering in this table - it must be searched from 88 the top to obtain a correct match. */ 89 90 static const struct arm_opcode arm_opcodes[] = 91 { 92 /* ARM instructions. */ 93 {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, 94 {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 95 {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, 96 {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, 97 {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, 98 {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, 99 {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, 100 101 /* ARM V6 instructions. */ 102 {0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 103 {0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 104 {0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"}, 105 {0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, 106 {0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"}, 107 {0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, 108 {0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, 109 {0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"}, 110 {0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"}, 111 {0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"}, 112 {0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"}, 113 {0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"}, 114 {0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"}, 115 {0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"}, 116 {0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 117 {0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"}, 118 {0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"}, 119 {0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 120 {0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"}, 121 {0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"}, 122 {0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"}, 123 {0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"}, 124 {0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"}, 125 {0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 126 {0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"}, 127 {0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"}, 128 {0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 129 {0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"}, 130 {0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"}, 131 {0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"}, 132 {0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"}, 133 {0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"}, 134 {0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 135 {0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"}, 136 {0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"}, 137 {0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 138 {0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"}, 139 {0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"}, 140 {0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 141 {0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"}, 142 {0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"}, 143 {0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 144 {0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"}, 145 {0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"}, 146 {0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 147 {0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"}, 148 {0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"}, 149 {0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"}, 150 {0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"}, 151 {0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"}, 152 {0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"}, 153 {0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"}, 154 {0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"}, 155 {0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"}, 156 {0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"}, 157 {0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"}, 158 {0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"}, 159 {0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"}, 160 {0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"}, 161 {0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"}, 162 {0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"}, 163 {0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"}, 164 {0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"}, 165 {0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"}, 166 {0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"}, 167 {0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"}, 168 {0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"}, 169 {0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"}, 170 {0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"}, 171 {0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"}, 172 {0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"}, 173 {0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"}, 174 {0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"}, 175 {0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"}, 176 {0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"}, 177 {0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"}, 178 {0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"}, 179 {0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, 180 {0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, 181 {0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, 182 {0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"}, 183 {0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, 184 {0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, 185 {0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, 186 {0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"}, 187 {0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, 188 {0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, 189 {0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, 190 {0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"}, 191 {0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, 192 {0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, 193 {0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, 194 {0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"}, 195 {0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, 196 {0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, 197 {0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, 198 {0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"}, 199 {0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, 200 {0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, 201 {0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, 202 {0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, 203 {0xf1010000, 0xfffffc00, "setend\t%9?ble"}, 204 {0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, 205 {0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"}, 206 {0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 207 {0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 208 {0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 209 {0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 210 {0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"}, 211 {0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 212 {0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 213 {0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"}, 214 {0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"}, 215 {0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"}, 216 {0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"}, 217 {0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, 218 {0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"}, 219 {0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 220 {0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"}, 221 {0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 222 {0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"}, 223 {0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"}, 224 {0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"}, 225 {0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"}, 226 227 /* V5J instruction. */ 228 {0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, 229 230 /* XScale instructions. */ 231 {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, 232 {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, 233 {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, 234 {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, 235 {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, 236 {0xf450f000, 0xfc70f000, "pld\t%a"}, 237 238 /* Intel Wireless MMX technology instructions. */ 239 #define FIRST_IWMMXT_INSN 0x0e130130 240 #define IWMMXT_INSN_COUNT 47 241 {0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 242 {0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 243 {0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, 244 {0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, 245 {0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, 246 {0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 247 {0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 248 {0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 249 {0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 250 {0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 251 {0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 252 {0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 253 {0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 254 {0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 255 {0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 256 {0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 257 {0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, 258 {0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 259 {0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 260 {0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 261 {0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 262 {0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 263 {0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 264 {0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 265 {0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 266 {0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"}, 267 {0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 268 {0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 269 {0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"}, 270 {0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 271 {0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 272 {0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 273 {0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 274 {0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 275 {0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, 276 {0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 277 {0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 278 {0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 279 {0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 280 {0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 281 {0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 282 {0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 283 {0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 284 {0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 285 {0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"}, 286 {0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 287 {0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 288 {0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 289 {0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 290 291 /* V5 Instructions. */ 292 {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, 293 {0xfa000000, 0xfe000000, "blx\t%B"}, 294 {0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, 295 {0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, 296 {0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"}, 297 {0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"}, 298 {0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 299 {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 300 {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 301 302 /* V5E "El Segundo" Instructions. */ 303 {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"}, 304 {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"}, 305 {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 306 {0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 307 {0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 308 {0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 309 310 {0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 311 {0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 312 313 {0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 314 {0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 315 {0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 316 {0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 317 318 {0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, 319 {0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, 320 {0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, 321 {0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, 322 323 {0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, 324 {0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, 325 326 {0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, 327 {0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, 328 {0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, 329 {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, 330 331 /* ARM Instructions. */ 332 {0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, 333 {0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, 334 {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, 335 {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, 336 {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, 337 {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, 338 {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, 339 {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, 340 {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, 341 {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, 342 {0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, 343 {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, 344 {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, 345 {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, 346 {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, 347 {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, 348 {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, 349 {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, 350 {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, 351 {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, 352 {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"}, 353 {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"}, 354 {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"}, 355 {0x06000010, 0x0e000010, "undefined"}, 356 {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, 357 {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, 358 {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, 359 {0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 360 {0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, 361 362 /* Floating point coprocessor (FPA) instructions */ 363 {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 364 {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 365 {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 366 {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 367 {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 368 {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 369 {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 370 {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 371 {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 372 {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 373 {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 374 {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 375 {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 376 {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 377 {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 378 {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 379 {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 380 {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 381 {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 382 {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 383 {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 384 {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 385 {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 386 {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 387 {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 388 {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 389 {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 390 {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 391 {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 392 {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 393 {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 394 {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 395 {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 396 {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 397 {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 398 {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 399 {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 400 {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 401 {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 402 {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 403 {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 404 {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 405 {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 406 407 /* Floating point coprocessor (VFP) instructions */ 408 {0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"}, 409 {0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%1y, %0y"}, 410 {0x0e300b00, 0x0ff00ff0, "faddd%c\t%1z, %2z, %0z"}, 411 {0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %1y"}, 412 {0x0eb40b40, 0x0fff0f70, "fcmp%7'ed%c\t%1z, %0z"}, 413 {0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%1y, %0y"}, 414 {0x0eb50b40, 0x0fff0f70, "fcmp%7'ezd%c\t%1z"}, 415 {0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%1y"}, 416 {0x0eb00b40, 0x0fff0ff0, "fcpyd%c\t%1z, %0z"}, 417 {0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%1y, %0y"}, 418 {0x0eb70ac0, 0x0fff0fd0, "fcvtds%c\t%1z, %0y"}, 419 {0x0eb70bc0, 0x0fbf0ff0, "fcvtsd%c\t%1y, %0z"}, 420 {0x0e800b00, 0x0ff00ff0, "fdivd%c\t%1z, %2z, %0z"}, 421 {0x0e800a00, 0x0fb00f50, "fdivs%c\t%1y, %2y, %0y"}, 422 {0x0d100b00, 0x0f700f00, "fldd%c\t%1z, %A"}, 423 {0x0c900b00, 0x0fd00f00, "fldmia%0?xd%c\t%16-19r%21'!, %3z"}, 424 {0x0d300b00, 0x0ff00f00, "fldmdb%0?xd%c\t%16-19r!, %3z"}, 425 {0x0d100a00, 0x0f300f00, "flds%c\t%1y, %A"}, 426 {0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %3y"}, 427 {0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %3y"}, 428 {0x0e000b00, 0x0ff00ff0, "fmacd%c\t%1z, %2z, %0z"}, 429 {0x0e000a00, 0x0fb00f50, "fmacs%c\t%1y, %2y, %0y"}, 430 {0x0e200b10, 0x0ff00fff, "fmdhr%c\t%2z, %12-15r"}, 431 {0x0e000b10, 0x0ff00fff, "fmdlr%c\t%2z, %12-15r"}, 432 {0x0c400b10, 0x0ff00ff0, "fmdrr%c\t%0z, %12-15r, %16-19r"}, 433 {0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %2z"}, 434 {0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %2z"}, 435 {0x0c500b10, 0x0ff00ff0, "fmrrd%c\t%12-15r, %16-19r, %0z"}, 436 {0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %4y"}, 437 {0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %2y"}, 438 {0x0ef1fa10, 0x0fffffff, "fmstat%c"}, 439 {0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"}, 440 {0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"}, 441 {0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"}, 442 {0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"}, 443 {0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"}, 444 {0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def 0x%16-19x>"}, 445 {0x0e100b00, 0x0ff00ff0, "fmscd%c\t%1z, %2z, %0z"}, 446 {0x0e100a00, 0x0fb00f50, "fmscs%c\t%1y, %2y, %0y"}, 447 {0x0e000a10, 0x0ff00f7f, "fmsr%c\t%2y, %12-15r"}, 448 {0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %4y"}, 449 {0x0e200b00, 0x0ff00ff0, "fmuld%c\t%1z, %2z, %0z"}, 450 {0x0e200a00, 0x0fb00f50, "fmuls%c\t%1y, %2y, %0y"}, 451 {0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"}, 452 {0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"}, 453 {0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"}, 454 {0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"}, 455 {0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"}, 456 {0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def 0x%16-19x>, %12-15r"}, 457 {0x0eb10b40, 0x0fff0ff0, "fnegd%c\t%1z, %0z"}, 458 {0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%1y, %0y"}, 459 {0x0e000b40, 0x0ff00ff0, "fnmacd%c\t%1z, %2z, %0z"}, 460 {0x0e000a40, 0x0fb00f50, "fnmacs%c\t%1y, %2y, %0y"}, 461 {0x0e100b40, 0x0ff00ff0, "fnmscd%c\t%1z, %2z, %0z"}, 462 {0x0e100a40, 0x0fb00f50, "fnmscs%c\t%1y, %2y, %0y"}, 463 {0x0e200b40, 0x0ff00ff0, "fnmuld%c\t%1z, %2z, %0z"}, 464 {0x0e200a40, 0x0fb00f50, "fnmuls%c\t%1y, %2y, %0y"}, 465 {0x0eb80bc0, 0x0fff0fd0, "fsitod%c\t%1z, %0y"}, 466 {0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%1y, %0y"}, 467 {0x0eb10bc0, 0x0fff0ff0, "fsqrtd%c\t%1z, %0z"}, 468 {0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%1y, %0y"}, 469 {0x0d000b00, 0x0f700f00, "fstd%c\t%1z, %A"}, 470 {0x0c800b00, 0x0fd00f00, "fstmia%0?xd%c\t%16-19r%21'!, %3z"}, 471 {0x0d200b00, 0x0ff00f00, "fstmdb%0?xd%c\t%16-19r!, %3z"}, 472 {0x0d000a00, 0x0f300f00, "fsts%c\t%1y, %A"}, 473 {0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %3y"}, 474 {0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %3y"}, 475 {0x0e300b40, 0x0ff00ff0, "fsubd%c\t%1z, %2z, %0z"}, 476 {0x0e300a40, 0x0fb00f50, "fsubs%c\t%1y, %2y, %0y"}, 477 {0x0ebc0b40, 0x0fbe0f70, "fto%16?sui%7'zd%c\t%1y, %0z"}, 478 {0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%1y, %0y"}, 479 {0x0eb80b40, 0x0fff0fd0, "fuitod%c\t%1z, %0y"}, 480 {0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%1y, %0y"}, 481 482 /* Cirrus coprocessor instructions. */ 483 {0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 484 {0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 485 {0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 486 {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 487 {0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 488 {0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 489 {0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 490 {0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 491 {0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 492 {0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 493 {0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 494 {0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 495 {0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 496 {0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 497 {0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 498 {0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 499 {0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, 500 {0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, 501 {0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, 502 {0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, 503 {0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, 504 {0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, 505 {0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, 506 {0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, 507 {0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, 508 {0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, 509 {0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, 510 {0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, 511 {0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, 512 {0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, 513 {0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, 514 {0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, 515 {0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, 516 {0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, 517 {0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, 518 {0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, 519 {0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, 520 {0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, 521 {0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, 522 {0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, 523 {0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, 524 {0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, 525 {0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, 526 {0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, 527 {0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, 528 {0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, 529 {0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, 530 {0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, 531 {0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, 532 {0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, 533 {0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, 534 {0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, 535 {0x0e000500, 0x0ff00f00, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, 536 {0x0e200500, 0x0ff00f00, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, 537 {0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, 538 {0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, 539 {0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, 540 {0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, 541 {0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, 542 {0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, 543 {0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, 544 {0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, 545 {0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 546 {0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 547 {0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 548 {0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 549 {0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 550 {0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 551 {0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, 552 {0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, 553 {0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, 554 {0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, 555 {0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 556 {0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 557 {0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 558 {0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 559 {0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 560 {0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 561 {0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 562 {0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 563 {0x0e000600, 0x0ff00f00, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 564 {0x0e100600, 0x0ff00f00, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 565 {0x0e200600, 0x0ff00f00, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 566 {0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 567 568 /* Generic coprocessor instructions */ 569 {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 570 {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 571 {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 572 {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 573 {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 574 {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"}, 575 {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"}, 576 577 /* The rest. */ 578 {0x00000000, 0x00000000, "undefined instruction %0-31x"}, 579 {0x00000000, 0x00000000, 0} 580 }; 581 582 #define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */ 583 584 static const struct thumb_opcode thumb_opcodes[] = 585 { 586 /* Thumb instructions. */ 587 588 /* ARM V6. */ 589 {0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"}, 590 {0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"}, 591 {0x4600, 0xffc0, "cpy\t%0-2r, %3-5r"}, 592 {0xba00, 0xffc0, "rev\t%0-2r, %3-5r"}, 593 {0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"}, 594 {0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"}, 595 {0xb650, 0xfff7, "setend\t%3?ble\t"}, 596 {0xb200, 0xffc0, "sxth\t%0-2r, %3-5r"}, 597 {0xb240, 0xffc0, "sxtb\t%0-2r, %3-5r"}, 598 {0xb280, 0xffc0, "uxth\t%0-2r, %3-5r"}, 599 {0xb2c0, 0xffc0, "uxtb\t%0-2r, %3-5r"}, 600 601 /* ARM V5 ISA extends Thumb. */ 602 {0xbe00, 0xff00, "bkpt\t%0-7x"}, 603 {0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */ 604 /* Note: this is BLX(2). BLX(1) is done in arm-dis.c/print_insn_thumb() 605 as an extension of the special processing there for Thumb BL. 606 BL and BLX(1) involve 2 successive 16-bit instructions, which must 607 always appear together in the correct order. So, the empty 608 string is put in this table, and the string interpreter takes <empty> 609 to mean it has a pair of BL-ish instructions. */ 610 {0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"}, 611 /* Format 5 instructions do not update the PSR. */ 612 {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"}, 613 /* Format 4. */ 614 {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"}, 615 {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"}, 616 {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"}, 617 {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"}, 618 {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"}, 619 {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"}, 620 {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"}, 621 {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"}, 622 {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"}, 623 {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"}, 624 {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"}, 625 {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"}, 626 {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"}, 627 {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"}, 628 {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"}, 629 {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"}, 630 /* format 13 */ 631 {0xB000, 0xFF80, "add\tsp, #%0-6W"}, 632 {0xB080, 0xFF80, "sub\tsp, #%0-6W"}, 633 /* format 5 */ 634 {0x4700, 0xFF80, "bx\t%S"}, 635 {0x4400, 0xFF00, "add\t%D, %S"}, 636 {0x4500, 0xFF00, "cmp\t%D, %S"}, 637 {0x4600, 0xFF00, "mov\t%D, %S"}, 638 /* format 14 */ 639 {0xB400, 0xFE00, "push\t%N"}, 640 {0xBC00, 0xFE00, "pop\t%O"}, 641 /* format 2 */ 642 {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"}, 643 {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"}, 644 {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"}, 645 {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"}, 646 /* format 8 */ 647 {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"}, 648 {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"}, 649 {0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"}, 650 /* format 7 */ 651 {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"}, 652 {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"}, 653 /* format 1 */ 654 {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"}, 655 {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"}, 656 {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"}, 657 /* format 3 */ 658 {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"}, 659 {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"}, 660 {0x3000, 0xF800, "add\t%8-10r, #%0-7d"}, 661 {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"}, 662 /* format 6 */ 663 {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 664 /* format 9 */ 665 {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, 666 {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, 667 {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, 668 {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, 669 /* format 10 */ 670 {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"}, 671 {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"}, 672 /* format 11 */ 673 {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"}, 674 {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"}, 675 /* format 12 */ 676 {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"}, 677 {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"}, 678 /* format 15 */ 679 {0xC000, 0xF800, "stmia\t%8-10r!,%M"}, 680 {0xC800, 0xF800, "ldmia\t%8-10r!,%M"}, 681 /* format 18 */ 682 {0xE000, 0xF800, "b\t%0-10B"}, 683 {0xE800, 0xF800, "undefined"}, 684 /* format 19 */ 685 {0xF000, 0xF800, ""}, /* special processing required in disassembler */ 686 {0xF800, 0xF800, "second half of BL instruction %0-15x"}, 687 /* format 16 */ 688 {0xD000, 0xFF00, "beq\t%0-7B"}, 689 {0xD100, 0xFF00, "bne\t%0-7B"}, 690 {0xD200, 0xFF00, "bcs\t%0-7B"}, 691 {0xD300, 0xFF00, "bcc\t%0-7B"}, 692 {0xD400, 0xFF00, "bmi\t%0-7B"}, 693 {0xD500, 0xFF00, "bpl\t%0-7B"}, 694 {0xD600, 0xFF00, "bvs\t%0-7B"}, 695 {0xD700, 0xFF00, "bvc\t%0-7B"}, 696 {0xD800, 0xFF00, "bhi\t%0-7B"}, 697 {0xD900, 0xFF00, "bls\t%0-7B"}, 698 {0xDA00, 0xFF00, "bge\t%0-7B"}, 699 {0xDB00, 0xFF00, "blt\t%0-7B"}, 700 {0xDC00, 0xFF00, "bgt\t%0-7B"}, 701 {0xDD00, 0xFF00, "ble\t%0-7B"}, 702 /* format 17 */ 703 {0xDE00, 0xFF00, "bal\t%0-7B"}, 704 {0xDF00, 0xFF00, "swi\t%0-7d"}, 705 /* format 9 */ 706 {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, 707 {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, 708 {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, 709 {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, 710 /* the rest */ 711 {0x0000, 0x0000, "undefined instruction %0-15x"}, 712 {0x0000, 0x0000, 0} 713 }; 714 715 #define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \ 716 ^ 0x200000) - 0x200000) /* 23bit */ 717 718