1# $OpenBSD: Makefile,v 1.8 2021/04/28 12:55:38 patrick Exp $ 2 3.include <bsd.own.mk> 4 5LLVM_SRCS= ${.CURDIR}/../../../../../llvm/llvm 6 7HDRS= X86GenAsmMatcher.inc \ 8 X86GenAsmWriter.inc \ 9 X86GenAsmWriter1.inc \ 10 X86GenCallingConv.inc \ 11 X86GenDAGISel.inc \ 12 X86GenDisassemblerTables.inc \ 13 X86GenEVEX2VEXTables.inc \ 14 X86GenExegesis.inc \ 15 X86GenFastISel.inc \ 16 X86GenGlobalISel.inc \ 17 X86GenInstrInfo.inc \ 18 X86GenRegisterBank.inc \ 19 X86GenRegisterInfo.inc \ 20 X86GenSubtargetInfo.inc 21 22all: ${HDRS} 23 24install: 25 @# Nothing here so far ... 26 27clean cleandir: 28 rm -f ${HDRS} 29 30X86GenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 31 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-matcher \ 32 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 33 -o ${.TARGET} ${.ALLSRC} 34 35X86GenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 36 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \ 37 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 38 -o ${.TARGET} ${.ALLSRC} 39 40X86GenAsmWriter1.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 41 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer -asmwriternum=1 \ 42 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 43 -o ${.TARGET} ${.ALLSRC} 44 45X86GenCallingConv.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 46 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \ 47 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 48 -o ${.TARGET} ${.ALLSRC} 49 50X86GenDAGISel.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 51 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \ 52 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 53 -o ${.TARGET} ${.ALLSRC} 54 55X86GenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 56 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \ 57 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 58 -o ${.TARGET} ${.ALLSRC} 59 60X86GenEVEX2VEXTables.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 61 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-x86-EVEX2VEX-tables \ 62 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 63 -o ${.TARGET} ${.ALLSRC} 64 65X86GenExegesis.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 66 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-exegesis \ 67 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 68 -o ${.TARGET} ${.ALLSRC} 69 70X86GenFastISel.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 71 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-fast-isel \ 72 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 73 -o ${.TARGET} ${.ALLSRC} 74 75X86GenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 76 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel \ 77 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 78 -o ${.TARGET} ${.ALLSRC} 79 80X86GenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 81 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \ 82 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 83 -o ${.TARGET} ${.ALLSRC} 84 85X86GenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 86 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-bank \ 87 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 88 -o ${.TARGET} ${.ALLSRC} 89 90X86GenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 91 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \ 92 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 93 -o ${.TARGET} ${.ALLSRC} 94 95X86GenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/X86/X86.td 96 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \ 97 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/X86 \ 98 -o ${.TARGET} ${.ALLSRC} 99 100.include <bsd.obj.mk> 101