1*c87b03e5Sespie;; Scheduling description for Alpha EV4. 2*c87b03e5Sespie;; Copyright (C) 2002 Free Software Foundation, Inc. 3*c87b03e5Sespie;; 4*c87b03e5Sespie;; This file is part of GNU CC. 5*c87b03e5Sespie;; 6*c87b03e5Sespie;; GNU CC is free software; you can redistribute it and/or modify 7*c87b03e5Sespie;; it under the terms of the GNU General Public License as published by 8*c87b03e5Sespie;; the Free Software Foundation; either version 2, or (at your option) 9*c87b03e5Sespie;; any later version. 10*c87b03e5Sespie;; 11*c87b03e5Sespie;; GNU CC is distributed in the hope that it will be useful, 12*c87b03e5Sespie;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13*c87b03e5Sespie;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*c87b03e5Sespie;; GNU General Public License for more details. 15*c87b03e5Sespie;; 16*c87b03e5Sespie;; You should have received a copy of the GNU General Public License 17*c87b03e5Sespie;; along with GNU CC; see the file COPYING. If not, write to 18*c87b03e5Sespie;; the Free Software Foundation, 59 Temple Place - Suite 330, 19*c87b03e5Sespie;; Boston, MA 02111-1307, USA. 20*c87b03e5Sespie 21*c87b03e5Sespie; On EV4 there are two classes of resources to consider: resources needed 22*c87b03e5Sespie; to issue, and resources needed to execute. IBUS[01] are in the first 23*c87b03e5Sespie; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second. 24*c87b03e5Sespie; (There are a few other register-like resources, but ...) 25*c87b03e5Sespie 26*c87b03e5Sespie(define_automaton "ev4_0,ev4_1,ev4_2") 27*c87b03e5Sespie(define_cpu_unit "ev4_ib0,ev4_ib1,ev4_abox,ev4_bbox" "ev4_0") 28*c87b03e5Sespie(define_cpu_unit "ev4_ebox,ev4_imul" "ev4_1") 29*c87b03e5Sespie(define_cpu_unit "ev4_fbox,ev4_fdiv" "ev4_2") 30*c87b03e5Sespie(define_reservation "ev4_ib01" "ev4_ib0|ev4_ib1") 31*c87b03e5Sespie 32*c87b03e5Sespie; Assume type "multi" single issues. 33*c87b03e5Sespie(define_insn_reservation "ev4_multi" 1 34*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 35*c87b03e5Sespie (eq_attr "type" "multi")) 36*c87b03e5Sespie "ev4_ib0+ev4_ib1") 37*c87b03e5Sespie 38*c87b03e5Sespie; Loads from L0 completes in three cycles. adjust_cost still factors 39*c87b03e5Sespie; in user-specified memory latency, so return 1 here. 40*c87b03e5Sespie(define_insn_reservation "ev4_ld" 1 41*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 42*c87b03e5Sespie (eq_attr "type" "ild,fld,ldsym")) 43*c87b03e5Sespie "ev4_ib01+ev4_abox") 44*c87b03e5Sespie 45*c87b03e5Sespie; Stores can issue before the data (but not address) is ready. 46*c87b03e5Sespie(define_insn_reservation "ev4_ist" 1 47*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 48*c87b03e5Sespie (eq_attr "type" "ist")) 49*c87b03e5Sespie "ev4_ib1+ev4_abox") 50*c87b03e5Sespie 51*c87b03e5Sespie(define_insn_reservation "ev4_fst" 1 52*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 53*c87b03e5Sespie (eq_attr "type" "fst")) 54*c87b03e5Sespie "ev4_ib0+ev4_abox") 55*c87b03e5Sespie 56*c87b03e5Sespie; Branches have no delay cost, but do tie up the unit for two cycles. 57*c87b03e5Sespie(define_insn_reservation "ev4_ibr" 2 58*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 59*c87b03e5Sespie (eq_attr "type" "ibr,jsr")) 60*c87b03e5Sespie "ev4_ib1+ev4_bbox,ev4_bbox") 61*c87b03e5Sespie 62*c87b03e5Sespie(define_insn_reservation "ev4_callpal" 2 63*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 64*c87b03e5Sespie (eq_attr "type" "callpal")) 65*c87b03e5Sespie "ev4_ib1+ev4_bbox,ev4_bbox") 66*c87b03e5Sespie 67*c87b03e5Sespie(define_insn_reservation "ev4_fbr" 2 68*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 69*c87b03e5Sespie (eq_attr "type" "fbr")) 70*c87b03e5Sespie "ev4_ib0+ev4_bbox,ev4_bbox") 71*c87b03e5Sespie 72*c87b03e5Sespie; Arithmetic insns are normally have their results available after 73*c87b03e5Sespie; two cycles. There are a number of exceptions. 74*c87b03e5Sespie 75*c87b03e5Sespie(define_insn_reservation "ev4_iaddlog" 2 76*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 77*c87b03e5Sespie (eq_attr "type" "iadd,ilog")) 78*c87b03e5Sespie "ev4_ib0+ev4_ebox") 79*c87b03e5Sespie 80*c87b03e5Sespie(define_bypass 1 81*c87b03e5Sespie "ev4_iaddlog" 82*c87b03e5Sespie "ev4_ibr,ev4_iaddlog,ev4_shiftcm,ev4_icmp,ev4_imulsi,ev4_imuldi") 83*c87b03e5Sespie 84*c87b03e5Sespie(define_insn_reservation "ev4_shiftcm" 2 85*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 86*c87b03e5Sespie (eq_attr "type" "shift,icmov")) 87*c87b03e5Sespie "ev4_ib0+ev4_ebox") 88*c87b03e5Sespie 89*c87b03e5Sespie(define_insn_reservation "ev4_icmp" 2 90*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 91*c87b03e5Sespie (eq_attr "type" "icmp")) 92*c87b03e5Sespie "ev4_ib0+ev4_ebox") 93*c87b03e5Sespie 94*c87b03e5Sespie(define_bypass 1 "ev4_icmp" "ev4_ibr") 95*c87b03e5Sespie 96*c87b03e5Sespie(define_bypass 0 97*c87b03e5Sespie "ev4_iaddlog,ev4_shiftcm,ev4_icmp" 98*c87b03e5Sespie "ev4_ist" 99*c87b03e5Sespie "store_data_bypass_p") 100*c87b03e5Sespie 101*c87b03e5Sespie; Multiplies use a non-piplined imul unit. Also, "no [ebox] insn can 102*c87b03e5Sespie; be issued exactly three cycles before an integer multiply completes". 103*c87b03e5Sespie 104*c87b03e5Sespie(define_insn_reservation "ev4_imulsi" 21 105*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 106*c87b03e5Sespie (and (eq_attr "type" "imul") 107*c87b03e5Sespie (eq_attr "opsize" "si"))) 108*c87b03e5Sespie "ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox") 109*c87b03e5Sespie 110*c87b03e5Sespie(define_bypass 20 "ev4_imulsi" "ev4_ist" "store_data_bypass_p") 111*c87b03e5Sespie 112*c87b03e5Sespie(define_insn_reservation "ev4_imuldi" 23 113*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 114*c87b03e5Sespie (and (eq_attr "type" "imul") 115*c87b03e5Sespie (eq_attr "opsize" "!si"))) 116*c87b03e5Sespie "ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox") 117*c87b03e5Sespie 118*c87b03e5Sespie(define_bypass 22 "ev4_imuldi" "ev4_ist" "store_data_bypass_p") 119*c87b03e5Sespie 120*c87b03e5Sespie; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in. 121*c87b03e5Sespie(define_insn_reservation "ev4_fpop" 6 122*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 123*c87b03e5Sespie (eq_attr "type" "fadd,fmul,fcpys,fcmov")) 124*c87b03e5Sespie "ev4_ib1+ev4_fbox") 125*c87b03e5Sespie 126*c87b03e5Sespie(define_bypass 4 "ev4_fpop" "ev4_fpop") 127*c87b03e5Sespie 128*c87b03e5Sespie; The floating point divider is not pipelined. Also, "no FPOP insn can be 129*c87b03e5Sespie; issued exactly five or exactly six cycles before an fdiv insn completes". 130*c87b03e5Sespie 131*c87b03e5Sespie(define_insn_reservation "ev4_fdivsf" 34 132*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 133*c87b03e5Sespie (and (eq_attr "type" "fdiv") 134*c87b03e5Sespie (eq_attr "opsize" "si"))) 135*c87b03e5Sespie "ev4_ib1+ev4_fdiv,ev4_fdiv*28,ev4_fdiv+ev4_fbox,ev4_fbox") 136*c87b03e5Sespie 137*c87b03e5Sespie(define_insn_reservation "ev4_fdivdf" 63 138*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 139*c87b03e5Sespie (and (eq_attr "type" "fdiv") 140*c87b03e5Sespie (eq_attr "opsize" "di"))) 141*c87b03e5Sespie "ev4_ib1+ev4_fdiv,ev4_fdiv*57,ev4_fdiv+ev4_fbox,ev4_fbox") 142*c87b03e5Sespie 143*c87b03e5Sespie; Traps don't consume or produce data. 144*c87b03e5Sespie(define_insn_reservation "ev4_misc" 1 145*c87b03e5Sespie (and (eq_attr "cpu" "ev4") 146*c87b03e5Sespie (eq_attr "type" "misc")) 147*c87b03e5Sespie "ev4_ib1") 148