1c87b03e5Sespie;;- Machine description for HP PA-RISC architecture for GNU C compiler 2c87b03e5Sespie;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 3c87b03e5Sespie;; 2002, 2003 Free Software Foundation, Inc. 4c87b03e5Sespie;; Contributed by the Center for Software Science at the University 5c87b03e5Sespie;; of Utah. 6c87b03e5Sespie 7c87b03e5Sespie;; This file is part of GNU CC. 8c87b03e5Sespie 9c87b03e5Sespie;; GNU CC is free software; you can redistribute it and/or modify 10c87b03e5Sespie;; it under the terms of the GNU General Public License as published by 11c87b03e5Sespie;; the Free Software Foundation; either version 2, or (at your option) 12c87b03e5Sespie;; any later version. 13c87b03e5Sespie 14c87b03e5Sespie;; GNU CC is distributed in the hope that it will be useful, 15c87b03e5Sespie;; but WITHOUT ANY WARRANTY; without even the implied warranty of 16c87b03e5Sespie;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17c87b03e5Sespie;; GNU General Public License for more details. 18c87b03e5Sespie 19c87b03e5Sespie;; You should have received a copy of the GNU General Public License 20c87b03e5Sespie;; along with GNU CC; see the file COPYING. If not, write to 21c87b03e5Sespie;; the Free Software Foundation, 59 Temple Place - Suite 330, 22c87b03e5Sespie;; Boston, MA 02111-1307, USA. 23c87b03e5Sespie 24c87b03e5Sespie;; This gcc Version 2 machine description is inspired by sparc.md and 25c87b03e5Sespie;; mips.md. 26c87b03e5Sespie 27c87b03e5Sespie;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 28c87b03e5Sespie 29c87b03e5Sespie;; Insn type. Used to default other attribute values. 30c87b03e5Sespie 31c87b03e5Sespie;; type "unary" insns have one input operand (1) and one output operand (0) 32c87b03e5Sespie;; type "binary" insns have two input operands (1,2) and one output (0) 33c87b03e5Sespie 34c87b03e5Sespie(define_attr "type" 35c87b03e5Sespie "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch" 36c87b03e5Sespie (const_string "binary")) 37c87b03e5Sespie 38c87b03e5Sespie(define_attr "pa_combine_type" 39c87b03e5Sespie "fmpy,faddsub,uncond_branch,addmove,none" 40c87b03e5Sespie (const_string "none")) 41c87b03e5Sespie 42c87b03e5Sespie;; Processor type (for scheduling, not code generation) -- this attribute 43c87b03e5Sespie;; must exactly match the processor_type enumeration in pa.h. 44c87b03e5Sespie;; 45c87b03e5Sespie;; FIXME: Add 800 scheduling for completeness? 46c87b03e5Sespie 47c87b03e5Sespie(define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr"))) 48c87b03e5Sespie 49c87b03e5Sespie;; Length (in # of bytes). 50c87b03e5Sespie(define_attr "length" "" 51c87b03e5Sespie (cond [(eq_attr "type" "load,fpload") 52c87b03e5Sespie (if_then_else (match_operand 1 "symbolic_memory_operand" "") 53c87b03e5Sespie (const_int 8) (const_int 4)) 54c87b03e5Sespie 55c87b03e5Sespie (eq_attr "type" "store,fpstore") 56c87b03e5Sespie (if_then_else (match_operand 0 "symbolic_memory_operand" "") 57c87b03e5Sespie (const_int 8) (const_int 4)) 58c87b03e5Sespie 59c87b03e5Sespie (eq_attr "type" "binary,shift,nullshift") 60c87b03e5Sespie (if_then_else (match_operand 2 "arith_operand" "") 61c87b03e5Sespie (const_int 4) (const_int 12)) 62c87b03e5Sespie 63c87b03e5Sespie (eq_attr "type" "move,unary,shift,nullshift") 64c87b03e5Sespie (if_then_else (match_operand 1 "arith_operand" "") 65c87b03e5Sespie (const_int 4) (const_int 8))] 66c87b03e5Sespie 67c87b03e5Sespie (const_int 4))) 68c87b03e5Sespie 69c87b03e5Sespie(define_asm_attributes 70c87b03e5Sespie [(set_attr "length" "4") 71c87b03e5Sespie (set_attr "type" "multi")]) 72c87b03e5Sespie 73c87b03e5Sespie;; Attributes for instruction and branch scheduling 74c87b03e5Sespie 75c87b03e5Sespie;; For conditional branches. 76c87b03e5Sespie(define_attr "in_branch_delay" "false,true" 77c87b03e5Sespie (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch") 78c87b03e5Sespie (eq_attr "length" "4")) 79c87b03e5Sespie (const_string "true") 80c87b03e5Sespie (const_string "false"))) 81c87b03e5Sespie 82c87b03e5Sespie;; Disallow instructions which use the FPU since they will tie up the FPU 83c87b03e5Sespie;; even if the instruction is nullified. 84c87b03e5Sespie(define_attr "in_nullified_branch_delay" "false,true" 85c87b03e5Sespie (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch") 86c87b03e5Sespie (eq_attr "length" "4")) 87c87b03e5Sespie (const_string "true") 88c87b03e5Sespie (const_string "false"))) 89c87b03e5Sespie 90c87b03e5Sespie;; For calls and millicode calls. Allow unconditional branches in the 91c87b03e5Sespie;; delay slot. 92c87b03e5Sespie(define_attr "in_call_delay" "false,true" 93c87b03e5Sespie (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch") 94c87b03e5Sespie (eq_attr "length" "4")) 95c87b03e5Sespie (const_string "true") 96c87b03e5Sespie (eq_attr "type" "uncond_branch") 97c87b03e5Sespie (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY") 98c87b03e5Sespie (const_int 0)) 99c87b03e5Sespie (const_string "true") 100c87b03e5Sespie (const_string "false"))] 101c87b03e5Sespie (const_string "false"))) 102c87b03e5Sespie 103c87b03e5Sespie 104c87b03e5Sespie;; Call delay slot description. 105c87b03e5Sespie(define_delay (eq_attr "type" "call") 106c87b03e5Sespie [(eq_attr "in_call_delay" "true") (nil) (nil)]) 107c87b03e5Sespie 108c87b03e5Sespie;; Millicode call delay slot description. 109c87b03e5Sespie(define_delay (eq_attr "type" "milli") 110c87b03e5Sespie [(eq_attr "in_call_delay" "true") (nil) (nil)]) 111c87b03e5Sespie 112c87b03e5Sespie;; Return and other similar instructions. 113c87b03e5Sespie(define_delay (eq_attr "type" "branch,parallel_branch") 114c87b03e5Sespie [(eq_attr "in_branch_delay" "true") (nil) (nil)]) 115c87b03e5Sespie 116c87b03e5Sespie;; Floating point conditional branch delay slot description and 117c87b03e5Sespie(define_delay (eq_attr "type" "fbranch") 118c87b03e5Sespie [(eq_attr "in_branch_delay" "true") 119c87b03e5Sespie (eq_attr "in_nullified_branch_delay" "true") 120c87b03e5Sespie (nil)]) 121c87b03e5Sespie 122c87b03e5Sespie;; Integer conditional branch delay slot description. 123c87b03e5Sespie;; Nullification of conditional branches on the PA is dependent on the 124c87b03e5Sespie;; direction of the branch. Forward branches nullify true and 125c87b03e5Sespie;; backward branches nullify false. If the direction is unknown 126c87b03e5Sespie;; then nullification is not allowed. 127c87b03e5Sespie(define_delay (eq_attr "type" "cbranch") 128c87b03e5Sespie [(eq_attr "in_branch_delay" "true") 129c87b03e5Sespie (and (eq_attr "in_nullified_branch_delay" "true") 130c87b03e5Sespie (attr_flag "forward")) 131c87b03e5Sespie (and (eq_attr "in_nullified_branch_delay" "true") 132c87b03e5Sespie (attr_flag "backward"))]) 133c87b03e5Sespie 134c87b03e5Sespie(define_delay (and (eq_attr "type" "uncond_branch") 135c87b03e5Sespie (eq (symbol_ref "following_call (insn)") 136c87b03e5Sespie (const_int 0))) 137c87b03e5Sespie [(eq_attr "in_branch_delay" "true") (nil) (nil)]) 138c87b03e5Sespie 139c87b03e5Sespie;; Memory. Disregarding Cache misses, the Mustang memory times are: 140c87b03e5Sespie;; load: 2, fpload: 3 141c87b03e5Sespie;; store, fpstore: 3, no D-cache operations should be scheduled. 142c87b03e5Sespie 143c87b03e5Sespie;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT. 144c87b03e5Sespie;; Timings: 145c87b03e5Sespie;; Instruction Time Unit Minimum Distance (unit contention) 146c87b03e5Sespie;; fcpy 3 ALU 2 147c87b03e5Sespie;; fabs 3 ALU 2 148c87b03e5Sespie;; fadd 3 ALU 2 149c87b03e5Sespie;; fsub 3 ALU 2 150c87b03e5Sespie;; fcmp 3 ALU 2 151c87b03e5Sespie;; fcnv 3 ALU 2 152c87b03e5Sespie;; fmpyadd 3 ALU,MPY 2 153c87b03e5Sespie;; fmpysub 3 ALU,MPY 2 154c87b03e5Sespie;; fmpycfxt 3 ALU,MPY 2 155c87b03e5Sespie;; fmpy 3 MPY 2 156c87b03e5Sespie;; fmpyi 3 MPY 2 157c87b03e5Sespie;; fdiv,sgl 10 MPY 10 158c87b03e5Sespie;; fdiv,dbl 12 MPY 12 159c87b03e5Sespie;; fsqrt,sgl 14 MPY 14 160c87b03e5Sespie;; fsqrt,dbl 18 MPY 18 161c87b03e5Sespie;; 162c87b03e5Sespie;; We don't model fmpyadd/fmpysub properly as those instructions 163c87b03e5Sespie;; keep both the FP ALU and MPY units busy. Given that these 164c87b03e5Sespie;; processors are obsolete, I'm not going to spend the time to 165c87b03e5Sespie;; model those instructions correctly. 166c87b03e5Sespie 167c87b03e5Sespie(define_automaton "pa700") 168c87b03e5Sespie(define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700") 169c87b03e5Sespie 170c87b03e5Sespie(define_insn_reservation "W0" 4 171c87b03e5Sespie (and (eq_attr "type" "fpcc") 172c87b03e5Sespie (eq_attr "cpu" "700")) 173c87b03e5Sespie "fpalu_700*2") 174c87b03e5Sespie 175c87b03e5Sespie(define_insn_reservation "W1" 3 176c87b03e5Sespie (and (eq_attr "type" "fpalu") 177c87b03e5Sespie (eq_attr "cpu" "700")) 178c87b03e5Sespie "fpalu_700*2") 179c87b03e5Sespie 180c87b03e5Sespie(define_insn_reservation "W2" 3 181c87b03e5Sespie (and (eq_attr "type" "fpmulsgl,fpmuldbl") 182c87b03e5Sespie (eq_attr "cpu" "700")) 183c87b03e5Sespie "fpmpy_700*2") 184c87b03e5Sespie 185c87b03e5Sespie(define_insn_reservation "W3" 10 186c87b03e5Sespie (and (eq_attr "type" "fpdivsgl") 187c87b03e5Sespie (eq_attr "cpu" "700")) 188c87b03e5Sespie "fpmpy_700*10") 189c87b03e5Sespie 190c87b03e5Sespie(define_insn_reservation "W4" 12 191c87b03e5Sespie (and (eq_attr "type" "fpdivdbl") 192c87b03e5Sespie (eq_attr "cpu" "700")) 193c87b03e5Sespie "fpmpy_700*12") 194c87b03e5Sespie 195c87b03e5Sespie(define_insn_reservation "W5" 14 196c87b03e5Sespie (and (eq_attr "type" "fpsqrtsgl") 197c87b03e5Sespie (eq_attr "cpu" "700")) 198c87b03e5Sespie "fpmpy_700*14") 199c87b03e5Sespie 200c87b03e5Sespie(define_insn_reservation "W6" 18 201c87b03e5Sespie (and (eq_attr "type" "fpsqrtdbl") 202c87b03e5Sespie (eq_attr "cpu" "700")) 203c87b03e5Sespie "fpmpy_700*18") 204c87b03e5Sespie 205c87b03e5Sespie(define_insn_reservation "W7" 2 206c87b03e5Sespie (and (eq_attr "type" "load") 207c87b03e5Sespie (eq_attr "cpu" "700")) 208c87b03e5Sespie "mem_700") 209c87b03e5Sespie 210c87b03e5Sespie(define_insn_reservation "W8" 2 211c87b03e5Sespie (and (eq_attr "type" "fpload") 212c87b03e5Sespie (eq_attr "cpu" "700")) 213c87b03e5Sespie "mem_700") 214c87b03e5Sespie 215c87b03e5Sespie(define_insn_reservation "W9" 3 216c87b03e5Sespie (and (eq_attr "type" "store") 217c87b03e5Sespie (eq_attr "cpu" "700")) 218c87b03e5Sespie "mem_700*3") 219c87b03e5Sespie 220c87b03e5Sespie(define_insn_reservation "W10" 3 221c87b03e5Sespie (and (eq_attr "type" "fpstore") 222c87b03e5Sespie (eq_attr "cpu" "700")) 223c87b03e5Sespie "mem_700*3") 224c87b03e5Sespie 225c87b03e5Sespie(define_insn_reservation "W11" 1 226c87b03e5Sespie (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore") 227c87b03e5Sespie (eq_attr "cpu" "700")) 228c87b03e5Sespie "dummy_700") 229c87b03e5Sespie 230c87b03e5Sespie;; We have a bypass for all computations in the FP unit which feed an 231c87b03e5Sespie;; FP store as long as the sizes are the same. 232c87b03e5Sespie(define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p") 233c87b03e5Sespie(define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p") 234c87b03e5Sespie(define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p") 235c87b03e5Sespie(define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p") 236c87b03e5Sespie(define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p") 237c87b03e5Sespie 238c87b03e5Sespie;; We have an "anti-bypass" for FP loads which feed an FP store. 239c87b03e5Sespie(define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p") 240c87b03e5Sespie 241c87b03e5Sespie;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue 242c87b03e5Sespie;; floating point computations with non-floating point computations (fp loads 243c87b03e5Sespie;; and stores are not fp computations). 244c87b03e5Sespie;; 245c87b03e5Sespie;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also 246c87b03e5Sespie;; take two cycles, during which no Dcache operations should be scheduled. 247c87b03e5Sespie;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC 248c87b03e5Sespie;; all have the same memory characteristics if one disregards cache misses. 249c87b03e5Sespie;; 250c87b03e5Sespie;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV. 251c87b03e5Sespie;; There's no value in modeling the ALU and MUL separately though 252c87b03e5Sespie;; since there can never be a functional unit conflict given the 253c87b03e5Sespie;; latency and issue rates for those units. 254c87b03e5Sespie;; 255c87b03e5Sespie;; Timings: 256c87b03e5Sespie;; Instruction Time Unit Minimum Distance (unit contention) 257c87b03e5Sespie;; fcpy 2 ALU 1 258c87b03e5Sespie;; fabs 2 ALU 1 259c87b03e5Sespie;; fadd 2 ALU 1 260c87b03e5Sespie;; fsub 2 ALU 1 261c87b03e5Sespie;; fcmp 2 ALU 1 262c87b03e5Sespie;; fcnv 2 ALU 1 263c87b03e5Sespie;; fmpyadd 2 ALU,MPY 1 264c87b03e5Sespie;; fmpysub 2 ALU,MPY 1 265c87b03e5Sespie;; fmpycfxt 2 ALU,MPY 1 266c87b03e5Sespie;; fmpy 2 MPY 1 267c87b03e5Sespie;; fmpyi 2 MPY 1 268c87b03e5Sespie;; fdiv,sgl 8 DIV 8 269c87b03e5Sespie;; fdiv,dbl 15 DIV 15 270c87b03e5Sespie;; fsqrt,sgl 8 DIV 8 271c87b03e5Sespie;; fsqrt,dbl 15 DIV 15 272c87b03e5Sespie 273c87b03e5Sespie(define_automaton "pa7100") 274c87b03e5Sespie(define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100") 275c87b03e5Sespie 276c87b03e5Sespie(define_insn_reservation "X0" 2 277c87b03e5Sespie (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl") 278c87b03e5Sespie (eq_attr "cpu" "7100")) 279c87b03e5Sespie "f_7100,fpmac_7100") 280c87b03e5Sespie 281c87b03e5Sespie(define_insn_reservation "X1" 8 282c87b03e5Sespie (and (eq_attr "type" "fpdivsgl,fpsqrtsgl") 283c87b03e5Sespie (eq_attr "cpu" "7100")) 284c87b03e5Sespie "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7") 285c87b03e5Sespie 286c87b03e5Sespie(define_insn_reservation "X2" 15 287c87b03e5Sespie (and (eq_attr "type" "fpdivdbl,fpsqrtdbl") 288c87b03e5Sespie (eq_attr "cpu" "7100")) 289c87b03e5Sespie "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14") 290c87b03e5Sespie 291c87b03e5Sespie(define_insn_reservation "X3" 2 292c87b03e5Sespie (and (eq_attr "type" "load") 293c87b03e5Sespie (eq_attr "cpu" "7100")) 294c87b03e5Sespie "i_7100+mem_7100") 295c87b03e5Sespie 296c87b03e5Sespie(define_insn_reservation "X4" 2 297c87b03e5Sespie (and (eq_attr "type" "fpload") 298c87b03e5Sespie (eq_attr "cpu" "7100")) 299c87b03e5Sespie "i_7100+mem_7100") 300c87b03e5Sespie 301c87b03e5Sespie(define_insn_reservation "X5" 2 302c87b03e5Sespie (and (eq_attr "type" "store") 303c87b03e5Sespie (eq_attr "cpu" "7100")) 304c87b03e5Sespie "i_7100+mem_7100,mem_7100") 305c87b03e5Sespie 306c87b03e5Sespie(define_insn_reservation "X6" 2 307c87b03e5Sespie (and (eq_attr "type" "fpstore") 308c87b03e5Sespie (eq_attr "cpu" "7100")) 309c87b03e5Sespie "i_7100+mem_7100,mem_7100") 310c87b03e5Sespie 311c87b03e5Sespie(define_insn_reservation "X7" 1 312c87b03e5Sespie (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore") 313c87b03e5Sespie (eq_attr "cpu" "7100")) 314c87b03e5Sespie "i_7100") 315c87b03e5Sespie 316c87b03e5Sespie;; We have a bypass for all computations in the FP unit which feed an 317c87b03e5Sespie;; FP store as long as the sizes are the same. 318c87b03e5Sespie(define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p") 319c87b03e5Sespie(define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p") 320c87b03e5Sespie(define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p") 321c87b03e5Sespie 322c87b03e5Sespie;; We have an "anti-bypass" for FP loads which feed an FP store. 323c87b03e5Sespie(define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p") 324c87b03e5Sespie 325c87b03e5Sespie;; The 7100LC has three floating-point units: ALU, MUL, and DIV. 326c87b03e5Sespie;; There's no value in modeling the ALU and MUL separately though 327c87b03e5Sespie;; since there can never be a functional unit conflict that 328c87b03e5Sespie;; can be avoided given the latency, issue rates and mandatory 329c87b03e5Sespie;; one cycle cpu-wide lock for a double precision fp multiply. 330c87b03e5Sespie;; 331c87b03e5Sespie;; Timings: 332c87b03e5Sespie;; Instruction Time Unit Minimum Distance (unit contention) 333c87b03e5Sespie;; fcpy 2 ALU 1 334c87b03e5Sespie;; fabs 2 ALU 1 335c87b03e5Sespie;; fadd 2 ALU 1 336c87b03e5Sespie;; fsub 2 ALU 1 337c87b03e5Sespie;; fcmp 2 ALU 1 338c87b03e5Sespie;; fcnv 2 ALU 1 339c87b03e5Sespie;; fmpyadd,sgl 2 ALU,MPY 1 340c87b03e5Sespie;; fmpyadd,dbl 3 ALU,MPY 2 341c87b03e5Sespie;; fmpysub,sgl 2 ALU,MPY 1 342c87b03e5Sespie;; fmpysub,dbl 3 ALU,MPY 2 343c87b03e5Sespie;; fmpycfxt,sgl 2 ALU,MPY 1 344c87b03e5Sespie;; fmpycfxt,dbl 3 ALU,MPY 2 345c87b03e5Sespie;; fmpy,sgl 2 MPY 1 346c87b03e5Sespie;; fmpy,dbl 3 MPY 2 347c87b03e5Sespie;; fmpyi 3 MPY 2 348c87b03e5Sespie;; fdiv,sgl 8 DIV 8 349c87b03e5Sespie;; fdiv,dbl 15 DIV 15 350c87b03e5Sespie;; fsqrt,sgl 8 DIV 8 351c87b03e5Sespie;; fsqrt,dbl 15 DIV 15 352c87b03e5Sespie;; 353c87b03e5Sespie;; The PA7200 is just like the PA7100LC except that there is 354c87b03e5Sespie;; no store-store penalty. 355c87b03e5Sespie;; 356c87b03e5Sespie;; The PA7300 is just like the PA7200 except that there is 357c87b03e5Sespie;; no store-load penalty. 358c87b03e5Sespie;; 359c87b03e5Sespie;; Note there are some aspects of the 7100LC we are not modeling 360c87b03e5Sespie;; at the moment. I'll be reviewing the 7100LC scheduling info 361c87b03e5Sespie;; shortly and updating this description. 362c87b03e5Sespie;; 363c87b03e5Sespie;; load-load pairs 364c87b03e5Sespie;; store-store pairs 365c87b03e5Sespie;; other issue modeling 366c87b03e5Sespie 367c87b03e5Sespie(define_automaton "pa7100lc") 368c87b03e5Sespie(define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc") 369c87b03e5Sespie(define_cpu_unit "fpmac_7100lc" "pa7100lc") 370c87b03e5Sespie(define_cpu_unit "mem_7100lc" "pa7100lc") 371c87b03e5Sespie 372c87b03e5Sespie;; Double precision multiplies lock the entire CPU for one 373c87b03e5Sespie;; cycle. There is no way to avoid this lock and trying to 374c87b03e5Sespie;; schedule around the lock is pointless and thus there is no 375c87b03e5Sespie;; value in trying to model this lock. 376c87b03e5Sespie;; 377c87b03e5Sespie;; Not modeling the lock allows us to treat fp multiplies just 378c87b03e5Sespie;; like any other FP alu instruction. It allows for a smaller 379c87b03e5Sespie;; DFA and may reduce register pressure. 380c87b03e5Sespie(define_insn_reservation "Y0" 2 381c87b03e5Sespie (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl") 382c87b03e5Sespie (eq_attr "cpu" "7100LC,7200,7300")) 383c87b03e5Sespie "f_7100lc,fpmac_7100lc") 384c87b03e5Sespie 385c87b03e5Sespie;; fp division and sqrt instructions lock the entire CPU for 386c87b03e5Sespie;; 7 cycles (single precision) or 14 cycles (double precision). 387c87b03e5Sespie;; There is no way to avoid this lock and trying to schedule 388c87b03e5Sespie;; around the lock is pointless and thus there is no value in 389c87b03e5Sespie;; trying to model this lock. Not modeling the lock allows 390c87b03e5Sespie;; for a smaller DFA and may reduce register pressure. 391c87b03e5Sespie(define_insn_reservation "Y1" 1 392c87b03e5Sespie (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl") 393c87b03e5Sespie (eq_attr "cpu" "7100LC,7200,7300")) 394c87b03e5Sespie "f_7100lc") 395c87b03e5Sespie 396c87b03e5Sespie(define_insn_reservation "Y2" 2 397c87b03e5Sespie (and (eq_attr "type" "load") 398c87b03e5Sespie (eq_attr "cpu" "7100LC,7200,7300")) 399c87b03e5Sespie "i1_7100lc+mem_7100lc") 400c87b03e5Sespie 401c87b03e5Sespie(define_insn_reservation "Y3" 2 402c87b03e5Sespie (and (eq_attr "type" "fpload") 403c87b03e5Sespie (eq_attr "cpu" "7100LC,7200,7300")) 404c87b03e5Sespie "i1_7100lc+mem_7100lc") 405c87b03e5Sespie 406c87b03e5Sespie(define_insn_reservation "Y4" 2 407c87b03e5Sespie (and (eq_attr "type" "store") 408c87b03e5Sespie (eq_attr "cpu" "7100LC")) 409c87b03e5Sespie "i1_7100lc+mem_7100lc,mem_7100lc") 410c87b03e5Sespie 411c87b03e5Sespie(define_insn_reservation "Y5" 2 412c87b03e5Sespie (and (eq_attr "type" "fpstore") 413c87b03e5Sespie (eq_attr "cpu" "7100LC")) 414c87b03e5Sespie "i1_7100lc+mem_7100lc,mem_7100lc") 415c87b03e5Sespie 416c87b03e5Sespie(define_insn_reservation "Y6" 1 417c87b03e5Sespie (and (eq_attr "type" "shift,nullshift") 418c87b03e5Sespie (eq_attr "cpu" "7100LC,7200,7300")) 419c87b03e5Sespie "i1_7100lc") 420c87b03e5Sespie 421c87b03e5Sespie(define_insn_reservation "Y7" 1 422c87b03e5Sespie (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift") 423c87b03e5Sespie (eq_attr "cpu" "7100LC,7200,7300")) 424c87b03e5Sespie "(i0_7100lc|i1_7100lc)") 425c87b03e5Sespie 426c87b03e5Sespie;; The 7200 has a store-load penalty 427c87b03e5Sespie(define_insn_reservation "Y8" 2 428c87b03e5Sespie (and (eq_attr "type" "store") 429c87b03e5Sespie (eq_attr "cpu" "7200")) 430c87b03e5Sespie "i1_7100lc,mem_7100lc") 431c87b03e5Sespie 432c87b03e5Sespie(define_insn_reservation "Y9" 2 433c87b03e5Sespie (and (eq_attr "type" "fpstore") 434c87b03e5Sespie (eq_attr "cpu" "7200")) 435c87b03e5Sespie "i1_7100lc,mem_7100lc") 436c87b03e5Sespie 437c87b03e5Sespie;; The 7300 has no penalty for store-store or store-load 438c87b03e5Sespie(define_insn_reservation "Y10" 2 439c87b03e5Sespie (and (eq_attr "type" "store") 440c87b03e5Sespie (eq_attr "cpu" "7300")) 441c87b03e5Sespie "i1_7100lc") 442c87b03e5Sespie 443c87b03e5Sespie(define_insn_reservation "Y11" 2 444c87b03e5Sespie (and (eq_attr "type" "fpstore") 445c87b03e5Sespie (eq_attr "cpu" "7300")) 446c87b03e5Sespie "i1_7100lc") 447c87b03e5Sespie 448c87b03e5Sespie;; We have an "anti-bypass" for FP loads which feed an FP store. 449c87b03e5Sespie(define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p") 450c87b03e5Sespie 451c87b03e5Sespie;; Scheduling for the PA8000 is somewhat different than scheduling for a 452c87b03e5Sespie;; traditional architecture. 453c87b03e5Sespie;; 454c87b03e5Sespie;; The PA8000 has a large (56) entry reorder buffer that is split between 455c87b03e5Sespie;; memory and non-memory operations. 456c87b03e5Sespie;; 457c87b03e5Sespie;; The PA8000 can issue two memory and two non-memory operations per cycle to 458c87b03e5Sespie;; the function units, with the exception of branches and multi-output 459c87b03e5Sespie;; instructions. The PA8000 can retire two non-memory operations per cycle 460c87b03e5Sespie;; and two memory operations per cycle, only one of which may be a store. 461c87b03e5Sespie;; 462c87b03e5Sespie;; Given the large reorder buffer, the processor can hide most latencies. 463c87b03e5Sespie;; According to HP, they've got the best results by scheduling for retirement 464c87b03e5Sespie;; bandwidth with limited latency scheduling for floating point operations. 465c87b03e5Sespie;; Latency for integer operations and memory references is ignored. 466c87b03e5Sespie;; 467c87b03e5Sespie;; 468c87b03e5Sespie;; We claim floating point operations have a 2 cycle latency and are 469c87b03e5Sespie;; fully pipelined, except for div and sqrt which are not pipelined and 470c87b03e5Sespie;; take from 17 to 31 cycles to complete. 471c87b03e5Sespie;; 472c87b03e5Sespie;; It's worth noting that there is no way to saturate all the functional 473c87b03e5Sespie;; units on the PA8000 as there is not enough issue bandwidth. 474c87b03e5Sespie 475c87b03e5Sespie(define_automaton "pa8000") 476c87b03e5Sespie(define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000") 477c87b03e5Sespie(define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000") 478c87b03e5Sespie(define_cpu_unit "store_8000" "pa8000") 479c87b03e5Sespie(define_cpu_unit "f0_8000, f1_8000" "pa8000") 480c87b03e5Sespie(define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000") 481c87b03e5Sespie(define_reservation "inm_8000" "inm0_8000 | inm1_8000") 482c87b03e5Sespie(define_reservation "im_8000" "im0_8000 | im1_8000") 483c87b03e5Sespie(define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000") 484c87b03e5Sespie(define_reservation "rm_8000" "rm0_8000 | rm1_8000") 485c87b03e5Sespie(define_reservation "f_8000" "f0_8000 | f1_8000") 486c87b03e5Sespie(define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000") 487c87b03e5Sespie 488c87b03e5Sespie;; We can issue any two memops per cycle, but we can only retire 489c87b03e5Sespie;; one memory store per cycle. We assume that the reorder buffer 490c87b03e5Sespie;; will hide any memory latencies per HP's recommendation. 491c87b03e5Sespie(define_insn_reservation "Z0" 0 492c87b03e5Sespie (and 493c87b03e5Sespie (eq_attr "type" "load,fpload") 494c87b03e5Sespie (eq_attr "cpu" "8000")) 495c87b03e5Sespie "im_8000,rm_8000") 496c87b03e5Sespie 497c87b03e5Sespie(define_insn_reservation "Z1" 0 498c87b03e5Sespie (and 499c87b03e5Sespie (eq_attr "type" "store,fpstore") 500c87b03e5Sespie (eq_attr "cpu" "8000")) 501c87b03e5Sespie "im_8000,rm_8000+store_8000") 502c87b03e5Sespie 503c87b03e5Sespie;; We can issue and retire two non-memory operations per cycle with 504c87b03e5Sespie;; a few exceptions (branches). This group catches those we want 505c87b03e5Sespie;; to assume have zero latency. 506c87b03e5Sespie(define_insn_reservation "Z2" 0 507c87b03e5Sespie (and 508c87b03e5Sespie (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl") 509c87b03e5Sespie (eq_attr "cpu" "8000")) 510c87b03e5Sespie "inm_8000,rnm_8000") 511c87b03e5Sespie 512c87b03e5Sespie;; Branches use both slots in the non-memory issue and 513c87b03e5Sespie;; retirement unit. 514c87b03e5Sespie(define_insn_reservation "Z3" 0 515c87b03e5Sespie (and 516c87b03e5Sespie (eq_attr "type" "uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch") 517c87b03e5Sespie (eq_attr "cpu" "8000")) 518c87b03e5Sespie "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000") 519c87b03e5Sespie 520c87b03e5Sespie;; We partial latency schedule the floating point units. 521c87b03e5Sespie;; They can issue/retire two at a time in the non-memory 522c87b03e5Sespie;; units. We fix their latency at 2 cycles and they 523c87b03e5Sespie;; are fully pipelined. 524c87b03e5Sespie(define_insn_reservation "Z4" 1 525c87b03e5Sespie (and 526c87b03e5Sespie (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl") 527c87b03e5Sespie (eq_attr "cpu" "8000")) 528c87b03e5Sespie "inm_8000,f_8000,rnm_8000") 529c87b03e5Sespie 530c87b03e5Sespie;; The fdivsqrt units are not pipelined and have a very long latency. 531c87b03e5Sespie;; To keep the DFA from exploding, we do not show all the 532c87b03e5Sespie;; reservations for the divsqrt unit. 533c87b03e5Sespie(define_insn_reservation "Z5" 17 534c87b03e5Sespie (and 535c87b03e5Sespie (eq_attr "type" "fpdivsgl,fpsqrtsgl") 536c87b03e5Sespie (eq_attr "cpu" "8000")) 537c87b03e5Sespie "inm_8000,fdivsqrt_8000*6,rnm_8000") 538c87b03e5Sespie 539c87b03e5Sespie(define_insn_reservation "Z6" 31 540c87b03e5Sespie (and 541c87b03e5Sespie (eq_attr "type" "fpdivdbl,fpsqrtdbl") 542c87b03e5Sespie (eq_attr "cpu" "8000")) 543c87b03e5Sespie "inm_8000,fdivsqrt_8000*6,rnm_8000") 544c87b03e5Sespie 545c87b03e5Sespie 546c87b03e5Sespie 547c87b03e5Sespie;; Compare instructions. 548c87b03e5Sespie;; This controls RTL generation and register allocation. 549c87b03e5Sespie 550c87b03e5Sespie;; We generate RTL for comparisons and branches by having the cmpxx 551c87b03e5Sespie;; patterns store away the operands. Then, the scc and bcc patterns 552c87b03e5Sespie;; emit RTL for both the compare and the branch. 553c87b03e5Sespie;; 554c87b03e5Sespie 555c87b03e5Sespie(define_expand "cmpdi" 556c87b03e5Sespie [(set (reg:CC 0) 557c87b03e5Sespie (compare:CC (match_operand:DI 0 "reg_or_0_operand" "") 558c87b03e5Sespie (match_operand:DI 1 "register_operand" "")))] 559c87b03e5Sespie "TARGET_64BIT" 560c87b03e5Sespie 561c87b03e5Sespie " 562c87b03e5Sespie{ 563c87b03e5Sespie hppa_compare_op0 = operands[0]; 564c87b03e5Sespie hppa_compare_op1 = operands[1]; 565c87b03e5Sespie hppa_branch_type = CMP_SI; 566c87b03e5Sespie DONE; 567c87b03e5Sespie}") 568c87b03e5Sespie 569c87b03e5Sespie(define_expand "cmpsi" 570c87b03e5Sespie [(set (reg:CC 0) 571c87b03e5Sespie (compare:CC (match_operand:SI 0 "reg_or_0_operand" "") 572c87b03e5Sespie (match_operand:SI 1 "arith5_operand" "")))] 573c87b03e5Sespie "" 574c87b03e5Sespie " 575c87b03e5Sespie{ 576c87b03e5Sespie hppa_compare_op0 = operands[0]; 577c87b03e5Sespie hppa_compare_op1 = operands[1]; 578c87b03e5Sespie hppa_branch_type = CMP_SI; 579c87b03e5Sespie DONE; 580c87b03e5Sespie}") 581c87b03e5Sespie 582c87b03e5Sespie(define_expand "cmpsf" 583c87b03e5Sespie [(set (reg:CCFP 0) 584c87b03e5Sespie (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "") 585c87b03e5Sespie (match_operand:SF 1 "reg_or_0_operand" "")))] 586c87b03e5Sespie "! TARGET_SOFT_FLOAT" 587c87b03e5Sespie " 588c87b03e5Sespie{ 589c87b03e5Sespie hppa_compare_op0 = operands[0]; 590c87b03e5Sespie hppa_compare_op1 = operands[1]; 591c87b03e5Sespie hppa_branch_type = CMP_SF; 592c87b03e5Sespie DONE; 593c87b03e5Sespie}") 594c87b03e5Sespie 595c87b03e5Sespie(define_expand "cmpdf" 596c87b03e5Sespie [(set (reg:CCFP 0) 597c87b03e5Sespie (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "") 598c87b03e5Sespie (match_operand:DF 1 "reg_or_0_operand" "")))] 599c87b03e5Sespie "! TARGET_SOFT_FLOAT" 600c87b03e5Sespie " 601c87b03e5Sespie{ 602c87b03e5Sespie hppa_compare_op0 = operands[0]; 603c87b03e5Sespie hppa_compare_op1 = operands[1]; 604c87b03e5Sespie hppa_branch_type = CMP_DF; 605c87b03e5Sespie DONE; 606c87b03e5Sespie}") 607c87b03e5Sespie 608c87b03e5Sespie(define_insn "" 609c87b03e5Sespie [(set (reg:CCFP 0) 610c87b03e5Sespie (match_operator:CCFP 2 "comparison_operator" 611c87b03e5Sespie [(match_operand:SF 0 "reg_or_0_operand" "fG") 612c87b03e5Sespie (match_operand:SF 1 "reg_or_0_operand" "fG")]))] 613c87b03e5Sespie "! TARGET_SOFT_FLOAT" 614c87b03e5Sespie "fcmp,sgl,%Y2 %f0,%f1" 615c87b03e5Sespie [(set_attr "length" "4") 616c87b03e5Sespie (set_attr "type" "fpcc")]) 617c87b03e5Sespie 618c87b03e5Sespie(define_insn "" 619c87b03e5Sespie [(set (reg:CCFP 0) 620c87b03e5Sespie (match_operator:CCFP 2 "comparison_operator" 621c87b03e5Sespie [(match_operand:DF 0 "reg_or_0_operand" "fG") 622c87b03e5Sespie (match_operand:DF 1 "reg_or_0_operand" "fG")]))] 623c87b03e5Sespie "! TARGET_SOFT_FLOAT" 624c87b03e5Sespie "fcmp,dbl,%Y2 %f0,%f1" 625c87b03e5Sespie [(set_attr "length" "4") 626c87b03e5Sespie (set_attr "type" "fpcc")]) 627c87b03e5Sespie 628c87b03e5Sespie;; Provide a means to emit the movccfp0 and movccfp1 optimization 629c87b03e5Sespie;; placeholders. This is necessary in rare situations when a 630c87b03e5Sespie;; placeholder is re-emitted (see PR 8705). 631c87b03e5Sespie 632c87b03e5Sespie(define_expand "movccfp" 633c87b03e5Sespie [(set (reg:CCFP 0) 634c87b03e5Sespie (match_operand 0 "const_int_operand" ""))] 635c87b03e5Sespie "! TARGET_SOFT_FLOAT" 636c87b03e5Sespie " 637c87b03e5Sespie{ 638c87b03e5Sespie if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1) 639c87b03e5Sespie FAIL; 640c87b03e5Sespie}") 641c87b03e5Sespie 642c87b03e5Sespie;; The following patterns are optimization placeholders. In almost 643c87b03e5Sespie;; all cases, the user of the condition code will be simplified and the 644c87b03e5Sespie;; original condition code setting insn should be eliminated. 645c87b03e5Sespie 646c87b03e5Sespie(define_insn "*movccfp0" 647c87b03e5Sespie [(set (reg:CCFP 0) 648c87b03e5Sespie (const_int 0))] 649c87b03e5Sespie "! TARGET_SOFT_FLOAT" 650c87b03e5Sespie "fcmp,dbl,= %%fr0,%%fr0" 651c87b03e5Sespie [(set_attr "length" "4") 652c87b03e5Sespie (set_attr "type" "fpcc")]) 653c87b03e5Sespie 654c87b03e5Sespie(define_insn "*movccfp1" 655c87b03e5Sespie [(set (reg:CCFP 0) 656c87b03e5Sespie (const_int 1))] 657c87b03e5Sespie "! TARGET_SOFT_FLOAT" 658c87b03e5Sespie "fcmp,dbl,!= %%fr0,%%fr0" 659c87b03e5Sespie [(set_attr "length" "4") 660c87b03e5Sespie (set_attr "type" "fpcc")]) 661c87b03e5Sespie 662c87b03e5Sespie;; scc insns. 663c87b03e5Sespie 664c87b03e5Sespie(define_expand "seq" 665c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 666c87b03e5Sespie (eq:SI (match_dup 1) 667c87b03e5Sespie (match_dup 2)))] 668c87b03e5Sespie "!TARGET_64BIT" 669c87b03e5Sespie " 670c87b03e5Sespie{ 671c87b03e5Sespie /* fp scc patterns rarely match, and are not a win on the PA. */ 672c87b03e5Sespie if (hppa_branch_type != CMP_SI) 673c87b03e5Sespie FAIL; 674c87b03e5Sespie /* set up operands from compare. */ 675c87b03e5Sespie operands[1] = hppa_compare_op0; 676c87b03e5Sespie operands[2] = hppa_compare_op1; 677c87b03e5Sespie /* fall through and generate default code */ 678c87b03e5Sespie}") 679c87b03e5Sespie 680c87b03e5Sespie(define_expand "sne" 681c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 682c87b03e5Sespie (ne:SI (match_dup 1) 683c87b03e5Sespie (match_dup 2)))] 684c87b03e5Sespie "!TARGET_64BIT" 685c87b03e5Sespie " 686c87b03e5Sespie{ 687c87b03e5Sespie /* fp scc patterns rarely match, and are not a win on the PA. */ 688c87b03e5Sespie if (hppa_branch_type != CMP_SI) 689c87b03e5Sespie FAIL; 690c87b03e5Sespie operands[1] = hppa_compare_op0; 691c87b03e5Sespie operands[2] = hppa_compare_op1; 692c87b03e5Sespie}") 693c87b03e5Sespie 694c87b03e5Sespie(define_expand "slt" 695c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 696c87b03e5Sespie (lt:SI (match_dup 1) 697c87b03e5Sespie (match_dup 2)))] 698c87b03e5Sespie "!TARGET_64BIT" 699c87b03e5Sespie " 700c87b03e5Sespie{ 701c87b03e5Sespie /* fp scc patterns rarely match, and are not a win on the PA. */ 702c87b03e5Sespie if (hppa_branch_type != CMP_SI) 703c87b03e5Sespie FAIL; 704c87b03e5Sespie operands[1] = hppa_compare_op0; 705c87b03e5Sespie operands[2] = hppa_compare_op1; 706c87b03e5Sespie}") 707c87b03e5Sespie 708c87b03e5Sespie(define_expand "sgt" 709c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 710c87b03e5Sespie (gt:SI (match_dup 1) 711c87b03e5Sespie (match_dup 2)))] 712c87b03e5Sespie "!TARGET_64BIT" 713c87b03e5Sespie " 714c87b03e5Sespie{ 715c87b03e5Sespie /* fp scc patterns rarely match, and are not a win on the PA. */ 716c87b03e5Sespie if (hppa_branch_type != CMP_SI) 717c87b03e5Sespie FAIL; 718c87b03e5Sespie operands[1] = hppa_compare_op0; 719c87b03e5Sespie operands[2] = hppa_compare_op1; 720c87b03e5Sespie}") 721c87b03e5Sespie 722c87b03e5Sespie(define_expand "sle" 723c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 724c87b03e5Sespie (le:SI (match_dup 1) 725c87b03e5Sespie (match_dup 2)))] 726c87b03e5Sespie "!TARGET_64BIT" 727c87b03e5Sespie " 728c87b03e5Sespie{ 729c87b03e5Sespie /* fp scc patterns rarely match, and are not a win on the PA. */ 730c87b03e5Sespie if (hppa_branch_type != CMP_SI) 731c87b03e5Sespie FAIL; 732c87b03e5Sespie operands[1] = hppa_compare_op0; 733c87b03e5Sespie operands[2] = hppa_compare_op1; 734c87b03e5Sespie}") 735c87b03e5Sespie 736c87b03e5Sespie(define_expand "sge" 737c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 738c87b03e5Sespie (ge:SI (match_dup 1) 739c87b03e5Sespie (match_dup 2)))] 740c87b03e5Sespie "!TARGET_64BIT" 741c87b03e5Sespie " 742c87b03e5Sespie{ 743c87b03e5Sespie /* fp scc patterns rarely match, and are not a win on the PA. */ 744c87b03e5Sespie if (hppa_branch_type != CMP_SI) 745c87b03e5Sespie FAIL; 746c87b03e5Sespie operands[1] = hppa_compare_op0; 747c87b03e5Sespie operands[2] = hppa_compare_op1; 748c87b03e5Sespie}") 749c87b03e5Sespie 750c87b03e5Sespie(define_expand "sltu" 751c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 752c87b03e5Sespie (ltu:SI (match_dup 1) 753c87b03e5Sespie (match_dup 2)))] 754c87b03e5Sespie "!TARGET_64BIT" 755c87b03e5Sespie " 756c87b03e5Sespie{ 757c87b03e5Sespie if (hppa_branch_type != CMP_SI) 758c87b03e5Sespie FAIL; 759c87b03e5Sespie operands[1] = hppa_compare_op0; 760c87b03e5Sespie operands[2] = hppa_compare_op1; 761c87b03e5Sespie}") 762c87b03e5Sespie 763c87b03e5Sespie(define_expand "sgtu" 764c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 765c87b03e5Sespie (gtu:SI (match_dup 1) 766c87b03e5Sespie (match_dup 2)))] 767c87b03e5Sespie "!TARGET_64BIT" 768c87b03e5Sespie " 769c87b03e5Sespie{ 770c87b03e5Sespie if (hppa_branch_type != CMP_SI) 771c87b03e5Sespie FAIL; 772c87b03e5Sespie operands[1] = hppa_compare_op0; 773c87b03e5Sespie operands[2] = hppa_compare_op1; 774c87b03e5Sespie}") 775c87b03e5Sespie 776c87b03e5Sespie(define_expand "sleu" 777c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 778c87b03e5Sespie (leu:SI (match_dup 1) 779c87b03e5Sespie (match_dup 2)))] 780c87b03e5Sespie "!TARGET_64BIT" 781c87b03e5Sespie " 782c87b03e5Sespie{ 783c87b03e5Sespie if (hppa_branch_type != CMP_SI) 784c87b03e5Sespie FAIL; 785c87b03e5Sespie operands[1] = hppa_compare_op0; 786c87b03e5Sespie operands[2] = hppa_compare_op1; 787c87b03e5Sespie}") 788c87b03e5Sespie 789c87b03e5Sespie(define_expand "sgeu" 790c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 791c87b03e5Sespie (geu:SI (match_dup 1) 792c87b03e5Sespie (match_dup 2)))] 793c87b03e5Sespie "!TARGET_64BIT" 794c87b03e5Sespie " 795c87b03e5Sespie{ 796c87b03e5Sespie if (hppa_branch_type != CMP_SI) 797c87b03e5Sespie FAIL; 798c87b03e5Sespie operands[1] = hppa_compare_op0; 799c87b03e5Sespie operands[2] = hppa_compare_op1; 800c87b03e5Sespie}") 801c87b03e5Sespie 802c87b03e5Sespie;; Instruction canonicalization puts immediate operands second, which 803c87b03e5Sespie;; is the reverse of what we want. 804c87b03e5Sespie 805c87b03e5Sespie(define_insn "scc" 806c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 807c87b03e5Sespie (match_operator:SI 3 "comparison_operator" 808c87b03e5Sespie [(match_operand:SI 1 "register_operand" "r") 809c87b03e5Sespie (match_operand:SI 2 "arith11_operand" "rI")]))] 810c87b03e5Sespie "" 811c87b03e5Sespie "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0" 812c87b03e5Sespie [(set_attr "type" "binary") 813c87b03e5Sespie (set_attr "length" "8")]) 814c87b03e5Sespie 815c87b03e5Sespie(define_insn "" 816c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 817c87b03e5Sespie (match_operator:DI 3 "comparison_operator" 818c87b03e5Sespie [(match_operand:DI 1 "register_operand" "r") 819c87b03e5Sespie (match_operand:DI 2 "arith11_operand" "rI")]))] 820c87b03e5Sespie "TARGET_64BIT" 821c87b03e5Sespie "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0" 822c87b03e5Sespie [(set_attr "type" "binary") 823c87b03e5Sespie (set_attr "length" "8")]) 824c87b03e5Sespie 825c87b03e5Sespie(define_insn "iorscc" 826c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 827c87b03e5Sespie (ior:SI (match_operator:SI 3 "comparison_operator" 828c87b03e5Sespie [(match_operand:SI 1 "register_operand" "r") 829c87b03e5Sespie (match_operand:SI 2 "arith11_operand" "rI")]) 830c87b03e5Sespie (match_operator:SI 6 "comparison_operator" 831c87b03e5Sespie [(match_operand:SI 4 "register_operand" "r") 832c87b03e5Sespie (match_operand:SI 5 "arith11_operand" "rI")])))] 833c87b03e5Sespie "" 834c87b03e5Sespie "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0" 835c87b03e5Sespie [(set_attr "type" "binary") 836c87b03e5Sespie (set_attr "length" "12")]) 837c87b03e5Sespie 838c87b03e5Sespie(define_insn "" 839c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 840c87b03e5Sespie (ior:DI (match_operator:DI 3 "comparison_operator" 841c87b03e5Sespie [(match_operand:DI 1 "register_operand" "r") 842c87b03e5Sespie (match_operand:DI 2 "arith11_operand" "rI")]) 843c87b03e5Sespie (match_operator:DI 6 "comparison_operator" 844c87b03e5Sespie [(match_operand:DI 4 "register_operand" "r") 845c87b03e5Sespie (match_operand:DI 5 "arith11_operand" "rI")])))] 846c87b03e5Sespie "TARGET_64BIT" 847c87b03e5Sespie "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0" 848c87b03e5Sespie [(set_attr "type" "binary") 849c87b03e5Sespie (set_attr "length" "12")]) 850c87b03e5Sespie 851c87b03e5Sespie;; Combiner patterns for common operations performed with the output 852c87b03e5Sespie;; from an scc insn (negscc and incscc). 853c87b03e5Sespie(define_insn "negscc" 854c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 855c87b03e5Sespie (neg:SI (match_operator:SI 3 "comparison_operator" 856c87b03e5Sespie [(match_operand:SI 1 "register_operand" "r") 857c87b03e5Sespie (match_operand:SI 2 "arith11_operand" "rI")])))] 858c87b03e5Sespie "" 859c87b03e5Sespie "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0" 860c87b03e5Sespie [(set_attr "type" "binary") 861c87b03e5Sespie (set_attr "length" "8")]) 862c87b03e5Sespie 863c87b03e5Sespie(define_insn "" 864c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 865c87b03e5Sespie (neg:DI (match_operator:DI 3 "comparison_operator" 866c87b03e5Sespie [(match_operand:DI 1 "register_operand" "r") 867c87b03e5Sespie (match_operand:DI 2 "arith11_operand" "rI")])))] 868c87b03e5Sespie "TARGET_64BIT" 869c87b03e5Sespie "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0" 870c87b03e5Sespie [(set_attr "type" "binary") 871c87b03e5Sespie (set_attr "length" "8")]) 872c87b03e5Sespie 873c87b03e5Sespie;; Patterns for adding/subtracting the result of a boolean expression from 874c87b03e5Sespie;; a register. First we have special patterns that make use of the carry 875c87b03e5Sespie;; bit, and output only two instructions. For the cases we can't in 876c87b03e5Sespie;; general do in two instructions, the incscc pattern at the end outputs 877c87b03e5Sespie;; two or three instructions. 878c87b03e5Sespie 879c87b03e5Sespie(define_insn "" 880c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 881c87b03e5Sespie (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r") 882c87b03e5Sespie (match_operand:SI 3 "arith11_operand" "rI")) 883c87b03e5Sespie (match_operand:SI 1 "register_operand" "r")))] 884c87b03e5Sespie "" 885c87b03e5Sespie "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0" 886c87b03e5Sespie [(set_attr "type" "binary") 887c87b03e5Sespie (set_attr "length" "8")]) 888c87b03e5Sespie 889c87b03e5Sespie(define_insn "" 890c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 891c87b03e5Sespie (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r") 892c87b03e5Sespie (match_operand:DI 3 "arith11_operand" "rI")) 893c87b03e5Sespie (match_operand:DI 1 "register_operand" "r")))] 894c87b03e5Sespie "TARGET_64BIT" 895c87b03e5Sespie "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0" 896c87b03e5Sespie [(set_attr "type" "binary") 897c87b03e5Sespie (set_attr "length" "8")]) 898c87b03e5Sespie 899c87b03e5Sespie; This need only accept registers for op3, since canonicalization 900c87b03e5Sespie; replaces geu with gtu when op3 is an integer. 901c87b03e5Sespie(define_insn "" 902c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 903c87b03e5Sespie (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r") 904c87b03e5Sespie (match_operand:SI 3 "register_operand" "r")) 905c87b03e5Sespie (match_operand:SI 1 "register_operand" "r")))] 906c87b03e5Sespie "" 907c87b03e5Sespie "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0" 908c87b03e5Sespie [(set_attr "type" "binary") 909c87b03e5Sespie (set_attr "length" "8")]) 910c87b03e5Sespie 911c87b03e5Sespie(define_insn "" 912c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 913c87b03e5Sespie (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r") 914c87b03e5Sespie (match_operand:DI 3 "register_operand" "r")) 915c87b03e5Sespie (match_operand:DI 1 "register_operand" "r")))] 916c87b03e5Sespie "TARGET_64BIT" 917c87b03e5Sespie "sub %2,%3,%%r0\;add,dc %%r0,%1,%0" 918c87b03e5Sespie [(set_attr "type" "binary") 919c87b03e5Sespie (set_attr "length" "8")]) 920c87b03e5Sespie 921c87b03e5Sespie; Match only integers for op3 here. This is used as canonical form of the 922c87b03e5Sespie; geu pattern when op3 is an integer. Don't match registers since we can't 923c87b03e5Sespie; make better code than the general incscc pattern. 924c87b03e5Sespie(define_insn "" 925c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 926c87b03e5Sespie (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r") 927c87b03e5Sespie (match_operand:SI 3 "int11_operand" "I")) 928c87b03e5Sespie (match_operand:SI 1 "register_operand" "r")))] 929c87b03e5Sespie "" 930c87b03e5Sespie "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0" 931c87b03e5Sespie [(set_attr "type" "binary") 932c87b03e5Sespie (set_attr "length" "8")]) 933c87b03e5Sespie 934c87b03e5Sespie(define_insn "" 935c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 936c87b03e5Sespie (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r") 937c87b03e5Sespie (match_operand:DI 3 "int11_operand" "I")) 938c87b03e5Sespie (match_operand:DI 1 "register_operand" "r")))] 939c87b03e5Sespie "TARGET_64BIT" 940c87b03e5Sespie "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0" 941c87b03e5Sespie [(set_attr "type" "binary") 942c87b03e5Sespie (set_attr "length" "8")]) 943c87b03e5Sespie 944c87b03e5Sespie(define_insn "incscc" 945c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 946c87b03e5Sespie (plus:SI (match_operator:SI 4 "comparison_operator" 947c87b03e5Sespie [(match_operand:SI 2 "register_operand" "r,r") 948c87b03e5Sespie (match_operand:SI 3 "arith11_operand" "rI,rI")]) 949c87b03e5Sespie (match_operand:SI 1 "register_operand" "0,?r")))] 950c87b03e5Sespie "" 951c87b03e5Sespie "@ 952c87b03e5Sespie {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0 953c87b03e5Sespie {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0" 954c87b03e5Sespie [(set_attr "type" "binary,binary") 955c87b03e5Sespie (set_attr "length" "8,12")]) 956c87b03e5Sespie 957c87b03e5Sespie(define_insn "" 958c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r") 959c87b03e5Sespie (plus:DI (match_operator:DI 4 "comparison_operator" 960c87b03e5Sespie [(match_operand:DI 2 "register_operand" "r,r") 961c87b03e5Sespie (match_operand:DI 3 "arith11_operand" "rI,rI")]) 962c87b03e5Sespie (match_operand:DI 1 "register_operand" "0,?r")))] 963c87b03e5Sespie "TARGET_64BIT" 964c87b03e5Sespie "@ 965c87b03e5Sespie cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0 966c87b03e5Sespie cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0" 967c87b03e5Sespie [(set_attr "type" "binary,binary") 968c87b03e5Sespie (set_attr "length" "8,12")]) 969c87b03e5Sespie 970c87b03e5Sespie(define_insn "" 971c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 972c87b03e5Sespie (minus:SI (match_operand:SI 1 "register_operand" "r") 973c87b03e5Sespie (gtu:SI (match_operand:SI 2 "register_operand" "r") 974c87b03e5Sespie (match_operand:SI 3 "arith11_operand" "rI"))))] 975c87b03e5Sespie "" 976c87b03e5Sespie "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0" 977c87b03e5Sespie [(set_attr "type" "binary") 978c87b03e5Sespie (set_attr "length" "8")]) 979c87b03e5Sespie 980c87b03e5Sespie(define_insn "" 981c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 982c87b03e5Sespie (minus:DI (match_operand:DI 1 "register_operand" "r") 983c87b03e5Sespie (gtu:DI (match_operand:DI 2 "register_operand" "r") 984c87b03e5Sespie (match_operand:DI 3 "arith11_operand" "rI"))))] 985c87b03e5Sespie "TARGET_64BIT" 986c87b03e5Sespie "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0" 987c87b03e5Sespie [(set_attr "type" "binary") 988c87b03e5Sespie (set_attr "length" "8")]) 989c87b03e5Sespie 990c87b03e5Sespie(define_insn "" 991c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 992c87b03e5Sespie (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r") 993c87b03e5Sespie (gtu:SI (match_operand:SI 2 "register_operand" "r") 994c87b03e5Sespie (match_operand:SI 3 "arith11_operand" "rI"))) 995c87b03e5Sespie (match_operand:SI 4 "register_operand" "r")))] 996c87b03e5Sespie "" 997c87b03e5Sespie "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0" 998c87b03e5Sespie [(set_attr "type" "binary") 999c87b03e5Sespie (set_attr "length" "8")]) 1000c87b03e5Sespie 1001c87b03e5Sespie(define_insn "" 1002c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 1003c87b03e5Sespie (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r") 1004c87b03e5Sespie (gtu:DI (match_operand:DI 2 "register_operand" "r") 1005c87b03e5Sespie (match_operand:DI 3 "arith11_operand" "rI"))) 1006c87b03e5Sespie (match_operand:DI 4 "register_operand" "r")))] 1007c87b03e5Sespie "TARGET_64BIT" 1008c87b03e5Sespie "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0" 1009c87b03e5Sespie [(set_attr "type" "binary") 1010c87b03e5Sespie (set_attr "length" "8")]) 1011c87b03e5Sespie 1012c87b03e5Sespie; This need only accept registers for op3, since canonicalization 1013c87b03e5Sespie; replaces ltu with leu when op3 is an integer. 1014c87b03e5Sespie(define_insn "" 1015c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 1016c87b03e5Sespie (minus:SI (match_operand:SI 1 "register_operand" "r") 1017c87b03e5Sespie (ltu:SI (match_operand:SI 2 "register_operand" "r") 1018c87b03e5Sespie (match_operand:SI 3 "register_operand" "r"))))] 1019c87b03e5Sespie "" 1020c87b03e5Sespie "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0" 1021c87b03e5Sespie [(set_attr "type" "binary") 1022c87b03e5Sespie (set_attr "length" "8")]) 1023c87b03e5Sespie 1024c87b03e5Sespie(define_insn "" 1025c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 1026c87b03e5Sespie (minus:DI (match_operand:DI 1 "register_operand" "r") 1027c87b03e5Sespie (ltu:DI (match_operand:DI 2 "register_operand" "r") 1028c87b03e5Sespie (match_operand:DI 3 "register_operand" "r"))))] 1029c87b03e5Sespie "TARGET_64BIT" 1030c87b03e5Sespie "sub %2,%3,%%r0\;sub,db %1,%%r0,%0" 1031c87b03e5Sespie [(set_attr "type" "binary") 1032c87b03e5Sespie (set_attr "length" "8")]) 1033c87b03e5Sespie 1034c87b03e5Sespie(define_insn "" 1035c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 1036c87b03e5Sespie (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r") 1037c87b03e5Sespie (ltu:SI (match_operand:SI 2 "register_operand" "r") 1038c87b03e5Sespie (match_operand:SI 3 "register_operand" "r"))) 1039c87b03e5Sespie (match_operand:SI 4 "register_operand" "r")))] 1040c87b03e5Sespie "" 1041c87b03e5Sespie "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0" 1042c87b03e5Sespie [(set_attr "type" "binary") 1043c87b03e5Sespie (set_attr "length" "8")]) 1044c87b03e5Sespie 1045c87b03e5Sespie(define_insn "" 1046c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 1047c87b03e5Sespie (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r") 1048c87b03e5Sespie (ltu:DI (match_operand:DI 2 "register_operand" "r") 1049c87b03e5Sespie (match_operand:DI 3 "register_operand" "r"))) 1050c87b03e5Sespie (match_operand:DI 4 "register_operand" "r")))] 1051c87b03e5Sespie "TARGET_64BIT" 1052c87b03e5Sespie "sub %2,%3,%%r0\;sub,db %1,%4,%0" 1053c87b03e5Sespie [(set_attr "type" "binary") 1054c87b03e5Sespie (set_attr "length" "8")]) 1055c87b03e5Sespie 1056c87b03e5Sespie; Match only integers for op3 here. This is used as canonical form of the 1057c87b03e5Sespie; ltu pattern when op3 is an integer. Don't match registers since we can't 1058c87b03e5Sespie; make better code than the general incscc pattern. 1059c87b03e5Sespie(define_insn "" 1060c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 1061c87b03e5Sespie (minus:SI (match_operand:SI 1 "register_operand" "r") 1062c87b03e5Sespie (leu:SI (match_operand:SI 2 "register_operand" "r") 1063c87b03e5Sespie (match_operand:SI 3 "int11_operand" "I"))))] 1064c87b03e5Sespie "" 1065c87b03e5Sespie "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0" 1066c87b03e5Sespie [(set_attr "type" "binary") 1067c87b03e5Sespie (set_attr "length" "8")]) 1068c87b03e5Sespie 1069c87b03e5Sespie(define_insn "" 1070c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 1071c87b03e5Sespie (minus:DI (match_operand:DI 1 "register_operand" "r") 1072c87b03e5Sespie (leu:DI (match_operand:DI 2 "register_operand" "r") 1073c87b03e5Sespie (match_operand:DI 3 "int11_operand" "I"))))] 1074c87b03e5Sespie "TARGET_64BIT" 1075c87b03e5Sespie "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0" 1076c87b03e5Sespie [(set_attr "type" "binary") 1077c87b03e5Sespie (set_attr "length" "8")]) 1078c87b03e5Sespie 1079c87b03e5Sespie(define_insn "" 1080c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 1081c87b03e5Sespie (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r") 1082c87b03e5Sespie (leu:SI (match_operand:SI 2 "register_operand" "r") 1083c87b03e5Sespie (match_operand:SI 3 "int11_operand" "I"))) 1084c87b03e5Sespie (match_operand:SI 4 "register_operand" "r")))] 1085c87b03e5Sespie "" 1086c87b03e5Sespie "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0" 1087c87b03e5Sespie [(set_attr "type" "binary") 1088c87b03e5Sespie (set_attr "length" "8")]) 1089c87b03e5Sespie 1090c87b03e5Sespie(define_insn "" 1091c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 1092c87b03e5Sespie (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r") 1093c87b03e5Sespie (leu:DI (match_operand:DI 2 "register_operand" "r") 1094c87b03e5Sespie (match_operand:DI 3 "int11_operand" "I"))) 1095c87b03e5Sespie (match_operand:DI 4 "register_operand" "r")))] 1096c87b03e5Sespie "TARGET_64BIT" 1097c87b03e5Sespie "addi %k3,%2,%%r0\;sub,db %1,%4,%0" 1098c87b03e5Sespie [(set_attr "type" "binary") 1099c87b03e5Sespie (set_attr "length" "8")]) 1100c87b03e5Sespie 1101c87b03e5Sespie(define_insn "decscc" 1102c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 1103c87b03e5Sespie (minus:SI (match_operand:SI 1 "register_operand" "0,?r") 1104c87b03e5Sespie (match_operator:SI 4 "comparison_operator" 1105c87b03e5Sespie [(match_operand:SI 2 "register_operand" "r,r") 1106c87b03e5Sespie (match_operand:SI 3 "arith11_operand" "rI,rI")])))] 1107c87b03e5Sespie "" 1108c87b03e5Sespie "@ 1109c87b03e5Sespie {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0 1110c87b03e5Sespie {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0" 1111c87b03e5Sespie [(set_attr "type" "binary,binary") 1112c87b03e5Sespie (set_attr "length" "8,12")]) 1113c87b03e5Sespie 1114c87b03e5Sespie(define_insn "" 1115c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r") 1116c87b03e5Sespie (minus:DI (match_operand:DI 1 "register_operand" "0,?r") 1117c87b03e5Sespie (match_operator:DI 4 "comparison_operator" 1118c87b03e5Sespie [(match_operand:DI 2 "register_operand" "r,r") 1119c87b03e5Sespie (match_operand:DI 3 "arith11_operand" "rI,rI")])))] 1120c87b03e5Sespie "TARGET_64BIT" 1121c87b03e5Sespie "@ 1122c87b03e5Sespie cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0 1123c87b03e5Sespie cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0" 1124c87b03e5Sespie [(set_attr "type" "binary,binary") 1125c87b03e5Sespie (set_attr "length" "8,12")]) 1126c87b03e5Sespie 1127c87b03e5Sespie; Patterns for max and min. (There is no need for an earlyclobber in the 1128c87b03e5Sespie; last alternative since the middle alternative will match if op0 == op1.) 1129c87b03e5Sespie 1130c87b03e5Sespie(define_insn "sminsi3" 1131c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1132c87b03e5Sespie (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r") 1133c87b03e5Sespie (match_operand:SI 2 "arith11_operand" "r,I,M")))] 1134c87b03e5Sespie "" 1135c87b03e5Sespie "@ 1136c87b03e5Sespie {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0 1137c87b03e5Sespie {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0 1138c87b03e5Sespie {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0" 1139c87b03e5Sespie[(set_attr "type" "multi,multi,multi") 1140c87b03e5Sespie (set_attr "length" "8,8,8")]) 1141c87b03e5Sespie 1142c87b03e5Sespie(define_insn "smindi3" 1143c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r,r") 1144c87b03e5Sespie (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r") 1145c87b03e5Sespie (match_operand:DI 2 "arith11_operand" "r,I,M")))] 1146c87b03e5Sespie "TARGET_64BIT" 1147c87b03e5Sespie "@ 1148c87b03e5Sespie cmpclr,*> %2,%0,%%r0\;copy %2,%0 1149c87b03e5Sespie cmpiclr,*> %2,%0,%%r0\;ldi %2,%0 1150c87b03e5Sespie cmpclr,*> %1,%r2,%0\;copy %1,%0" 1151c87b03e5Sespie[(set_attr "type" "multi,multi,multi") 1152c87b03e5Sespie (set_attr "length" "8,8,8")]) 1153c87b03e5Sespie 1154c87b03e5Sespie(define_insn "uminsi3" 1155c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 1156c87b03e5Sespie (umin:SI (match_operand:SI 1 "register_operand" "%0,0") 1157c87b03e5Sespie (match_operand:SI 2 "arith11_operand" "r,I")))] 1158c87b03e5Sespie "" 1159c87b03e5Sespie "@ 1160c87b03e5Sespie {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0 1161c87b03e5Sespie {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0" 1162c87b03e5Sespie[(set_attr "type" "multi,multi") 1163c87b03e5Sespie (set_attr "length" "8,8")]) 1164c87b03e5Sespie 1165c87b03e5Sespie(define_insn "umindi3" 1166c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r") 1167c87b03e5Sespie (umin:DI (match_operand:DI 1 "register_operand" "%0,0") 1168c87b03e5Sespie (match_operand:DI 2 "arith11_operand" "r,I")))] 1169c87b03e5Sespie "TARGET_64BIT" 1170c87b03e5Sespie "@ 1171c87b03e5Sespie cmpclr,*>> %2,%0,%%r0\;copy %2,%0 1172c87b03e5Sespie cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0" 1173c87b03e5Sespie[(set_attr "type" "multi,multi") 1174c87b03e5Sespie (set_attr "length" "8,8")]) 1175c87b03e5Sespie 1176c87b03e5Sespie(define_insn "smaxsi3" 1177c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1178c87b03e5Sespie (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r") 1179c87b03e5Sespie (match_operand:SI 2 "arith11_operand" "r,I,M")))] 1180c87b03e5Sespie "" 1181c87b03e5Sespie "@ 1182c87b03e5Sespie {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0 1183c87b03e5Sespie {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0 1184c87b03e5Sespie {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0" 1185c87b03e5Sespie[(set_attr "type" "multi,multi,multi") 1186c87b03e5Sespie (set_attr "length" "8,8,8")]) 1187c87b03e5Sespie 1188c87b03e5Sespie(define_insn "smaxdi3" 1189c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r,r") 1190c87b03e5Sespie (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r") 1191c87b03e5Sespie (match_operand:DI 2 "arith11_operand" "r,I,M")))] 1192c87b03e5Sespie "TARGET_64BIT" 1193c87b03e5Sespie "@ 1194c87b03e5Sespie cmpclr,*< %2,%0,%%r0\;copy %2,%0 1195c87b03e5Sespie cmpiclr,*< %2,%0,%%r0\;ldi %2,%0 1196c87b03e5Sespie cmpclr,*< %1,%r2,%0\;copy %1,%0" 1197c87b03e5Sespie[(set_attr "type" "multi,multi,multi") 1198c87b03e5Sespie (set_attr "length" "8,8,8")]) 1199c87b03e5Sespie 1200c87b03e5Sespie(define_insn "umaxsi3" 1201c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 1202c87b03e5Sespie (umax:SI (match_operand:SI 1 "register_operand" "%0,0") 1203c87b03e5Sespie (match_operand:SI 2 "arith11_operand" "r,I")))] 1204c87b03e5Sespie "" 1205c87b03e5Sespie "@ 1206c87b03e5Sespie {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0 1207c87b03e5Sespie {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0" 1208c87b03e5Sespie[(set_attr "type" "multi,multi") 1209c87b03e5Sespie (set_attr "length" "8,8")]) 1210c87b03e5Sespie 1211c87b03e5Sespie(define_insn "umaxdi3" 1212c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r") 1213c87b03e5Sespie (umax:DI (match_operand:DI 1 "register_operand" "%0,0") 1214c87b03e5Sespie (match_operand:DI 2 "arith11_operand" "r,I")))] 1215c87b03e5Sespie "TARGET_64BIT" 1216c87b03e5Sespie "@ 1217c87b03e5Sespie cmpclr,*<< %2,%0,%%r0\;copy %2,%0 1218c87b03e5Sespie cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0" 1219c87b03e5Sespie[(set_attr "type" "multi,multi") 1220c87b03e5Sespie (set_attr "length" "8,8")]) 1221c87b03e5Sespie 1222c87b03e5Sespie(define_insn "abssi2" 1223c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 1224c87b03e5Sespie (abs:SI (match_operand:SI 1 "register_operand" "r")))] 1225c87b03e5Sespie "" 1226c87b03e5Sespie "or,>= %%r0,%1,%0\;subi 0,%0,%0" 1227c87b03e5Sespie [(set_attr "type" "multi") 1228c87b03e5Sespie (set_attr "length" "8")]) 1229c87b03e5Sespie 1230c87b03e5Sespie(define_insn "absdi2" 1231c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 1232c87b03e5Sespie (abs:DI (match_operand:DI 1 "register_operand" "r")))] 1233c87b03e5Sespie "TARGET_64BIT" 1234c87b03e5Sespie "or,*>= %%r0,%1,%0\;subi 0,%0,%0" 1235c87b03e5Sespie [(set_attr "type" "multi") 1236c87b03e5Sespie (set_attr "length" "8")]) 1237c87b03e5Sespie 1238c87b03e5Sespie;;; Experimental conditional move patterns 1239c87b03e5Sespie 1240c87b03e5Sespie(define_expand "movsicc" 1241c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 1242c87b03e5Sespie (if_then_else:SI 1243c87b03e5Sespie (match_operator 1 "comparison_operator" 1244c87b03e5Sespie [(match_dup 4) 1245c87b03e5Sespie (match_dup 5)]) 1246c87b03e5Sespie (match_operand:SI 2 "reg_or_cint_move_operand" "") 1247c87b03e5Sespie (match_operand:SI 3 "reg_or_cint_move_operand" "")))] 1248c87b03e5Sespie "" 1249c87b03e5Sespie " 1250c87b03e5Sespie{ 1251c87b03e5Sespie enum rtx_code code = GET_CODE (operands[1]); 1252c87b03e5Sespie 1253c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1254c87b03e5Sespie FAIL; 1255c87b03e5Sespie 1256c87b03e5Sespie if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1) 1257c87b03e5Sespie || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0])) 1258c87b03e5Sespie FAIL; 1259c87b03e5Sespie 1260c87b03e5Sespie /* operands[1] is currently the result of compare_from_rtx. We want to 1261c87b03e5Sespie emit a compare of the original operands. */ 1262c87b03e5Sespie operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1); 1263c87b03e5Sespie operands[4] = hppa_compare_op0; 1264c87b03e5Sespie operands[5] = hppa_compare_op1; 1265c87b03e5Sespie}") 1266c87b03e5Sespie 1267c87b03e5Sespie;; We used to accept any register for op1. 1268c87b03e5Sespie;; 1269c87b03e5Sespie;; However, it loses sometimes because the compiler will end up using 1270c87b03e5Sespie;; different registers for op0 and op1 in some critical cases. local-alloc 1271c87b03e5Sespie;; will not tie op0 and op1 because op0 is used in multiple basic blocks. 1272c87b03e5Sespie;; 1273c87b03e5Sespie;; If/when global register allocation supports tying we should allow any 1274c87b03e5Sespie;; register for op1 again. 1275c87b03e5Sespie(define_insn "" 1276c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 1277c87b03e5Sespie (if_then_else:SI 1278c87b03e5Sespie (match_operator 2 "comparison_operator" 1279c87b03e5Sespie [(match_operand:SI 3 "register_operand" "r,r,r,r") 1280c87b03e5Sespie (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")]) 1281c87b03e5Sespie (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K") 1282c87b03e5Sespie (const_int 0)))] 1283c87b03e5Sespie "" 1284c87b03e5Sespie "@ 1285c87b03e5Sespie {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0 1286c87b03e5Sespie {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0 1287c87b03e5Sespie {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0 1288c87b03e5Sespie {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0" 1289c87b03e5Sespie [(set_attr "type" "multi,multi,multi,nullshift") 1290c87b03e5Sespie (set_attr "length" "8,8,8,8")]) 1291c87b03e5Sespie 1292c87b03e5Sespie(define_insn "" 1293c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r") 1294c87b03e5Sespie (if_then_else:SI 1295c87b03e5Sespie (match_operator 5 "comparison_operator" 1296c87b03e5Sespie [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r") 1297c87b03e5Sespie (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")]) 1298c87b03e5Sespie (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K") 1299c87b03e5Sespie (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))] 1300c87b03e5Sespie "" 1301c87b03e5Sespie "@ 1302c87b03e5Sespie {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0 1303c87b03e5Sespie {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0 1304c87b03e5Sespie {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0 1305c87b03e5Sespie {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0 1306c87b03e5Sespie {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0 1307c87b03e5Sespie {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0 1308c87b03e5Sespie {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0 1309c87b03e5Sespie {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0" 1310c87b03e5Sespie [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift") 1311c87b03e5Sespie (set_attr "length" "8,8,8,8,8,8,8,8")]) 1312c87b03e5Sespie 1313c87b03e5Sespie(define_expand "movdicc" 1314c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 1315c87b03e5Sespie (if_then_else:DI 1316c87b03e5Sespie (match_operator 1 "comparison_operator" 1317c87b03e5Sespie [(match_dup 4) 1318c87b03e5Sespie (match_dup 5)]) 1319c87b03e5Sespie (match_operand:DI 2 "reg_or_cint_move_operand" "") 1320c87b03e5Sespie (match_operand:DI 3 "reg_or_cint_move_operand" "")))] 1321c87b03e5Sespie "TARGET_64BIT" 1322c87b03e5Sespie " 1323c87b03e5Sespie{ 1324c87b03e5Sespie enum rtx_code code = GET_CODE (operands[1]); 1325c87b03e5Sespie 1326c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1327c87b03e5Sespie FAIL; 1328c87b03e5Sespie 1329c87b03e5Sespie if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1) 1330c87b03e5Sespie || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0])) 1331c87b03e5Sespie FAIL; 1332c87b03e5Sespie 1333c87b03e5Sespie /* operands[1] is currently the result of compare_from_rtx. We want to 1334c87b03e5Sespie emit a compare of the original operands. */ 1335c87b03e5Sespie operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1); 1336c87b03e5Sespie operands[4] = hppa_compare_op0; 1337c87b03e5Sespie operands[5] = hppa_compare_op1; 1338c87b03e5Sespie}") 1339c87b03e5Sespie 1340c87b03e5Sespie; We need the first constraint alternative in order to avoid 1341c87b03e5Sespie; earlyclobbers on all other alternatives. 1342c87b03e5Sespie(define_insn "" 1343c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r") 1344c87b03e5Sespie (if_then_else:DI 1345c87b03e5Sespie (match_operator 2 "comparison_operator" 1346c87b03e5Sespie [(match_operand:DI 3 "register_operand" "r,r,r,r,r") 1347c87b03e5Sespie (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")]) 1348c87b03e5Sespie (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K") 1349c87b03e5Sespie (const_int 0)))] 1350c87b03e5Sespie "TARGET_64BIT" 1351c87b03e5Sespie "@ 1352c87b03e5Sespie cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0 1353c87b03e5Sespie cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0 1354c87b03e5Sespie cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0 1355c87b03e5Sespie cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0 1356c87b03e5Sespie cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0" 1357c87b03e5Sespie [(set_attr "type" "multi,multi,multi,multi,nullshift") 1358c87b03e5Sespie (set_attr "length" "8,8,8,8,8")]) 1359c87b03e5Sespie 1360c87b03e5Sespie(define_insn "" 1361c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r") 1362c87b03e5Sespie (if_then_else:DI 1363c87b03e5Sespie (match_operator 5 "comparison_operator" 1364c87b03e5Sespie [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r") 1365c87b03e5Sespie (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")]) 1366c87b03e5Sespie (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K") 1367c87b03e5Sespie (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))] 1368c87b03e5Sespie "TARGET_64BIT" 1369c87b03e5Sespie "@ 1370c87b03e5Sespie cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0 1371c87b03e5Sespie cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0 1372c87b03e5Sespie cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0 1373c87b03e5Sespie cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0 1374c87b03e5Sespie cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0 1375c87b03e5Sespie cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0 1376c87b03e5Sespie cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0 1377c87b03e5Sespie cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0" 1378c87b03e5Sespie [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift") 1379c87b03e5Sespie (set_attr "length" "8,8,8,8,8,8,8,8")]) 1380c87b03e5Sespie 1381c87b03e5Sespie;; Conditional Branches 1382c87b03e5Sespie 1383c87b03e5Sespie(define_expand "beq" 1384c87b03e5Sespie [(set (pc) 1385c87b03e5Sespie (if_then_else (eq (match_dup 1) (match_dup 2)) 1386c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1387c87b03e5Sespie (pc)))] 1388c87b03e5Sespie "" 1389c87b03e5Sespie " 1390c87b03e5Sespie{ 1391c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1392c87b03e5Sespie { 1393c87b03e5Sespie emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1)); 1394c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1395c87b03e5Sespie DONE; 1396c87b03e5Sespie } 1397c87b03e5Sespie /* set up operands from compare. */ 1398c87b03e5Sespie operands[1] = hppa_compare_op0; 1399c87b03e5Sespie operands[2] = hppa_compare_op1; 1400c87b03e5Sespie /* fall through and generate default code */ 1401c87b03e5Sespie}") 1402c87b03e5Sespie 1403c87b03e5Sespie(define_expand "bne" 1404c87b03e5Sespie [(set (pc) 1405c87b03e5Sespie (if_then_else (ne (match_dup 1) (match_dup 2)) 1406c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1407c87b03e5Sespie (pc)))] 1408c87b03e5Sespie "" 1409c87b03e5Sespie " 1410c87b03e5Sespie{ 1411c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1412c87b03e5Sespie { 1413c87b03e5Sespie emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1)); 1414c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1415c87b03e5Sespie DONE; 1416c87b03e5Sespie } 1417c87b03e5Sespie operands[1] = hppa_compare_op0; 1418c87b03e5Sespie operands[2] = hppa_compare_op1; 1419c87b03e5Sespie}") 1420c87b03e5Sespie 1421c87b03e5Sespie(define_expand "bgt" 1422c87b03e5Sespie [(set (pc) 1423c87b03e5Sespie (if_then_else (gt (match_dup 1) (match_dup 2)) 1424c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1425c87b03e5Sespie (pc)))] 1426c87b03e5Sespie "" 1427c87b03e5Sespie " 1428c87b03e5Sespie{ 1429c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1430c87b03e5Sespie { 1431c87b03e5Sespie emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1)); 1432c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1433c87b03e5Sespie DONE; 1434c87b03e5Sespie } 1435c87b03e5Sespie operands[1] = hppa_compare_op0; 1436c87b03e5Sespie operands[2] = hppa_compare_op1; 1437c87b03e5Sespie}") 1438c87b03e5Sespie 1439c87b03e5Sespie(define_expand "blt" 1440c87b03e5Sespie [(set (pc) 1441c87b03e5Sespie (if_then_else (lt (match_dup 1) (match_dup 2)) 1442c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1443c87b03e5Sespie (pc)))] 1444c87b03e5Sespie "" 1445c87b03e5Sespie " 1446c87b03e5Sespie{ 1447c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1448c87b03e5Sespie { 1449c87b03e5Sespie emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1)); 1450c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1451c87b03e5Sespie DONE; 1452c87b03e5Sespie } 1453c87b03e5Sespie operands[1] = hppa_compare_op0; 1454c87b03e5Sespie operands[2] = hppa_compare_op1; 1455c87b03e5Sespie}") 1456c87b03e5Sespie 1457c87b03e5Sespie(define_expand "bge" 1458c87b03e5Sespie [(set (pc) 1459c87b03e5Sespie (if_then_else (ge (match_dup 1) (match_dup 2)) 1460c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1461c87b03e5Sespie (pc)))] 1462c87b03e5Sespie "" 1463c87b03e5Sespie " 1464c87b03e5Sespie{ 1465c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1466c87b03e5Sespie { 1467c87b03e5Sespie emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1)); 1468c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1469c87b03e5Sespie DONE; 1470c87b03e5Sespie } 1471c87b03e5Sespie operands[1] = hppa_compare_op0; 1472c87b03e5Sespie operands[2] = hppa_compare_op1; 1473c87b03e5Sespie}") 1474c87b03e5Sespie 1475c87b03e5Sespie(define_expand "ble" 1476c87b03e5Sespie [(set (pc) 1477c87b03e5Sespie (if_then_else (le (match_dup 1) (match_dup 2)) 1478c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1479c87b03e5Sespie (pc)))] 1480c87b03e5Sespie "" 1481c87b03e5Sespie " 1482c87b03e5Sespie{ 1483c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1484c87b03e5Sespie { 1485c87b03e5Sespie emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1)); 1486c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1487c87b03e5Sespie DONE; 1488c87b03e5Sespie } 1489c87b03e5Sespie operands[1] = hppa_compare_op0; 1490c87b03e5Sespie operands[2] = hppa_compare_op1; 1491c87b03e5Sespie}") 1492c87b03e5Sespie 1493c87b03e5Sespie(define_expand "bgtu" 1494c87b03e5Sespie [(set (pc) 1495c87b03e5Sespie (if_then_else (gtu (match_dup 1) (match_dup 2)) 1496c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1497c87b03e5Sespie (pc)))] 1498c87b03e5Sespie "" 1499c87b03e5Sespie " 1500c87b03e5Sespie{ 1501c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1502c87b03e5Sespie FAIL; 1503c87b03e5Sespie operands[1] = hppa_compare_op0; 1504c87b03e5Sespie operands[2] = hppa_compare_op1; 1505c87b03e5Sespie}") 1506c87b03e5Sespie 1507c87b03e5Sespie(define_expand "bltu" 1508c87b03e5Sespie [(set (pc) 1509c87b03e5Sespie (if_then_else (ltu (match_dup 1) (match_dup 2)) 1510c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1511c87b03e5Sespie (pc)))] 1512c87b03e5Sespie "" 1513c87b03e5Sespie " 1514c87b03e5Sespie{ 1515c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1516c87b03e5Sespie FAIL; 1517c87b03e5Sespie operands[1] = hppa_compare_op0; 1518c87b03e5Sespie operands[2] = hppa_compare_op1; 1519c87b03e5Sespie}") 1520c87b03e5Sespie 1521c87b03e5Sespie(define_expand "bgeu" 1522c87b03e5Sespie [(set (pc) 1523c87b03e5Sespie (if_then_else (geu (match_dup 1) (match_dup 2)) 1524c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1525c87b03e5Sespie (pc)))] 1526c87b03e5Sespie "" 1527c87b03e5Sespie " 1528c87b03e5Sespie{ 1529c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1530c87b03e5Sespie FAIL; 1531c87b03e5Sespie operands[1] = hppa_compare_op0; 1532c87b03e5Sespie operands[2] = hppa_compare_op1; 1533c87b03e5Sespie}") 1534c87b03e5Sespie 1535c87b03e5Sespie(define_expand "bleu" 1536c87b03e5Sespie [(set (pc) 1537c87b03e5Sespie (if_then_else (leu (match_dup 1) (match_dup 2)) 1538c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1539c87b03e5Sespie (pc)))] 1540c87b03e5Sespie "" 1541c87b03e5Sespie " 1542c87b03e5Sespie{ 1543c87b03e5Sespie if (hppa_branch_type != CMP_SI) 1544c87b03e5Sespie FAIL; 1545c87b03e5Sespie operands[1] = hppa_compare_op0; 1546c87b03e5Sespie operands[2] = hppa_compare_op1; 1547c87b03e5Sespie}") 1548c87b03e5Sespie 1549c87b03e5Sespie(define_expand "bltgt" 1550c87b03e5Sespie [(set (pc) 1551c87b03e5Sespie (if_then_else (ltgt (match_dup 1) (match_dup 2)) 1552c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1553c87b03e5Sespie (pc)))] 1554c87b03e5Sespie "" 1555c87b03e5Sespie " 1556c87b03e5Sespie{ 1557c87b03e5Sespie if (hppa_branch_type == CMP_SI) 1558c87b03e5Sespie FAIL; 1559c87b03e5Sespie emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1)); 1560c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1561c87b03e5Sespie DONE; 1562c87b03e5Sespie}") 1563c87b03e5Sespie 1564c87b03e5Sespie(define_expand "bunle" 1565c87b03e5Sespie [(set (pc) 1566c87b03e5Sespie (if_then_else (unle (match_dup 1) (match_dup 2)) 1567c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1568c87b03e5Sespie (pc)))] 1569c87b03e5Sespie "" 1570c87b03e5Sespie " 1571c87b03e5Sespie{ 1572c87b03e5Sespie if (hppa_branch_type == CMP_SI) 1573c87b03e5Sespie FAIL; 1574c87b03e5Sespie emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1)); 1575c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1576c87b03e5Sespie DONE; 1577c87b03e5Sespie}") 1578c87b03e5Sespie 1579c87b03e5Sespie(define_expand "bunlt" 1580c87b03e5Sespie [(set (pc) 1581c87b03e5Sespie (if_then_else (unlt (match_dup 1) (match_dup 2)) 1582c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1583c87b03e5Sespie (pc)))] 1584c87b03e5Sespie "" 1585c87b03e5Sespie " 1586c87b03e5Sespie{ 1587c87b03e5Sespie if (hppa_branch_type == CMP_SI) 1588c87b03e5Sespie FAIL; 1589c87b03e5Sespie emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1)); 1590c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1591c87b03e5Sespie DONE; 1592c87b03e5Sespie}") 1593c87b03e5Sespie 1594c87b03e5Sespie(define_expand "bunge" 1595c87b03e5Sespie [(set (pc) 1596c87b03e5Sespie (if_then_else (unge (match_dup 1) (match_dup 2)) 1597c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1598c87b03e5Sespie (pc)))] 1599c87b03e5Sespie "" 1600c87b03e5Sespie " 1601c87b03e5Sespie{ 1602c87b03e5Sespie if (hppa_branch_type == CMP_SI) 1603c87b03e5Sespie FAIL; 1604c87b03e5Sespie emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1)); 1605c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1606c87b03e5Sespie DONE; 1607c87b03e5Sespie}") 1608c87b03e5Sespie 1609c87b03e5Sespie(define_expand "bungt" 1610c87b03e5Sespie [(set (pc) 1611c87b03e5Sespie (if_then_else (ungt (match_dup 1) (match_dup 2)) 1612c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1613c87b03e5Sespie (pc)))] 1614c87b03e5Sespie "" 1615c87b03e5Sespie " 1616c87b03e5Sespie{ 1617c87b03e5Sespie if (hppa_branch_type == CMP_SI) 1618c87b03e5Sespie FAIL; 1619c87b03e5Sespie emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1)); 1620c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1621c87b03e5Sespie DONE; 1622c87b03e5Sespie}") 1623c87b03e5Sespie 1624c87b03e5Sespie(define_expand "buneq" 1625c87b03e5Sespie [(set (pc) 1626c87b03e5Sespie (if_then_else (uneq (match_dup 1) (match_dup 2)) 1627c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1628c87b03e5Sespie (pc)))] 1629c87b03e5Sespie "" 1630c87b03e5Sespie " 1631c87b03e5Sespie{ 1632c87b03e5Sespie if (hppa_branch_type == CMP_SI) 1633c87b03e5Sespie FAIL; 1634c87b03e5Sespie emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1)); 1635c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1636c87b03e5Sespie DONE; 1637c87b03e5Sespie}") 1638c87b03e5Sespie 1639c87b03e5Sespie(define_expand "bunordered" 1640c87b03e5Sespie [(set (pc) 1641c87b03e5Sespie (if_then_else (unordered (match_dup 1) (match_dup 2)) 1642c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1643c87b03e5Sespie (pc)))] 1644c87b03e5Sespie "" 1645c87b03e5Sespie " 1646c87b03e5Sespie{ 1647c87b03e5Sespie if (hppa_branch_type == CMP_SI) 1648c87b03e5Sespie FAIL; 1649c87b03e5Sespie emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1)); 1650c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1651c87b03e5Sespie DONE; 1652c87b03e5Sespie}") 1653c87b03e5Sespie 1654c87b03e5Sespie(define_expand "bordered" 1655c87b03e5Sespie [(set (pc) 1656c87b03e5Sespie (if_then_else (ordered (match_dup 1) (match_dup 2)) 1657c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1658c87b03e5Sespie (pc)))] 1659c87b03e5Sespie "" 1660c87b03e5Sespie " 1661c87b03e5Sespie{ 1662c87b03e5Sespie if (hppa_branch_type == CMP_SI) 1663c87b03e5Sespie FAIL; 1664c87b03e5Sespie emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1)); 1665c87b03e5Sespie emit_bcond_fp (NE, operands[0]); 1666c87b03e5Sespie DONE; 1667c87b03e5Sespie}") 1668c87b03e5Sespie 1669c87b03e5Sespie;; Match the branch patterns. 1670c87b03e5Sespie 1671c87b03e5Sespie 1672c87b03e5Sespie;; Note a long backward conditional branch with an annulled delay slot 1673c87b03e5Sespie;; has a length of 12. 1674c87b03e5Sespie(define_insn "" 1675c87b03e5Sespie [(set (pc) 1676c87b03e5Sespie (if_then_else 1677c87b03e5Sespie (match_operator 3 "comparison_operator" 1678c87b03e5Sespie [(match_operand:SI 1 "reg_or_0_operand" "rM") 1679c87b03e5Sespie (match_operand:SI 2 "arith5_operand" "rL")]) 1680c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1681c87b03e5Sespie (pc)))] 1682c87b03e5Sespie "" 1683c87b03e5Sespie "* 1684c87b03e5Sespie{ 1685c87b03e5Sespie return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn), 1686c87b03e5Sespie get_attr_length (insn), 0, insn); 1687c87b03e5Sespie}" 1688c87b03e5Sespie[(set_attr "type" "cbranch") 1689c87b03e5Sespie (set (attr "length") 1690c87b03e5Sespie (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1691c87b03e5Sespie (const_int 8184)) 1692c87b03e5Sespie (const_int 4) 1693c87b03e5Sespie (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1694c87b03e5Sespie (const_int 262100)) 1695c87b03e5Sespie (const_int 8) 1696c87b03e5Sespie (eq (symbol_ref "flag_pic") (const_int 0)) 1697c87b03e5Sespie (const_int 20)] 1698c87b03e5Sespie (const_int 28)))]) 1699c87b03e5Sespie 1700c87b03e5Sespie;; Match the negated branch. 1701c87b03e5Sespie 1702c87b03e5Sespie(define_insn "" 1703c87b03e5Sespie [(set (pc) 1704c87b03e5Sespie (if_then_else 1705c87b03e5Sespie (match_operator 3 "comparison_operator" 1706c87b03e5Sespie [(match_operand:SI 1 "reg_or_0_operand" "rM") 1707c87b03e5Sespie (match_operand:SI 2 "arith5_operand" "rL")]) 1708c87b03e5Sespie (pc) 1709c87b03e5Sespie (label_ref (match_operand 0 "" ""))))] 1710c87b03e5Sespie "" 1711c87b03e5Sespie "* 1712c87b03e5Sespie{ 1713c87b03e5Sespie return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn), 1714c87b03e5Sespie get_attr_length (insn), 1, insn); 1715c87b03e5Sespie}" 1716c87b03e5Sespie[(set_attr "type" "cbranch") 1717c87b03e5Sespie (set (attr "length") 1718c87b03e5Sespie (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1719c87b03e5Sespie (const_int 8184)) 1720c87b03e5Sespie (const_int 4) 1721c87b03e5Sespie (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1722c87b03e5Sespie (const_int 262100)) 1723c87b03e5Sespie (const_int 8) 1724c87b03e5Sespie (eq (symbol_ref "flag_pic") (const_int 0)) 1725c87b03e5Sespie (const_int 20)] 1726c87b03e5Sespie (const_int 28)))]) 1727c87b03e5Sespie 1728c87b03e5Sespie(define_insn "" 1729c87b03e5Sespie [(set (pc) 1730c87b03e5Sespie (if_then_else 1731c87b03e5Sespie (match_operator 3 "comparison_operator" 1732c87b03e5Sespie [(match_operand:DI 1 "reg_or_0_operand" "rM") 1733c87b03e5Sespie (match_operand:DI 2 "reg_or_0_operand" "rM")]) 1734c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1735c87b03e5Sespie (pc)))] 1736c87b03e5Sespie "TARGET_64BIT" 1737c87b03e5Sespie "* 1738c87b03e5Sespie{ 1739c87b03e5Sespie return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn), 1740c87b03e5Sespie get_attr_length (insn), 0, insn); 1741c87b03e5Sespie}" 1742c87b03e5Sespie[(set_attr "type" "cbranch") 1743c87b03e5Sespie (set (attr "length") 1744c87b03e5Sespie (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1745c87b03e5Sespie (const_int 8184)) 1746c87b03e5Sespie (const_int 4) 1747c87b03e5Sespie (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1748c87b03e5Sespie (const_int 262100)) 1749c87b03e5Sespie (const_int 8) 1750c87b03e5Sespie (eq (symbol_ref "flag_pic") (const_int 0)) 1751c87b03e5Sespie (const_int 20)] 1752c87b03e5Sespie (const_int 28)))]) 1753c87b03e5Sespie 1754c87b03e5Sespie;; Match the negated branch. 1755c87b03e5Sespie 1756c87b03e5Sespie(define_insn "" 1757c87b03e5Sespie [(set (pc) 1758c87b03e5Sespie (if_then_else 1759c87b03e5Sespie (match_operator 3 "comparison_operator" 1760c87b03e5Sespie [(match_operand:DI 1 "reg_or_0_operand" "rM") 1761c87b03e5Sespie (match_operand:DI 2 "reg_or_0_operand" "rM")]) 1762c87b03e5Sespie (pc) 1763c87b03e5Sespie (label_ref (match_operand 0 "" ""))))] 1764c87b03e5Sespie "TARGET_64BIT" 1765c87b03e5Sespie "* 1766c87b03e5Sespie{ 1767c87b03e5Sespie return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn), 1768c87b03e5Sespie get_attr_length (insn), 1, insn); 1769c87b03e5Sespie}" 1770c87b03e5Sespie[(set_attr "type" "cbranch") 1771c87b03e5Sespie (set (attr "length") 1772c87b03e5Sespie (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1773c87b03e5Sespie (const_int 8184)) 1774c87b03e5Sespie (const_int 4) 1775c87b03e5Sespie (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1776c87b03e5Sespie (const_int 262100)) 1777c87b03e5Sespie (const_int 8) 1778c87b03e5Sespie (eq (symbol_ref "flag_pic") (const_int 0)) 1779c87b03e5Sespie (const_int 20)] 1780c87b03e5Sespie (const_int 28)))]) 1781c87b03e5Sespie(define_insn "" 1782c87b03e5Sespie [(set (pc) 1783c87b03e5Sespie (if_then_else 1784c87b03e5Sespie (match_operator 3 "cmpib_comparison_operator" 1785c87b03e5Sespie [(match_operand:DI 1 "reg_or_0_operand" "rM") 1786c87b03e5Sespie (match_operand:DI 2 "arith5_operand" "rL")]) 1787c87b03e5Sespie (label_ref (match_operand 0 "" "")) 1788c87b03e5Sespie (pc)))] 1789c87b03e5Sespie "TARGET_64BIT" 1790c87b03e5Sespie "* 1791c87b03e5Sespie{ 1792c87b03e5Sespie return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn), 1793c87b03e5Sespie get_attr_length (insn), 0, insn); 1794c87b03e5Sespie}" 1795c87b03e5Sespie[(set_attr "type" "cbranch") 1796c87b03e5Sespie (set (attr "length") 1797c87b03e5Sespie (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1798c87b03e5Sespie (const_int 8184)) 1799c87b03e5Sespie (const_int 4) 1800c87b03e5Sespie (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1801c87b03e5Sespie (const_int 262100)) 1802c87b03e5Sespie (const_int 8) 1803c87b03e5Sespie (eq (symbol_ref "flag_pic") (const_int 0)) 1804c87b03e5Sespie (const_int 20)] 1805c87b03e5Sespie (const_int 28)))]) 1806c87b03e5Sespie 1807c87b03e5Sespie;; Match the negated branch. 1808c87b03e5Sespie 1809c87b03e5Sespie(define_insn "" 1810c87b03e5Sespie [(set (pc) 1811c87b03e5Sespie (if_then_else 1812c87b03e5Sespie (match_operator 3 "cmpib_comparison_operator" 1813c87b03e5Sespie [(match_operand:DI 1 "reg_or_0_operand" "rM") 1814c87b03e5Sespie (match_operand:DI 2 "arith5_operand" "rL")]) 1815c87b03e5Sespie (pc) 1816c87b03e5Sespie (label_ref (match_operand 0 "" ""))))] 1817c87b03e5Sespie "TARGET_64BIT" 1818c87b03e5Sespie "* 1819c87b03e5Sespie{ 1820c87b03e5Sespie return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn), 1821c87b03e5Sespie get_attr_length (insn), 1, insn); 1822c87b03e5Sespie}" 1823c87b03e5Sespie[(set_attr "type" "cbranch") 1824c87b03e5Sespie (set (attr "length") 1825c87b03e5Sespie (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1826c87b03e5Sespie (const_int 8184)) 1827c87b03e5Sespie (const_int 4) 1828c87b03e5Sespie (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 1829c87b03e5Sespie (const_int 262100)) 1830c87b03e5Sespie (const_int 8) 1831c87b03e5Sespie (eq (symbol_ref "flag_pic") (const_int 0)) 1832c87b03e5Sespie (const_int 20)] 1833c87b03e5Sespie (const_int 28)))]) 1834c87b03e5Sespie 1835c87b03e5Sespie;; Branch on Bit patterns. 1836c87b03e5Sespie(define_insn "" 1837c87b03e5Sespie [(set (pc) 1838c87b03e5Sespie (if_then_else 1839c87b03e5Sespie (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 1840c87b03e5Sespie (const_int 1) 1841c87b03e5Sespie (match_operand:SI 1 "uint5_operand" "")) 1842c87b03e5Sespie (const_int 0)) 1843c87b03e5Sespie (label_ref (match_operand 2 "" "")) 1844c87b03e5Sespie (pc)))] 1845c87b03e5Sespie "" 1846c87b03e5Sespie "* 1847c87b03e5Sespie{ 1848c87b03e5Sespie return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn), 1849c87b03e5Sespie get_attr_length (insn), 0, insn, 0); 1850c87b03e5Sespie}" 1851c87b03e5Sespie[(set_attr "type" "cbranch") 1852c87b03e5Sespie (set (attr "length") 1853c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 1854c87b03e5Sespie (const_int 8184)) 1855c87b03e5Sespie (const_int 4) 1856c87b03e5Sespie (const_int 8)))]) 1857c87b03e5Sespie 1858c87b03e5Sespie(define_insn "" 1859c87b03e5Sespie [(set (pc) 1860c87b03e5Sespie (if_then_else 1861c87b03e5Sespie (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r") 1862c87b03e5Sespie (const_int 1) 1863c87b03e5Sespie (match_operand:DI 1 "uint32_operand" "")) 1864c87b03e5Sespie (const_int 0)) 1865c87b03e5Sespie (label_ref (match_operand 2 "" "")) 1866c87b03e5Sespie (pc)))] 1867c87b03e5Sespie "TARGET_64BIT" 1868c87b03e5Sespie "* 1869c87b03e5Sespie{ 1870c87b03e5Sespie return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn), 1871c87b03e5Sespie get_attr_length (insn), 0, insn, 0); 1872c87b03e5Sespie}" 1873c87b03e5Sespie[(set_attr "type" "cbranch") 1874c87b03e5Sespie (set (attr "length") 1875c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 1876c87b03e5Sespie (const_int 8184)) 1877c87b03e5Sespie (const_int 4) 1878c87b03e5Sespie (const_int 8)))]) 1879c87b03e5Sespie 1880c87b03e5Sespie(define_insn "" 1881c87b03e5Sespie [(set (pc) 1882c87b03e5Sespie (if_then_else 1883c87b03e5Sespie (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 1884c87b03e5Sespie (const_int 1) 1885c87b03e5Sespie (match_operand:SI 1 "uint5_operand" "")) 1886c87b03e5Sespie (const_int 0)) 1887c87b03e5Sespie (pc) 1888c87b03e5Sespie (label_ref (match_operand 2 "" ""))))] 1889c87b03e5Sespie "" 1890c87b03e5Sespie "* 1891c87b03e5Sespie{ 1892c87b03e5Sespie return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn), 1893c87b03e5Sespie get_attr_length (insn), 1, insn, 0); 1894c87b03e5Sespie}" 1895c87b03e5Sespie[(set_attr "type" "cbranch") 1896c87b03e5Sespie (set (attr "length") 1897c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 1898c87b03e5Sespie (const_int 8184)) 1899c87b03e5Sespie (const_int 4) 1900c87b03e5Sespie (const_int 8)))]) 1901c87b03e5Sespie 1902c87b03e5Sespie(define_insn "" 1903c87b03e5Sespie [(set (pc) 1904c87b03e5Sespie (if_then_else 1905c87b03e5Sespie (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r") 1906c87b03e5Sespie (const_int 1) 1907c87b03e5Sespie (match_operand:DI 1 "uint32_operand" "")) 1908c87b03e5Sespie (const_int 0)) 1909c87b03e5Sespie (pc) 1910c87b03e5Sespie (label_ref (match_operand 2 "" ""))))] 1911c87b03e5Sespie "TARGET_64BIT" 1912c87b03e5Sespie "* 1913c87b03e5Sespie{ 1914c87b03e5Sespie return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn), 1915c87b03e5Sespie get_attr_length (insn), 1, insn, 0); 1916c87b03e5Sespie}" 1917c87b03e5Sespie[(set_attr "type" "cbranch") 1918c87b03e5Sespie (set (attr "length") 1919c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 1920c87b03e5Sespie (const_int 8184)) 1921c87b03e5Sespie (const_int 4) 1922c87b03e5Sespie (const_int 8)))]) 1923c87b03e5Sespie 1924c87b03e5Sespie(define_insn "" 1925c87b03e5Sespie [(set (pc) 1926c87b03e5Sespie (if_then_else 1927c87b03e5Sespie (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 1928c87b03e5Sespie (const_int 1) 1929c87b03e5Sespie (match_operand:SI 1 "uint5_operand" "")) 1930c87b03e5Sespie (const_int 0)) 1931c87b03e5Sespie (label_ref (match_operand 2 "" "")) 1932c87b03e5Sespie (pc)))] 1933c87b03e5Sespie "" 1934c87b03e5Sespie "* 1935c87b03e5Sespie{ 1936c87b03e5Sespie return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn), 1937c87b03e5Sespie get_attr_length (insn), 0, insn, 1); 1938c87b03e5Sespie}" 1939c87b03e5Sespie[(set_attr "type" "cbranch") 1940c87b03e5Sespie (set (attr "length") 1941c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 1942c87b03e5Sespie (const_int 8184)) 1943c87b03e5Sespie (const_int 4) 1944c87b03e5Sespie (const_int 8)))]) 1945c87b03e5Sespie 1946c87b03e5Sespie(define_insn "" 1947c87b03e5Sespie [(set (pc) 1948c87b03e5Sespie (if_then_else 1949c87b03e5Sespie (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r") 1950c87b03e5Sespie (const_int 1) 1951c87b03e5Sespie (match_operand:DI 1 "uint32_operand" "")) 1952c87b03e5Sespie (const_int 0)) 1953c87b03e5Sespie (label_ref (match_operand 2 "" "")) 1954c87b03e5Sespie (pc)))] 1955c87b03e5Sespie "TARGET_64BIT" 1956c87b03e5Sespie "* 1957c87b03e5Sespie{ 1958c87b03e5Sespie return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn), 1959c87b03e5Sespie get_attr_length (insn), 0, insn, 1); 1960c87b03e5Sespie}" 1961c87b03e5Sespie[(set_attr "type" "cbranch") 1962c87b03e5Sespie (set (attr "length") 1963c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 1964c87b03e5Sespie (const_int 8184)) 1965c87b03e5Sespie (const_int 4) 1966c87b03e5Sespie (const_int 8)))]) 1967c87b03e5Sespie 1968c87b03e5Sespie(define_insn "" 1969c87b03e5Sespie [(set (pc) 1970c87b03e5Sespie (if_then_else 1971c87b03e5Sespie (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 1972c87b03e5Sespie (const_int 1) 1973c87b03e5Sespie (match_operand:SI 1 "uint5_operand" "")) 1974c87b03e5Sespie (const_int 0)) 1975c87b03e5Sespie (pc) 1976c87b03e5Sespie (label_ref (match_operand 2 "" ""))))] 1977c87b03e5Sespie "" 1978c87b03e5Sespie "* 1979c87b03e5Sespie{ 1980c87b03e5Sespie return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn), 1981c87b03e5Sespie get_attr_length (insn), 1, insn, 1); 1982c87b03e5Sespie}" 1983c87b03e5Sespie[(set_attr "type" "cbranch") 1984c87b03e5Sespie (set (attr "length") 1985c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 1986c87b03e5Sespie (const_int 8184)) 1987c87b03e5Sespie (const_int 4) 1988c87b03e5Sespie (const_int 8)))]) 1989c87b03e5Sespie 1990c87b03e5Sespie(define_insn "" 1991c87b03e5Sespie [(set (pc) 1992c87b03e5Sespie (if_then_else 1993c87b03e5Sespie (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r") 1994c87b03e5Sespie (const_int 1) 1995c87b03e5Sespie (match_operand:DI 1 "uint32_operand" "")) 1996c87b03e5Sespie (const_int 0)) 1997c87b03e5Sespie (pc) 1998c87b03e5Sespie (label_ref (match_operand 2 "" ""))))] 1999c87b03e5Sespie "TARGET_64BIT" 2000c87b03e5Sespie "* 2001c87b03e5Sespie{ 2002c87b03e5Sespie return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn), 2003c87b03e5Sespie get_attr_length (insn), 1, insn, 1); 2004c87b03e5Sespie}" 2005c87b03e5Sespie[(set_attr "type" "cbranch") 2006c87b03e5Sespie (set (attr "length") 2007c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 2008c87b03e5Sespie (const_int 8184)) 2009c87b03e5Sespie (const_int 4) 2010c87b03e5Sespie (const_int 8)))]) 2011c87b03e5Sespie 2012c87b03e5Sespie;; Branch on Variable Bit patterns. 2013c87b03e5Sespie(define_insn "" 2014c87b03e5Sespie [(set (pc) 2015c87b03e5Sespie (if_then_else 2016c87b03e5Sespie (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 2017c87b03e5Sespie (const_int 1) 2018c87b03e5Sespie (match_operand:SI 1 "register_operand" "q")) 2019c87b03e5Sespie (const_int 0)) 2020c87b03e5Sespie (label_ref (match_operand 2 "" "")) 2021c87b03e5Sespie (pc)))] 2022c87b03e5Sespie "" 2023c87b03e5Sespie "* 2024c87b03e5Sespie{ 2025c87b03e5Sespie return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn), 2026c87b03e5Sespie get_attr_length (insn), 0, insn, 0); 2027c87b03e5Sespie}" 2028c87b03e5Sespie[(set_attr "type" "cbranch") 2029c87b03e5Sespie (set (attr "length") 2030c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 2031c87b03e5Sespie (const_int 8184)) 2032c87b03e5Sespie (const_int 4) 2033c87b03e5Sespie (const_int 8)))]) 2034c87b03e5Sespie 2035c87b03e5Sespie(define_insn "" 2036c87b03e5Sespie [(set (pc) 2037c87b03e5Sespie (if_then_else 2038c87b03e5Sespie (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r") 2039c87b03e5Sespie (const_int 1) 2040c87b03e5Sespie (match_operand:DI 1 "register_operand" "q")) 2041c87b03e5Sespie (const_int 0)) 2042c87b03e5Sespie (label_ref (match_operand 2 "" "")) 2043c87b03e5Sespie (pc)))] 2044c87b03e5Sespie "TARGET_64BIT" 2045c87b03e5Sespie "* 2046c87b03e5Sespie{ 2047c87b03e5Sespie return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn), 2048c87b03e5Sespie get_attr_length (insn), 0, insn, 0); 2049c87b03e5Sespie}" 2050c87b03e5Sespie[(set_attr "type" "cbranch") 2051c87b03e5Sespie (set (attr "length") 2052c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 2053c87b03e5Sespie (const_int 8184)) 2054c87b03e5Sespie (const_int 4) 2055c87b03e5Sespie (const_int 8)))]) 2056c87b03e5Sespie 2057c87b03e5Sespie(define_insn "" 2058c87b03e5Sespie [(set (pc) 2059c87b03e5Sespie (if_then_else 2060c87b03e5Sespie (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 2061c87b03e5Sespie (const_int 1) 2062c87b03e5Sespie (match_operand:SI 1 "register_operand" "q")) 2063c87b03e5Sespie (const_int 0)) 2064c87b03e5Sespie (pc) 2065c87b03e5Sespie (label_ref (match_operand 2 "" ""))))] 2066c87b03e5Sespie "" 2067c87b03e5Sespie "* 2068c87b03e5Sespie{ 2069c87b03e5Sespie return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn), 2070c87b03e5Sespie get_attr_length (insn), 1, insn, 0); 2071c87b03e5Sespie}" 2072c87b03e5Sespie[(set_attr "type" "cbranch") 2073c87b03e5Sespie (set (attr "length") 2074c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 2075c87b03e5Sespie (const_int 8184)) 2076c87b03e5Sespie (const_int 4) 2077c87b03e5Sespie (const_int 8)))]) 2078c87b03e5Sespie 2079c87b03e5Sespie(define_insn "" 2080c87b03e5Sespie [(set (pc) 2081c87b03e5Sespie (if_then_else 2082c87b03e5Sespie (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r") 2083c87b03e5Sespie (const_int 1) 2084c87b03e5Sespie (match_operand:DI 1 "register_operand" "q")) 2085c87b03e5Sespie (const_int 0)) 2086c87b03e5Sespie (pc) 2087c87b03e5Sespie (label_ref (match_operand 2 "" ""))))] 2088c87b03e5Sespie "TARGET_64BIT" 2089c87b03e5Sespie "* 2090c87b03e5Sespie{ 2091c87b03e5Sespie return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn), 2092c87b03e5Sespie get_attr_length (insn), 1, insn, 0); 2093c87b03e5Sespie}" 2094c87b03e5Sespie[(set_attr "type" "cbranch") 2095c87b03e5Sespie (set (attr "length") 2096c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 2097c87b03e5Sespie (const_int 8184)) 2098c87b03e5Sespie (const_int 4) 2099c87b03e5Sespie (const_int 8)))]) 2100c87b03e5Sespie 2101c87b03e5Sespie(define_insn "" 2102c87b03e5Sespie [(set (pc) 2103c87b03e5Sespie (if_then_else 2104c87b03e5Sespie (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 2105c87b03e5Sespie (const_int 1) 2106c87b03e5Sespie (match_operand:SI 1 "register_operand" "q")) 2107c87b03e5Sespie (const_int 0)) 2108c87b03e5Sespie (label_ref (match_operand 2 "" "")) 2109c87b03e5Sespie (pc)))] 2110c87b03e5Sespie "" 2111c87b03e5Sespie "* 2112c87b03e5Sespie{ 2113c87b03e5Sespie return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn), 2114c87b03e5Sespie get_attr_length (insn), 0, insn, 1); 2115c87b03e5Sespie}" 2116c87b03e5Sespie[(set_attr "type" "cbranch") 2117c87b03e5Sespie (set (attr "length") 2118c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 2119c87b03e5Sespie (const_int 8184)) 2120c87b03e5Sespie (const_int 4) 2121c87b03e5Sespie (const_int 8)))]) 2122c87b03e5Sespie 2123c87b03e5Sespie(define_insn "" 2124c87b03e5Sespie [(set (pc) 2125c87b03e5Sespie (if_then_else 2126c87b03e5Sespie (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r") 2127c87b03e5Sespie (const_int 1) 2128c87b03e5Sespie (match_operand:DI 1 "register_operand" "q")) 2129c87b03e5Sespie (const_int 0)) 2130c87b03e5Sespie (label_ref (match_operand 2 "" "")) 2131c87b03e5Sespie (pc)))] 2132c87b03e5Sespie "TARGET_64BIT" 2133c87b03e5Sespie "* 2134c87b03e5Sespie{ 2135c87b03e5Sespie return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn), 2136c87b03e5Sespie get_attr_length (insn), 0, insn, 1); 2137c87b03e5Sespie}" 2138c87b03e5Sespie[(set_attr "type" "cbranch") 2139c87b03e5Sespie (set (attr "length") 2140c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 2141c87b03e5Sespie (const_int 8184)) 2142c87b03e5Sespie (const_int 4) 2143c87b03e5Sespie (const_int 8)))]) 2144c87b03e5Sespie 2145c87b03e5Sespie(define_insn "" 2146c87b03e5Sespie [(set (pc) 2147c87b03e5Sespie (if_then_else 2148c87b03e5Sespie (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 2149c87b03e5Sespie (const_int 1) 2150c87b03e5Sespie (match_operand:SI 1 "register_operand" "q")) 2151c87b03e5Sespie (const_int 0)) 2152c87b03e5Sespie (pc) 2153c87b03e5Sespie (label_ref (match_operand 2 "" ""))))] 2154c87b03e5Sespie "" 2155c87b03e5Sespie "* 2156c87b03e5Sespie{ 2157c87b03e5Sespie return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn), 2158c87b03e5Sespie get_attr_length (insn), 1, insn, 1); 2159c87b03e5Sespie}" 2160c87b03e5Sespie[(set_attr "type" "cbranch") 2161c87b03e5Sespie (set (attr "length") 2162c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 2163c87b03e5Sespie (const_int 8184)) 2164c87b03e5Sespie (const_int 4) 2165c87b03e5Sespie (const_int 8)))]) 2166c87b03e5Sespie 2167c87b03e5Sespie(define_insn "" 2168c87b03e5Sespie [(set (pc) 2169c87b03e5Sespie (if_then_else 2170c87b03e5Sespie (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r") 2171c87b03e5Sespie (const_int 1) 2172c87b03e5Sespie (match_operand:DI 1 "register_operand" "q")) 2173c87b03e5Sespie (const_int 0)) 2174c87b03e5Sespie (pc) 2175c87b03e5Sespie (label_ref (match_operand 2 "" ""))))] 2176c87b03e5Sespie "TARGET_64BIT" 2177c87b03e5Sespie "* 2178c87b03e5Sespie{ 2179c87b03e5Sespie return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn), 2180c87b03e5Sespie get_attr_length (insn), 1, insn, 1); 2181c87b03e5Sespie}" 2182c87b03e5Sespie[(set_attr "type" "cbranch") 2183c87b03e5Sespie (set (attr "length") 2184c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 2185c87b03e5Sespie (const_int 8184)) 2186c87b03e5Sespie (const_int 4) 2187c87b03e5Sespie (const_int 8)))]) 2188c87b03e5Sespie 2189c87b03e5Sespie;; Floating point branches 2190c87b03e5Sespie(define_insn "" 2191c87b03e5Sespie [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0)) 2192c87b03e5Sespie (label_ref (match_operand 0 "" "")) 2193c87b03e5Sespie (pc)))] 2194c87b03e5Sespie "! TARGET_SOFT_FLOAT" 2195c87b03e5Sespie "* 2196c87b03e5Sespie{ 2197c87b03e5Sespie if (INSN_ANNULLED_BRANCH_P (insn)) 2198c87b03e5Sespie return \"ftest\;b,n %0\"; 2199c87b03e5Sespie else 2200c87b03e5Sespie return \"ftest\;b%* %0\"; 2201c87b03e5Sespie}" 2202c87b03e5Sespie [(set_attr "type" "fbranch") 2203c87b03e5Sespie (set_attr "length" "8")]) 2204c87b03e5Sespie 2205c87b03e5Sespie(define_insn "" 2206c87b03e5Sespie [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0)) 2207c87b03e5Sespie (pc) 2208c87b03e5Sespie (label_ref (match_operand 0 "" ""))))] 2209c87b03e5Sespie "! TARGET_SOFT_FLOAT" 2210c87b03e5Sespie "* 2211c87b03e5Sespie{ 2212c87b03e5Sespie if (INSN_ANNULLED_BRANCH_P (insn)) 2213c87b03e5Sespie return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\"; 2214c87b03e5Sespie else 2215c87b03e5Sespie return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\"; 2216c87b03e5Sespie}" 2217c87b03e5Sespie [(set_attr "type" "fbranch") 2218c87b03e5Sespie (set_attr "length" "12")]) 2219c87b03e5Sespie 2220c87b03e5Sespie;; Move instructions 2221c87b03e5Sespie 2222c87b03e5Sespie(define_expand "movsi" 2223c87b03e5Sespie [(set (match_operand:SI 0 "general_operand" "") 2224c87b03e5Sespie (match_operand:SI 1 "general_operand" ""))] 2225c87b03e5Sespie "" 2226c87b03e5Sespie " 2227c87b03e5Sespie{ 2228c87b03e5Sespie if (emit_move_sequence (operands, SImode, 0)) 2229c87b03e5Sespie DONE; 2230c87b03e5Sespie}") 2231c87b03e5Sespie 2232c87b03e5Sespie;; Reloading an SImode or DImode value requires a scratch register if 2233c87b03e5Sespie;; going in to or out of float point registers. 2234c87b03e5Sespie 2235c87b03e5Sespie(define_expand "reload_insi" 2236c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=Z") 2237c87b03e5Sespie (match_operand:SI 1 "non_hard_reg_operand" "")) 2238c87b03e5Sespie (clobber (match_operand:SI 2 "register_operand" "=&r"))] 2239c87b03e5Sespie "" 2240c87b03e5Sespie " 2241c87b03e5Sespie{ 2242c87b03e5Sespie if (emit_move_sequence (operands, SImode, operands[2])) 2243c87b03e5Sespie DONE; 2244c87b03e5Sespie 2245c87b03e5Sespie /* We don't want the clobber emitted, so handle this ourselves. */ 2246c87b03e5Sespie emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 2247c87b03e5Sespie DONE; 2248c87b03e5Sespie}") 2249c87b03e5Sespie 2250c87b03e5Sespie(define_expand "reload_outsi" 2251c87b03e5Sespie [(set (match_operand:SI 0 "non_hard_reg_operand" "") 2252c87b03e5Sespie (match_operand:SI 1 "register_operand" "Z")) 2253c87b03e5Sespie (clobber (match_operand:SI 2 "register_operand" "=&r"))] 2254c87b03e5Sespie "" 2255c87b03e5Sespie " 2256c87b03e5Sespie{ 2257c87b03e5Sespie if (emit_move_sequence (operands, SImode, operands[2])) 2258c87b03e5Sespie DONE; 2259c87b03e5Sespie 2260c87b03e5Sespie /* We don't want the clobber emitted, so handle this ourselves. */ 2261c87b03e5Sespie emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 2262c87b03e5Sespie DONE; 2263c87b03e5Sespie}") 2264c87b03e5Sespie 2265c87b03e5Sespie(define_insn "" 2266c87b03e5Sespie [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" 22674e43c760Sespie "=r,r,r,r,r,r,Q,!*q,!r,!f,f,*TR") 2268c87b03e5Sespie (match_operand:SI 1 "move_operand" 22694e43c760Sespie "A,r,J,N,K,RQ,rM,!rM,!*q,!fM,*RT,f"))] 2270c87b03e5Sespie "(register_operand (operands[0], SImode) 2271c87b03e5Sespie || reg_or_0_operand (operands[1], SImode)) 2272c87b03e5Sespie && ! TARGET_SOFT_FLOAT" 2273c87b03e5Sespie "@ 2274c87b03e5Sespie ldw RT'%A1,%0 2275c87b03e5Sespie copy %1,%0 2276c87b03e5Sespie ldi %1,%0 2277c87b03e5Sespie ldil L'%1,%0 2278c87b03e5Sespie {zdepi|depwi,z} %Z1,%0 2279c87b03e5Sespie ldw%M1 %1,%0 2280c87b03e5Sespie stw%M0 %r1,%0 2281c87b03e5Sespie mtsar %r1 22824e43c760Sespie {mfctl|mfctl,w} %%sar,%0 2283c87b03e5Sespie fcpy,sgl %f1,%0 2284c87b03e5Sespie fldw%F1 %1,%0 2285c87b03e5Sespie fstw%F0 %1,%0" 22864e43c760Sespie [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore") 2287c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 22884e43c760Sespie (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")]) 2289c87b03e5Sespie 2290c87b03e5Sespie(define_insn "" 2291c87b03e5Sespie [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" 22924e43c760Sespie "=r,r,r,r,r,r,Q,!*q,!r") 2293c87b03e5Sespie (match_operand:SI 1 "move_operand" 22944e43c760Sespie "A,r,J,N,K,RQ,rM,!rM,!*q"))] 2295c87b03e5Sespie "(register_operand (operands[0], SImode) 2296c87b03e5Sespie || reg_or_0_operand (operands[1], SImode)) 2297c87b03e5Sespie && TARGET_SOFT_FLOAT" 2298c87b03e5Sespie "@ 2299c87b03e5Sespie ldw RT'%A1,%0 2300c87b03e5Sespie copy %1,%0 2301c87b03e5Sespie ldi %1,%0 2302c87b03e5Sespie ldil L'%1,%0 2303c87b03e5Sespie {zdepi|depwi,z} %Z1,%0 2304c87b03e5Sespie ldw%M1 %1,%0 2305c87b03e5Sespie stw%M0 %r1,%0 23064e43c760Sespie mtsar %r1 23074e43c760Sespie {mfctl|mfctl,w} %%sar,%0" 23084e43c760Sespie [(set_attr "type" "load,move,move,move,move,load,store,move,move") 2309c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 23104e43c760Sespie (set_attr "length" "4,4,4,4,4,4,4,4,4")]) 2311c87b03e5Sespie 2312c87b03e5Sespie(define_insn "" 2313c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2314c87b03e5Sespie (mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r") 2315c87b03e5Sespie (match_operand:SI 2 "register_operand" "r"))))] 2316c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2317c87b03e5Sespie "{ldwx|ldw} %2(%1),%0" 2318c87b03e5Sespie [(set_attr "type" "load") 2319c87b03e5Sespie (set_attr "length" "4")]) 2320c87b03e5Sespie 2321c87b03e5Sespie(define_insn "" 2322c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2323c87b03e5Sespie (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") 2324c87b03e5Sespie (match_operand:SI 2 "basereg_operand" "r"))))] 2325c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2326c87b03e5Sespie "{ldwx|ldw} %1(%2),%0" 2327c87b03e5Sespie [(set_attr "type" "load") 2328c87b03e5Sespie (set_attr "length" "4")]) 2329c87b03e5Sespie 2330c87b03e5Sespie;; Load or store with base-register modification. 2331c87b03e5Sespie 2332c87b03e5Sespie(define_expand "pre_load" 2333c87b03e5Sespie [(parallel [(set (match_operand:SI 0 "register_operand" "") 2334c87b03e5Sespie (mem (plus (match_operand 1 "register_operand" "") 2335c87b03e5Sespie (match_operand 2 "pre_cint_operand" "")))) 2336c87b03e5Sespie (set (match_dup 1) 2337c87b03e5Sespie (plus (match_dup 1) (match_dup 2)))])] 2338c87b03e5Sespie "" 2339c87b03e5Sespie " 2340c87b03e5Sespie{ 2341c87b03e5Sespie if (TARGET_64BIT) 2342c87b03e5Sespie { 2343c87b03e5Sespie emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2])); 2344c87b03e5Sespie DONE; 2345c87b03e5Sespie } 2346c87b03e5Sespie emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2])); 2347c87b03e5Sespie DONE; 2348c87b03e5Sespie}") 2349c87b03e5Sespie 2350c87b03e5Sespie(define_insn "pre_ldw" 2351c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2352c87b03e5Sespie (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r") 2353c87b03e5Sespie (match_operand:SI 2 "pre_cint_operand" "")))) 2354c87b03e5Sespie (set (match_dup 1) 2355c87b03e5Sespie (plus:SI (match_dup 1) (match_dup 2)))] 2356c87b03e5Sespie "" 2357c87b03e5Sespie "* 2358c87b03e5Sespie{ 2359c87b03e5Sespie if (INTVAL (operands[2]) < 0) 2360c87b03e5Sespie return \"{ldwm|ldw,mb} %2(%1),%0\"; 2361c87b03e5Sespie return \"{ldws|ldw},mb %2(%1),%0\"; 2362c87b03e5Sespie}" 2363c87b03e5Sespie [(set_attr "type" "load") 2364c87b03e5Sespie (set_attr "length" "4")]) 2365c87b03e5Sespie 2366c87b03e5Sespie(define_insn "pre_ldd" 2367c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 2368c87b03e5Sespie (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r") 2369c87b03e5Sespie (match_operand:DI 2 "pre_cint_operand" "")))) 2370c87b03e5Sespie (set (match_dup 1) 2371c87b03e5Sespie (plus:DI (match_dup 1) (match_dup 2)))] 2372c87b03e5Sespie "TARGET_64BIT" 2373c87b03e5Sespie "ldd,mb %2(%1),%0" 2374c87b03e5Sespie [(set_attr "type" "load") 2375c87b03e5Sespie (set_attr "length" "4")]) 2376c87b03e5Sespie 2377c87b03e5Sespie(define_insn "" 2378c87b03e5Sespie [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r") 2379c87b03e5Sespie (match_operand:SI 1 "pre_cint_operand" ""))) 2380c87b03e5Sespie (match_operand:SI 2 "reg_or_0_operand" "rM")) 2381c87b03e5Sespie (set (match_dup 0) 2382c87b03e5Sespie (plus:SI (match_dup 0) (match_dup 1)))] 2383c87b03e5Sespie "" 2384c87b03e5Sespie "* 2385c87b03e5Sespie{ 2386c87b03e5Sespie if (INTVAL (operands[1]) < 0) 2387c87b03e5Sespie return \"{stwm|stw,mb} %r2,%1(%0)\"; 2388c87b03e5Sespie return \"{stws|stw},mb %r2,%1(%0)\"; 2389c87b03e5Sespie}" 2390c87b03e5Sespie [(set_attr "type" "store") 2391c87b03e5Sespie (set_attr "length" "4")]) 2392c87b03e5Sespie 2393c87b03e5Sespie(define_insn "" 2394c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2395c87b03e5Sespie (mem:SI (match_operand:SI 1 "register_operand" "+r"))) 2396c87b03e5Sespie (set (match_dup 1) 2397c87b03e5Sespie (plus:SI (match_dup 1) 2398c87b03e5Sespie (match_operand:SI 2 "post_cint_operand" "")))] 2399c87b03e5Sespie "" 2400c87b03e5Sespie "* 2401c87b03e5Sespie{ 2402c87b03e5Sespie if (INTVAL (operands[2]) > 0) 2403c87b03e5Sespie return \"{ldwm|ldw,ma} %2(%1),%0\"; 2404c87b03e5Sespie return \"{ldws|ldw},ma %2(%1),%0\"; 2405c87b03e5Sespie}" 2406c87b03e5Sespie [(set_attr "type" "load") 2407c87b03e5Sespie (set_attr "length" "4")]) 2408c87b03e5Sespie 2409c87b03e5Sespie(define_expand "post_store" 2410c87b03e5Sespie [(parallel [(set (mem (match_operand 0 "register_operand" "")) 2411c87b03e5Sespie (match_operand 1 "reg_or_0_operand" "")) 2412c87b03e5Sespie (set (match_dup 0) 2413c87b03e5Sespie (plus (match_dup 0) 2414c87b03e5Sespie (match_operand 2 "post_cint_operand" "")))])] 2415c87b03e5Sespie "" 2416c87b03e5Sespie " 2417c87b03e5Sespie{ 2418c87b03e5Sespie if (TARGET_64BIT) 2419c87b03e5Sespie { 2420c87b03e5Sespie emit_insn (gen_post_std (operands[0], operands[1], operands[2])); 2421c87b03e5Sespie DONE; 2422c87b03e5Sespie } 2423c87b03e5Sespie emit_insn (gen_post_stw (operands[0], operands[1], operands[2])); 2424c87b03e5Sespie DONE; 2425c87b03e5Sespie}") 2426c87b03e5Sespie 2427c87b03e5Sespie(define_insn "post_stw" 2428c87b03e5Sespie [(set (mem:SI (match_operand:SI 0 "register_operand" "+r")) 2429c87b03e5Sespie (match_operand:SI 1 "reg_or_0_operand" "rM")) 2430c87b03e5Sespie (set (match_dup 0) 2431c87b03e5Sespie (plus:SI (match_dup 0) 2432c87b03e5Sespie (match_operand:SI 2 "post_cint_operand" "")))] 2433c87b03e5Sespie "" 2434c87b03e5Sespie "* 2435c87b03e5Sespie{ 2436c87b03e5Sespie if (INTVAL (operands[2]) > 0) 2437c87b03e5Sespie return \"{stwm|stw,ma} %r1,%2(%0)\"; 2438c87b03e5Sespie return \"{stws|stw},ma %r1,%2(%0)\"; 2439c87b03e5Sespie}" 2440c87b03e5Sespie [(set_attr "type" "store") 2441c87b03e5Sespie (set_attr "length" "4")]) 2442c87b03e5Sespie 2443c87b03e5Sespie(define_insn "post_std" 2444c87b03e5Sespie [(set (mem:DI (match_operand:DI 0 "register_operand" "+r")) 2445c87b03e5Sespie (match_operand:DI 1 "reg_or_0_operand" "rM")) 2446c87b03e5Sespie (set (match_dup 0) 2447c87b03e5Sespie (plus:DI (match_dup 0) 2448c87b03e5Sespie (match_operand:DI 2 "post_cint_operand" "")))] 2449c87b03e5Sespie "TARGET_64BIT" 2450c87b03e5Sespie "std,ma %r1,%2(%0)" 2451c87b03e5Sespie [(set_attr "type" "store") 2452c87b03e5Sespie (set_attr "length" "4")]) 2453c87b03e5Sespie 2454c87b03e5Sespie;; For loading the address of a label while generating PIC code. 2455c87b03e5Sespie;; Note since this pattern can be created at reload time (via movsi), all 2456c87b03e5Sespie;; the same rules for movsi apply here. (no new pseudos, no temporaries). 2457c87b03e5Sespie(define_insn "" 2458c87b03e5Sespie [(set (match_operand 0 "pmode_register_operand" "=a") 2459c87b03e5Sespie (match_operand 1 "pic_label_operand" ""))] 2460c87b03e5Sespie "" 2461c87b03e5Sespie "* 2462c87b03e5Sespie{ 2463c87b03e5Sespie rtx xoperands[3]; 2464c87b03e5Sespie extern FILE *asm_out_file; 2465c87b03e5Sespie 2466c87b03e5Sespie xoperands[0] = operands[0]; 2467c87b03e5Sespie xoperands[1] = operands[1]; 2468c87b03e5Sespie if (TARGET_SOM || ! TARGET_GAS) 2469c87b03e5Sespie xoperands[2] = gen_label_rtx (); 2470c87b03e5Sespie 2471c87b03e5Sespie output_asm_insn (\"{bl|b,l} .+8,%0\", xoperands); 2472c87b03e5Sespie output_asm_insn (\"{depi|depwi} 0,31,2,%0\", xoperands); 2473c87b03e5Sespie if (TARGET_SOM || ! TARGET_GAS) 2474c87b03e5Sespie ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", 2475c87b03e5Sespie CODE_LABEL_NUMBER (xoperands[2])); 2476c87b03e5Sespie 2477c87b03e5Sespie /* If we're trying to load the address of a label that happens to be 2478c87b03e5Sespie close, then we can use a shorter sequence. */ 2479c87b03e5Sespie if (GET_CODE (operands[1]) == LABEL_REF 2480c87b03e5Sespie && INSN_ADDRESSES_SET_P () 2481c87b03e5Sespie && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0))) 2482c87b03e5Sespie - INSN_ADDRESSES (INSN_UID (insn))) < 8100) 2483c87b03e5Sespie { 2484c87b03e5Sespie /* Prefixing with R% here is wrong, it extracts just 11 bits and is 2485c87b03e5Sespie always non-negative. */ 2486c87b03e5Sespie if (TARGET_SOM || ! TARGET_GAS) 2487c87b03e5Sespie output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands); 2488c87b03e5Sespie else 2489c87b03e5Sespie output_asm_insn (\"ldo %1-$PIC_pcrel$0+8(%0),%0\", xoperands); 2490c87b03e5Sespie } 2491c87b03e5Sespie else 2492c87b03e5Sespie { 2493c87b03e5Sespie if (TARGET_SOM || ! TARGET_GAS) 2494c87b03e5Sespie { 2495c87b03e5Sespie output_asm_insn (\"addil L%%%1-%2,%0\", xoperands); 2496c87b03e5Sespie output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands); 2497c87b03e5Sespie } 2498c87b03e5Sespie else 2499c87b03e5Sespie { 2500c87b03e5Sespie output_asm_insn (\"addil L%%%1-$PIC_pcrel$0+8,%0\", xoperands); 2501c87b03e5Sespie output_asm_insn (\"ldo R%%%1-$PIC_pcrel$0+12(%0),%0\", 2502c87b03e5Sespie xoperands); 2503c87b03e5Sespie } 2504c87b03e5Sespie } 2505c87b03e5Sespie return \"\"; 2506c87b03e5Sespie}" 2507c87b03e5Sespie [(set_attr "type" "multi") 2508c87b03e5Sespie (set_attr "length" "16")]) ; 12 or 16 2509c87b03e5Sespie 2510c87b03e5Sespie(define_insn "" 2511c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=a") 2512c87b03e5Sespie (plus:SI (match_operand:SI 1 "register_operand" "r") 2513c87b03e5Sespie (high:SI (match_operand 2 "" ""))))] 2514c87b03e5Sespie "symbolic_operand (operands[2], Pmode) 2515c87b03e5Sespie && ! function_label_operand (operands[2], Pmode) 2516c87b03e5Sespie && flag_pic" 2517c87b03e5Sespie "addil LT'%G2,%1" 2518c87b03e5Sespie [(set_attr "type" "binary") 2519c87b03e5Sespie (set_attr "length" "4")]) 2520c87b03e5Sespie 2521c87b03e5Sespie(define_insn "" 2522c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=a") 2523c87b03e5Sespie (plus:DI (match_operand:DI 1 "register_operand" "r") 2524c87b03e5Sespie (high:DI (match_operand 2 "" ""))))] 2525c87b03e5Sespie "symbolic_operand (operands[2], Pmode) 2526c87b03e5Sespie && ! function_label_operand (operands[2], Pmode) 2527c87b03e5Sespie && TARGET_64BIT 2528c87b03e5Sespie && flag_pic" 2529c87b03e5Sespie "addil LT'%G2,%1" 2530c87b03e5Sespie [(set_attr "type" "binary") 2531c87b03e5Sespie (set_attr "length" "4")]) 2532c87b03e5Sespie 2533c87b03e5Sespie;; Always use addil rather than ldil;add sequences. This allows the 2534c87b03e5Sespie;; HP linker to eliminate the dp relocation if the symbolic operand 2535c87b03e5Sespie;; lives in the TEXT space. 2536c87b03e5Sespie(define_insn "" 2537c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=a") 2538c87b03e5Sespie (high:SI (match_operand 1 "" "")))] 2539c87b03e5Sespie "symbolic_operand (operands[1], Pmode) 2540c87b03e5Sespie && ! function_label_operand (operands[1], Pmode) 2541c87b03e5Sespie && ! read_only_operand (operands[1], Pmode) 2542c87b03e5Sespie && ! flag_pic" 2543c87b03e5Sespie "* 2544c87b03e5Sespie{ 2545c87b03e5Sespie if (TARGET_LONG_LOAD_STORE) 2546c87b03e5Sespie return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\"; 2547c87b03e5Sespie else 2548c87b03e5Sespie return \"addil LR'%H1,%%r27\"; 2549c87b03e5Sespie}" 2550c87b03e5Sespie [(set_attr "type" "binary") 2551c87b03e5Sespie (set (attr "length") 2552c87b03e5Sespie (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0)) 2553c87b03e5Sespie (const_int 4) 2554c87b03e5Sespie (const_int 8)))]) 2555c87b03e5Sespie 2556c87b03e5Sespie 2557c87b03e5Sespie;; This is for use in the prologue/epilogue code. We need it 2558c87b03e5Sespie;; to add large constants to a stack pointer or frame pointer. 2559c87b03e5Sespie;; Because of the additional %r1 pressure, we probably do not 2560c87b03e5Sespie;; want to use this in general code, so make it available 2561c87b03e5Sespie;; only after reload. 2562c87b03e5Sespie(define_insn "" 2563c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=!a,*r") 2564c87b03e5Sespie (plus:SI (match_operand:SI 1 "register_operand" "r,r") 2565c87b03e5Sespie (high:SI (match_operand 2 "const_int_operand" ""))))] 2566c87b03e5Sespie "reload_completed" 2567c87b03e5Sespie "@ 2568c87b03e5Sespie addil L'%G2,%1 2569c87b03e5Sespie ldil L'%G2,%0\;{addl|add,l} %0,%1,%0" 2570c87b03e5Sespie [(set_attr "type" "binary,binary") 2571c87b03e5Sespie (set_attr "length" "4,8")]) 2572c87b03e5Sespie 2573c87b03e5Sespie(define_insn "" 2574c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=!a,*r") 2575c87b03e5Sespie (plus:DI (match_operand:DI 1 "register_operand" "r,r") 2576c87b03e5Sespie (high:DI (match_operand 2 "const_int_operand" ""))))] 2577c87b03e5Sespie "reload_completed && TARGET_64BIT" 2578c87b03e5Sespie "@ 2579c87b03e5Sespie addil L'%G2,%1 2580c87b03e5Sespie ldil L'%G2,%0\;{addl|add,l} %0,%1,%0" 2581c87b03e5Sespie [(set_attr "type" "binary,binary") 2582c87b03e5Sespie (set_attr "length" "4,8")]) 2583c87b03e5Sespie 2584c87b03e5Sespie(define_insn "" 2585c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2586c87b03e5Sespie (high:SI (match_operand 1 "" "")))] 2587c87b03e5Sespie "(!flag_pic || !symbolic_operand (operands[1], Pmode)) 2588c87b03e5Sespie && !is_function_label_plus_const (operands[1])" 2589c87b03e5Sespie "* 2590c87b03e5Sespie{ 2591c87b03e5Sespie if (symbolic_operand (operands[1], Pmode)) 2592c87b03e5Sespie return \"ldil LR'%H1,%0\"; 2593c87b03e5Sespie else 2594c87b03e5Sespie return \"ldil L'%G1,%0\"; 2595c87b03e5Sespie}" 2596c87b03e5Sespie [(set_attr "type" "move") 2597c87b03e5Sespie (set_attr "length" "4")]) 2598c87b03e5Sespie 2599c87b03e5Sespie(define_insn "" 2600c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 2601c87b03e5Sespie (high:DI (match_operand 1 "const_int_operand" "")))] 2602c87b03e5Sespie "TARGET_64BIT" 2603c87b03e5Sespie "ldil L'%G1,%0"; 2604c87b03e5Sespie [(set_attr "type" "move") 2605c87b03e5Sespie (set_attr "length" "4")]) 2606c87b03e5Sespie 2607c87b03e5Sespie(define_insn "" 2608c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 2609c87b03e5Sespie (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 2610c87b03e5Sespie (match_operand:DI 2 "const_int_operand" "i")))] 2611c87b03e5Sespie "TARGET_64BIT" 2612c87b03e5Sespie "ldo R'%G2(%1),%0"; 2613c87b03e5Sespie [(set_attr "type" "move") 2614c87b03e5Sespie (set_attr "length" "4")]) 2615c87b03e5Sespie 2616c87b03e5Sespie(define_insn "" 2617c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2618c87b03e5Sespie (lo_sum:SI (match_operand:SI 1 "register_operand" "r") 2619c87b03e5Sespie (match_operand:SI 2 "immediate_operand" "i")))] 2620c87b03e5Sespie "!is_function_label_plus_const (operands[2])" 2621c87b03e5Sespie "* 2622c87b03e5Sespie{ 2623c87b03e5Sespie if (flag_pic && symbolic_operand (operands[2], Pmode)) 2624c87b03e5Sespie abort (); 2625c87b03e5Sespie else if (symbolic_operand (operands[2], Pmode)) 2626c87b03e5Sespie return \"ldo RR'%G2(%1),%0\"; 2627c87b03e5Sespie else 2628c87b03e5Sespie return \"ldo R'%G2(%1),%0\"; 2629c87b03e5Sespie}" 2630c87b03e5Sespie [(set_attr "type" "move") 2631c87b03e5Sespie (set_attr "length" "4")]) 2632c87b03e5Sespie 2633c87b03e5Sespie;; Now that a symbolic_address plus a constant is broken up early 2634c87b03e5Sespie;; in the compilation phase (for better CSE) we need a special 2635c87b03e5Sespie;; combiner pattern to load the symbolic address plus the constant 2636c87b03e5Sespie;; in only 2 instructions. (For cases where the symbolic address 2637c87b03e5Sespie;; was not a common subexpression.) 2638c87b03e5Sespie(define_split 2639c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 2640c87b03e5Sespie (match_operand:SI 1 "symbolic_operand" "")) 2641c87b03e5Sespie (clobber (match_operand:SI 2 "register_operand" ""))] 2642c87b03e5Sespie "! (flag_pic && pic_label_operand (operands[1], SImode))" 2643c87b03e5Sespie [(set (match_dup 2) (high:SI (match_dup 1))) 2644c87b03e5Sespie (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))] 2645c87b03e5Sespie "") 2646c87b03e5Sespie 2647c87b03e5Sespie;; hppa_legitimize_address goes to a great deal of trouble to 2648c87b03e5Sespie;; create addresses which use indexing. In some cases, this 2649c87b03e5Sespie;; is a lose because there isn't any store instructions which 2650c87b03e5Sespie;; allow indexed addresses (with integer register source). 2651c87b03e5Sespie;; 2652c87b03e5Sespie;; These define_splits try to turn a 3 insn store into 2653c87b03e5Sespie;; a 2 insn store with some creative RTL rewriting. 2654c87b03e5Sespie(define_split 2655c87b03e5Sespie [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "") 2656c87b03e5Sespie (match_operand:SI 1 "shadd_operand" "")) 2657c87b03e5Sespie (plus:SI (match_operand:SI 2 "register_operand" "") 2658c87b03e5Sespie (match_operand:SI 3 "const_int_operand" "")))) 2659c87b03e5Sespie (match_operand:SI 4 "register_operand" "")) 2660c87b03e5Sespie (clobber (match_operand:SI 5 "register_operand" ""))] 2661c87b03e5Sespie "" 2662c87b03e5Sespie [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) 2663c87b03e5Sespie (match_dup 2))) 2664c87b03e5Sespie (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))] 2665c87b03e5Sespie "") 2666c87b03e5Sespie 2667c87b03e5Sespie(define_split 2668c87b03e5Sespie [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "") 2669c87b03e5Sespie (match_operand:SI 1 "shadd_operand" "")) 2670c87b03e5Sespie (plus:SI (match_operand:SI 2 "register_operand" "") 2671c87b03e5Sespie (match_operand:SI 3 "const_int_operand" "")))) 2672c87b03e5Sespie (match_operand:HI 4 "register_operand" "")) 2673c87b03e5Sespie (clobber (match_operand:SI 5 "register_operand" ""))] 2674c87b03e5Sespie "" 2675c87b03e5Sespie [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) 2676c87b03e5Sespie (match_dup 2))) 2677c87b03e5Sespie (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))] 2678c87b03e5Sespie "") 2679c87b03e5Sespie 2680c87b03e5Sespie(define_split 2681c87b03e5Sespie [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "") 2682c87b03e5Sespie (match_operand:SI 1 "shadd_operand" "")) 2683c87b03e5Sespie (plus:SI (match_operand:SI 2 "register_operand" "") 2684c87b03e5Sespie (match_operand:SI 3 "const_int_operand" "")))) 2685c87b03e5Sespie (match_operand:QI 4 "register_operand" "")) 2686c87b03e5Sespie (clobber (match_operand:SI 5 "register_operand" ""))] 2687c87b03e5Sespie "" 2688c87b03e5Sespie [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) 2689c87b03e5Sespie (match_dup 2))) 2690c87b03e5Sespie (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))] 2691c87b03e5Sespie "") 2692c87b03e5Sespie 2693c87b03e5Sespie(define_expand "movhi" 2694c87b03e5Sespie [(set (match_operand:HI 0 "general_operand" "") 2695c87b03e5Sespie (match_operand:HI 1 "general_operand" ""))] 2696c87b03e5Sespie "" 2697c87b03e5Sespie " 2698c87b03e5Sespie{ 2699c87b03e5Sespie if (emit_move_sequence (operands, HImode, 0)) 2700c87b03e5Sespie DONE; 2701c87b03e5Sespie}") 2702c87b03e5Sespie 2703c87b03e5Sespie(define_insn "" 27044e43c760Sespie [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" 27054e43c760Sespie "=r,r,r,r,r,Q,!*q,!r,!*f") 27064e43c760Sespie (match_operand:HI 1 "move_operand" 27074e43c760Sespie "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))] 2708c87b03e5Sespie "register_operand (operands[0], HImode) 2709c87b03e5Sespie || reg_or_0_operand (operands[1], HImode)" 2710c87b03e5Sespie "@ 2711c87b03e5Sespie copy %1,%0 2712c87b03e5Sespie ldi %1,%0 2713c87b03e5Sespie ldil L'%1,%0 2714c87b03e5Sespie {zdepi|depwi,z} %Z1,%0 2715c87b03e5Sespie ldh%M1 %1,%0 2716c87b03e5Sespie sth%M0 %r1,%0 2717c87b03e5Sespie mtsar %r1 27184e43c760Sespie {mfctl|mfctl,w} %sar,%0 2719c87b03e5Sespie fcpy,sgl %f1,%0" 27204e43c760Sespie [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu") 2721c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 27224e43c760Sespie (set_attr "length" "4,4,4,4,4,4,4,4,4")]) 2723c87b03e5Sespie 2724c87b03e5Sespie(define_insn "" 2725c87b03e5Sespie [(set (match_operand:HI 0 "register_operand" "=r") 2726c87b03e5Sespie (mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r") 2727c87b03e5Sespie (match_operand:SI 2 "register_operand" "r"))))] 2728c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2729c87b03e5Sespie "{ldhx|ldh} %2(%1),%0" 2730c87b03e5Sespie [(set_attr "type" "load") 2731c87b03e5Sespie (set_attr "length" "4")]) 2732c87b03e5Sespie 2733c87b03e5Sespie(define_insn "" 2734c87b03e5Sespie [(set (match_operand:HI 0 "register_operand" "=r") 2735c87b03e5Sespie (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r") 2736c87b03e5Sespie (match_operand:SI 2 "basereg_operand" "r"))))] 2737c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2738c87b03e5Sespie "{ldhx|ldh} %1(%2),%0" 2739c87b03e5Sespie [(set_attr "type" "load") 2740c87b03e5Sespie (set_attr "length" "4")]) 2741c87b03e5Sespie 2742c87b03e5Sespie; Now zero extended variants. 2743c87b03e5Sespie(define_insn "" 2744c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2745c87b03e5Sespie (zero_extend:SI (mem:HI 2746c87b03e5Sespie (plus:SI 2747c87b03e5Sespie (match_operand:SI 1 "basereg_operand" "r") 2748c87b03e5Sespie (match_operand:SI 2 "register_operand" "r")))))] 2749c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2750c87b03e5Sespie "{ldhx|ldh} %2(%1),%0" 2751c87b03e5Sespie [(set_attr "type" "load") 2752c87b03e5Sespie (set_attr "length" "4")]) 2753c87b03e5Sespie 2754c87b03e5Sespie(define_insn "" 2755c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2756c87b03e5Sespie (zero_extend:SI (mem:HI 2757c87b03e5Sespie (plus:SI 2758c87b03e5Sespie (match_operand:SI 1 "register_operand" "r") 2759c87b03e5Sespie (match_operand:SI 2 "basereg_operand" "r")))))] 2760c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2761c87b03e5Sespie "{ldhx|ldh} %1(%2),%0" 2762c87b03e5Sespie [(set_attr "type" "load") 2763c87b03e5Sespie (set_attr "length" "4")]) 2764c87b03e5Sespie 2765c87b03e5Sespie(define_insn "" 2766c87b03e5Sespie [(set (match_operand:HI 0 "register_operand" "=r") 2767c87b03e5Sespie (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r") 2768c87b03e5Sespie (match_operand:SI 2 "int5_operand" "L")))) 2769c87b03e5Sespie (set (match_dup 1) 2770c87b03e5Sespie (plus:SI (match_dup 1) (match_dup 2)))] 2771c87b03e5Sespie "" 2772c87b03e5Sespie "{ldhs|ldh},mb %2(%1),%0" 2773c87b03e5Sespie [(set_attr "type" "load") 2774c87b03e5Sespie (set_attr "length" "4")]) 2775c87b03e5Sespie 2776c87b03e5Sespie; And a zero extended variant. 2777c87b03e5Sespie(define_insn "" 2778c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2779c87b03e5Sespie (zero_extend:SI (mem:HI 2780c87b03e5Sespie (plus:SI 2781c87b03e5Sespie (match_operand:SI 1 "register_operand" "+r") 2782c87b03e5Sespie (match_operand:SI 2 "int5_operand" "L"))))) 2783c87b03e5Sespie (set (match_dup 1) 2784c87b03e5Sespie (plus:SI (match_dup 1) (match_dup 2)))] 2785c87b03e5Sespie "" 2786c87b03e5Sespie "{ldhs|ldh},mb %2(%1),%0" 2787c87b03e5Sespie [(set_attr "type" "load") 2788c87b03e5Sespie (set_attr "length" "4")]) 2789c87b03e5Sespie 2790c87b03e5Sespie(define_insn "" 2791c87b03e5Sespie [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r") 2792c87b03e5Sespie (match_operand:SI 1 "int5_operand" "L"))) 2793c87b03e5Sespie (match_operand:HI 2 "reg_or_0_operand" "rM")) 2794c87b03e5Sespie (set (match_dup 0) 2795c87b03e5Sespie (plus:SI (match_dup 0) (match_dup 1)))] 2796c87b03e5Sespie "" 2797c87b03e5Sespie "{sths|sth},mb %r2,%1(%0)" 2798c87b03e5Sespie [(set_attr "type" "store") 2799c87b03e5Sespie (set_attr "length" "4")]) 2800c87b03e5Sespie 2801c87b03e5Sespie(define_insn "" 2802c87b03e5Sespie [(set (match_operand:HI 0 "register_operand" "=r") 2803c87b03e5Sespie (plus:HI (match_operand:HI 1 "register_operand" "r") 2804c87b03e5Sespie (match_operand 2 "const_int_operand" "J")))] 2805c87b03e5Sespie "" 2806c87b03e5Sespie "ldo %2(%1),%0" 2807c87b03e5Sespie [(set_attr "type" "binary") 2808c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 2809c87b03e5Sespie (set_attr "length" "4")]) 2810c87b03e5Sespie 2811c87b03e5Sespie(define_expand "movqi" 2812c87b03e5Sespie [(set (match_operand:QI 0 "general_operand" "") 2813c87b03e5Sespie (match_operand:QI 1 "general_operand" ""))] 2814c87b03e5Sespie "" 2815c87b03e5Sespie " 2816c87b03e5Sespie{ 2817c87b03e5Sespie if (emit_move_sequence (operands, QImode, 0)) 2818c87b03e5Sespie DONE; 2819c87b03e5Sespie}") 2820c87b03e5Sespie 2821c87b03e5Sespie(define_insn "" 28224e43c760Sespie [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" 28234e43c760Sespie "=r,r,r,r,r,Q,!*q,!r,!*f") 28244e43c760Sespie (match_operand:QI 1 "move_operand" 28254e43c760Sespie "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))] 2826c87b03e5Sespie "register_operand (operands[0], QImode) 2827c87b03e5Sespie || reg_or_0_operand (operands[1], QImode)" 2828c87b03e5Sespie "@ 2829c87b03e5Sespie copy %1,%0 2830c87b03e5Sespie ldi %1,%0 2831c87b03e5Sespie ldil L'%1,%0 2832c87b03e5Sespie {zdepi|depwi,z} %Z1,%0 2833c87b03e5Sespie ldb%M1 %1,%0 2834c87b03e5Sespie stb%M0 %r1,%0 2835c87b03e5Sespie mtsar %r1 28364e43c760Sespie {mfctl|mfctl,w} %%sar,%0 2837c87b03e5Sespie fcpy,sgl %f1,%0" 28384e43c760Sespie [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu") 2839c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 28404e43c760Sespie (set_attr "length" "4,4,4,4,4,4,4,4,4")]) 2841c87b03e5Sespie 2842c87b03e5Sespie(define_insn "" 2843c87b03e5Sespie [(set (match_operand:QI 0 "register_operand" "=r") 2844c87b03e5Sespie (mem:QI (plus:SI (match_operand:SI 1 "basereg_operand" "r") 2845c87b03e5Sespie (match_operand:SI 2 "register_operand" "r"))))] 2846c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2847c87b03e5Sespie "{ldbx|ldb} %2(%1),%0" 2848c87b03e5Sespie [(set_attr "type" "load") 2849c87b03e5Sespie (set_attr "length" "4")]) 2850c87b03e5Sespie 2851c87b03e5Sespie(define_insn "" 2852c87b03e5Sespie [(set (match_operand:QI 0 "register_operand" "=r") 2853c87b03e5Sespie (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r") 2854c87b03e5Sespie (match_operand:SI 2 "basereg_operand" "r"))))] 2855c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2856c87b03e5Sespie "{ldbx|ldb} %1(%2),%0" 2857c87b03e5Sespie [(set_attr "type" "load") 2858c87b03e5Sespie (set_attr "length" "4")]) 2859c87b03e5Sespie 2860c87b03e5Sespie; Indexed byte load with zero extension to SImode or HImode. 2861c87b03e5Sespie(define_insn "" 2862c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2863c87b03e5Sespie (zero_extend:SI (mem:QI 2864c87b03e5Sespie (plus:SI 2865c87b03e5Sespie (match_operand:SI 1 "basereg_operand" "r") 2866c87b03e5Sespie (match_operand:SI 2 "register_operand" "r")))))] 2867c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2868c87b03e5Sespie "{ldbx|ldb} %2(%1),%0" 2869c87b03e5Sespie [(set_attr "type" "load") 2870c87b03e5Sespie (set_attr "length" "4")]) 2871c87b03e5Sespie 2872c87b03e5Sespie(define_insn "" 2873c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2874c87b03e5Sespie (zero_extend:SI (mem:QI 2875c87b03e5Sespie (plus:SI 2876c87b03e5Sespie (match_operand:SI 1 "register_operand" "r") 2877c87b03e5Sespie (match_operand:SI 2 "basereg_operand" "r")))))] 2878c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2879c87b03e5Sespie "{ldbx|ldb} %1(%2),%0" 2880c87b03e5Sespie [(set_attr "type" "load") 2881c87b03e5Sespie (set_attr "length" "4")]) 2882c87b03e5Sespie 2883c87b03e5Sespie(define_insn "" 2884c87b03e5Sespie [(set (match_operand:HI 0 "register_operand" "=r") 2885c87b03e5Sespie (zero_extend:HI (mem:QI 2886c87b03e5Sespie (plus:SI 2887c87b03e5Sespie (match_operand:SI 1 "basereg_operand" "r") 2888c87b03e5Sespie (match_operand:SI 2 "register_operand" "r")))))] 2889c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2890c87b03e5Sespie "{ldbx|ldb} %2(%1),%0" 2891c87b03e5Sespie [(set_attr "type" "load") 2892c87b03e5Sespie (set_attr "length" "4")]) 2893c87b03e5Sespie 2894c87b03e5Sespie(define_insn "" 2895c87b03e5Sespie [(set (match_operand:HI 0 "register_operand" "=r") 2896c87b03e5Sespie (zero_extend:HI (mem:QI 2897c87b03e5Sespie (plus:SI 2898c87b03e5Sespie (match_operand:SI 1 "register_operand" "r") 2899c87b03e5Sespie (match_operand:SI 2 "basereg_operand" "r")))))] 2900c87b03e5Sespie "! TARGET_DISABLE_INDEXING" 2901c87b03e5Sespie "{ldbx|ldb} %1(%2),%0" 2902c87b03e5Sespie [(set_attr "type" "load") 2903c87b03e5Sespie (set_attr "length" "4")]) 2904c87b03e5Sespie 2905c87b03e5Sespie(define_insn "" 2906c87b03e5Sespie [(set (match_operand:QI 0 "register_operand" "=r") 2907c87b03e5Sespie (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r") 2908c87b03e5Sespie (match_operand:SI 2 "int5_operand" "L")))) 2909c87b03e5Sespie (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))] 2910c87b03e5Sespie "" 2911c87b03e5Sespie "{ldbs|ldb},mb %2(%1),%0" 2912c87b03e5Sespie [(set_attr "type" "load") 2913c87b03e5Sespie (set_attr "length" "4")]) 2914c87b03e5Sespie 2915c87b03e5Sespie; Now the same thing with zero extensions. 2916c87b03e5Sespie(define_insn "" 2917c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 2918c87b03e5Sespie (zero_extend:SI (mem:QI (plus:SI 2919c87b03e5Sespie (match_operand:SI 1 "register_operand" "+r") 2920c87b03e5Sespie (match_operand:SI 2 "int5_operand" "L"))))) 2921c87b03e5Sespie (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))] 2922c87b03e5Sespie "" 2923c87b03e5Sespie "{ldbs|ldb},mb %2(%1),%0" 2924c87b03e5Sespie [(set_attr "type" "load") 2925c87b03e5Sespie (set_attr "length" "4")]) 2926c87b03e5Sespie 2927c87b03e5Sespie(define_insn "" 2928c87b03e5Sespie [(set (match_operand:HI 0 "register_operand" "=r") 2929c87b03e5Sespie (zero_extend:HI (mem:QI (plus:SI 2930c87b03e5Sespie (match_operand:SI 1 "register_operand" "+r") 2931c87b03e5Sespie (match_operand:SI 2 "int5_operand" "L"))))) 2932c87b03e5Sespie (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))] 2933c87b03e5Sespie "" 2934c87b03e5Sespie "{ldbs|ldb},mb %2(%1),%0" 2935c87b03e5Sespie [(set_attr "type" "load") 2936c87b03e5Sespie (set_attr "length" "4")]) 2937c87b03e5Sespie 2938c87b03e5Sespie(define_insn "" 2939c87b03e5Sespie [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r") 2940c87b03e5Sespie (match_operand:SI 1 "int5_operand" "L"))) 2941c87b03e5Sespie (match_operand:QI 2 "reg_or_0_operand" "rM")) 2942c87b03e5Sespie (set (match_dup 0) 2943c87b03e5Sespie (plus:SI (match_dup 0) (match_dup 1)))] 2944c87b03e5Sespie "" 2945c87b03e5Sespie "{stbs|stb},mb %r2,%1(%0)" 2946c87b03e5Sespie [(set_attr "type" "store") 2947c87b03e5Sespie (set_attr "length" "4")]) 2948c87b03e5Sespie 2949c87b03e5Sespie;; The definition of this insn does not really explain what it does, 2950c87b03e5Sespie;; but it should suffice 2951c87b03e5Sespie;; that anything generated as this insn will be recognized as one 2952c87b03e5Sespie;; and that it will not successfully combine with anything. 2953c87b03e5Sespie(define_expand "movstrsi" 2954c87b03e5Sespie [(parallel [(set (match_operand:BLK 0 "" "") 2955c87b03e5Sespie (match_operand:BLK 1 "" "")) 2956c87b03e5Sespie (clobber (match_dup 7)) 2957c87b03e5Sespie (clobber (match_dup 8)) 2958c87b03e5Sespie (clobber (match_dup 4)) 2959c87b03e5Sespie (clobber (match_dup 5)) 2960c87b03e5Sespie (clobber (match_dup 6)) 2961c87b03e5Sespie (use (match_operand:SI 2 "arith_operand" "")) 2962c87b03e5Sespie (use (match_operand:SI 3 "const_int_operand" ""))])] 2963c87b03e5Sespie "!TARGET_64BIT" 2964c87b03e5Sespie " 2965c87b03e5Sespie{ 2966c87b03e5Sespie int size, align; 2967c87b03e5Sespie 2968c87b03e5Sespie /* HP provides very fast block move library routine for the PA; 2969c87b03e5Sespie this routine includes: 2970c87b03e5Sespie 2971c87b03e5Sespie 4x4 byte at a time block moves, 2972c87b03e5Sespie 1x4 byte at a time with alignment checked at runtime with 2973c87b03e5Sespie attempts to align the source and destination as needed 2974c87b03e5Sespie 1x1 byte loop 2975c87b03e5Sespie 2976c87b03e5Sespie With that in mind, here's the heuristics to try and guess when 2977c87b03e5Sespie the inlined block move will be better than the library block 2978c87b03e5Sespie move: 2979c87b03e5Sespie 2980c87b03e5Sespie If the size isn't constant, then always use the library routines. 2981c87b03e5Sespie 2982c87b03e5Sespie If the size is large in respect to the known alignment, then use 2983c87b03e5Sespie the library routines. 2984c87b03e5Sespie 2985c87b03e5Sespie If the size is small in repsect to the known alignment, then open 2986c87b03e5Sespie code the copy (since that will lead to better scheduling). 2987c87b03e5Sespie 2988c87b03e5Sespie Else use the block move pattern. */ 2989c87b03e5Sespie 2990c87b03e5Sespie /* Undetermined size, use the library routine. */ 2991c87b03e5Sespie if (GET_CODE (operands[2]) != CONST_INT) 2992c87b03e5Sespie FAIL; 2993c87b03e5Sespie 2994c87b03e5Sespie size = INTVAL (operands[2]); 2995c87b03e5Sespie align = INTVAL (operands[3]); 2996c87b03e5Sespie align = align > 4 ? 4 : align; 2997c87b03e5Sespie 2998c87b03e5Sespie /* If size/alignment > 8 (eg size is large in respect to alignment), 2999c87b03e5Sespie then use the library routines. */ 3000c87b03e5Sespie if (size / align > 16) 3001c87b03e5Sespie FAIL; 3002c87b03e5Sespie 3003c87b03e5Sespie /* This does happen, but not often enough to worry much about. */ 3004c87b03e5Sespie if (size / align < MOVE_RATIO) 3005c87b03e5Sespie FAIL; 3006c87b03e5Sespie 3007c87b03e5Sespie /* Fall through means we're going to use our block move pattern. */ 3008c87b03e5Sespie operands[0] 3009c87b03e5Sespie = replace_equiv_address (operands[0], 3010c87b03e5Sespie copy_to_mode_reg (SImode, XEXP (operands[0], 0))); 3011c87b03e5Sespie operands[1] 3012c87b03e5Sespie = replace_equiv_address (operands[1], 3013c87b03e5Sespie copy_to_mode_reg (SImode, XEXP (operands[1], 0))); 3014c87b03e5Sespie operands[4] = gen_reg_rtx (SImode); 3015c87b03e5Sespie operands[5] = gen_reg_rtx (SImode); 3016c87b03e5Sespie operands[6] = gen_reg_rtx (SImode); 3017c87b03e5Sespie operands[7] = XEXP (operands[0], 0); 3018c87b03e5Sespie operands[8] = XEXP (operands[1], 0); 3019c87b03e5Sespie}") 3020c87b03e5Sespie 3021c87b03e5Sespie;; The operand constraints are written like this to support both compile-time 3022c87b03e5Sespie;; and run-time determined byte count. If the count is run-time determined, 3023c87b03e5Sespie;; the register with the byte count is clobbered by the copying code, and 3024c87b03e5Sespie;; therefore it is forced to operand 2. If the count is compile-time 3025c87b03e5Sespie;; determined, we need two scratch registers for the unrolled code. 3026c87b03e5Sespie(define_insn "movstrsi_internal" 3027c87b03e5Sespie [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r")) 3028c87b03e5Sespie (mem:BLK (match_operand:SI 1 "register_operand" "+r,r"))) 3029c87b03e5Sespie (clobber (match_dup 0)) 3030c87b03e5Sespie (clobber (match_dup 1)) 3031c87b03e5Sespie (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp 3032c87b03e5Sespie (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp 3033c87b03e5Sespie (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2 3034c87b03e5Sespie (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count 3035c87b03e5Sespie (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment 3036c87b03e5Sespie "!TARGET_64BIT" 3037c87b03e5Sespie "* return output_block_move (operands, !which_alternative);" 3038c87b03e5Sespie [(set_attr "type" "multi,multi")]) 3039c87b03e5Sespie 3040c87b03e5Sespie;; Floating point move insns 3041c87b03e5Sespie 3042c87b03e5Sespie;; This pattern forces (set (reg:DF ...) (const_double ...)) 3043c87b03e5Sespie;; to be reloaded by putting the constant into memory when 3044c87b03e5Sespie;; reg is a floating point register. 3045c87b03e5Sespie;; 3046c87b03e5Sespie;; For integer registers we use ldil;ldo to set the appropriate 3047c87b03e5Sespie;; value. 3048c87b03e5Sespie;; 3049c87b03e5Sespie;; This must come before the movdf pattern, and it must be present 3050c87b03e5Sespie;; to handle obscure reloading cases. 3051c87b03e5Sespie(define_insn "" 3052c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=?r,f") 3053c87b03e5Sespie (match_operand:DF 1 "" "?F,m"))] 3054c87b03e5Sespie "GET_CODE (operands[1]) == CONST_DOUBLE 3055c87b03e5Sespie && operands[1] != CONST0_RTX (DFmode) 3056c87b03e5Sespie && !TARGET_64BIT 3057c87b03e5Sespie && ! TARGET_SOFT_FLOAT" 3058c87b03e5Sespie "* return (which_alternative == 0 ? output_move_double (operands) 3059c87b03e5Sespie : \"fldd%F1 %1,%0\");" 3060c87b03e5Sespie [(set_attr "type" "move,fpload") 3061c87b03e5Sespie (set_attr "length" "16,4")]) 3062c87b03e5Sespie 3063c87b03e5Sespie(define_expand "movdf" 3064c87b03e5Sespie [(set (match_operand:DF 0 "general_operand" "") 3065c87b03e5Sespie (match_operand:DF 1 "general_operand" ""))] 3066c87b03e5Sespie "" 3067c87b03e5Sespie " 3068c87b03e5Sespie{ 3069c87b03e5Sespie if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT) 3070c87b03e5Sespie operands[1] = force_const_mem (DFmode, operands[1]); 3071c87b03e5Sespie 3072c87b03e5Sespie if (emit_move_sequence (operands, DFmode, 0)) 3073c87b03e5Sespie DONE; 3074c87b03e5Sespie}") 3075c87b03e5Sespie 3076c87b03e5Sespie;; Reloading an SImode or DImode value requires a scratch register if 3077c87b03e5Sespie;; going in to or out of float point registers. 3078c87b03e5Sespie 3079c87b03e5Sespie(define_expand "reload_indf" 3080c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=Z") 3081c87b03e5Sespie (match_operand:DF 1 "non_hard_reg_operand" "")) 3082c87b03e5Sespie (clobber (match_operand:DF 2 "register_operand" "=&r"))] 3083c87b03e5Sespie "" 3084c87b03e5Sespie " 3085c87b03e5Sespie{ 3086c87b03e5Sespie if (emit_move_sequence (operands, DFmode, operands[2])) 3087c87b03e5Sespie DONE; 3088c87b03e5Sespie 3089c87b03e5Sespie /* We don't want the clobber emitted, so handle this ourselves. */ 3090c87b03e5Sespie emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 3091c87b03e5Sespie DONE; 3092c87b03e5Sespie}") 3093c87b03e5Sespie 3094c87b03e5Sespie(define_expand "reload_outdf" 3095c87b03e5Sespie [(set (match_operand:DF 0 "non_hard_reg_operand" "") 3096c87b03e5Sespie (match_operand:DF 1 "register_operand" "Z")) 3097c87b03e5Sespie (clobber (match_operand:DF 2 "register_operand" "=&r"))] 3098c87b03e5Sespie "" 3099c87b03e5Sespie " 3100c87b03e5Sespie{ 3101c87b03e5Sespie if (emit_move_sequence (operands, DFmode, operands[2])) 3102c87b03e5Sespie DONE; 3103c87b03e5Sespie 3104c87b03e5Sespie /* We don't want the clobber emitted, so handle this ourselves. */ 3105c87b03e5Sespie emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 3106c87b03e5Sespie DONE; 3107c87b03e5Sespie}") 3108c87b03e5Sespie 3109c87b03e5Sespie(define_insn "" 3110c87b03e5Sespie [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" 3111c87b03e5Sespie "=f,*r,RQ,?o,?Q,f,*r,*r") 3112c87b03e5Sespie (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand" 3113c87b03e5Sespie "fG,*rG,f,*r,*r,RQ,o,RQ"))] 3114c87b03e5Sespie "(register_operand (operands[0], DFmode) 3115c87b03e5Sespie || reg_or_0_operand (operands[1], DFmode)) 3116c87b03e5Sespie && ! (GET_CODE (operands[1]) == CONST_DOUBLE 3117c87b03e5Sespie && GET_CODE (operands[0]) == MEM) 3118c87b03e5Sespie && ! TARGET_64BIT 3119c87b03e5Sespie && ! TARGET_SOFT_FLOAT" 3120c87b03e5Sespie "* 3121c87b03e5Sespie{ 3122c87b03e5Sespie if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]) 3123c87b03e5Sespie || operands[1] == CONST0_RTX (DFmode)) 3124c87b03e5Sespie return output_fp_move_double (operands); 3125c87b03e5Sespie return output_move_double (operands); 3126c87b03e5Sespie}" 3127c87b03e5Sespie [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load") 3128c87b03e5Sespie (set_attr "length" "4,8,4,8,16,4,8,16")]) 3129c87b03e5Sespie 3130c87b03e5Sespie(define_insn "" 3131c87b03e5Sespie [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" 3132c87b03e5Sespie "=r,?o,?Q,r,r") 3133c87b03e5Sespie (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand" 3134c87b03e5Sespie "rG,r,r,o,Q"))] 3135c87b03e5Sespie "(register_operand (operands[0], DFmode) 3136c87b03e5Sespie || reg_or_0_operand (operands[1], DFmode)) 3137c87b03e5Sespie && ! TARGET_64BIT 3138c87b03e5Sespie && TARGET_SOFT_FLOAT" 3139c87b03e5Sespie "* 3140c87b03e5Sespie{ 3141c87b03e5Sespie return output_move_double (operands); 3142c87b03e5Sespie}" 3143c87b03e5Sespie [(set_attr "type" "move,store,store,load,load") 3144c87b03e5Sespie (set_attr "length" "8,8,16,8,16")]) 3145c87b03e5Sespie 3146c87b03e5Sespie(define_insn "" 3147c87b03e5Sespie [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" 31484e43c760Sespie "=r,r,r,r,r,Q,!f,f,*TR") 3149c87b03e5Sespie (match_operand:DF 1 "move_operand" 31504e43c760Sespie "r,J,N,K,RQ,rM,!fM,*RT,f"))] 3151c87b03e5Sespie "(register_operand (operands[0], DFmode) 3152c87b03e5Sespie || reg_or_0_operand (operands[1], DFmode)) 3153c87b03e5Sespie && ! TARGET_SOFT_FLOAT && TARGET_64BIT" 3154c87b03e5Sespie "@ 3155c87b03e5Sespie copy %1,%0 3156c87b03e5Sespie ldi %1,%0 3157c87b03e5Sespie ldil L'%1,%0 3158c87b03e5Sespie depdi,z %z1,%0 3159c87b03e5Sespie ldd%M1 %1,%0 3160c87b03e5Sespie std%M0 %r1,%0 3161c87b03e5Sespie fcpy,dbl %f1,%0 3162c87b03e5Sespie fldd%F1 %1,%0 3163c87b03e5Sespie fstd%F0 %1,%0" 31644e43c760Sespie [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore") 3165c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 31664e43c760Sespie (set_attr "length" "4,4,4,4,4,4,4,4,4")]) 3167c87b03e5Sespie 3168c87b03e5Sespie(define_insn "" 3169c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=fx") 3170c87b03e5Sespie (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r") 3171c87b03e5Sespie (match_operand:SI 2 "register_operand" "r"))))] 3172c87b03e5Sespie "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT" 3173c87b03e5Sespie "{flddx|fldd} %2(%1),%0" 3174c87b03e5Sespie [(set_attr "type" "fpload") 3175c87b03e5Sespie (set_attr "length" "4")]) 3176c87b03e5Sespie 3177c87b03e5Sespie(define_insn "" 3178c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=fx") 3179c87b03e5Sespie (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r") 3180c87b03e5Sespie (match_operand:SI 2 "basereg_operand" "r"))))] 3181c87b03e5Sespie "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT" 3182c87b03e5Sespie "{flddx|fldd} %1(%2),%0" 3183c87b03e5Sespie [(set_attr "type" "fpload") 3184c87b03e5Sespie (set_attr "length" "4")]) 3185c87b03e5Sespie 3186c87b03e5Sespie(define_insn "" 3187c87b03e5Sespie [(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r") 3188c87b03e5Sespie (match_operand:SI 2 "register_operand" "r"))) 3189c87b03e5Sespie (match_operand:DF 0 "register_operand" "fx"))] 3190c87b03e5Sespie "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT" 3191c87b03e5Sespie "{fstdx|fstd} %0,%2(%1)" 3192c87b03e5Sespie [(set_attr "type" "fpstore") 3193c87b03e5Sespie (set_attr "length" "4")]) 3194c87b03e5Sespie 3195c87b03e5Sespie(define_insn "" 3196c87b03e5Sespie [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r") 3197c87b03e5Sespie (match_operand:SI 2 "basereg_operand" "r"))) 3198c87b03e5Sespie (match_operand:DF 0 "register_operand" "fx"))] 3199c87b03e5Sespie "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT" 3200c87b03e5Sespie "{fstdx|fstd} %0,%1(%2)" 3201c87b03e5Sespie [(set_attr "type" "fpstore") 3202c87b03e5Sespie (set_attr "length" "4")]) 3203c87b03e5Sespie 3204c87b03e5Sespie(define_expand "movdi" 3205c87b03e5Sespie [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "") 3206c87b03e5Sespie (match_operand:DI 1 "general_operand" ""))] 3207c87b03e5Sespie "" 3208c87b03e5Sespie " 3209c87b03e5Sespie{ 3210c87b03e5Sespie if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT) 3211c87b03e5Sespie operands[1] = force_const_mem (DImode, operands[1]); 3212c87b03e5Sespie 3213c87b03e5Sespie if (emit_move_sequence (operands, DImode, 0)) 3214c87b03e5Sespie DONE; 3215c87b03e5Sespie}") 3216c87b03e5Sespie 3217c87b03e5Sespie(define_expand "reload_indi" 3218c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=Z") 3219c87b03e5Sespie (match_operand:DI 1 "non_hard_reg_operand" "")) 3220c87b03e5Sespie (clobber (match_operand:SI 2 "register_operand" "=&r"))] 3221c87b03e5Sespie "" 3222c87b03e5Sespie " 3223c87b03e5Sespie{ 3224c87b03e5Sespie if (emit_move_sequence (operands, DImode, operands[2])) 3225c87b03e5Sespie DONE; 3226c87b03e5Sespie 3227c87b03e5Sespie /* We don't want the clobber emitted, so handle this ourselves. */ 3228c87b03e5Sespie emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 3229c87b03e5Sespie DONE; 3230c87b03e5Sespie}") 3231c87b03e5Sespie 3232c87b03e5Sespie(define_expand "reload_outdi" 3233c87b03e5Sespie [(set (match_operand:DI 0 "non_hard_reg_operand" "") 3234c87b03e5Sespie (match_operand:DI 1 "register_operand" "Z")) 3235c87b03e5Sespie (clobber (match_operand:SI 2 "register_operand" "=&r"))] 3236c87b03e5Sespie "" 3237c87b03e5Sespie " 3238c87b03e5Sespie{ 3239c87b03e5Sespie if (emit_move_sequence (operands, DImode, operands[2])) 3240c87b03e5Sespie DONE; 3241c87b03e5Sespie 3242c87b03e5Sespie /* We don't want the clobber emitted, so handle this ourselves. */ 3243c87b03e5Sespie emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 3244c87b03e5Sespie DONE; 3245c87b03e5Sespie}") 3246c87b03e5Sespie 3247c87b03e5Sespie(define_insn "" 3248c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 3249c87b03e5Sespie (high:DI (match_operand 1 "" "")))] 3250c87b03e5Sespie "!TARGET_64BIT" 3251c87b03e5Sespie "* 3252c87b03e5Sespie{ 3253c87b03e5Sespie rtx op0 = operands[0]; 3254c87b03e5Sespie rtx op1 = operands[1]; 3255c87b03e5Sespie 3256c87b03e5Sespie if (GET_CODE (op1) == CONST_INT) 3257c87b03e5Sespie { 3258c87b03e5Sespie operands[0] = operand_subword (op0, 1, 0, DImode); 3259c87b03e5Sespie output_asm_insn (\"ldil L'%1,%0\", operands); 3260c87b03e5Sespie 3261c87b03e5Sespie operands[0] = operand_subword (op0, 0, 0, DImode); 3262c87b03e5Sespie if (INTVAL (op1) < 0) 3263c87b03e5Sespie output_asm_insn (\"ldi -1,%0\", operands); 3264c87b03e5Sespie else 3265c87b03e5Sespie output_asm_insn (\"ldi 0,%0\", operands); 3266c87b03e5Sespie return \"\"; 3267c87b03e5Sespie } 3268c87b03e5Sespie else if (GET_CODE (op1) == CONST_DOUBLE) 3269c87b03e5Sespie { 3270c87b03e5Sespie operands[0] = operand_subword (op0, 1, 0, DImode); 3271c87b03e5Sespie operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1)); 3272c87b03e5Sespie output_asm_insn (\"ldil L'%1,%0\", operands); 3273c87b03e5Sespie 3274c87b03e5Sespie operands[0] = operand_subword (op0, 0, 0, DImode); 3275c87b03e5Sespie operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1)); 3276c87b03e5Sespie output_asm_insn (singlemove_string (operands), operands); 3277c87b03e5Sespie return \"\"; 3278c87b03e5Sespie } 3279c87b03e5Sespie else 3280c87b03e5Sespie abort (); 3281c87b03e5Sespie}" 3282c87b03e5Sespie [(set_attr "type" "move") 3283c87b03e5Sespie (set_attr "length" "8")]) 3284c87b03e5Sespie 3285c87b03e5Sespie(define_insn "" 3286c87b03e5Sespie [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" 3287c87b03e5Sespie "=r,o,Q,r,r,r,f,f,*TR") 3288c87b03e5Sespie (match_operand:DI 1 "general_operand" 3289c87b03e5Sespie "rM,r,r,o*R,Q,i,fM,*TR,f"))] 3290c87b03e5Sespie "(register_operand (operands[0], DImode) 3291c87b03e5Sespie || reg_or_0_operand (operands[1], DImode)) 3292c87b03e5Sespie && ! TARGET_64BIT 3293c87b03e5Sespie && ! TARGET_SOFT_FLOAT" 3294c87b03e5Sespie "* 3295c87b03e5Sespie{ 3296c87b03e5Sespie if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]) 3297c87b03e5Sespie || (operands[1] == CONST0_RTX (DImode))) 3298c87b03e5Sespie return output_fp_move_double (operands); 3299c87b03e5Sespie return output_move_double (operands); 3300c87b03e5Sespie}" 3301c87b03e5Sespie [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore") 3302c87b03e5Sespie (set_attr "length" "8,8,16,8,16,16,4,4,4")]) 3303c87b03e5Sespie 3304c87b03e5Sespie(define_insn "" 3305c87b03e5Sespie [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" 33064e43c760Sespie "=r,r,r,r,r,r,Q,!*q,!r,!f,f,*TR") 3307c87b03e5Sespie (match_operand:DI 1 "move_operand" 33084e43c760Sespie "A,r,J,N,K,RQ,rM,!rM,!*q,!fM,*RT,f"))] 3309c87b03e5Sespie "(register_operand (operands[0], DImode) 3310c87b03e5Sespie || reg_or_0_operand (operands[1], DImode)) 3311c87b03e5Sespie && ! TARGET_SOFT_FLOAT && TARGET_64BIT" 3312c87b03e5Sespie "@ 3313c87b03e5Sespie ldd RT'%A1,%0 3314c87b03e5Sespie copy %1,%0 3315c87b03e5Sespie ldi %1,%0 3316c87b03e5Sespie ldil L'%1,%0 3317c87b03e5Sespie depdi,z %z1,%0 3318c87b03e5Sespie ldd%M1 %1,%0 3319c87b03e5Sespie std%M0 %r1,%0 3320c87b03e5Sespie mtsar %r1 33214e43c760Sespie {mfctl|mfctl,w} %%sar,%0 3322c87b03e5Sespie fcpy,dbl %f1,%0 3323c87b03e5Sespie fldd%F1 %1,%0 3324c87b03e5Sespie fstd%F0 %1,%0" 33254e43c760Sespie [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore") 3326c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 33274e43c760Sespie (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")]) 3328c87b03e5Sespie 3329c87b03e5Sespie(define_insn "" 3330c87b03e5Sespie [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" 3331c87b03e5Sespie "=r,o,Q,r,r,r") 3332c87b03e5Sespie (match_operand:DI 1 "general_operand" 3333c87b03e5Sespie "rM,r,r,o,Q,i"))] 3334c87b03e5Sespie "(register_operand (operands[0], DImode) 3335c87b03e5Sespie || reg_or_0_operand (operands[1], DImode)) 3336c87b03e5Sespie && ! TARGET_64BIT 3337c87b03e5Sespie && TARGET_SOFT_FLOAT" 3338c87b03e5Sespie "* 3339c87b03e5Sespie{ 3340c87b03e5Sespie return output_move_double (operands); 3341c87b03e5Sespie}" 3342c87b03e5Sespie [(set_attr "type" "move,store,store,load,load,multi") 3343c87b03e5Sespie (set_attr "length" "8,8,16,8,16,16")]) 3344c87b03e5Sespie 3345c87b03e5Sespie(define_insn "" 3346c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,&r") 3347c87b03e5Sespie (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r") 3348c87b03e5Sespie (match_operand:DI 2 "immediate_operand" "i,i")))] 3349c87b03e5Sespie "!TARGET_64BIT" 3350c87b03e5Sespie "* 3351c87b03e5Sespie{ 3352c87b03e5Sespie /* Don't output a 64 bit constant, since we can't trust the assembler to 3353c87b03e5Sespie handle it correctly. */ 3354c87b03e5Sespie if (GET_CODE (operands[2]) == CONST_DOUBLE) 3355c87b03e5Sespie operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2])); 3356c87b03e5Sespie if (which_alternative == 1) 3357c87b03e5Sespie output_asm_insn (\"copy %1,%0\", operands); 3358c87b03e5Sespie return \"ldo R'%G2(%R1),%R0\"; 3359c87b03e5Sespie}" 3360c87b03e5Sespie [(set_attr "type" "move,move") 3361c87b03e5Sespie (set_attr "length" "4,8")]) 3362c87b03e5Sespie 3363c87b03e5Sespie;; This pattern forces (set (reg:SF ...) (const_double ...)) 3364c87b03e5Sespie;; to be reloaded by putting the constant into memory when 3365c87b03e5Sespie;; reg is a floating point register. 3366c87b03e5Sespie;; 3367c87b03e5Sespie;; For integer registers we use ldil;ldo to set the appropriate 3368c87b03e5Sespie;; value. 3369c87b03e5Sespie;; 3370c87b03e5Sespie;; This must come before the movsf pattern, and it must be present 3371c87b03e5Sespie;; to handle obscure reloading cases. 3372c87b03e5Sespie(define_insn "" 3373c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=?r,f") 3374c87b03e5Sespie (match_operand:SF 1 "" "?F,m"))] 3375c87b03e5Sespie "GET_CODE (operands[1]) == CONST_DOUBLE 3376c87b03e5Sespie && operands[1] != CONST0_RTX (SFmode) 3377c87b03e5Sespie && ! TARGET_SOFT_FLOAT" 3378c87b03e5Sespie "* return (which_alternative == 0 ? singlemove_string (operands) 3379c87b03e5Sespie : \" fldw%F1 %1,%0\");" 3380c87b03e5Sespie [(set_attr "type" "move,fpload") 3381c87b03e5Sespie (set_attr "length" "8,4")]) 3382c87b03e5Sespie 3383c87b03e5Sespie(define_expand "movsf" 3384c87b03e5Sespie [(set (match_operand:SF 0 "general_operand" "") 3385c87b03e5Sespie (match_operand:SF 1 "general_operand" ""))] 3386c87b03e5Sespie "" 3387c87b03e5Sespie " 3388c87b03e5Sespie{ 3389c87b03e5Sespie if (emit_move_sequence (operands, SFmode, 0)) 3390c87b03e5Sespie DONE; 3391c87b03e5Sespie}") 3392c87b03e5Sespie 3393c87b03e5Sespie;; Reloading an SImode or DImode value requires a scratch register if 3394c87b03e5Sespie;; going in to or out of float point registers. 3395c87b03e5Sespie 3396c87b03e5Sespie(define_expand "reload_insf" 3397c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=Z") 3398c87b03e5Sespie (match_operand:SF 1 "non_hard_reg_operand" "")) 3399c87b03e5Sespie (clobber (match_operand:SF 2 "register_operand" "=&r"))] 3400c87b03e5Sespie "" 3401c87b03e5Sespie " 3402c87b03e5Sespie{ 3403c87b03e5Sespie if (emit_move_sequence (operands, SFmode, operands[2])) 3404c87b03e5Sespie DONE; 3405c87b03e5Sespie 3406c87b03e5Sespie /* We don't want the clobber emitted, so handle this ourselves. */ 3407c87b03e5Sespie emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 3408c87b03e5Sespie DONE; 3409c87b03e5Sespie}") 3410c87b03e5Sespie 3411c87b03e5Sespie(define_expand "reload_outsf" 3412c87b03e5Sespie [(set (match_operand:SF 0 "non_hard_reg_operand" "") 3413c87b03e5Sespie (match_operand:SF 1 "register_operand" "Z")) 3414c87b03e5Sespie (clobber (match_operand:SF 2 "register_operand" "=&r"))] 3415c87b03e5Sespie "" 3416c87b03e5Sespie " 3417c87b03e5Sespie{ 3418c87b03e5Sespie if (emit_move_sequence (operands, SFmode, operands[2])) 3419c87b03e5Sespie DONE; 3420c87b03e5Sespie 3421c87b03e5Sespie /* We don't want the clobber emitted, so handle this ourselves. */ 3422c87b03e5Sespie emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 3423c87b03e5Sespie DONE; 3424c87b03e5Sespie}") 3425c87b03e5Sespie 3426c87b03e5Sespie(define_insn "" 3427c87b03e5Sespie [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand" 3428c87b03e5Sespie "=f,r,f,r,RQ,Q") 3429c87b03e5Sespie (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand" 3430c87b03e5Sespie "fG,rG,RQ,RQ,f,rG"))] 3431c87b03e5Sespie "(register_operand (operands[0], SFmode) 3432c87b03e5Sespie || reg_or_0_operand (operands[1], SFmode)) 3433c87b03e5Sespie && ! TARGET_SOFT_FLOAT" 3434c87b03e5Sespie "@ 3435c87b03e5Sespie fcpy,sgl %f1,%0 3436c87b03e5Sespie copy %r1,%0 3437c87b03e5Sespie fldw%F1 %1,%0 3438c87b03e5Sespie ldw%M1 %1,%0 3439c87b03e5Sespie fstw%F0 %r1,%0 3440c87b03e5Sespie stw%M0 %r1,%0" 3441c87b03e5Sespie [(set_attr "type" "fpalu,move,fpload,load,fpstore,store") 3442c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 3443c87b03e5Sespie (set_attr "length" "4,4,4,4,4,4")]) 3444c87b03e5Sespie 3445c87b03e5Sespie(define_insn "" 3446c87b03e5Sespie [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand" 3447c87b03e5Sespie "=r,r,Q") 3448c87b03e5Sespie (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand" 3449c87b03e5Sespie "rG,RQ,rG"))] 3450c87b03e5Sespie "(register_operand (operands[0], SFmode) 3451c87b03e5Sespie || reg_or_0_operand (operands[1], SFmode)) 3452c87b03e5Sespie && TARGET_SOFT_FLOAT" 3453c87b03e5Sespie "@ 3454c87b03e5Sespie copy %r1,%0 3455c87b03e5Sespie ldw%M1 %1,%0 3456c87b03e5Sespie stw%M0 %r1,%0" 3457c87b03e5Sespie [(set_attr "type" "move,load,store") 3458c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 3459c87b03e5Sespie (set_attr "length" "4,4,4")]) 3460c87b03e5Sespie 3461c87b03e5Sespie(define_insn "" 3462c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=fx") 3463c87b03e5Sespie (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r") 3464c87b03e5Sespie (match_operand:SI 2 "register_operand" "r"))))] 3465c87b03e5Sespie "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT" 3466c87b03e5Sespie "{fldwx|fldw} %2(%1),%0" 3467c87b03e5Sespie [(set_attr "type" "fpload") 3468c87b03e5Sespie (set_attr "length" "4")]) 3469c87b03e5Sespie 3470c87b03e5Sespie(define_insn "" 3471c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=fx") 3472c87b03e5Sespie (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r") 3473c87b03e5Sespie (match_operand:SI 2 "basereg_operand" "r"))))] 3474c87b03e5Sespie "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT" 3475c87b03e5Sespie "{fldwx|fldw} %1(%2),%0" 3476c87b03e5Sespie [(set_attr "type" "fpload") 3477c87b03e5Sespie (set_attr "length" "4")]) 3478c87b03e5Sespie 3479c87b03e5Sespie(define_insn "" 3480c87b03e5Sespie [(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r") 3481c87b03e5Sespie (match_operand:SI 2 "register_operand" "r"))) 3482c87b03e5Sespie (match_operand:SF 0 "register_operand" "fx"))] 3483c87b03e5Sespie "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT" 3484c87b03e5Sespie "{fstwx|fstw} %0,%2(%1)" 3485c87b03e5Sespie [(set_attr "type" "fpstore") 3486c87b03e5Sespie (set_attr "length" "4")]) 3487c87b03e5Sespie 3488c87b03e5Sespie(define_insn "" 3489c87b03e5Sespie [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r") 3490c87b03e5Sespie (match_operand:SI 2 "basereg_operand" "r"))) 3491c87b03e5Sespie (match_operand:SF 0 "register_operand" "fx"))] 3492c87b03e5Sespie "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT" 3493c87b03e5Sespie "{fstwx|fstw} %0,%1(%2)" 3494c87b03e5Sespie [(set_attr "type" "fpstore") 3495c87b03e5Sespie (set_attr "length" "4")]) 3496c87b03e5Sespie 3497c87b03e5Sespie 3498c87b03e5Sespie;;- zero extension instructions 3499c87b03e5Sespie;; We have define_expand for zero extension patterns to make sure the 3500c87b03e5Sespie;; operands get loaded into registers. The define_insns accept 3501c87b03e5Sespie;; memory operands. This gives us better overall code than just 3502c87b03e5Sespie;; having a pattern that does or does not accept memory operands. 3503c87b03e5Sespie 3504c87b03e5Sespie(define_expand "zero_extendhisi2" 3505c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 3506c87b03e5Sespie (zero_extend:SI 3507c87b03e5Sespie (match_operand:HI 1 "register_operand" "")))] 3508c87b03e5Sespie "" 3509c87b03e5Sespie "") 3510c87b03e5Sespie 3511c87b03e5Sespie(define_insn "" 3512c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 3513c87b03e5Sespie (zero_extend:SI 3514c87b03e5Sespie (match_operand:HI 1 "move_operand" "r,RQ")))] 3515c87b03e5Sespie "GET_CODE (operands[1]) != CONST_INT" 3516c87b03e5Sespie "@ 3517c87b03e5Sespie {extru|extrw,u} %1,31,16,%0 3518c87b03e5Sespie ldh%M1 %1,%0" 3519c87b03e5Sespie [(set_attr "type" "shift,load") 3520c87b03e5Sespie (set_attr "length" "4,4")]) 3521c87b03e5Sespie 3522c87b03e5Sespie(define_expand "zero_extendqihi2" 3523c87b03e5Sespie [(set (match_operand:HI 0 "register_operand" "") 3524c87b03e5Sespie (zero_extend:HI 3525c87b03e5Sespie (match_operand:QI 1 "register_operand" "")))] 3526c87b03e5Sespie "" 3527c87b03e5Sespie "") 3528c87b03e5Sespie 3529c87b03e5Sespie(define_insn "" 3530c87b03e5Sespie [(set (match_operand:HI 0 "register_operand" "=r,r") 3531c87b03e5Sespie (zero_extend:HI 3532c87b03e5Sespie (match_operand:QI 1 "move_operand" "r,RQ")))] 3533c87b03e5Sespie "GET_CODE (operands[1]) != CONST_INT" 3534c87b03e5Sespie "@ 3535c87b03e5Sespie {extru|extrw,u} %1,31,8,%0 3536c87b03e5Sespie ldb%M1 %1,%0" 3537c87b03e5Sespie [(set_attr "type" "shift,load") 3538c87b03e5Sespie (set_attr "length" "4,4")]) 3539c87b03e5Sespie 3540c87b03e5Sespie(define_expand "zero_extendqisi2" 3541c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 3542c87b03e5Sespie (zero_extend:SI 3543c87b03e5Sespie (match_operand:QI 1 "register_operand" "")))] 3544c87b03e5Sespie "" 3545c87b03e5Sespie "") 3546c87b03e5Sespie 3547c87b03e5Sespie(define_insn "" 3548c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 3549c87b03e5Sespie (zero_extend:SI 3550c87b03e5Sespie (match_operand:QI 1 "move_operand" "r,RQ")))] 3551c87b03e5Sespie "GET_CODE (operands[1]) != CONST_INT" 3552c87b03e5Sespie "@ 3553c87b03e5Sespie {extru|extrw,u} %1,31,8,%0 3554c87b03e5Sespie ldb%M1 %1,%0" 3555c87b03e5Sespie [(set_attr "type" "shift,load") 3556c87b03e5Sespie (set_attr "length" "4,4")]) 3557c87b03e5Sespie 3558c87b03e5Sespie(define_insn "zero_extendqidi2" 3559c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 3560c87b03e5Sespie (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))] 3561c87b03e5Sespie "TARGET_64BIT" 3562c87b03e5Sespie "extrd,u %1,63,8,%0" 3563c87b03e5Sespie [(set_attr "type" "shift") 3564c87b03e5Sespie (set_attr "length" "4")]) 3565c87b03e5Sespie 3566c87b03e5Sespie(define_insn "zero_extendhidi2" 3567c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 3568c87b03e5Sespie (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))] 3569c87b03e5Sespie "TARGET_64BIT" 3570c87b03e5Sespie "extrd,u %1,63,16,%0" 3571c87b03e5Sespie [(set_attr "type" "shift") 3572c87b03e5Sespie (set_attr "length" "4")]) 3573c87b03e5Sespie 3574c87b03e5Sespie(define_insn "zero_extendsidi2" 3575c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 3576c87b03e5Sespie (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] 3577c87b03e5Sespie "TARGET_64BIT" 3578c87b03e5Sespie "extrd,u %1,63,32,%0" 3579c87b03e5Sespie [(set_attr "type" "shift") 3580c87b03e5Sespie (set_attr "length" "4")]) 3581c87b03e5Sespie 3582c87b03e5Sespie;;- sign extension instructions 3583c87b03e5Sespie 3584c87b03e5Sespie(define_insn "extendhisi2" 3585c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 3586c87b03e5Sespie (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] 3587c87b03e5Sespie "" 3588c87b03e5Sespie "{extrs|extrw,s} %1,31,16,%0" 3589c87b03e5Sespie [(set_attr "type" "shift") 3590c87b03e5Sespie (set_attr "length" "4")]) 3591c87b03e5Sespie 3592c87b03e5Sespie(define_insn "extendqihi2" 3593c87b03e5Sespie [(set (match_operand:HI 0 "register_operand" "=r") 3594c87b03e5Sespie (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))] 3595c87b03e5Sespie "" 3596c87b03e5Sespie "{extrs|extrw,s} %1,31,8,%0" 3597c87b03e5Sespie [(set_attr "type" "shift") 3598c87b03e5Sespie (set_attr "length" "4")]) 3599c87b03e5Sespie 3600c87b03e5Sespie(define_insn "extendqisi2" 3601c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 3602c87b03e5Sespie (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))] 3603c87b03e5Sespie "" 3604c87b03e5Sespie "{extrs|extrw,s} %1,31,8,%0" 3605c87b03e5Sespie [(set_attr "type" "shift") 3606c87b03e5Sespie (set_attr "length" "4")]) 3607c87b03e5Sespie 3608c87b03e5Sespie(define_insn "extendqidi2" 3609c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 3610c87b03e5Sespie (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))] 3611c87b03e5Sespie "TARGET_64BIT" 3612c87b03e5Sespie "extrd,s %1,63,8,%0" 3613c87b03e5Sespie [(set_attr "type" "shift") 3614c87b03e5Sespie (set_attr "length" "4")]) 3615c87b03e5Sespie 3616c87b03e5Sespie(define_insn "extendhidi2" 3617c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 3618c87b03e5Sespie (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))] 3619c87b03e5Sespie "TARGET_64BIT" 3620c87b03e5Sespie "extrd,s %1,63,16,%0" 3621c87b03e5Sespie [(set_attr "type" "shift") 3622c87b03e5Sespie (set_attr "length" "4")]) 3623c87b03e5Sespie 3624c87b03e5Sespie(define_insn "extendsidi2" 3625c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 3626c87b03e5Sespie (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))] 3627c87b03e5Sespie "TARGET_64BIT" 3628c87b03e5Sespie "extrd,s %1,63,32,%0" 3629c87b03e5Sespie [(set_attr "type" "shift") 3630c87b03e5Sespie (set_attr "length" "4")]) 3631c87b03e5Sespie 3632c87b03e5Sespie 3633c87b03e5Sespie;; Conversions between float and double. 3634c87b03e5Sespie 3635c87b03e5Sespie(define_insn "extendsfdf2" 3636c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 3637c87b03e5Sespie (float_extend:DF 3638c87b03e5Sespie (match_operand:SF 1 "register_operand" "f")))] 3639c87b03e5Sespie "! TARGET_SOFT_FLOAT" 3640c87b03e5Sespie "{fcnvff|fcnv},sgl,dbl %1,%0" 3641c87b03e5Sespie [(set_attr "type" "fpalu") 3642c87b03e5Sespie (set_attr "length" "4")]) 3643c87b03e5Sespie 3644c87b03e5Sespie(define_insn "truncdfsf2" 3645c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 3646c87b03e5Sespie (float_truncate:SF 3647c87b03e5Sespie (match_operand:DF 1 "register_operand" "f")))] 3648c87b03e5Sespie "! TARGET_SOFT_FLOAT" 3649c87b03e5Sespie "{fcnvff|fcnv},dbl,sgl %1,%0" 3650c87b03e5Sespie [(set_attr "type" "fpalu") 3651c87b03e5Sespie (set_attr "length" "4")]) 3652c87b03e5Sespie 3653c87b03e5Sespie;; Conversion between fixed point and floating point. 3654c87b03e5Sespie;; Note that among the fix-to-float insns 3655c87b03e5Sespie;; the ones that start with SImode come first. 3656c87b03e5Sespie;; That is so that an operand that is a CONST_INT 3657c87b03e5Sespie;; (and therefore lacks a specific machine mode). 3658c87b03e5Sespie;; will be recognized as SImode (which is always valid) 3659c87b03e5Sespie;; rather than as QImode or HImode. 3660c87b03e5Sespie 3661c87b03e5Sespie;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...))) 3662c87b03e5Sespie;; to be reloaded by putting the constant into memory. 3663c87b03e5Sespie;; It must come before the more general floatsisf2 pattern. 3664c87b03e5Sespie(define_insn "" 3665c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 3666c87b03e5Sespie (float:SF (match_operand:SI 1 "const_int_operand" "m")))] 3667c87b03e5Sespie "! TARGET_SOFT_FLOAT" 3668c87b03e5Sespie "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0" 3669c87b03e5Sespie [(set_attr "type" "fpalu") 3670c87b03e5Sespie (set_attr "length" "8")]) 3671c87b03e5Sespie 3672c87b03e5Sespie(define_insn "floatsisf2" 3673c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 3674c87b03e5Sespie (float:SF (match_operand:SI 1 "register_operand" "f")))] 3675c87b03e5Sespie "! TARGET_SOFT_FLOAT" 3676c87b03e5Sespie "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0" 3677c87b03e5Sespie [(set_attr "type" "fpalu") 3678c87b03e5Sespie (set_attr "length" "4")]) 3679c87b03e5Sespie 3680c87b03e5Sespie;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...))) 3681c87b03e5Sespie;; to be reloaded by putting the constant into memory. 3682c87b03e5Sespie;; It must come before the more general floatsidf2 pattern. 3683c87b03e5Sespie(define_insn "" 3684c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 3685c87b03e5Sespie (float:DF (match_operand:SI 1 "const_int_operand" "m")))] 3686c87b03e5Sespie "! TARGET_SOFT_FLOAT" 3687c87b03e5Sespie "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0" 3688c87b03e5Sespie [(set_attr "type" "fpalu") 3689c87b03e5Sespie (set_attr "length" "8")]) 3690c87b03e5Sespie 3691c87b03e5Sespie(define_insn "floatsidf2" 3692c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 3693c87b03e5Sespie (float:DF (match_operand:SI 1 "register_operand" "f")))] 3694c87b03e5Sespie "! TARGET_SOFT_FLOAT" 3695c87b03e5Sespie "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0" 3696c87b03e5Sespie [(set_attr "type" "fpalu") 3697c87b03e5Sespie (set_attr "length" "4")]) 3698c87b03e5Sespie 3699c87b03e5Sespie(define_expand "floatunssisf2" 3700c87b03e5Sespie [(set (subreg:SI (match_dup 2) 4) 3701c87b03e5Sespie (match_operand:SI 1 "register_operand" "")) 3702c87b03e5Sespie (set (subreg:SI (match_dup 2) 0) 3703c87b03e5Sespie (const_int 0)) 3704c87b03e5Sespie (set (match_operand:SF 0 "register_operand" "") 3705c87b03e5Sespie (float:SF (match_dup 2)))] 3706c87b03e5Sespie "TARGET_PA_11 && ! TARGET_SOFT_FLOAT" 3707c87b03e5Sespie " 3708c87b03e5Sespie{ 3709c87b03e5Sespie if (TARGET_PA_20) 3710c87b03e5Sespie { 3711c87b03e5Sespie emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1])); 3712c87b03e5Sespie DONE; 3713c87b03e5Sespie } 3714c87b03e5Sespie operands[2] = gen_reg_rtx (DImode); 3715c87b03e5Sespie}") 3716c87b03e5Sespie 3717c87b03e5Sespie(define_expand "floatunssidf2" 3718c87b03e5Sespie [(set (subreg:SI (match_dup 2) 4) 3719c87b03e5Sespie (match_operand:SI 1 "register_operand" "")) 3720c87b03e5Sespie (set (subreg:SI (match_dup 2) 0) 3721c87b03e5Sespie (const_int 0)) 3722c87b03e5Sespie (set (match_operand:DF 0 "register_operand" "") 3723c87b03e5Sespie (float:DF (match_dup 2)))] 3724c87b03e5Sespie "TARGET_PA_11 && ! TARGET_SOFT_FLOAT" 3725c87b03e5Sespie " 3726c87b03e5Sespie{ 3727c87b03e5Sespie if (TARGET_PA_20) 3728c87b03e5Sespie { 3729c87b03e5Sespie emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1])); 3730c87b03e5Sespie DONE; 3731c87b03e5Sespie } 3732c87b03e5Sespie operands[2] = gen_reg_rtx (DImode); 3733c87b03e5Sespie}") 3734c87b03e5Sespie 3735c87b03e5Sespie(define_insn "floatdisf2" 3736c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 3737c87b03e5Sespie (float:SF (match_operand:DI 1 "register_operand" "f")))] 3738c87b03e5Sespie "TARGET_PA_11 && ! TARGET_SOFT_FLOAT" 3739c87b03e5Sespie "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0" 3740c87b03e5Sespie [(set_attr "type" "fpalu") 3741c87b03e5Sespie (set_attr "length" "4")]) 3742c87b03e5Sespie 3743c87b03e5Sespie(define_insn "floatdidf2" 3744c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 3745c87b03e5Sespie (float:DF (match_operand:DI 1 "register_operand" "f")))] 3746c87b03e5Sespie "TARGET_PA_11 && ! TARGET_SOFT_FLOAT" 3747c87b03e5Sespie "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0" 3748c87b03e5Sespie [(set_attr "type" "fpalu") 3749c87b03e5Sespie (set_attr "length" "4")]) 3750c87b03e5Sespie 3751c87b03e5Sespie;; Convert a float to an actual integer. 3752c87b03e5Sespie;; Truncation is performed as part of the conversion. 3753c87b03e5Sespie 3754c87b03e5Sespie(define_insn "fix_truncsfsi2" 3755c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=f") 3756c87b03e5Sespie (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] 3757c87b03e5Sespie "! TARGET_SOFT_FLOAT" 3758c87b03e5Sespie "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0" 3759c87b03e5Sespie [(set_attr "type" "fpalu") 3760c87b03e5Sespie (set_attr "length" "4")]) 3761c87b03e5Sespie 3762c87b03e5Sespie(define_insn "fix_truncdfsi2" 3763c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=f") 3764c87b03e5Sespie (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))] 3765c87b03e5Sespie "! TARGET_SOFT_FLOAT" 3766c87b03e5Sespie "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0" 3767c87b03e5Sespie [(set_attr "type" "fpalu") 3768c87b03e5Sespie (set_attr "length" "4")]) 3769c87b03e5Sespie 3770c87b03e5Sespie(define_insn "fix_truncsfdi2" 3771c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=f") 3772c87b03e5Sespie (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] 3773c87b03e5Sespie "TARGET_PA_11 && ! TARGET_SOFT_FLOAT" 3774c87b03e5Sespie "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0" 3775c87b03e5Sespie [(set_attr "type" "fpalu") 3776c87b03e5Sespie (set_attr "length" "4")]) 3777c87b03e5Sespie 3778c87b03e5Sespie(define_insn "fix_truncdfdi2" 3779c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=f") 3780c87b03e5Sespie (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))] 3781c87b03e5Sespie "TARGET_PA_11 && ! TARGET_SOFT_FLOAT" 3782c87b03e5Sespie "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0" 3783c87b03e5Sespie [(set_attr "type" "fpalu") 3784c87b03e5Sespie (set_attr "length" "4")]) 3785c87b03e5Sespie 3786c87b03e5Sespie(define_insn "floatunssidf2_pa20" 3787c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 3788c87b03e5Sespie (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))] 3789c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 3790c87b03e5Sespie "fcnv,uw,dbl %1,%0" 3791c87b03e5Sespie [(set_attr "type" "fpalu") 3792c87b03e5Sespie (set_attr "length" "4")]) 3793c87b03e5Sespie 3794c87b03e5Sespie(define_insn "floatunssisf2_pa20" 3795c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 3796c87b03e5Sespie (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))] 3797c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 3798c87b03e5Sespie "fcnv,uw,sgl %1,%0" 3799c87b03e5Sespie [(set_attr "type" "fpalu") 3800c87b03e5Sespie (set_attr "length" "4")]) 3801c87b03e5Sespie 3802c87b03e5Sespie(define_insn "floatunsdisf2" 3803c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 3804c87b03e5Sespie (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))] 3805c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 3806c87b03e5Sespie "fcnv,udw,sgl %1,%0" 3807c87b03e5Sespie [(set_attr "type" "fpalu") 3808c87b03e5Sespie (set_attr "length" "4")]) 3809c87b03e5Sespie 3810c87b03e5Sespie(define_insn "floatunsdidf2" 3811c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 3812c87b03e5Sespie (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))] 3813c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 3814c87b03e5Sespie "fcnv,udw,dbl %1,%0" 3815c87b03e5Sespie [(set_attr "type" "fpalu") 3816c87b03e5Sespie (set_attr "length" "4")]) 3817c87b03e5Sespie 3818c87b03e5Sespie(define_insn "fixuns_truncsfsi2" 3819c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=f") 3820c87b03e5Sespie (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] 3821c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 3822c87b03e5Sespie "fcnv,t,sgl,uw %1,%0" 3823c87b03e5Sespie [(set_attr "type" "fpalu") 3824c87b03e5Sespie (set_attr "length" "4")]) 3825c87b03e5Sespie 3826c87b03e5Sespie(define_insn "fixuns_truncdfsi2" 3827c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=f") 3828c87b03e5Sespie (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))] 3829c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 3830c87b03e5Sespie "fcnv,t,dbl,uw %1,%0" 3831c87b03e5Sespie [(set_attr "type" "fpalu") 3832c87b03e5Sespie (set_attr "length" "4")]) 3833c87b03e5Sespie 3834c87b03e5Sespie(define_insn "fixuns_truncsfdi2" 3835c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=f") 3836c87b03e5Sespie (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] 3837c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 3838c87b03e5Sespie "fcnv,t,sgl,udw %1,%0" 3839c87b03e5Sespie [(set_attr "type" "fpalu") 3840c87b03e5Sespie (set_attr "length" "4")]) 3841c87b03e5Sespie 3842c87b03e5Sespie(define_insn "fixuns_truncdfdi2" 3843c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=f") 3844c87b03e5Sespie (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))] 3845c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 3846c87b03e5Sespie "fcnv,t,dbl,udw %1,%0" 3847c87b03e5Sespie [(set_attr "type" "fpalu") 3848c87b03e5Sespie (set_attr "length" "4")]) 3849c87b03e5Sespie 3850c87b03e5Sespie;;- arithmetic instructions 3851c87b03e5Sespie 3852c87b03e5Sespie(define_expand "adddi3" 3853c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 3854c87b03e5Sespie (plus:DI (match_operand:DI 1 "register_operand" "") 3855c87b03e5Sespie (match_operand:DI 2 "adddi3_operand" "")))] 3856c87b03e5Sespie "" 3857c87b03e5Sespie "") 3858c87b03e5Sespie 3859c87b03e5Sespie(define_insn "" 3860c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 3861c87b03e5Sespie (plus:DI (match_operand:DI 1 "register_operand" "%r") 3862c87b03e5Sespie (match_operand:DI 2 "arith11_operand" "rI")))] 3863c87b03e5Sespie "!TARGET_64BIT" 3864c87b03e5Sespie "* 3865c87b03e5Sespie{ 3866c87b03e5Sespie if (GET_CODE (operands[2]) == CONST_INT) 3867c87b03e5Sespie { 3868c87b03e5Sespie if (INTVAL (operands[2]) >= 0) 3869c87b03e5Sespie return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\"; 3870c87b03e5Sespie else 3871c87b03e5Sespie return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\"; 3872c87b03e5Sespie } 3873c87b03e5Sespie else 3874c87b03e5Sespie return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\"; 3875c87b03e5Sespie}" 3876c87b03e5Sespie [(set_attr "type" "binary") 3877c87b03e5Sespie (set_attr "length" "8")]) 3878c87b03e5Sespie 3879c87b03e5Sespie(define_insn "" 3880c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r") 3881c87b03e5Sespie (plus:DI (match_operand:DI 1 "register_operand" "%r,r") 3882c87b03e5Sespie (match_operand:DI 2 "arith_operand" "r,J")))] 3883c87b03e5Sespie "TARGET_64BIT" 3884c87b03e5Sespie "@ 3885c87b03e5Sespie {addl|add,l} %1,%2,%0 3886c87b03e5Sespie ldo %2(%1),%0" 3887c87b03e5Sespie [(set_attr "type" "binary,binary") 3888c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 3889c87b03e5Sespie (set_attr "length" "4,4")]) 3890c87b03e5Sespie 3891c87b03e5Sespie(define_insn "" 3892c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 3893c87b03e5Sespie (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r")) 3894c87b03e5Sespie (match_operand:DI 2 "register_operand" "r")))] 3895c87b03e5Sespie "TARGET_64BIT" 3896c87b03e5Sespie "uaddcm %2,%1,%0" 3897c87b03e5Sespie [(set_attr "type" "binary") 3898c87b03e5Sespie (set_attr "length" "4")]) 3899c87b03e5Sespie 3900c87b03e5Sespie(define_insn "" 3901c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 3902c87b03e5Sespie (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r")) 3903c87b03e5Sespie (match_operand:SI 2 "register_operand" "r")))] 3904c87b03e5Sespie "" 3905c87b03e5Sespie "uaddcm %2,%1,%0" 3906c87b03e5Sespie [(set_attr "type" "binary") 3907c87b03e5Sespie (set_attr "length" "4")]) 3908c87b03e5Sespie 3909c87b03e5Sespie;; define_splits to optimize cases of adding a constant integer 3910c87b03e5Sespie;; to a register when the constant does not fit in 14 bits. */ 3911c87b03e5Sespie(define_split 3912c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 3913c87b03e5Sespie (plus:SI (match_operand:SI 1 "register_operand" "") 3914c87b03e5Sespie (match_operand:SI 2 "const_int_operand" ""))) 3915c87b03e5Sespie (clobber (match_operand:SI 4 "register_operand" ""))] 3916c87b03e5Sespie "! cint_ok_for_move (INTVAL (operands[2])) 3917c87b03e5Sespie && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)" 3918c87b03e5Sespie [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2))) 3919c87b03e5Sespie (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))] 3920c87b03e5Sespie " 3921c87b03e5Sespie{ 3922c87b03e5Sespie int val = INTVAL (operands[2]); 3923c87b03e5Sespie int low = (val < 0) ? -0x2000 : 0x1fff; 3924c87b03e5Sespie int rest = val - low; 3925c87b03e5Sespie 3926c87b03e5Sespie operands[2] = GEN_INT (rest); 3927c87b03e5Sespie operands[3] = GEN_INT (low); 3928c87b03e5Sespie}") 3929c87b03e5Sespie 3930c87b03e5Sespie(define_split 3931c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 3932c87b03e5Sespie (plus:SI (match_operand:SI 1 "register_operand" "") 3933c87b03e5Sespie (match_operand:SI 2 "const_int_operand" ""))) 3934c87b03e5Sespie (clobber (match_operand:SI 4 "register_operand" ""))] 3935c87b03e5Sespie "! cint_ok_for_move (INTVAL (operands[2]))" 3936c87b03e5Sespie [(set (match_dup 4) (match_dup 2)) 3937c87b03e5Sespie (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3)) 3938c87b03e5Sespie (match_dup 1)))] 3939c87b03e5Sespie " 3940c87b03e5Sespie{ 3941c87b03e5Sespie HOST_WIDE_INT intval = INTVAL (operands[2]); 3942c87b03e5Sespie 3943c87b03e5Sespie /* Try dividing the constant by 2, then 4, and finally 8 to see 3944c87b03e5Sespie if we can get a constant which can be loaded into a register 3945c87b03e5Sespie in a single instruction (cint_ok_for_move). 3946c87b03e5Sespie 3947c87b03e5Sespie If that fails, try to negate the constant and subtract it 3948c87b03e5Sespie from our input operand. */ 3949c87b03e5Sespie if (intval % 2 == 0 && cint_ok_for_move (intval / 2)) 3950c87b03e5Sespie { 3951c87b03e5Sespie operands[2] = GEN_INT (intval / 2); 3952c87b03e5Sespie operands[3] = GEN_INT (2); 3953c87b03e5Sespie } 3954c87b03e5Sespie else if (intval % 4 == 0 && cint_ok_for_move (intval / 4)) 3955c87b03e5Sespie { 3956c87b03e5Sespie operands[2] = GEN_INT (intval / 4); 3957c87b03e5Sespie operands[3] = GEN_INT (4); 3958c87b03e5Sespie } 3959c87b03e5Sespie else if (intval % 8 == 0 && cint_ok_for_move (intval / 8)) 3960c87b03e5Sespie { 3961c87b03e5Sespie operands[2] = GEN_INT (intval / 8); 3962c87b03e5Sespie operands[3] = GEN_INT (8); 3963c87b03e5Sespie } 3964c87b03e5Sespie else if (cint_ok_for_move (-intval)) 3965c87b03e5Sespie { 3966c87b03e5Sespie emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval))); 3967c87b03e5Sespie emit_insn (gen_subsi3 (operands[0], operands[1], operands[4])); 3968c87b03e5Sespie DONE; 3969c87b03e5Sespie } 3970c87b03e5Sespie else 3971c87b03e5Sespie FAIL; 3972c87b03e5Sespie}") 3973c87b03e5Sespie 3974c87b03e5Sespie(define_insn "addsi3" 3975c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 3976c87b03e5Sespie (plus:SI (match_operand:SI 1 "register_operand" "%r,r") 3977c87b03e5Sespie (match_operand:SI 2 "arith_operand" "r,J")))] 3978c87b03e5Sespie "" 3979c87b03e5Sespie "@ 3980c87b03e5Sespie {addl|add,l} %1,%2,%0 3981c87b03e5Sespie ldo %2(%1),%0" 3982c87b03e5Sespie [(set_attr "type" "binary,binary") 3983c87b03e5Sespie (set_attr "pa_combine_type" "addmove") 3984c87b03e5Sespie (set_attr "length" "4,4")]) 3985c87b03e5Sespie 3986c87b03e5Sespie(define_expand "subdi3" 3987c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 3988c87b03e5Sespie (minus:DI (match_operand:DI 1 "register_operand" "") 3989c87b03e5Sespie (match_operand:DI 2 "register_operand" "")))] 3990c87b03e5Sespie "" 3991c87b03e5Sespie "") 3992c87b03e5Sespie 3993c87b03e5Sespie(define_insn "" 3994c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 3995c87b03e5Sespie (minus:DI (match_operand:DI 1 "register_operand" "r") 3996c87b03e5Sespie (match_operand:DI 2 "register_operand" "r")))] 3997c87b03e5Sespie "!TARGET_64BIT" 3998c87b03e5Sespie "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0" 3999c87b03e5Sespie [(set_attr "type" "binary") 4000c87b03e5Sespie (set_attr "length" "8")]) 4001c87b03e5Sespie 4002c87b03e5Sespie(define_insn "" 4003c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r,!q") 4004c87b03e5Sespie (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U") 4005c87b03e5Sespie (match_operand:DI 2 "register_operand" "r,r,!r")))] 4006c87b03e5Sespie "TARGET_64BIT" 4007c87b03e5Sespie "@ 4008c87b03e5Sespie sub %1,%2,%0 4009c87b03e5Sespie subi %1,%2,%0 4010c87b03e5Sespie mtsarcm %2" 4011c87b03e5Sespie [(set_attr "type" "binary,binary,move") 4012c87b03e5Sespie (set_attr "length" "4,4,4")]) 4013c87b03e5Sespie 4014c87b03e5Sespie(define_expand "subsi3" 4015c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 4016c87b03e5Sespie (minus:SI (match_operand:SI 1 "arith11_operand" "") 4017c87b03e5Sespie (match_operand:SI 2 "register_operand" "")))] 4018c87b03e5Sespie "" 4019c87b03e5Sespie "") 4020c87b03e5Sespie 4021c87b03e5Sespie(define_insn "" 4022c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 4023c87b03e5Sespie (minus:SI (match_operand:SI 1 "arith11_operand" "r,I") 4024c87b03e5Sespie (match_operand:SI 2 "register_operand" "r,r")))] 4025c87b03e5Sespie "!TARGET_PA_20" 4026c87b03e5Sespie "@ 4027c87b03e5Sespie sub %1,%2,%0 4028c87b03e5Sespie subi %1,%2,%0" 4029c87b03e5Sespie [(set_attr "type" "binary,binary") 4030c87b03e5Sespie (set_attr "length" "4,4")]) 4031c87b03e5Sespie 4032c87b03e5Sespie(define_insn "" 4033c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r,!q") 4034c87b03e5Sespie (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S") 4035c87b03e5Sespie (match_operand:SI 2 "register_operand" "r,r,!r")))] 4036c87b03e5Sespie "TARGET_PA_20" 4037c87b03e5Sespie "@ 4038c87b03e5Sespie sub %1,%2,%0 4039c87b03e5Sespie subi %1,%2,%0 4040c87b03e5Sespie mtsarcm %2" 4041c87b03e5Sespie [(set_attr "type" "binary,binary,move") 4042c87b03e5Sespie (set_attr "length" "4,4,4")]) 4043c87b03e5Sespie 4044c87b03e5Sespie;; Clobbering a "register_operand" instead of a match_scratch 4045c87b03e5Sespie;; in operand3 of millicode calls avoids spilling %r1 and 4046c87b03e5Sespie;; produces better code. 4047c87b03e5Sespie 4048c87b03e5Sespie;; The mulsi3 insns set up registers for the millicode call. 4049c87b03e5Sespie(define_expand "mulsi3" 4050c87b03e5Sespie [(set (reg:SI 26) (match_operand:SI 1 "move_operand" "")) 4051c87b03e5Sespie (set (reg:SI 25) (match_operand:SI 2 "move_operand" "")) 4052c87b03e5Sespie (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25))) 4053c87b03e5Sespie (clobber (match_dup 3)) 4054c87b03e5Sespie (clobber (reg:SI 26)) 4055c87b03e5Sespie (clobber (reg:SI 25)) 4056c87b03e5Sespie (clobber (match_dup 4))]) 4057c87b03e5Sespie (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))] 4058c87b03e5Sespie "" 4059c87b03e5Sespie " 4060c87b03e5Sespie{ 4061c87b03e5Sespie operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31); 4062c87b03e5Sespie if (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT) 4063c87b03e5Sespie { 4064c87b03e5Sespie rtx scratch = gen_reg_rtx (DImode); 4065c87b03e5Sespie operands[1] = force_reg (SImode, operands[1]); 4066c87b03e5Sespie operands[2] = force_reg (SImode, operands[2]); 4067c87b03e5Sespie emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2])); 4068c87b03e5Sespie emit_insn (gen_rtx_SET (VOIDmode, operands[0], 4069c87b03e5Sespie gen_rtx_SUBREG (SImode, scratch, GET_MODE_SIZE (SImode)))); 4070c87b03e5Sespie DONE; 4071c87b03e5Sespie } 4072c87b03e5Sespie operands[3] = gen_reg_rtx (SImode); 4073c87b03e5Sespie}") 4074c87b03e5Sespie 4075c87b03e5Sespie(define_insn "umulsidi3" 4076c87b03e5Sespie [(set (match_operand:DI 0 "nonimmediate_operand" "=f") 4077c87b03e5Sespie (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f")) 4078c87b03e5Sespie (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))] 4079c87b03e5Sespie "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT" 4080c87b03e5Sespie "xmpyu %1,%2,%0" 4081c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4082c87b03e5Sespie (set_attr "length" "4")]) 4083c87b03e5Sespie 4084c87b03e5Sespie(define_insn "" 4085c87b03e5Sespie [(set (match_operand:DI 0 "nonimmediate_operand" "=f") 4086c87b03e5Sespie (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f")) 4087c87b03e5Sespie (match_operand:DI 2 "uint32_operand" "f")))] 4088c87b03e5Sespie "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT" 4089c87b03e5Sespie "xmpyu %1,%R2,%0" 4090c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4091c87b03e5Sespie (set_attr "length" "4")]) 4092c87b03e5Sespie 4093c87b03e5Sespie(define_insn "" 4094c87b03e5Sespie [(set (match_operand:DI 0 "nonimmediate_operand" "=f") 4095c87b03e5Sespie (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f")) 4096c87b03e5Sespie (match_operand:DI 2 "uint32_operand" "f")))] 4097c87b03e5Sespie "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT" 4098c87b03e5Sespie "xmpyu %1,%2R,%0" 4099c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4100c87b03e5Sespie (set_attr "length" "4")]) 4101c87b03e5Sespie 4102c87b03e5Sespie(define_insn "" 4103c87b03e5Sespie [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25))) 4104c87b03e5Sespie (clobber (match_operand:SI 0 "register_operand" "=a")) 4105c87b03e5Sespie (clobber (reg:SI 26)) 4106c87b03e5Sespie (clobber (reg:SI 25)) 4107c87b03e5Sespie (clobber (reg:SI 31))] 4108c87b03e5Sespie "!TARGET_64BIT" 4109c87b03e5Sespie "* return output_mul_insn (0, insn);" 4110c87b03e5Sespie [(set_attr "type" "milli") 4111c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) 4112c87b03e5Sespie 4113c87b03e5Sespie(define_insn "" 4114c87b03e5Sespie [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25))) 4115c87b03e5Sespie (clobber (match_operand:SI 0 "register_operand" "=a")) 4116c87b03e5Sespie (clobber (reg:SI 26)) 4117c87b03e5Sespie (clobber (reg:SI 25)) 4118c87b03e5Sespie (clobber (reg:SI 2))] 4119c87b03e5Sespie "TARGET_64BIT" 4120c87b03e5Sespie "* return output_mul_insn (0, insn);" 4121c87b03e5Sespie [(set_attr "type" "milli") 4122c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) 4123c87b03e5Sespie 4124c87b03e5Sespie(define_expand "muldi3" 4125c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 4126c87b03e5Sespie (mult:DI (match_operand:DI 1 "register_operand" "") 4127c87b03e5Sespie (match_operand:DI 2 "register_operand" "")))] 4128c87b03e5Sespie "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT" 4129c87b03e5Sespie " 4130c87b03e5Sespie{ 4131c87b03e5Sespie rtx low_product = gen_reg_rtx (DImode); 4132c87b03e5Sespie rtx cross_product1 = gen_reg_rtx (DImode); 4133c87b03e5Sespie rtx cross_product2 = gen_reg_rtx (DImode); 4134c87b03e5Sespie rtx cross_scratch = gen_reg_rtx (DImode); 4135c87b03e5Sespie rtx cross_product = gen_reg_rtx (DImode); 4136c87b03e5Sespie rtx op1l, op1r, op2l, op2r; 4137c87b03e5Sespie rtx op1shifted, op2shifted; 4138c87b03e5Sespie 4139c87b03e5Sespie op1shifted = gen_reg_rtx (DImode); 4140c87b03e5Sespie op2shifted = gen_reg_rtx (DImode); 4141c87b03e5Sespie op1l = gen_reg_rtx (SImode); 4142c87b03e5Sespie op1r = gen_reg_rtx (SImode); 4143c87b03e5Sespie op2l = gen_reg_rtx (SImode); 4144c87b03e5Sespie op2r = gen_reg_rtx (SImode); 4145c87b03e5Sespie 4146c87b03e5Sespie emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1], 4147c87b03e5Sespie GEN_INT (32))); 4148c87b03e5Sespie emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2], 4149c87b03e5Sespie GEN_INT (32))); 4150c87b03e5Sespie op1r = gen_rtx_SUBREG (SImode, operands[1], 4); 4151c87b03e5Sespie op2r = gen_rtx_SUBREG (SImode, operands[2], 4); 4152c87b03e5Sespie op1l = gen_rtx_SUBREG (SImode, op1shifted, 4); 4153c87b03e5Sespie op2l = gen_rtx_SUBREG (SImode, op2shifted, 4); 4154c87b03e5Sespie 4155c87b03e5Sespie /* Emit multiplies for the cross products. */ 4156c87b03e5Sespie emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l)); 4157c87b03e5Sespie emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r)); 4158c87b03e5Sespie 4159c87b03e5Sespie /* Emit a multiply for the low sub-word. */ 4160c87b03e5Sespie emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r))); 4161c87b03e5Sespie 4162c87b03e5Sespie /* Sum the cross products and shift them into proper position. */ 4163c87b03e5Sespie emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2)); 4164c87b03e5Sespie emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32))); 4165c87b03e5Sespie 4166c87b03e5Sespie /* Add the cross product to the low product and store the result 4167c87b03e5Sespie into the output operand . */ 4168c87b03e5Sespie emit_insn (gen_adddi3 (operands[0], cross_product, low_product)); 4169c87b03e5Sespie DONE; 4170c87b03e5Sespie}") 4171c87b03e5Sespie 4172c87b03e5Sespie;;; Division and mod. 4173c87b03e5Sespie(define_expand "divsi3" 4174c87b03e5Sespie [(set (reg:SI 26) (match_operand:SI 1 "move_operand" "")) 4175c87b03e5Sespie (set (reg:SI 25) (match_operand:SI 2 "move_operand" "")) 4176c87b03e5Sespie (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25))) 4177c87b03e5Sespie (clobber (match_dup 3)) 4178c87b03e5Sespie (clobber (match_dup 4)) 4179c87b03e5Sespie (clobber (reg:SI 26)) 4180c87b03e5Sespie (clobber (reg:SI 25)) 4181c87b03e5Sespie (clobber (match_dup 5))]) 4182c87b03e5Sespie (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))] 4183c87b03e5Sespie "" 4184c87b03e5Sespie " 4185c87b03e5Sespie{ 4186c87b03e5Sespie operands[3] = gen_reg_rtx (SImode); 4187c87b03e5Sespie if (TARGET_64BIT) 4188c87b03e5Sespie { 4189c87b03e5Sespie operands[5] = gen_rtx_REG (SImode, 2); 4190c87b03e5Sespie operands[4] = operands[5]; 4191c87b03e5Sespie } 4192c87b03e5Sespie else 4193c87b03e5Sespie { 4194c87b03e5Sespie operands[5] = gen_rtx_REG (SImode, 31); 4195c87b03e5Sespie operands[4] = gen_reg_rtx (SImode); 4196c87b03e5Sespie } 4197c87b03e5Sespie if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0)) 4198c87b03e5Sespie DONE; 4199c87b03e5Sespie}") 4200c87b03e5Sespie 4201c87b03e5Sespie(define_insn "" 4202c87b03e5Sespie [(set (reg:SI 29) 4203c87b03e5Sespie (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" ""))) 4204c87b03e5Sespie (clobber (match_operand:SI 1 "register_operand" "=a")) 4205c87b03e5Sespie (clobber (match_operand:SI 2 "register_operand" "=&r")) 4206c87b03e5Sespie (clobber (reg:SI 26)) 4207c87b03e5Sespie (clobber (reg:SI 25)) 4208c87b03e5Sespie (clobber (reg:SI 31))] 4209c87b03e5Sespie "!TARGET_64BIT" 4210c87b03e5Sespie "* 4211c87b03e5Sespie return output_div_insn (operands, 0, insn);" 4212c87b03e5Sespie [(set_attr "type" "milli") 4213c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) 4214c87b03e5Sespie 4215c87b03e5Sespie(define_insn "" 4216c87b03e5Sespie [(set (reg:SI 29) 4217c87b03e5Sespie (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" ""))) 4218c87b03e5Sespie (clobber (match_operand:SI 1 "register_operand" "=a")) 4219c87b03e5Sespie (clobber (match_operand:SI 2 "register_operand" "=&r")) 4220c87b03e5Sespie (clobber (reg:SI 26)) 4221c87b03e5Sespie (clobber (reg:SI 25)) 4222c87b03e5Sespie (clobber (reg:SI 2))] 4223c87b03e5Sespie "TARGET_64BIT" 4224c87b03e5Sespie "* 4225c87b03e5Sespie return output_div_insn (operands, 0, insn);" 4226c87b03e5Sespie [(set_attr "type" "milli") 4227c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) 4228c87b03e5Sespie 4229c87b03e5Sespie(define_expand "udivsi3" 4230c87b03e5Sespie [(set (reg:SI 26) (match_operand:SI 1 "move_operand" "")) 4231c87b03e5Sespie (set (reg:SI 25) (match_operand:SI 2 "move_operand" "")) 4232c87b03e5Sespie (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25))) 4233c87b03e5Sespie (clobber (match_dup 3)) 4234c87b03e5Sespie (clobber (match_dup 4)) 4235c87b03e5Sespie (clobber (reg:SI 26)) 4236c87b03e5Sespie (clobber (reg:SI 25)) 4237c87b03e5Sespie (clobber (match_dup 5))]) 4238c87b03e5Sespie (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))] 4239c87b03e5Sespie "" 4240c87b03e5Sespie " 4241c87b03e5Sespie{ 4242c87b03e5Sespie operands[3] = gen_reg_rtx (SImode); 4243c87b03e5Sespie 4244c87b03e5Sespie if (TARGET_64BIT) 4245c87b03e5Sespie { 4246c87b03e5Sespie operands[5] = gen_rtx_REG (SImode, 2); 4247c87b03e5Sespie operands[4] = operands[5]; 4248c87b03e5Sespie } 4249c87b03e5Sespie else 4250c87b03e5Sespie { 4251c87b03e5Sespie operands[5] = gen_rtx_REG (SImode, 31); 4252c87b03e5Sespie operands[4] = gen_reg_rtx (SImode); 4253c87b03e5Sespie } 4254c87b03e5Sespie if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1)) 4255c87b03e5Sespie DONE; 4256c87b03e5Sespie}") 4257c87b03e5Sespie 4258c87b03e5Sespie(define_insn "" 4259c87b03e5Sespie [(set (reg:SI 29) 4260c87b03e5Sespie (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" ""))) 4261c87b03e5Sespie (clobber (match_operand:SI 1 "register_operand" "=a")) 4262c87b03e5Sespie (clobber (match_operand:SI 2 "register_operand" "=&r")) 4263c87b03e5Sespie (clobber (reg:SI 26)) 4264c87b03e5Sespie (clobber (reg:SI 25)) 4265c87b03e5Sespie (clobber (reg:SI 31))] 4266c87b03e5Sespie "!TARGET_64BIT" 4267c87b03e5Sespie "* 4268c87b03e5Sespie return output_div_insn (operands, 1, insn);" 4269c87b03e5Sespie [(set_attr "type" "milli") 4270c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) 4271c87b03e5Sespie 4272c87b03e5Sespie(define_insn "" 4273c87b03e5Sespie [(set (reg:SI 29) 4274c87b03e5Sespie (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" ""))) 4275c87b03e5Sespie (clobber (match_operand:SI 1 "register_operand" "=a")) 4276c87b03e5Sespie (clobber (match_operand:SI 2 "register_operand" "=&r")) 4277c87b03e5Sespie (clobber (reg:SI 26)) 4278c87b03e5Sespie (clobber (reg:SI 25)) 4279c87b03e5Sespie (clobber (reg:SI 2))] 4280c87b03e5Sespie "TARGET_64BIT" 4281c87b03e5Sespie "* 4282c87b03e5Sespie return output_div_insn (operands, 1, insn);" 4283c87b03e5Sespie [(set_attr "type" "milli") 4284c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) 4285c87b03e5Sespie 4286c87b03e5Sespie(define_expand "modsi3" 4287c87b03e5Sespie [(set (reg:SI 26) (match_operand:SI 1 "move_operand" "")) 4288c87b03e5Sespie (set (reg:SI 25) (match_operand:SI 2 "move_operand" "")) 4289c87b03e5Sespie (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25))) 4290c87b03e5Sespie (clobber (match_dup 3)) 4291c87b03e5Sespie (clobber (match_dup 4)) 4292c87b03e5Sespie (clobber (reg:SI 26)) 4293c87b03e5Sespie (clobber (reg:SI 25)) 4294c87b03e5Sespie (clobber (match_dup 5))]) 4295c87b03e5Sespie (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))] 4296c87b03e5Sespie "" 4297c87b03e5Sespie " 4298c87b03e5Sespie{ 4299c87b03e5Sespie if (TARGET_64BIT) 4300c87b03e5Sespie { 4301c87b03e5Sespie operands[5] = gen_rtx_REG (SImode, 2); 4302c87b03e5Sespie operands[4] = operands[5]; 4303c87b03e5Sespie } 4304c87b03e5Sespie else 4305c87b03e5Sespie { 4306c87b03e5Sespie operands[5] = gen_rtx_REG (SImode, 31); 4307c87b03e5Sespie operands[4] = gen_reg_rtx (SImode); 4308c87b03e5Sespie } 4309c87b03e5Sespie operands[3] = gen_reg_rtx (SImode); 4310c87b03e5Sespie}") 4311c87b03e5Sespie 4312c87b03e5Sespie(define_insn "" 4313c87b03e5Sespie [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25))) 4314c87b03e5Sespie (clobber (match_operand:SI 0 "register_operand" "=a")) 4315c87b03e5Sespie (clobber (match_operand:SI 1 "register_operand" "=&r")) 4316c87b03e5Sespie (clobber (reg:SI 26)) 4317c87b03e5Sespie (clobber (reg:SI 25)) 4318c87b03e5Sespie (clobber (reg:SI 31))] 4319c87b03e5Sespie "!TARGET_64BIT" 4320c87b03e5Sespie "* 4321c87b03e5Sespie return output_mod_insn (0, insn);" 4322c87b03e5Sespie [(set_attr "type" "milli") 4323c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) 4324c87b03e5Sespie 4325c87b03e5Sespie(define_insn "" 4326c87b03e5Sespie [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25))) 4327c87b03e5Sespie (clobber (match_operand:SI 0 "register_operand" "=a")) 4328c87b03e5Sespie (clobber (match_operand:SI 1 "register_operand" "=&r")) 4329c87b03e5Sespie (clobber (reg:SI 26)) 4330c87b03e5Sespie (clobber (reg:SI 25)) 4331c87b03e5Sespie (clobber (reg:SI 2))] 4332c87b03e5Sespie "TARGET_64BIT" 4333c87b03e5Sespie "* 4334c87b03e5Sespie return output_mod_insn (0, insn);" 4335c87b03e5Sespie [(set_attr "type" "milli") 4336c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) 4337c87b03e5Sespie 4338c87b03e5Sespie(define_expand "umodsi3" 4339c87b03e5Sespie [(set (reg:SI 26) (match_operand:SI 1 "move_operand" "")) 4340c87b03e5Sespie (set (reg:SI 25) (match_operand:SI 2 "move_operand" "")) 4341c87b03e5Sespie (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25))) 4342c87b03e5Sespie (clobber (match_dup 3)) 4343c87b03e5Sespie (clobber (match_dup 4)) 4344c87b03e5Sespie (clobber (reg:SI 26)) 4345c87b03e5Sespie (clobber (reg:SI 25)) 4346c87b03e5Sespie (clobber (match_dup 5))]) 4347c87b03e5Sespie (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))] 4348c87b03e5Sespie "" 4349c87b03e5Sespie " 4350c87b03e5Sespie{ 4351c87b03e5Sespie if (TARGET_64BIT) 4352c87b03e5Sespie { 4353c87b03e5Sespie operands[5] = gen_rtx_REG (SImode, 2); 4354c87b03e5Sespie operands[4] = operands[5]; 4355c87b03e5Sespie } 4356c87b03e5Sespie else 4357c87b03e5Sespie { 4358c87b03e5Sespie operands[5] = gen_rtx_REG (SImode, 31); 4359c87b03e5Sespie operands[4] = gen_reg_rtx (SImode); 4360c87b03e5Sespie } 4361c87b03e5Sespie operands[3] = gen_reg_rtx (SImode); 4362c87b03e5Sespie}") 4363c87b03e5Sespie 4364c87b03e5Sespie(define_insn "" 4365c87b03e5Sespie [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25))) 4366c87b03e5Sespie (clobber (match_operand:SI 0 "register_operand" "=a")) 4367c87b03e5Sespie (clobber (match_operand:SI 1 "register_operand" "=&r")) 4368c87b03e5Sespie (clobber (reg:SI 26)) 4369c87b03e5Sespie (clobber (reg:SI 25)) 4370c87b03e5Sespie (clobber (reg:SI 31))] 4371c87b03e5Sespie "!TARGET_64BIT" 4372c87b03e5Sespie "* 4373c87b03e5Sespie return output_mod_insn (1, insn);" 4374c87b03e5Sespie [(set_attr "type" "milli") 4375c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) 4376c87b03e5Sespie 4377c87b03e5Sespie(define_insn "" 4378c87b03e5Sespie [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25))) 4379c87b03e5Sespie (clobber (match_operand:SI 0 "register_operand" "=a")) 4380c87b03e5Sespie (clobber (match_operand:SI 1 "register_operand" "=&r")) 4381c87b03e5Sespie (clobber (reg:SI 26)) 4382c87b03e5Sespie (clobber (reg:SI 25)) 4383c87b03e5Sespie (clobber (reg:SI 2))] 4384c87b03e5Sespie "TARGET_64BIT" 4385c87b03e5Sespie "* 4386c87b03e5Sespie return output_mod_insn (1, insn);" 4387c87b03e5Sespie [(set_attr "type" "milli") 4388c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) 4389c87b03e5Sespie 4390c87b03e5Sespie;;- and instructions 4391c87b03e5Sespie;; We define DImode `and` so with DImode `not` we can get 4392c87b03e5Sespie;; DImode `andn`. Other combinations are possible. 4393c87b03e5Sespie 4394c87b03e5Sespie(define_expand "anddi3" 4395c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 4396*a67f0032Smiod (and:DI (match_operand:DI 1 "register_operand" "") 4397c87b03e5Sespie (match_operand:DI 2 "arith_double_operand" "")))] 4398c87b03e5Sespie "" 4399c87b03e5Sespie " 4400c87b03e5Sespie{ 44014e43c760Sespie /* Both operands must be register operands. */ 4402*a67f0032Smiod if (!TARGET_64BIT && !register_operand (operands[2], DImode)) 4403c87b03e5Sespie FAIL; 4404c87b03e5Sespie}") 4405c87b03e5Sespie 4406c87b03e5Sespie(define_insn "" 4407c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4408c87b03e5Sespie (and:DI (match_operand:DI 1 "register_operand" "%r") 4409c87b03e5Sespie (match_operand:DI 2 "register_operand" "r")))] 4410c87b03e5Sespie "!TARGET_64BIT" 4411c87b03e5Sespie "and %1,%2,%0\;and %R1,%R2,%R0" 4412c87b03e5Sespie [(set_attr "type" "binary") 4413c87b03e5Sespie (set_attr "length" "8")]) 4414c87b03e5Sespie 4415c87b03e5Sespie(define_insn "" 4416c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r") 4417c87b03e5Sespie (and:DI (match_operand:DI 1 "register_operand" "%?r,0") 4418c87b03e5Sespie (match_operand:DI 2 "and_operand" "rO,P")))] 4419c87b03e5Sespie "TARGET_64BIT" 4420c87b03e5Sespie "* return output_64bit_and (operands); " 4421c87b03e5Sespie [(set_attr "type" "binary") 4422c87b03e5Sespie (set_attr "length" "4")]) 4423c87b03e5Sespie 4424c87b03e5Sespie; The ? for op1 makes reload prefer zdepi instead of loading a huge 4425c87b03e5Sespie; constant with ldil;ldo. 4426c87b03e5Sespie(define_insn "andsi3" 4427c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 4428c87b03e5Sespie (and:SI (match_operand:SI 1 "register_operand" "%?r,0") 4429c87b03e5Sespie (match_operand:SI 2 "and_operand" "rO,P")))] 4430c87b03e5Sespie "" 4431c87b03e5Sespie "* return output_and (operands); " 4432c87b03e5Sespie [(set_attr "type" "binary,shift") 4433c87b03e5Sespie (set_attr "length" "4,4")]) 4434c87b03e5Sespie 4435c87b03e5Sespie(define_insn "" 4436c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4437c87b03e5Sespie (and:DI (not:DI (match_operand:DI 1 "register_operand" "r")) 4438c87b03e5Sespie (match_operand:DI 2 "register_operand" "r")))] 4439c87b03e5Sespie "!TARGET_64BIT" 4440c87b03e5Sespie "andcm %2,%1,%0\;andcm %R2,%R1,%R0" 4441c87b03e5Sespie [(set_attr "type" "binary") 4442c87b03e5Sespie (set_attr "length" "8")]) 4443c87b03e5Sespie 4444c87b03e5Sespie(define_insn "" 4445c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4446c87b03e5Sespie (and:DI (not:DI (match_operand:DI 1 "register_operand" "r")) 4447c87b03e5Sespie (match_operand:DI 2 "register_operand" "r")))] 4448c87b03e5Sespie "TARGET_64BIT" 4449c87b03e5Sespie "andcm %2,%1,%0" 4450c87b03e5Sespie [(set_attr "type" "binary") 4451c87b03e5Sespie (set_attr "length" "4")]) 4452c87b03e5Sespie 4453c87b03e5Sespie(define_insn "" 4454c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 4455c87b03e5Sespie (and:SI (not:SI (match_operand:SI 1 "register_operand" "r")) 4456c87b03e5Sespie (match_operand:SI 2 "register_operand" "r")))] 4457c87b03e5Sespie "" 4458c87b03e5Sespie "andcm %2,%1,%0" 4459c87b03e5Sespie [(set_attr "type" "binary") 4460c87b03e5Sespie (set_attr "length" "4")]) 4461c87b03e5Sespie 4462c87b03e5Sespie(define_expand "iordi3" 4463c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 4464*a67f0032Smiod (ior:DI (match_operand:DI 1 "register_operand" "") 4465c87b03e5Sespie (match_operand:DI 2 "arith_double_operand" "")))] 4466c87b03e5Sespie "" 4467c87b03e5Sespie " 4468c87b03e5Sespie{ 4469*a67f0032Smiod /* Both operands must be register operands. */ 4470*a67f0032Smiod if (!TARGET_64BIT && !register_operand (operands[2], DImode)) 4471c87b03e5Sespie FAIL; 4472c87b03e5Sespie}") 4473c87b03e5Sespie 4474c87b03e5Sespie(define_insn "" 4475c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4476c87b03e5Sespie (ior:DI (match_operand:DI 1 "register_operand" "%r") 4477c87b03e5Sespie (match_operand:DI 2 "register_operand" "r")))] 4478c87b03e5Sespie "!TARGET_64BIT" 4479c87b03e5Sespie "or %1,%2,%0\;or %R1,%R2,%R0" 4480c87b03e5Sespie [(set_attr "type" "binary") 4481c87b03e5Sespie (set_attr "length" "8")]) 4482c87b03e5Sespie 4483c87b03e5Sespie(define_insn "" 4484c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r") 4485c87b03e5Sespie (ior:DI (match_operand:DI 1 "register_operand" "0,0") 4486c87b03e5Sespie (match_operand:DI 2 "ior_operand" "M,i")))] 4487c87b03e5Sespie "TARGET_64BIT" 4488c87b03e5Sespie "* return output_64bit_ior (operands); " 4489c87b03e5Sespie [(set_attr "type" "binary,shift") 4490c87b03e5Sespie (set_attr "length" "4,4")]) 4491c87b03e5Sespie 4492c87b03e5Sespie(define_insn "" 4493c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4494c87b03e5Sespie (ior:DI (match_operand:DI 1 "register_operand" "%r") 4495c87b03e5Sespie (match_operand:DI 2 "register_operand" "r")))] 4496c87b03e5Sespie "TARGET_64BIT" 4497c87b03e5Sespie "or %1,%2,%0" 4498c87b03e5Sespie [(set_attr "type" "binary") 4499c87b03e5Sespie (set_attr "length" "4")]) 4500c87b03e5Sespie 4501c87b03e5Sespie;; Need a define_expand because we've run out of CONST_OK... characters. 4502c87b03e5Sespie(define_expand "iorsi3" 4503c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 4504c87b03e5Sespie (ior:SI (match_operand:SI 1 "register_operand" "") 4505c87b03e5Sespie (match_operand:SI 2 "arith32_operand" "")))] 4506c87b03e5Sespie "" 4507c87b03e5Sespie " 4508c87b03e5Sespie{ 4509c87b03e5Sespie if (! (ior_operand (operands[2], SImode) 4510c87b03e5Sespie || register_operand (operands[2], SImode))) 4511c87b03e5Sespie operands[2] = force_reg (SImode, operands[2]); 4512c87b03e5Sespie}") 4513c87b03e5Sespie 4514c87b03e5Sespie(define_insn "" 4515c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 4516c87b03e5Sespie (ior:SI (match_operand:SI 1 "register_operand" "0,0") 4517c87b03e5Sespie (match_operand:SI 2 "ior_operand" "M,i")))] 4518c87b03e5Sespie "" 4519c87b03e5Sespie "* return output_ior (operands); " 4520c87b03e5Sespie [(set_attr "type" "binary,shift") 4521c87b03e5Sespie (set_attr "length" "4,4")]) 4522c87b03e5Sespie 4523c87b03e5Sespie(define_insn "" 4524c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 4525c87b03e5Sespie (ior:SI (match_operand:SI 1 "register_operand" "%r") 4526c87b03e5Sespie (match_operand:SI 2 "register_operand" "r")))] 4527c87b03e5Sespie "" 4528c87b03e5Sespie "or %1,%2,%0" 4529c87b03e5Sespie [(set_attr "type" "binary") 4530c87b03e5Sespie (set_attr "length" "4")]) 4531c87b03e5Sespie 4532c87b03e5Sespie(define_expand "xordi3" 4533c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 4534c87b03e5Sespie (xor:DI (match_operand:DI 1 "arith_double_operand" "") 4535c87b03e5Sespie (match_operand:DI 2 "arith_double_operand" "")))] 4536c87b03e5Sespie "" 4537c87b03e5Sespie " 4538c87b03e5Sespie{ 4539c87b03e5Sespie if (! register_operand (operands[1], DImode) 4540c87b03e5Sespie || ! register_operand (operands[2], DImode)) 4541c87b03e5Sespie /* Let GCC break this into word-at-a-time operations. */ 4542c87b03e5Sespie FAIL; 4543c87b03e5Sespie}") 4544c87b03e5Sespie 4545c87b03e5Sespie(define_insn "" 4546c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4547c87b03e5Sespie (xor:DI (match_operand:DI 1 "register_operand" "%r") 4548c87b03e5Sespie (match_operand:DI 2 "register_operand" "r")))] 4549c87b03e5Sespie "!TARGET_64BIT" 4550c87b03e5Sespie "xor %1,%2,%0\;xor %R1,%R2,%R0" 4551c87b03e5Sespie [(set_attr "type" "binary") 4552c87b03e5Sespie (set_attr "length" "8")]) 4553c87b03e5Sespie 4554c87b03e5Sespie(define_insn "" 4555c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4556c87b03e5Sespie (xor:DI (match_operand:DI 1 "register_operand" "%r") 4557c87b03e5Sespie (match_operand:DI 2 "register_operand" "r")))] 4558c87b03e5Sespie "TARGET_64BIT" 4559c87b03e5Sespie "xor %1,%2,%0" 4560c87b03e5Sespie [(set_attr "type" "binary") 4561c87b03e5Sespie (set_attr "length" "4")]) 4562c87b03e5Sespie 4563c87b03e5Sespie(define_insn "xorsi3" 4564c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 4565c87b03e5Sespie (xor:SI (match_operand:SI 1 "register_operand" "%r") 4566c87b03e5Sespie (match_operand:SI 2 "register_operand" "r")))] 4567c87b03e5Sespie "" 4568c87b03e5Sespie "xor %1,%2,%0" 4569c87b03e5Sespie [(set_attr "type" "binary") 4570c87b03e5Sespie (set_attr "length" "4")]) 4571c87b03e5Sespie 4572c87b03e5Sespie(define_expand "negdi2" 4573c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 4574c87b03e5Sespie (neg:DI (match_operand:DI 1 "register_operand" "")))] 4575c87b03e5Sespie "" 4576c87b03e5Sespie "") 4577c87b03e5Sespie 4578c87b03e5Sespie(define_insn "" 4579c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4580c87b03e5Sespie (neg:DI (match_operand:DI 1 "register_operand" "r")))] 4581c87b03e5Sespie "!TARGET_64BIT" 4582c87b03e5Sespie "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0" 4583c87b03e5Sespie [(set_attr "type" "unary") 4584c87b03e5Sespie (set_attr "length" "8")]) 4585c87b03e5Sespie 4586c87b03e5Sespie(define_insn "" 4587c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4588c87b03e5Sespie (neg:DI (match_operand:DI 1 "register_operand" "r")))] 4589c87b03e5Sespie "TARGET_64BIT" 4590c87b03e5Sespie "sub %%r0,%1,%0" 4591c87b03e5Sespie [(set_attr "type" "unary") 4592c87b03e5Sespie (set_attr "length" "4")]) 4593c87b03e5Sespie 4594c87b03e5Sespie(define_insn "negsi2" 4595c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 4596c87b03e5Sespie (neg:SI (match_operand:SI 1 "register_operand" "r")))] 4597c87b03e5Sespie "" 4598c87b03e5Sespie "sub %%r0,%1,%0" 4599c87b03e5Sespie [(set_attr "type" "unary") 4600c87b03e5Sespie (set_attr "length" "4")]) 4601c87b03e5Sespie 4602c87b03e5Sespie(define_expand "one_cmpldi2" 4603c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 4604c87b03e5Sespie (not:DI (match_operand:DI 1 "arith_double_operand" "")))] 4605c87b03e5Sespie "" 4606c87b03e5Sespie " 4607c87b03e5Sespie{ 4608c87b03e5Sespie if (! register_operand (operands[1], DImode)) 4609c87b03e5Sespie FAIL; 4610c87b03e5Sespie}") 4611c87b03e5Sespie 4612c87b03e5Sespie(define_insn "" 4613c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4614c87b03e5Sespie (not:DI (match_operand:DI 1 "register_operand" "r")))] 4615c87b03e5Sespie "!TARGET_64BIT" 4616c87b03e5Sespie "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0" 4617c87b03e5Sespie [(set_attr "type" "unary") 4618c87b03e5Sespie (set_attr "length" "8")]) 4619c87b03e5Sespie 4620c87b03e5Sespie(define_insn "" 4621c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 4622c87b03e5Sespie (not:DI (match_operand:DI 1 "register_operand" "r")))] 4623c87b03e5Sespie "TARGET_64BIT" 4624c87b03e5Sespie "uaddcm %%r0,%1,%0" 4625c87b03e5Sespie [(set_attr "type" "unary") 4626c87b03e5Sespie (set_attr "length" "4")]) 4627c87b03e5Sespie 4628c87b03e5Sespie(define_insn "one_cmplsi2" 4629c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 4630c87b03e5Sespie (not:SI (match_operand:SI 1 "register_operand" "r")))] 4631c87b03e5Sespie "" 4632c87b03e5Sespie "uaddcm %%r0,%1,%0" 4633c87b03e5Sespie [(set_attr "type" "unary") 4634c87b03e5Sespie (set_attr "length" "4")]) 4635c87b03e5Sespie 4636c87b03e5Sespie;; Floating point arithmetic instructions. 4637c87b03e5Sespie 4638c87b03e5Sespie(define_insn "adddf3" 4639c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4640c87b03e5Sespie (plus:DF (match_operand:DF 1 "register_operand" "f") 4641c87b03e5Sespie (match_operand:DF 2 "register_operand" "f")))] 4642c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4643c87b03e5Sespie "fadd,dbl %1,%2,%0" 4644c87b03e5Sespie [(set_attr "type" "fpalu") 4645c87b03e5Sespie (set_attr "pa_combine_type" "faddsub") 4646c87b03e5Sespie (set_attr "length" "4")]) 4647c87b03e5Sespie 4648c87b03e5Sespie(define_insn "addsf3" 4649c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4650c87b03e5Sespie (plus:SF (match_operand:SF 1 "register_operand" "f") 4651c87b03e5Sespie (match_operand:SF 2 "register_operand" "f")))] 4652c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4653c87b03e5Sespie "fadd,sgl %1,%2,%0" 4654c87b03e5Sespie [(set_attr "type" "fpalu") 4655c87b03e5Sespie (set_attr "pa_combine_type" "faddsub") 4656c87b03e5Sespie (set_attr "length" "4")]) 4657c87b03e5Sespie 4658c87b03e5Sespie(define_insn "subdf3" 4659c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4660c87b03e5Sespie (minus:DF (match_operand:DF 1 "register_operand" "f") 4661c87b03e5Sespie (match_operand:DF 2 "register_operand" "f")))] 4662c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4663c87b03e5Sespie "fsub,dbl %1,%2,%0" 4664c87b03e5Sespie [(set_attr "type" "fpalu") 4665c87b03e5Sespie (set_attr "pa_combine_type" "faddsub") 4666c87b03e5Sespie (set_attr "length" "4")]) 4667c87b03e5Sespie 4668c87b03e5Sespie(define_insn "subsf3" 4669c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4670c87b03e5Sespie (minus:SF (match_operand:SF 1 "register_operand" "f") 4671c87b03e5Sespie (match_operand:SF 2 "register_operand" "f")))] 4672c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4673c87b03e5Sespie "fsub,sgl %1,%2,%0" 4674c87b03e5Sespie [(set_attr "type" "fpalu") 4675c87b03e5Sespie (set_attr "pa_combine_type" "faddsub") 4676c87b03e5Sespie (set_attr "length" "4")]) 4677c87b03e5Sespie 4678c87b03e5Sespie(define_insn "muldf3" 4679c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4680c87b03e5Sespie (mult:DF (match_operand:DF 1 "register_operand" "f") 4681c87b03e5Sespie (match_operand:DF 2 "register_operand" "f")))] 4682c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4683c87b03e5Sespie "fmpy,dbl %1,%2,%0" 4684c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4685c87b03e5Sespie (set_attr "pa_combine_type" "fmpy") 4686c87b03e5Sespie (set_attr "length" "4")]) 4687c87b03e5Sespie 4688c87b03e5Sespie(define_insn "mulsf3" 4689c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4690c87b03e5Sespie (mult:SF (match_operand:SF 1 "register_operand" "f") 4691c87b03e5Sespie (match_operand:SF 2 "register_operand" "f")))] 4692c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4693c87b03e5Sespie "fmpy,sgl %1,%2,%0" 4694c87b03e5Sespie [(set_attr "type" "fpmulsgl") 4695c87b03e5Sespie (set_attr "pa_combine_type" "fmpy") 4696c87b03e5Sespie (set_attr "length" "4")]) 4697c87b03e5Sespie 4698c87b03e5Sespie(define_insn "divdf3" 4699c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4700c87b03e5Sespie (div:DF (match_operand:DF 1 "register_operand" "f") 4701c87b03e5Sespie (match_operand:DF 2 "register_operand" "f")))] 4702c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4703c87b03e5Sespie "fdiv,dbl %1,%2,%0" 4704c87b03e5Sespie [(set_attr "type" "fpdivdbl") 4705c87b03e5Sespie (set_attr "length" "4")]) 4706c87b03e5Sespie 4707c87b03e5Sespie(define_insn "divsf3" 4708c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4709c87b03e5Sespie (div:SF (match_operand:SF 1 "register_operand" "f") 4710c87b03e5Sespie (match_operand:SF 2 "register_operand" "f")))] 4711c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4712c87b03e5Sespie "fdiv,sgl %1,%2,%0" 4713c87b03e5Sespie [(set_attr "type" "fpdivsgl") 4714c87b03e5Sespie (set_attr "length" "4")]) 4715c87b03e5Sespie 4716c87b03e5Sespie;; Processors prior to PA 2.0 don't have a fneg instruction. Fast 4717c87b03e5Sespie;; negation can be done by subtracting from plus zero. However, this 4718c87b03e5Sespie;; violates the IEEE standard when negating plus and minus zero. 4719c87b03e5Sespie(define_expand "negdf2" 4720c87b03e5Sespie [(parallel [(set (match_operand:DF 0 "register_operand" "") 4721c87b03e5Sespie (neg:DF (match_operand:DF 1 "register_operand" ""))) 4722c87b03e5Sespie (use (match_dup 2))])] 4723c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4724c87b03e5Sespie{ 4725c87b03e5Sespie if (TARGET_PA_20 || flag_unsafe_math_optimizations) 4726c87b03e5Sespie emit_insn (gen_negdf2_fast (operands[0], operands[1])); 4727c87b03e5Sespie else 4728c87b03e5Sespie { 4729c87b03e5Sespie operands[2] = force_reg (DFmode, 4730c87b03e5Sespie CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode)); 4731c87b03e5Sespie emit_insn (gen_muldf3 (operands[0], operands[1], operands[2])); 4732c87b03e5Sespie } 4733c87b03e5Sespie DONE; 4734c87b03e5Sespie}) 4735c87b03e5Sespie 4736c87b03e5Sespie(define_insn "negdf2_fast" 4737c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4738c87b03e5Sespie (neg:DF (match_operand:DF 1 "register_operand" "f")))] 4739c87b03e5Sespie "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)" 4740c87b03e5Sespie "* 4741c87b03e5Sespie{ 4742c87b03e5Sespie if (TARGET_PA_20) 4743c87b03e5Sespie return \"fneg,dbl %1,%0\"; 4744c87b03e5Sespie else 4745c87b03e5Sespie return \"fsub,dbl %%fr0,%1,%0\"; 4746c87b03e5Sespie}" 4747c87b03e5Sespie [(set_attr "type" "fpalu") 4748c87b03e5Sespie (set_attr "length" "4")]) 4749c87b03e5Sespie 4750c87b03e5Sespie(define_expand "negsf2" 4751c87b03e5Sespie [(parallel [(set (match_operand:SF 0 "register_operand" "") 4752c87b03e5Sespie (neg:SF (match_operand:SF 1 "register_operand" ""))) 4753c87b03e5Sespie (use (match_dup 2))])] 4754c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4755c87b03e5Sespie{ 4756c87b03e5Sespie if (TARGET_PA_20 || flag_unsafe_math_optimizations) 4757c87b03e5Sespie emit_insn (gen_negsf2_fast (operands[0], operands[1])); 4758c87b03e5Sespie else 4759c87b03e5Sespie { 4760c87b03e5Sespie operands[2] = force_reg (SFmode, 4761c87b03e5Sespie CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode)); 4762c87b03e5Sespie emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2])); 4763c87b03e5Sespie } 4764c87b03e5Sespie DONE; 4765c87b03e5Sespie}) 4766c87b03e5Sespie 4767c87b03e5Sespie(define_insn "negsf2_fast" 4768c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4769c87b03e5Sespie (neg:SF (match_operand:SF 1 "register_operand" "f")))] 4770c87b03e5Sespie "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)" 4771c87b03e5Sespie "* 4772c87b03e5Sespie{ 4773c87b03e5Sespie if (TARGET_PA_20) 4774c87b03e5Sespie return \"fneg,sgl %1,%0\"; 4775c87b03e5Sespie else 4776c87b03e5Sespie return \"fsub,sgl %%fr0,%1,%0\"; 4777c87b03e5Sespie}" 4778c87b03e5Sespie [(set_attr "type" "fpalu") 4779c87b03e5Sespie (set_attr "length" "4")]) 4780c87b03e5Sespie 4781c87b03e5Sespie(define_insn "absdf2" 4782c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4783c87b03e5Sespie (abs:DF (match_operand:DF 1 "register_operand" "f")))] 4784c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4785c87b03e5Sespie "fabs,dbl %1,%0" 4786c87b03e5Sespie [(set_attr "type" "fpalu") 4787c87b03e5Sespie (set_attr "length" "4")]) 4788c87b03e5Sespie 4789c87b03e5Sespie(define_insn "abssf2" 4790c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4791c87b03e5Sespie (abs:SF (match_operand:SF 1 "register_operand" "f")))] 4792c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4793c87b03e5Sespie "fabs,sgl %1,%0" 4794c87b03e5Sespie [(set_attr "type" "fpalu") 4795c87b03e5Sespie (set_attr "length" "4")]) 4796c87b03e5Sespie 4797c87b03e5Sespie(define_insn "sqrtdf2" 4798c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4799c87b03e5Sespie (sqrt:DF (match_operand:DF 1 "register_operand" "f")))] 4800c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4801c87b03e5Sespie "fsqrt,dbl %1,%0" 4802c87b03e5Sespie [(set_attr "type" "fpsqrtdbl") 4803c87b03e5Sespie (set_attr "length" "4")]) 4804c87b03e5Sespie 4805c87b03e5Sespie(define_insn "sqrtsf2" 4806c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4807c87b03e5Sespie (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] 4808c87b03e5Sespie "! TARGET_SOFT_FLOAT" 4809c87b03e5Sespie "fsqrt,sgl %1,%0" 4810c87b03e5Sespie [(set_attr "type" "fpsqrtsgl") 4811c87b03e5Sespie (set_attr "length" "4")]) 4812c87b03e5Sespie 4813c87b03e5Sespie;; PA 2.0 floating point instructions 4814c87b03e5Sespie 4815c87b03e5Sespie; fmpyfadd patterns 4816c87b03e5Sespie(define_insn "" 4817c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4818c87b03e5Sespie (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") 4819c87b03e5Sespie (match_operand:DF 2 "register_operand" "f")) 4820c87b03e5Sespie (match_operand:DF 3 "register_operand" "f")))] 4821c87b03e5Sespie "TARGET_PA_20 && ! TARGET_SOFT_FLOAT" 4822c87b03e5Sespie "fmpyfadd,dbl %1,%2,%3,%0" 4823c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4824c87b03e5Sespie (set_attr "length" "4")]) 4825c87b03e5Sespie 4826c87b03e5Sespie(define_insn "" 4827c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4828c87b03e5Sespie (plus:DF (match_operand:DF 1 "register_operand" "f") 4829c87b03e5Sespie (mult:DF (match_operand:DF 2 "register_operand" "f") 4830c87b03e5Sespie (match_operand:DF 3 "register_operand" "f"))))] 4831c87b03e5Sespie "TARGET_PA_20 && ! TARGET_SOFT_FLOAT" 4832c87b03e5Sespie "fmpyfadd,dbl %2,%3,%1,%0" 4833c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4834c87b03e5Sespie (set_attr "length" "4")]) 4835c87b03e5Sespie 4836c87b03e5Sespie(define_insn "" 4837c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4838c87b03e5Sespie (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") 4839c87b03e5Sespie (match_operand:SF 2 "register_operand" "f")) 4840c87b03e5Sespie (match_operand:SF 3 "register_operand" "f")))] 4841c87b03e5Sespie "TARGET_PA_20 && ! TARGET_SOFT_FLOAT" 4842c87b03e5Sespie "fmpyfadd,sgl %1,%2,%3,%0" 4843c87b03e5Sespie [(set_attr "type" "fpmulsgl") 4844c87b03e5Sespie (set_attr "length" "4")]) 4845c87b03e5Sespie 4846c87b03e5Sespie(define_insn "" 4847c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4848c87b03e5Sespie (plus:SF (match_operand:SF 1 "register_operand" "f") 4849c87b03e5Sespie (mult:SF (match_operand:SF 2 "register_operand" "f") 4850c87b03e5Sespie (match_operand:SF 3 "register_operand" "f"))))] 4851c87b03e5Sespie "TARGET_PA_20 && ! TARGET_SOFT_FLOAT" 4852c87b03e5Sespie "fmpyfadd,sgl %2,%3,%1,%0" 4853c87b03e5Sespie [(set_attr "type" "fpmulsgl") 4854c87b03e5Sespie (set_attr "length" "4")]) 4855c87b03e5Sespie 4856c87b03e5Sespie; fmpynfadd patterns 4857c87b03e5Sespie(define_insn "" 4858c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4859c87b03e5Sespie (minus:DF (match_operand:DF 1 "register_operand" "f") 4860c87b03e5Sespie (mult:DF (match_operand:DF 2 "register_operand" "f") 4861c87b03e5Sespie (match_operand:DF 3 "register_operand" "f"))))] 4862c87b03e5Sespie "TARGET_PA_20 && ! TARGET_SOFT_FLOAT" 4863c87b03e5Sespie "fmpynfadd,dbl %2,%3,%1,%0" 4864c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4865c87b03e5Sespie (set_attr "length" "4")]) 4866c87b03e5Sespie 4867c87b03e5Sespie(define_insn "" 4868c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4869c87b03e5Sespie (minus:SF (match_operand:SF 1 "register_operand" "f") 4870c87b03e5Sespie (mult:SF (match_operand:SF 2 "register_operand" "f") 4871c87b03e5Sespie (match_operand:SF 3 "register_operand" "f"))))] 4872c87b03e5Sespie "TARGET_PA_20 && ! TARGET_SOFT_FLOAT" 4873c87b03e5Sespie "fmpynfadd,sgl %2,%3,%1,%0" 4874c87b03e5Sespie [(set_attr "type" "fpmulsgl") 4875c87b03e5Sespie (set_attr "length" "4")]) 4876c87b03e5Sespie 4877c87b03e5Sespie; fnegabs patterns 4878c87b03e5Sespie(define_insn "" 4879c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4880c87b03e5Sespie (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))] 4881c87b03e5Sespie "TARGET_PA_20 && ! TARGET_SOFT_FLOAT" 4882c87b03e5Sespie "fnegabs,dbl %1,%0" 4883c87b03e5Sespie [(set_attr "type" "fpalu") 4884c87b03e5Sespie (set_attr "length" "4")]) 4885c87b03e5Sespie 4886c87b03e5Sespie(define_insn "" 4887c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4888c87b03e5Sespie (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))] 4889c87b03e5Sespie "TARGET_PA_20 && ! TARGET_SOFT_FLOAT" 4890c87b03e5Sespie "fnegabs,sgl %1,%0" 4891c87b03e5Sespie [(set_attr "type" "fpalu") 4892c87b03e5Sespie (set_attr "length" "4")]) 4893c87b03e5Sespie 4894c87b03e5Sespie;; Generating a fused multiply sequence is a win for this case as it will 4895c87b03e5Sespie;; reduce the latency for the fused case without impacting the plain 4896c87b03e5Sespie;; multiply case. 4897c87b03e5Sespie;; 4898c87b03e5Sespie;; Similar possibilities exist for fnegabs, shadd and other insns which 4899c87b03e5Sespie;; perform two operations with the result of the first feeding the second. 4900c87b03e5Sespie(define_insn "" 4901c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4902c87b03e5Sespie (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") 4903c87b03e5Sespie (match_operand:DF 2 "register_operand" "f")) 4904c87b03e5Sespie (match_operand:DF 3 "register_operand" "f"))) 4905c87b03e5Sespie (set (match_operand:DF 4 "register_operand" "=&f") 4906c87b03e5Sespie (mult:DF (match_dup 1) (match_dup 2)))] 4907c87b03e5Sespie "(! TARGET_SOFT_FLOAT && TARGET_PA_20 4908c87b03e5Sespie && ! (reg_overlap_mentioned_p (operands[4], operands[1]) 4909c87b03e5Sespie || reg_overlap_mentioned_p (operands[4], operands[2])))" 4910c87b03e5Sespie "#" 4911c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4912c87b03e5Sespie (set_attr "length" "8")]) 4913c87b03e5Sespie 4914c87b03e5Sespie;; We want to split this up during scheduling since we want both insns 4915c87b03e5Sespie;; to schedule independently. 4916c87b03e5Sespie(define_split 4917c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "") 4918c87b03e5Sespie (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "") 4919c87b03e5Sespie (match_operand:DF 2 "register_operand" "")) 4920c87b03e5Sespie (match_operand:DF 3 "register_operand" ""))) 4921c87b03e5Sespie (set (match_operand:DF 4 "register_operand" "") 4922c87b03e5Sespie (mult:DF (match_dup 1) (match_dup 2)))] 4923c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 4924c87b03e5Sespie [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2))) 4925c87b03e5Sespie (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2)) 4926c87b03e5Sespie (match_dup 3)))] 4927c87b03e5Sespie "") 4928c87b03e5Sespie 4929c87b03e5Sespie(define_insn "" 4930c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4931c87b03e5Sespie (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") 4932c87b03e5Sespie (match_operand:SF 2 "register_operand" "f")) 4933c87b03e5Sespie (match_operand:SF 3 "register_operand" "f"))) 4934c87b03e5Sespie (set (match_operand:SF 4 "register_operand" "=&f") 4935c87b03e5Sespie (mult:SF (match_dup 1) (match_dup 2)))] 4936c87b03e5Sespie "(! TARGET_SOFT_FLOAT && TARGET_PA_20 4937c87b03e5Sespie && ! (reg_overlap_mentioned_p (operands[4], operands[1]) 4938c87b03e5Sespie || reg_overlap_mentioned_p (operands[4], operands[2])))" 4939c87b03e5Sespie "#" 4940c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4941c87b03e5Sespie (set_attr "length" "8")]) 4942c87b03e5Sespie 4943c87b03e5Sespie;; We want to split this up during scheduling since we want both insns 4944c87b03e5Sespie;; to schedule independently. 4945c87b03e5Sespie(define_split 4946c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "") 4947c87b03e5Sespie (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "") 4948c87b03e5Sespie (match_operand:SF 2 "register_operand" "")) 4949c87b03e5Sespie (match_operand:SF 3 "register_operand" ""))) 4950c87b03e5Sespie (set (match_operand:SF 4 "register_operand" "") 4951c87b03e5Sespie (mult:SF (match_dup 1) (match_dup 2)))] 4952c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 4953c87b03e5Sespie [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2))) 4954c87b03e5Sespie (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2)) 4955c87b03e5Sespie (match_dup 3)))] 4956c87b03e5Sespie "") 4957c87b03e5Sespie 4958c87b03e5Sespie;; Negating a multiply can be faked by adding zero in a fused multiply-add 4959c87b03e5Sespie;; instruction. 4960c87b03e5Sespie(define_insn "" 4961c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4962c87b03e5Sespie (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f") 4963c87b03e5Sespie (match_operand:DF 2 "register_operand" "f"))))] 4964c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 4965c87b03e5Sespie "fmpynfadd,dbl %1,%2,%%fr0,%0" 4966c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4967c87b03e5Sespie (set_attr "length" "4")]) 4968c87b03e5Sespie 4969c87b03e5Sespie(define_insn "" 4970c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 4971c87b03e5Sespie (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f") 4972c87b03e5Sespie (match_operand:SF 2 "register_operand" "f"))))] 4973c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 4974c87b03e5Sespie "fmpynfadd,sgl %1,%2,%%fr0,%0" 4975c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4976c87b03e5Sespie (set_attr "length" "4")]) 4977c87b03e5Sespie 4978c87b03e5Sespie(define_insn "" 4979c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 4980c87b03e5Sespie (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f") 4981c87b03e5Sespie (match_operand:DF 2 "register_operand" "f")))) 4982c87b03e5Sespie (set (match_operand:DF 3 "register_operand" "=&f") 4983c87b03e5Sespie (mult:DF (match_dup 1) (match_dup 2)))] 4984c87b03e5Sespie "(! TARGET_SOFT_FLOAT && TARGET_PA_20 4985c87b03e5Sespie && ! (reg_overlap_mentioned_p (operands[3], operands[1]) 4986c87b03e5Sespie || reg_overlap_mentioned_p (operands[3], operands[2])))" 4987c87b03e5Sespie "#" 4988c87b03e5Sespie [(set_attr "type" "fpmuldbl") 4989c87b03e5Sespie (set_attr "length" "8")]) 4990c87b03e5Sespie 4991c87b03e5Sespie(define_split 4992c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "") 4993c87b03e5Sespie (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "") 4994c87b03e5Sespie (match_operand:DF 2 "register_operand" "")))) 4995c87b03e5Sespie (set (match_operand:DF 3 "register_operand" "") 4996c87b03e5Sespie (mult:DF (match_dup 1) (match_dup 2)))] 4997c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 4998c87b03e5Sespie [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2))) 4999c87b03e5Sespie (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))] 5000c87b03e5Sespie "") 5001c87b03e5Sespie 5002c87b03e5Sespie(define_insn "" 5003c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 5004c87b03e5Sespie (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f") 5005c87b03e5Sespie (match_operand:SF 2 "register_operand" "f")))) 5006c87b03e5Sespie (set (match_operand:SF 3 "register_operand" "=&f") 5007c87b03e5Sespie (mult:SF (match_dup 1) (match_dup 2)))] 5008c87b03e5Sespie "(! TARGET_SOFT_FLOAT && TARGET_PA_20 5009c87b03e5Sespie && ! (reg_overlap_mentioned_p (operands[3], operands[1]) 5010c87b03e5Sespie || reg_overlap_mentioned_p (operands[3], operands[2])))" 5011c87b03e5Sespie "#" 5012c87b03e5Sespie [(set_attr "type" "fpmuldbl") 5013c87b03e5Sespie (set_attr "length" "8")]) 5014c87b03e5Sespie 5015c87b03e5Sespie(define_split 5016c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "") 5017c87b03e5Sespie (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "") 5018c87b03e5Sespie (match_operand:SF 2 "register_operand" "")))) 5019c87b03e5Sespie (set (match_operand:SF 3 "register_operand" "") 5020c87b03e5Sespie (mult:SF (match_dup 1) (match_dup 2)))] 5021c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 5022c87b03e5Sespie [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2))) 5023c87b03e5Sespie (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))] 5024c87b03e5Sespie "") 5025c87b03e5Sespie 5026c87b03e5Sespie;; Now fused multiplies with the result of the multiply negated. 5027c87b03e5Sespie(define_insn "" 5028c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 5029c87b03e5Sespie (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f") 5030c87b03e5Sespie (match_operand:DF 2 "register_operand" "f"))) 5031c87b03e5Sespie (match_operand:DF 3 "register_operand" "f")))] 5032c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 5033c87b03e5Sespie "fmpynfadd,dbl %1,%2,%3,%0" 5034c87b03e5Sespie [(set_attr "type" "fpmuldbl") 5035c87b03e5Sespie (set_attr "length" "4")]) 5036c87b03e5Sespie 5037c87b03e5Sespie(define_insn "" 5038c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 5039c87b03e5Sespie (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f") 5040c87b03e5Sespie (match_operand:SF 2 "register_operand" "f"))) 5041c87b03e5Sespie (match_operand:SF 3 "register_operand" "f")))] 5042c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 5043c87b03e5Sespie "fmpynfadd,sgl %1,%2,%3,%0" 5044c87b03e5Sespie [(set_attr "type" "fpmuldbl") 5045c87b03e5Sespie (set_attr "length" "4")]) 5046c87b03e5Sespie 5047c87b03e5Sespie(define_insn "" 5048c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 5049c87b03e5Sespie (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f") 5050c87b03e5Sespie (match_operand:DF 2 "register_operand" "f"))) 5051c87b03e5Sespie (match_operand:DF 3 "register_operand" "f"))) 5052c87b03e5Sespie (set (match_operand:DF 4 "register_operand" "=&f") 5053c87b03e5Sespie (mult:DF (match_dup 1) (match_dup 2)))] 5054c87b03e5Sespie "(! TARGET_SOFT_FLOAT && TARGET_PA_20 5055c87b03e5Sespie && ! (reg_overlap_mentioned_p (operands[4], operands[1]) 5056c87b03e5Sespie || reg_overlap_mentioned_p (operands[4], operands[2])))" 5057c87b03e5Sespie "#" 5058c87b03e5Sespie [(set_attr "type" "fpmuldbl") 5059c87b03e5Sespie (set_attr "length" "8")]) 5060c87b03e5Sespie 5061c87b03e5Sespie(define_split 5062c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "") 5063c87b03e5Sespie (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "") 5064c87b03e5Sespie (match_operand:DF 2 "register_operand" ""))) 5065c87b03e5Sespie (match_operand:DF 3 "register_operand" ""))) 5066c87b03e5Sespie (set (match_operand:DF 4 "register_operand" "") 5067c87b03e5Sespie (mult:DF (match_dup 1) (match_dup 2)))] 5068c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 5069c87b03e5Sespie [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2))) 5070c87b03e5Sespie (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2))) 5071c87b03e5Sespie (match_dup 3)))] 5072c87b03e5Sespie "") 5073c87b03e5Sespie 5074c87b03e5Sespie(define_insn "" 5075c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 5076c87b03e5Sespie (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f") 5077c87b03e5Sespie (match_operand:SF 2 "register_operand" "f"))) 5078c87b03e5Sespie (match_operand:SF 3 "register_operand" "f"))) 5079c87b03e5Sespie (set (match_operand:SF 4 "register_operand" "=&f") 5080c87b03e5Sespie (mult:SF (match_dup 1) (match_dup 2)))] 5081c87b03e5Sespie "(! TARGET_SOFT_FLOAT && TARGET_PA_20 5082c87b03e5Sespie && ! (reg_overlap_mentioned_p (operands[4], operands[1]) 5083c87b03e5Sespie || reg_overlap_mentioned_p (operands[4], operands[2])))" 5084c87b03e5Sespie "#" 5085c87b03e5Sespie [(set_attr "type" "fpmuldbl") 5086c87b03e5Sespie (set_attr "length" "8")]) 5087c87b03e5Sespie 5088c87b03e5Sespie(define_split 5089c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "") 5090c87b03e5Sespie (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "") 5091c87b03e5Sespie (match_operand:SF 2 "register_operand" ""))) 5092c87b03e5Sespie (match_operand:SF 3 "register_operand" ""))) 5093c87b03e5Sespie (set (match_operand:SF 4 "register_operand" "") 5094c87b03e5Sespie (mult:SF (match_dup 1) (match_dup 2)))] 5095c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 5096c87b03e5Sespie [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2))) 5097c87b03e5Sespie (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2))) 5098c87b03e5Sespie (match_dup 3)))] 5099c87b03e5Sespie "") 5100c87b03e5Sespie 5101c87b03e5Sespie(define_insn "" 5102c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 5103c87b03e5Sespie (minus:DF (match_operand:DF 3 "register_operand" "f") 5104c87b03e5Sespie (mult:DF (match_operand:DF 1 "register_operand" "f") 5105c87b03e5Sespie (match_operand:DF 2 "register_operand" "f")))) 5106c87b03e5Sespie (set (match_operand:DF 4 "register_operand" "=&f") 5107c87b03e5Sespie (mult:DF (match_dup 1) (match_dup 2)))] 5108c87b03e5Sespie "(! TARGET_SOFT_FLOAT && TARGET_PA_20 5109c87b03e5Sespie && ! (reg_overlap_mentioned_p (operands[4], operands[1]) 5110c87b03e5Sespie || reg_overlap_mentioned_p (operands[4], operands[2])))" 5111c87b03e5Sespie "#" 5112c87b03e5Sespie [(set_attr "type" "fpmuldbl") 5113c87b03e5Sespie (set_attr "length" "8")]) 5114c87b03e5Sespie 5115c87b03e5Sespie(define_split 5116c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "") 5117c87b03e5Sespie (minus:DF (match_operand:DF 3 "register_operand" "") 5118c87b03e5Sespie (mult:DF (match_operand:DF 1 "register_operand" "") 5119c87b03e5Sespie (match_operand:DF 2 "register_operand" "")))) 5120c87b03e5Sespie (set (match_operand:DF 4 "register_operand" "") 5121c87b03e5Sespie (mult:DF (match_dup 1) (match_dup 2)))] 5122c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 5123c87b03e5Sespie [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2))) 5124c87b03e5Sespie (set (match_dup 0) (minus:DF (match_dup 3) 5125c87b03e5Sespie (mult:DF (match_dup 1) (match_dup 2))))] 5126c87b03e5Sespie "") 5127c87b03e5Sespie 5128c87b03e5Sespie(define_insn "" 5129c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 5130c87b03e5Sespie (minus:SF (match_operand:SF 3 "register_operand" "f") 5131c87b03e5Sespie (mult:SF (match_operand:SF 1 "register_operand" "f") 5132c87b03e5Sespie (match_operand:SF 2 "register_operand" "f")))) 5133c87b03e5Sespie (set (match_operand:SF 4 "register_operand" "=&f") 5134c87b03e5Sespie (mult:SF (match_dup 1) (match_dup 2)))] 5135c87b03e5Sespie "(! TARGET_SOFT_FLOAT && TARGET_PA_20 5136c87b03e5Sespie && ! (reg_overlap_mentioned_p (operands[4], operands[1]) 5137c87b03e5Sespie || reg_overlap_mentioned_p (operands[4], operands[2])))" 5138c87b03e5Sespie "#" 5139c87b03e5Sespie [(set_attr "type" "fpmuldbl") 5140c87b03e5Sespie (set_attr "length" "8")]) 5141c87b03e5Sespie 5142c87b03e5Sespie(define_split 5143c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "") 5144c87b03e5Sespie (minus:SF (match_operand:SF 3 "register_operand" "") 5145c87b03e5Sespie (mult:SF (match_operand:SF 1 "register_operand" "") 5146c87b03e5Sespie (match_operand:SF 2 "register_operand" "")))) 5147c87b03e5Sespie (set (match_operand:SF 4 "register_operand" "") 5148c87b03e5Sespie (mult:SF (match_dup 1) (match_dup 2)))] 5149c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 5150c87b03e5Sespie [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2))) 5151c87b03e5Sespie (set (match_dup 0) (minus:SF (match_dup 3) 5152c87b03e5Sespie (mult:SF (match_dup 1) (match_dup 2))))] 5153c87b03e5Sespie "") 5154c87b03e5Sespie 5155c87b03e5Sespie(define_insn "" 5156c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "=f") 5157c87b03e5Sespie (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) 5158c87b03e5Sespie (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))] 5159c87b03e5Sespie "(! TARGET_SOFT_FLOAT && TARGET_PA_20 5160c87b03e5Sespie && ! reg_overlap_mentioned_p (operands[2], operands[1]))" 5161c87b03e5Sespie "#" 5162c87b03e5Sespie [(set_attr "type" "fpalu") 5163c87b03e5Sespie (set_attr "length" "8")]) 5164c87b03e5Sespie 5165c87b03e5Sespie(define_split 5166c87b03e5Sespie [(set (match_operand:DF 0 "register_operand" "") 5167c87b03e5Sespie (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "")))) 5168c87b03e5Sespie (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))] 5169c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 5170c87b03e5Sespie [(set (match_dup 2) (abs:DF (match_dup 1))) 5171c87b03e5Sespie (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))] 5172c87b03e5Sespie "") 5173c87b03e5Sespie 5174c87b03e5Sespie(define_insn "" 5175c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "=f") 5176c87b03e5Sespie (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) 5177c87b03e5Sespie (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))] 5178c87b03e5Sespie "(! TARGET_SOFT_FLOAT && TARGET_PA_20 5179c87b03e5Sespie && ! reg_overlap_mentioned_p (operands[2], operands[1]))" 5180c87b03e5Sespie "#" 5181c87b03e5Sespie [(set_attr "type" "fpalu") 5182c87b03e5Sespie (set_attr "length" "8")]) 5183c87b03e5Sespie 5184c87b03e5Sespie(define_split 5185c87b03e5Sespie [(set (match_operand:SF 0 "register_operand" "") 5186c87b03e5Sespie (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "")))) 5187c87b03e5Sespie (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))] 5188c87b03e5Sespie "! TARGET_SOFT_FLOAT && TARGET_PA_20" 5189c87b03e5Sespie [(set (match_dup 2) (abs:SF (match_dup 1))) 5190c87b03e5Sespie (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))] 5191c87b03e5Sespie "") 5192c87b03e5Sespie 5193c87b03e5Sespie;;- Shift instructions 5194c87b03e5Sespie 5195c87b03e5Sespie;; Optimized special case of shifting. 5196c87b03e5Sespie 5197c87b03e5Sespie(define_insn "" 5198c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5199c87b03e5Sespie (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") 5200c87b03e5Sespie (const_int 24)))] 5201c87b03e5Sespie "" 5202c87b03e5Sespie "ldb%M1 %1,%0" 5203c87b03e5Sespie [(set_attr "type" "load") 5204c87b03e5Sespie (set_attr "length" "4")]) 5205c87b03e5Sespie 5206c87b03e5Sespie(define_insn "" 5207c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5208c87b03e5Sespie (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") 5209c87b03e5Sespie (const_int 16)))] 5210c87b03e5Sespie "" 5211c87b03e5Sespie "ldh%M1 %1,%0" 5212c87b03e5Sespie [(set_attr "type" "load") 5213c87b03e5Sespie (set_attr "length" "4")]) 5214c87b03e5Sespie 5215c87b03e5Sespie(define_insn "" 5216c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5217c87b03e5Sespie (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r") 5218c87b03e5Sespie (match_operand:SI 3 "shadd_operand" "")) 5219c87b03e5Sespie (match_operand:SI 1 "register_operand" "r")))] 5220c87b03e5Sespie "" 5221c87b03e5Sespie "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} " 5222c87b03e5Sespie [(set_attr "type" "binary") 5223c87b03e5Sespie (set_attr "length" "4")]) 5224c87b03e5Sespie 5225c87b03e5Sespie(define_insn "" 5226c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 5227c87b03e5Sespie (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r") 5228c87b03e5Sespie (match_operand:DI 3 "shadd_operand" "")) 5229c87b03e5Sespie (match_operand:DI 1 "register_operand" "r")))] 5230c87b03e5Sespie "TARGET_64BIT" 5231c87b03e5Sespie "shladd,l %2,%O3,%1,%0" 5232c87b03e5Sespie [(set_attr "type" "binary") 5233c87b03e5Sespie (set_attr "length" "4")]) 5234c87b03e5Sespie 5235c87b03e5Sespie(define_expand "ashlsi3" 5236c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 5237c87b03e5Sespie (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "") 5238c87b03e5Sespie (match_operand:SI 2 "arith32_operand" "")))] 5239c87b03e5Sespie "" 5240c87b03e5Sespie " 5241c87b03e5Sespie{ 5242c87b03e5Sespie if (GET_CODE (operands[2]) != CONST_INT) 5243c87b03e5Sespie { 5244c87b03e5Sespie rtx temp = gen_reg_rtx (SImode); 5245c87b03e5Sespie emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2])); 5246c87b03e5Sespie if (GET_CODE (operands[1]) == CONST_INT) 5247c87b03e5Sespie emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp)); 5248c87b03e5Sespie else 5249c87b03e5Sespie emit_insn (gen_zvdep32 (operands[0], operands[1], temp)); 5250c87b03e5Sespie DONE; 5251c87b03e5Sespie } 5252c87b03e5Sespie /* Make sure both inputs are not constants, 5253c87b03e5Sespie there are no patterns for that. */ 5254c87b03e5Sespie operands[1] = force_reg (SImode, operands[1]); 5255c87b03e5Sespie}") 5256c87b03e5Sespie 5257c87b03e5Sespie(define_insn "" 5258c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5259c87b03e5Sespie (ashift:SI (match_operand:SI 1 "register_operand" "r") 5260c87b03e5Sespie (match_operand:SI 2 "const_int_operand" "n")))] 5261c87b03e5Sespie "" 5262c87b03e5Sespie "{zdep|depw,z} %1,%P2,%L2,%0" 5263c87b03e5Sespie [(set_attr "type" "shift") 5264c87b03e5Sespie (set_attr "length" "4")]) 5265c87b03e5Sespie 5266c87b03e5Sespie; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle. 5267c87b03e5Sespie; Doing it like this makes slightly better code since reload can 5268c87b03e5Sespie; replace a register with a known value in range -16..15 with a 5269c87b03e5Sespie; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32, 5270c87b03e5Sespie; but since we have no more CONST_OK... characters, that is not 5271c87b03e5Sespie; possible. 5272c87b03e5Sespie(define_insn "zvdep32" 5273c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 5274c87b03e5Sespie (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L") 5275c87b03e5Sespie (minus:SI (const_int 31) 5276c87b03e5Sespie (match_operand:SI 2 "register_operand" "q,q"))))] 5277c87b03e5Sespie "" 5278c87b03e5Sespie "@ 5279c87b03e5Sespie {zvdep %1,32,%0|depw,z %1,%%sar,32,%0} 5280c87b03e5Sespie {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}" 5281c87b03e5Sespie [(set_attr "type" "shift,shift") 5282c87b03e5Sespie (set_attr "length" "4,4")]) 5283c87b03e5Sespie 5284c87b03e5Sespie(define_insn "zvdep_imm32" 5285c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5286c87b03e5Sespie (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "") 5287c87b03e5Sespie (minus:SI (const_int 31) 5288c87b03e5Sespie (match_operand:SI 2 "register_operand" "q"))))] 5289c87b03e5Sespie "" 5290c87b03e5Sespie "* 5291c87b03e5Sespie{ 5292c87b03e5Sespie int x = INTVAL (operands[1]); 5293c87b03e5Sespie operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1)); 5294c87b03e5Sespie operands[1] = GEN_INT ((x & 0xf) - 0x10); 5295c87b03e5Sespie return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\"; 5296c87b03e5Sespie}" 5297c87b03e5Sespie [(set_attr "type" "shift") 5298c87b03e5Sespie (set_attr "length" "4")]) 5299c87b03e5Sespie 5300c87b03e5Sespie(define_insn "vdepi_ior" 5301c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5302c87b03e5Sespie (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "") 5303c87b03e5Sespie (minus:SI (const_int 31) 5304c87b03e5Sespie (match_operand:SI 2 "register_operand" "q"))) 5305c87b03e5Sespie (match_operand:SI 3 "register_operand" "0")))] 5306c87b03e5Sespie ; accept ...0001...1, can this be generalized? 5307c87b03e5Sespie "exact_log2 (INTVAL (operands[1]) + 1) >= 0" 5308c87b03e5Sespie "* 5309c87b03e5Sespie{ 5310c87b03e5Sespie int x = INTVAL (operands[1]); 5311c87b03e5Sespie operands[2] = GEN_INT (exact_log2 (x + 1)); 5312c87b03e5Sespie return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\"; 5313c87b03e5Sespie}" 5314c87b03e5Sespie [(set_attr "type" "shift") 5315c87b03e5Sespie (set_attr "length" "4")]) 5316c87b03e5Sespie 5317c87b03e5Sespie(define_insn "vdepi_and" 5318c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5319c87b03e5Sespie (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "") 5320c87b03e5Sespie (minus:SI (const_int 31) 5321c87b03e5Sespie (match_operand:SI 2 "register_operand" "q"))) 5322c87b03e5Sespie (match_operand:SI 3 "register_operand" "0")))] 5323c87b03e5Sespie ; this can be generalized...! 5324c87b03e5Sespie "INTVAL (operands[1]) == -2" 5325c87b03e5Sespie "* 5326c87b03e5Sespie{ 5327c87b03e5Sespie int x = INTVAL (operands[1]); 5328c87b03e5Sespie operands[2] = GEN_INT (exact_log2 ((~x) + 1)); 5329c87b03e5Sespie return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\"; 5330c87b03e5Sespie}" 5331c87b03e5Sespie [(set_attr "type" "shift") 5332c87b03e5Sespie (set_attr "length" "4")]) 5333c87b03e5Sespie 5334c87b03e5Sespie(define_expand "ashldi3" 5335c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 5336c87b03e5Sespie (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "") 5337c87b03e5Sespie (match_operand:DI 2 "arith32_operand" "")))] 5338c87b03e5Sespie "TARGET_64BIT" 5339c87b03e5Sespie " 5340c87b03e5Sespie{ 5341c87b03e5Sespie if (GET_CODE (operands[2]) != CONST_INT) 5342c87b03e5Sespie { 5343c87b03e5Sespie rtx temp = gen_reg_rtx (DImode); 5344c87b03e5Sespie emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2])); 5345c87b03e5Sespie if (GET_CODE (operands[1]) == CONST_INT) 5346c87b03e5Sespie emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp)); 5347c87b03e5Sespie else 5348c87b03e5Sespie emit_insn (gen_zvdep64 (operands[0], operands[1], temp)); 5349c87b03e5Sespie DONE; 5350c87b03e5Sespie } 5351c87b03e5Sespie /* Make sure both inputs are not constants, 5352c87b03e5Sespie there are no patterns for that. */ 5353c87b03e5Sespie operands[1] = force_reg (DImode, operands[1]); 5354c87b03e5Sespie}") 5355c87b03e5Sespie 5356c87b03e5Sespie(define_insn "" 5357c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 5358c87b03e5Sespie (ashift:DI (match_operand:DI 1 "register_operand" "r") 5359c87b03e5Sespie (match_operand:DI 2 "const_int_operand" "n")))] 5360c87b03e5Sespie "TARGET_64BIT" 5361c87b03e5Sespie "depd,z %1,%p2,%Q2,%0" 5362c87b03e5Sespie [(set_attr "type" "shift") 5363c87b03e5Sespie (set_attr "length" "4")]) 5364c87b03e5Sespie 5365c87b03e5Sespie; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle. 5366c87b03e5Sespie; Doing it like this makes slightly better code since reload can 5367c87b03e5Sespie; replace a register with a known value in range -16..15 with a 5368c87b03e5Sespie; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64, 5369c87b03e5Sespie; but since we have no more CONST_OK... characters, that is not 5370c87b03e5Sespie; possible. 5371c87b03e5Sespie(define_insn "zvdep64" 5372c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r") 5373c87b03e5Sespie (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L") 5374c87b03e5Sespie (minus:DI (const_int 63) 5375c87b03e5Sespie (match_operand:DI 2 "register_operand" "q,q"))))] 5376c87b03e5Sespie "TARGET_64BIT" 5377c87b03e5Sespie "@ 5378c87b03e5Sespie depd,z %1,%%sar,64,%0 5379c87b03e5Sespie depdi,z %1,%%sar,64,%0" 5380c87b03e5Sespie [(set_attr "type" "shift,shift") 5381c87b03e5Sespie (set_attr "length" "4,4")]) 5382c87b03e5Sespie 5383c87b03e5Sespie(define_insn "zvdep_imm64" 5384c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 5385c87b03e5Sespie (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "") 5386c87b03e5Sespie (minus:DI (const_int 63) 5387c87b03e5Sespie (match_operand:DI 2 "register_operand" "q"))))] 5388c87b03e5Sespie "TARGET_64BIT" 5389c87b03e5Sespie "* 5390c87b03e5Sespie{ 5391c87b03e5Sespie int x = INTVAL (operands[1]); 5392c87b03e5Sespie operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1)); 5393c87b03e5Sespie operands[1] = GEN_INT ((x & 0x1f) - 0x20); 5394c87b03e5Sespie return \"depdi,z %1,%%sar,%2,%0\"; 5395c87b03e5Sespie}" 5396c87b03e5Sespie [(set_attr "type" "shift") 5397c87b03e5Sespie (set_attr "length" "4")]) 5398c87b03e5Sespie 5399c87b03e5Sespie(define_insn "" 5400c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 5401c87b03e5Sespie (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "") 5402c87b03e5Sespie (minus:DI (const_int 63) 5403c87b03e5Sespie (match_operand:DI 2 "register_operand" "q"))) 5404c87b03e5Sespie (match_operand:DI 3 "register_operand" "0")))] 5405c87b03e5Sespie ; accept ...0001...1, can this be generalized? 5406c87b03e5Sespie "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0" 5407c87b03e5Sespie "* 5408c87b03e5Sespie{ 5409c87b03e5Sespie int x = INTVAL (operands[1]); 5410c87b03e5Sespie operands[2] = GEN_INT (exact_log2 (x + 1)); 5411c87b03e5Sespie return \"depdi -1,%%sar,%2,%0\"; 5412c87b03e5Sespie}" 5413c87b03e5Sespie [(set_attr "type" "shift") 5414c87b03e5Sespie (set_attr "length" "4")]) 5415c87b03e5Sespie 5416c87b03e5Sespie(define_insn "" 5417c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 5418c87b03e5Sespie (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "") 5419c87b03e5Sespie (minus:DI (const_int 63) 5420c87b03e5Sespie (match_operand:DI 2 "register_operand" "q"))) 5421c87b03e5Sespie (match_operand:DI 3 "register_operand" "0")))] 5422c87b03e5Sespie ; this can be generalized...! 5423c87b03e5Sespie "TARGET_64BIT && INTVAL (operands[1]) == -2" 5424c87b03e5Sespie "* 5425c87b03e5Sespie{ 5426c87b03e5Sespie int x = INTVAL (operands[1]); 5427c87b03e5Sespie operands[2] = GEN_INT (exact_log2 ((~x) + 1)); 5428c87b03e5Sespie return \"depdi 0,%%sar,%2,%0\"; 5429c87b03e5Sespie}" 5430c87b03e5Sespie [(set_attr "type" "shift") 5431c87b03e5Sespie (set_attr "length" "4")]) 5432c87b03e5Sespie 5433c87b03e5Sespie(define_expand "ashrsi3" 5434c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 5435c87b03e5Sespie (ashiftrt:SI (match_operand:SI 1 "register_operand" "") 5436c87b03e5Sespie (match_operand:SI 2 "arith32_operand" "")))] 5437c87b03e5Sespie "" 5438c87b03e5Sespie " 5439c87b03e5Sespie{ 5440c87b03e5Sespie if (GET_CODE (operands[2]) != CONST_INT) 5441c87b03e5Sespie { 5442c87b03e5Sespie rtx temp = gen_reg_rtx (SImode); 5443c87b03e5Sespie emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2])); 5444c87b03e5Sespie emit_insn (gen_vextrs32 (operands[0], operands[1], temp)); 5445c87b03e5Sespie DONE; 5446c87b03e5Sespie } 5447c87b03e5Sespie}") 5448c87b03e5Sespie 5449c87b03e5Sespie(define_insn "" 5450c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5451c87b03e5Sespie (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") 5452c87b03e5Sespie (match_operand:SI 2 "const_int_operand" "n")))] 5453c87b03e5Sespie "" 5454c87b03e5Sespie "{extrs|extrw,s} %1,%P2,%L2,%0" 5455c87b03e5Sespie [(set_attr "type" "shift") 5456c87b03e5Sespie (set_attr "length" "4")]) 5457c87b03e5Sespie 5458c87b03e5Sespie(define_insn "vextrs32" 5459c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5460c87b03e5Sespie (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") 5461c87b03e5Sespie (minus:SI (const_int 31) 5462c87b03e5Sespie (match_operand:SI 2 "register_operand" "q"))))] 5463c87b03e5Sespie "" 5464c87b03e5Sespie "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}" 5465c87b03e5Sespie [(set_attr "type" "shift") 5466c87b03e5Sespie (set_attr "length" "4")]) 5467c87b03e5Sespie 5468c87b03e5Sespie(define_expand "ashrdi3" 5469c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "") 5470c87b03e5Sespie (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 5471c87b03e5Sespie (match_operand:DI 2 "arith32_operand" "")))] 5472c87b03e5Sespie "TARGET_64BIT" 5473c87b03e5Sespie " 5474c87b03e5Sespie{ 5475c87b03e5Sespie if (GET_CODE (operands[2]) != CONST_INT) 5476c87b03e5Sespie { 5477c87b03e5Sespie rtx temp = gen_reg_rtx (DImode); 5478c87b03e5Sespie emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2])); 5479c87b03e5Sespie emit_insn (gen_vextrs64 (operands[0], operands[1], temp)); 5480c87b03e5Sespie DONE; 5481c87b03e5Sespie } 5482c87b03e5Sespie}") 5483c87b03e5Sespie 5484c87b03e5Sespie(define_insn "" 5485c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 5486c87b03e5Sespie (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") 5487c87b03e5Sespie (match_operand:DI 2 "const_int_operand" "n")))] 5488c87b03e5Sespie "TARGET_64BIT" 5489c87b03e5Sespie "extrd,s %1,%p2,%Q2,%0" 5490c87b03e5Sespie [(set_attr "type" "shift") 5491c87b03e5Sespie (set_attr "length" "4")]) 5492c87b03e5Sespie 5493c87b03e5Sespie(define_insn "vextrs64" 5494c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 5495c87b03e5Sespie (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") 5496c87b03e5Sespie (minus:DI (const_int 63) 5497c87b03e5Sespie (match_operand:DI 2 "register_operand" "q"))))] 5498c87b03e5Sespie "TARGET_64BIT" 5499c87b03e5Sespie "extrd,s %1,%%sar,64,%0" 5500c87b03e5Sespie [(set_attr "type" "shift") 5501c87b03e5Sespie (set_attr "length" "4")]) 5502c87b03e5Sespie 5503c87b03e5Sespie(define_insn "lshrsi3" 5504c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 5505c87b03e5Sespie (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r") 5506c87b03e5Sespie (match_operand:SI 2 "arith32_operand" "q,n")))] 5507c87b03e5Sespie "" 5508c87b03e5Sespie "@ 5509c87b03e5Sespie {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0} 5510c87b03e5Sespie {extru|extrw,u} %1,%P2,%L2,%0" 5511c87b03e5Sespie [(set_attr "type" "shift") 5512c87b03e5Sespie (set_attr "length" "4")]) 5513c87b03e5Sespie 5514c87b03e5Sespie(define_insn "lshrdi3" 5515c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r,r") 5516c87b03e5Sespie (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r") 5517c87b03e5Sespie (match_operand:DI 2 "arith32_operand" "q,n")))] 5518c87b03e5Sespie "TARGET_64BIT" 5519c87b03e5Sespie "@ 5520c87b03e5Sespie shrpd %%r0,%1,%%sar,%0 5521c87b03e5Sespie extrd,u %1,%p2,%Q2,%0" 5522c87b03e5Sespie [(set_attr "type" "shift") 5523c87b03e5Sespie (set_attr "length" "4")]) 5524c87b03e5Sespie 5525c87b03e5Sespie(define_insn "rotrsi3" 5526c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r,r") 5527c87b03e5Sespie (rotatert:SI (match_operand:SI 1 "register_operand" "r,r") 5528c87b03e5Sespie (match_operand:SI 2 "arith32_operand" "q,n")))] 5529c87b03e5Sespie "" 5530c87b03e5Sespie "* 5531c87b03e5Sespie{ 5532c87b03e5Sespie if (GET_CODE (operands[2]) == CONST_INT) 5533c87b03e5Sespie { 5534c87b03e5Sespie operands[2] = GEN_INT (INTVAL (operands[2]) & 31); 5535c87b03e5Sespie return \"{shd|shrpw} %1,%1,%2,%0\"; 5536c87b03e5Sespie } 5537c87b03e5Sespie else 5538c87b03e5Sespie return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\"; 5539c87b03e5Sespie}" 5540c87b03e5Sespie [(set_attr "type" "shift") 5541c87b03e5Sespie (set_attr "length" "4")]) 5542c87b03e5Sespie 5543c87b03e5Sespie(define_expand "rotlsi3" 5544c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "") 5545c87b03e5Sespie (rotate:SI (match_operand:SI 1 "register_operand" "") 5546c87b03e5Sespie (match_operand:SI 2 "arith32_operand" "")))] 5547c87b03e5Sespie "" 5548c87b03e5Sespie " 5549c87b03e5Sespie{ 5550c87b03e5Sespie if (GET_CODE (operands[2]) != CONST_INT) 5551c87b03e5Sespie { 5552c87b03e5Sespie rtx temp = gen_reg_rtx (SImode); 5553c87b03e5Sespie emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2])); 5554c87b03e5Sespie emit_insn (gen_rotrsi3 (operands[0], operands[1], temp)); 5555c87b03e5Sespie DONE; 5556c87b03e5Sespie } 5557c87b03e5Sespie /* Else expand normally. */ 5558c87b03e5Sespie}") 5559c87b03e5Sespie 5560c87b03e5Sespie(define_insn "" 5561c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5562c87b03e5Sespie (rotate:SI (match_operand:SI 1 "register_operand" "r") 5563c87b03e5Sespie (match_operand:SI 2 "const_int_operand" "n")))] 5564c87b03e5Sespie "" 5565c87b03e5Sespie "* 5566c87b03e5Sespie{ 5567c87b03e5Sespie operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31); 5568c87b03e5Sespie return \"{shd|shrpw} %1,%1,%2,%0\"; 5569c87b03e5Sespie}" 5570c87b03e5Sespie [(set_attr "type" "shift") 5571c87b03e5Sespie (set_attr "length" "4")]) 5572c87b03e5Sespie 5573c87b03e5Sespie(define_insn "" 5574c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5575c87b03e5Sespie (match_operator:SI 5 "plus_xor_ior_operator" 5576c87b03e5Sespie [(ashift:SI (match_operand:SI 1 "register_operand" "r") 5577c87b03e5Sespie (match_operand:SI 3 "const_int_operand" "n")) 5578c87b03e5Sespie (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 5579c87b03e5Sespie (match_operand:SI 4 "const_int_operand" "n"))]))] 5580c87b03e5Sespie "INTVAL (operands[3]) + INTVAL (operands[4]) == 32" 5581c87b03e5Sespie "{shd|shrpw} %1,%2,%4,%0" 5582c87b03e5Sespie [(set_attr "type" "shift") 5583c87b03e5Sespie (set_attr "length" "4")]) 5584c87b03e5Sespie 5585c87b03e5Sespie(define_insn "" 5586c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5587c87b03e5Sespie (match_operator:SI 5 "plus_xor_ior_operator" 5588c87b03e5Sespie [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 5589c87b03e5Sespie (match_operand:SI 4 "const_int_operand" "n")) 5590c87b03e5Sespie (ashift:SI (match_operand:SI 1 "register_operand" "r") 5591c87b03e5Sespie (match_operand:SI 3 "const_int_operand" "n"))]))] 5592c87b03e5Sespie "INTVAL (operands[3]) + INTVAL (operands[4]) == 32" 5593c87b03e5Sespie "{shd|shrpw} %1,%2,%4,%0" 5594c87b03e5Sespie [(set_attr "type" "shift") 5595c87b03e5Sespie (set_attr "length" "4")]) 5596c87b03e5Sespie 5597c87b03e5Sespie(define_insn "" 5598c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 5599c87b03e5Sespie (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") 5600c87b03e5Sespie (match_operand:SI 2 "const_int_operand" "")) 5601c87b03e5Sespie (match_operand:SI 3 "const_int_operand" "")))] 5602c87b03e5Sespie "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0" 5603c87b03e5Sespie "* 5604c87b03e5Sespie{ 5605c87b03e5Sespie int cnt = INTVAL (operands[2]) & 31; 5606c87b03e5Sespie operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt))); 5607c87b03e5Sespie operands[2] = GEN_INT (31 - cnt); 5608c87b03e5Sespie return \"{zdep|depw,z} %1,%2,%3,%0\"; 5609c87b03e5Sespie}" 5610c87b03e5Sespie [(set_attr "type" "shift") 5611c87b03e5Sespie (set_attr "length" "4")]) 5612c87b03e5Sespie 5613c87b03e5Sespie;; Unconditional and other jump instructions. 5614c87b03e5Sespie 5615c87b03e5Sespie;; This can only be used in a leaf function, so we do 5616c87b03e5Sespie;; not need to use the PIC register when generating PIC code. 5617c87b03e5Sespie(define_insn "return" 5618c87b03e5Sespie [(return) 5619c87b03e5Sespie (use (reg:SI 2)) 5620c87b03e5Sespie (const_int 0)] 5621c87b03e5Sespie "hppa_can_use_return_insn_p ()" 5622c87b03e5Sespie "* 5623c87b03e5Sespie{ 5624c87b03e5Sespie if (TARGET_PA_20) 5625c87b03e5Sespie return \"bve%* (%%r2)\"; 5626c87b03e5Sespie return \"bv%* %%r0(%%r2)\"; 5627c87b03e5Sespie}" 5628c87b03e5Sespie [(set_attr "type" "branch") 5629c87b03e5Sespie (set_attr "length" "4")]) 5630c87b03e5Sespie 5631c87b03e5Sespie;; Emit a different pattern for functions which have non-trivial 5632c87b03e5Sespie;; epilogues so as not to confuse jump and reorg. 5633c87b03e5Sespie(define_insn "return_internal" 5634c87b03e5Sespie [(return) 5635c87b03e5Sespie (use (reg:SI 2)) 5636c87b03e5Sespie (const_int 1)] 5637c87b03e5Sespie "" 5638c87b03e5Sespie "* 5639c87b03e5Sespie{ 5640c87b03e5Sespie if (TARGET_PA_20) 5641c87b03e5Sespie return \"bve%* (%%r2)\"; 5642c87b03e5Sespie return \"bv%* %%r0(%%r2)\"; 5643c87b03e5Sespie}" 5644c87b03e5Sespie [(set_attr "type" "branch") 5645c87b03e5Sespie (set_attr "length" "4")]) 5646c87b03e5Sespie 5647c87b03e5Sespie;; This is used for eh returns which bypass the return stub. 5648c87b03e5Sespie(define_insn "return_external_pic" 5649c87b03e5Sespie [(return) 5650c87b03e5Sespie (clobber (reg:SI 1)) 5651c87b03e5Sespie (use (reg:SI 2))] 5652c87b03e5Sespie "!TARGET_NO_SPACE_REGS 5653c87b03e5Sespie && !TARGET_PA_20 5654c87b03e5Sespie && flag_pic && current_function_calls_eh_return" 5655c87b03e5Sespie "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)" 5656c87b03e5Sespie [(set_attr "type" "branch") 5657c87b03e5Sespie (set_attr "length" "12")]) 5658c87b03e5Sespie 5659c87b03e5Sespie(define_expand "prologue" 5660c87b03e5Sespie [(const_int 0)] 5661c87b03e5Sespie "" 5662c87b03e5Sespie "hppa_expand_prologue ();DONE;") 5663c87b03e5Sespie 5664c87b03e5Sespie(define_expand "sibcall_epilogue" 5665c87b03e5Sespie [(return)] 5666c87b03e5Sespie "" 5667c87b03e5Sespie " 5668c87b03e5Sespie{ 5669c87b03e5Sespie hppa_expand_epilogue (); 5670c87b03e5Sespie DONE; 5671c87b03e5Sespie}") 5672c87b03e5Sespie 5673c87b03e5Sespie(define_expand "epilogue" 5674c87b03e5Sespie [(return)] 5675c87b03e5Sespie "" 5676c87b03e5Sespie " 5677c87b03e5Sespie{ 5678c87b03e5Sespie /* Try to use the trivial return first. Else use the full 5679c87b03e5Sespie epilogue. */ 5680c87b03e5Sespie if (hppa_can_use_return_insn_p ()) 5681c87b03e5Sespie emit_jump_insn (gen_return ()); 5682c87b03e5Sespie else 5683c87b03e5Sespie { 5684c87b03e5Sespie rtx x; 5685c87b03e5Sespie 5686c87b03e5Sespie hppa_expand_epilogue (); 5687c87b03e5Sespie 5688c87b03e5Sespie /* EH returns bypass the normal return stub. Thus, we must do an 5689c87b03e5Sespie interspace branch to return from functions that call eh_return. 5690c87b03e5Sespie This is only a problem for returns from shared code on ports 5691c87b03e5Sespie using space registers. */ 5692c87b03e5Sespie if (!TARGET_NO_SPACE_REGS 5693c87b03e5Sespie && !TARGET_PA_20 5694c87b03e5Sespie && flag_pic && current_function_calls_eh_return) 5695c87b03e5Sespie x = gen_return_external_pic (); 5696c87b03e5Sespie else 5697c87b03e5Sespie x = gen_return_internal (); 5698c87b03e5Sespie 5699c87b03e5Sespie emit_jump_insn (x); 5700c87b03e5Sespie } 5701c87b03e5Sespie DONE; 5702c87b03e5Sespie}") 5703c87b03e5Sespie 5704c87b03e5Sespie;; Special because we use the value placed in %r2 by the bl instruction 5705c87b03e5Sespie;; from within its delay slot to set the value for the 2nd parameter to 5706c87b03e5Sespie;; the call. 5707c87b03e5Sespie(define_insn "call_profiler" 5708c87b03e5Sespie [(call (mem:SI (match_operand 0 "call_operand_address" "")) 5709c87b03e5Sespie (match_operand 1 "" "")) 5710c87b03e5Sespie (use (match_operand 2 "" "")) 5711c87b03e5Sespie (use (reg:SI 25)) 5712c87b03e5Sespie (use (reg:SI 26)) 5713c87b03e5Sespie (clobber (reg:SI 2))] 5714c87b03e5Sespie "" 5715c87b03e5Sespie "* 5716c87b03e5Sespie{ 5717c87b03e5Sespie rtx xoperands[3]; 5718c87b03e5Sespie 5719c87b03e5Sespie output_arg_descriptor (insn); 5720c87b03e5Sespie 5721c87b03e5Sespie xoperands[0] = operands[0]; 5722c87b03e5Sespie xoperands[1] = operands[2]; 5723c87b03e5Sespie xoperands[2] = gen_label_rtx (); 5724c87b03e5Sespie output_asm_insn (\"{bl|b,l} %0,%%r2\;ldo %1-%2(%%r2),%%r25\", xoperands); 5725c87b03e5Sespie 5726c87b03e5Sespie ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", 5727c87b03e5Sespie CODE_LABEL_NUMBER (xoperands[2])); 5728c87b03e5Sespie return \"\"; 5729c87b03e5Sespie}" 5730c87b03e5Sespie [(set_attr "type" "multi") 5731c87b03e5Sespie (set_attr "length" "8")]) 5732c87b03e5Sespie 5733c87b03e5Sespie(define_insn "blockage" 5734c87b03e5Sespie [(unspec_volatile [(const_int 2)] 0)] 5735c87b03e5Sespie "" 5736c87b03e5Sespie "" 5737c87b03e5Sespie [(set_attr "length" "0")]) 5738c87b03e5Sespie 5739c87b03e5Sespie(define_insn "jump" 5740c87b03e5Sespie [(set (pc) (label_ref (match_operand 0 "" "")))] 5741c87b03e5Sespie "" 5742c87b03e5Sespie "* 5743c87b03e5Sespie{ 5744c87b03e5Sespie if (GET_MODE (insn) == SImode) 5745c87b03e5Sespie return \"b %l0%#\"; 5746c87b03e5Sespie 5747c87b03e5Sespie /* An unconditional branch which can reach its target. */ 5748c87b03e5Sespie if (get_attr_length (insn) != 24 5749c87b03e5Sespie && get_attr_length (insn) != 16) 5750c87b03e5Sespie return \"b%* %l0\"; 5751c87b03e5Sespie 5752c87b03e5Sespie return output_lbranch (operands[0], insn); 5753c87b03e5Sespie}" 5754c87b03e5Sespie [(set_attr "type" "uncond_branch") 5755c87b03e5Sespie (set_attr "pa_combine_type" "uncond_branch") 5756c87b03e5Sespie (set (attr "length") 5757c87b03e5Sespie (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1)) 5758c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 0) 5759c87b03e5Sespie (plus (pc) (const_int 8)))) 5760c87b03e5Sespie (const_int 8184)) 5761c87b03e5Sespie (const_int 4) 5762c87b03e5Sespie (const_int 8)) 5763c87b03e5Sespie (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8)))) 5764c87b03e5Sespie (const_int 262100)) 5765c87b03e5Sespie (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) 5766c87b03e5Sespie (const_int 16) 5767c87b03e5Sespie (const_int 24))] 5768c87b03e5Sespie (const_int 4)))]) 5769c87b03e5Sespie 5770c87b03e5Sespie;; Subroutines of "casesi". 5771c87b03e5Sespie;; operand 0 is index 5772c87b03e5Sespie;; operand 1 is the minimum bound 5773c87b03e5Sespie;; operand 2 is the maximum bound - minimum bound + 1 5774c87b03e5Sespie;; operand 3 is CODE_LABEL for the table; 5775c87b03e5Sespie;; operand 4 is the CODE_LABEL to go to if index out of range. 5776c87b03e5Sespie 5777c87b03e5Sespie(define_expand "casesi" 5778c87b03e5Sespie [(match_operand:SI 0 "general_operand" "") 5779c87b03e5Sespie (match_operand:SI 1 "const_int_operand" "") 5780c87b03e5Sespie (match_operand:SI 2 "const_int_operand" "") 5781c87b03e5Sespie (match_operand 3 "" "") 5782c87b03e5Sespie (match_operand 4 "" "")] 5783c87b03e5Sespie "" 5784c87b03e5Sespie " 5785c87b03e5Sespie{ 5786c87b03e5Sespie if (GET_CODE (operands[0]) != REG) 5787c87b03e5Sespie operands[0] = force_reg (SImode, operands[0]); 5788c87b03e5Sespie 5789c87b03e5Sespie if (operands[1] != const0_rtx) 5790c87b03e5Sespie { 5791c87b03e5Sespie rtx reg = gen_reg_rtx (SImode); 5792c87b03e5Sespie 5793c87b03e5Sespie operands[1] = GEN_INT (-INTVAL (operands[1])); 5794c87b03e5Sespie if (!INT_14_BITS (operands[1])) 5795c87b03e5Sespie operands[1] = force_reg (SImode, operands[1]); 5796c87b03e5Sespie emit_insn (gen_addsi3 (reg, operands[0], operands[1])); 5797c87b03e5Sespie 5798c87b03e5Sespie operands[0] = reg; 5799c87b03e5Sespie } 5800c87b03e5Sespie 5801c87b03e5Sespie /* In 64bit mode we must make sure to wipe the upper bits of the register 5802c87b03e5Sespie just in case the addition overflowed or we had random bits in the 5803c87b03e5Sespie high part of the register. */ 5804c87b03e5Sespie if (TARGET_64BIT) 5805c87b03e5Sespie { 5806c87b03e5Sespie rtx reg = gen_reg_rtx (DImode); 5807c87b03e5Sespie emit_insn (gen_extendsidi2 (reg, operands[0])); 5808c87b03e5Sespie operands[0] = gen_rtx_SUBREG (SImode, reg, 4); 5809c87b03e5Sespie } 5810c87b03e5Sespie 5811c87b03e5Sespie if (!INT_5_BITS (operands[2])) 5812c87b03e5Sespie operands[2] = force_reg (SImode, operands[2]); 5813c87b03e5Sespie 5814c87b03e5Sespie emit_insn (gen_cmpsi (operands[0], operands[2])); 5815c87b03e5Sespie emit_jump_insn (gen_bgtu (operands[4])); 5816c87b03e5Sespie if (TARGET_BIG_SWITCH) 5817c87b03e5Sespie { 5818c87b03e5Sespie rtx temp = gen_reg_rtx (SImode); 5819c87b03e5Sespie emit_move_insn (temp, gen_rtx_PLUS (SImode, operands[0], operands[0])); 5820c87b03e5Sespie operands[0] = temp; 5821c87b03e5Sespie } 5822c87b03e5Sespie emit_jump_insn (gen_casesi0 (operands[0], operands[3])); 5823c87b03e5Sespie DONE; 5824c87b03e5Sespie}") 5825c87b03e5Sespie 5826c87b03e5Sespie(define_insn "casesi0" 5827c87b03e5Sespie [(set (pc) (plus:SI 5828c87b03e5Sespie (mem:SI (plus:SI (pc) 5829c87b03e5Sespie (match_operand:SI 0 "register_operand" "r"))) 5830c87b03e5Sespie (label_ref (match_operand 1 "" ""))))] 5831c87b03e5Sespie "" 5832c87b03e5Sespie "blr %0,%%r0\;nop" 5833c87b03e5Sespie [(set_attr "type" "multi") 5834c87b03e5Sespie (set_attr "length" "8")]) 5835c87b03e5Sespie 5836c87b03e5Sespie;; Need nops for the calls because execution is supposed to continue 5837c87b03e5Sespie;; past; we don't want to nullify an instruction that we need. 5838c87b03e5Sespie;;- jump to subroutine 5839c87b03e5Sespie 5840c87b03e5Sespie(define_expand "call" 5841c87b03e5Sespie [(parallel [(call (match_operand:SI 0 "" "") 5842c87b03e5Sespie (match_operand 1 "" "")) 5843c87b03e5Sespie (clobber (reg:SI 2))])] 5844c87b03e5Sespie "" 5845c87b03e5Sespie " 5846c87b03e5Sespie{ 5847c87b03e5Sespie rtx op, call_insn; 5848c87b03e5Sespie rtx nb = operands[1]; 5849c87b03e5Sespie 5850c87b03e5Sespie if (TARGET_PORTABLE_RUNTIME) 5851c87b03e5Sespie op = force_reg (SImode, XEXP (operands[0], 0)); 5852c87b03e5Sespie else 5853c87b03e5Sespie op = XEXP (operands[0], 0); 5854c87b03e5Sespie 5855c87b03e5Sespie if (TARGET_64BIT) 5856c87b03e5Sespie { 5857c87b03e5Sespie if (!virtuals_instantiated) 5858c87b03e5Sespie emit_move_insn (arg_pointer_rtx, 5859c87b03e5Sespie gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, 5860c87b03e5Sespie GEN_INT (64))); 5861c87b03e5Sespie else 5862c87b03e5Sespie { 5863c87b03e5Sespie /* The loop pass can generate new libcalls after the virtual 5864c87b03e5Sespie registers are instantiated when fpregs are disabled because 5865c87b03e5Sespie the only method that we have for doing DImode multiplication 5866c87b03e5Sespie is with a libcall. This could be trouble if we haven't 5867c87b03e5Sespie allocated enough space for the outgoing arguments. */ 5868c87b03e5Sespie if (INTVAL (nb) > current_function_outgoing_args_size) 5869c87b03e5Sespie abort (); 5870c87b03e5Sespie 5871c87b03e5Sespie emit_move_insn (arg_pointer_rtx, 5872c87b03e5Sespie gen_rtx_PLUS (word_mode, stack_pointer_rtx, 5873c87b03e5Sespie GEN_INT (STACK_POINTER_OFFSET + 64))); 5874c87b03e5Sespie } 5875c87b03e5Sespie } 5876c87b03e5Sespie 5877c87b03e5Sespie /* Use two different patterns for calls to explicitly named functions 5878c87b03e5Sespie and calls through function pointers. This is necessary as these two 5879c87b03e5Sespie types of calls use different calling conventions, and CSE might try 5880c87b03e5Sespie to change the named call into an indirect call in some cases (using 5881c87b03e5Sespie two patterns keeps CSE from performing this optimization). 5882c87b03e5Sespie 5883c87b03e5Sespie We now use even more call patterns as there was a subtle bug in 5884c87b03e5Sespie attempting to restore the pic register after a call using a simple 5885c87b03e5Sespie move insn. During reload, a instruction involving a pseudo register 5886c87b03e5Sespie with no explicit dependence on the PIC register can be converted 5887c87b03e5Sespie to an equivalent load from memory using the PIC register. If we 5888c87b03e5Sespie emit a simple move to restore the PIC register in the initial rtl 5889c87b03e5Sespie generation, then it can potentially be repositioned during scheduling. 5890c87b03e5Sespie and an instruction that eventually uses the PIC register may end up 5891c87b03e5Sespie between the call and the PIC register restore. 5892c87b03e5Sespie 5893c87b03e5Sespie This only worked because there is a post call group of instructions 5894c87b03e5Sespie that are scheduled with the call. These instructions are included 5895c87b03e5Sespie in the same basic block as the call. However, calls can throw in 5896c87b03e5Sespie C++ code and a basic block has to terminate at the call if the call 5897c87b03e5Sespie can throw. This results in the PIC register restore being scheduled 5898c87b03e5Sespie independently from the call. So, we now hide the save and restore 5899c87b03e5Sespie of the PIC register in the call pattern until after reload. Then, 5900c87b03e5Sespie we split the moves out. A small side benefit is that we now don't 5901c87b03e5Sespie need to have a use of the PIC register in the return pattern and 5902c87b03e5Sespie the final save/restore operation is not needed. 5903c87b03e5Sespie 5904c87b03e5Sespie I elected to just clobber %r4 in the PIC patterns and use it instead 5905c87b03e5Sespie of trying to force hppa_pic_save_rtx () to a callee saved register. 5906c87b03e5Sespie This might have required a new register class and constraint. It 5907c87b03e5Sespie was also simpler to just handle the restore from a register than a 5908c87b03e5Sespie generic pseudo. */ 5909c87b03e5Sespie if (TARGET_64BIT) 5910c87b03e5Sespie { 5911c87b03e5Sespie if (GET_CODE (op) == SYMBOL_REF) 5912c87b03e5Sespie call_insn = emit_call_insn (gen_call_symref_64bit (op, nb)); 5913c87b03e5Sespie else 5914c87b03e5Sespie { 5915c87b03e5Sespie op = force_reg (word_mode, op); 5916c87b03e5Sespie call_insn = emit_call_insn (gen_call_reg_64bit (op, nb)); 5917c87b03e5Sespie } 5918c87b03e5Sespie } 5919c87b03e5Sespie else 5920c87b03e5Sespie { 5921c87b03e5Sespie if (GET_CODE (op) == SYMBOL_REF) 5922c87b03e5Sespie { 5923c87b03e5Sespie if (flag_pic) 5924c87b03e5Sespie call_insn = emit_call_insn (gen_call_symref_pic (op, nb)); 5925c87b03e5Sespie else 5926c87b03e5Sespie call_insn = emit_call_insn (gen_call_symref (op, nb)); 5927c87b03e5Sespie } 5928c87b03e5Sespie else 5929c87b03e5Sespie { 5930c87b03e5Sespie rtx tmpreg = gen_rtx_REG (word_mode, 22); 5931c87b03e5Sespie 5932c87b03e5Sespie emit_move_insn (tmpreg, force_reg (word_mode, op)); 5933c87b03e5Sespie if (flag_pic) 5934c87b03e5Sespie call_insn = emit_call_insn (gen_call_reg_pic (nb)); 5935c87b03e5Sespie else 5936c87b03e5Sespie call_insn = emit_call_insn (gen_call_reg (nb)); 5937c87b03e5Sespie } 5938c87b03e5Sespie } 5939c87b03e5Sespie 5940c87b03e5Sespie DONE; 5941c87b03e5Sespie}") 5942c87b03e5Sespie 5943c87b03e5Sespie;; We use function calls to set the attribute length of calls and millicode 5944c87b03e5Sespie;; calls. This is necessary because of the large variety of call sequences. 5945c87b03e5Sespie;; Implementing the calculation in rtl is difficult as well as ugly. As 5946c87b03e5Sespie;; we need the same calculation in several places, maintenance becomes a 5947c87b03e5Sespie;; nightmare. 5948c87b03e5Sespie;; 5949c87b03e5Sespie;; However, this has a subtle impact on branch shortening. When the 5950c87b03e5Sespie;; expression used to set the length attribute of an instruction depends 5951c87b03e5Sespie;; on a relative address (e.g., pc or a branch address), genattrtab 5952c87b03e5Sespie;; notes that the insn's length is variable, and attempts to determine a 5953c87b03e5Sespie;; worst-case default length and code to compute an insn's current length. 5954c87b03e5Sespie 5955c87b03e5Sespie;; The use of a function call hides the variable dependence of our calls 5956c87b03e5Sespie;; and millicode calls. The result is genattrtab doesn't treat the operation 5957c87b03e5Sespie;; as variable and it only generates code for the default case using our 5958c87b03e5Sespie;; function call. Because of this, calls and millicode calls have a fixed 5959c87b03e5Sespie;; length in the branch shortening pass, and some branches will use a longer 5960c87b03e5Sespie;; code sequence than necessary. However, the length of any given call 5961c87b03e5Sespie;; will still reflect its final code location and it may be shorter than 5962c87b03e5Sespie;; the initial length estimate. 5963c87b03e5Sespie 5964c87b03e5Sespie;; It's possible to trick genattrtab by adding an expression involving `pc' 5965c87b03e5Sespie;; in the set. However, when genattrtab hits a function call in its attempt 5966c87b03e5Sespie;; to compute the default length, it marks the result as unknown and sets 5967c87b03e5Sespie;; the default result to MAX_INT ;-( One possible fix that would allow 5968c87b03e5Sespie;; calls to participate in branch shortening would be to make the call to ;; insn_default_length a target option. Then, we could massage unknown ;; results. Another fix might be to change genattrtab so that it just does ;; the call in the variable case as it already does for the fixed case. 5969c87b03e5Sespie 5970c87b03e5Sespie(define_insn "call_symref" 5971c87b03e5Sespie [(call (mem:SI (match_operand 0 "call_operand_address" "")) 5972c87b03e5Sespie (match_operand 1 "" "i")) 5973c87b03e5Sespie (clobber (reg:SI 1)) 5974c87b03e5Sespie (clobber (reg:SI 2)) 5975c87b03e5Sespie (use (const_int 0))] 5976c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" 5977c87b03e5Sespie "* 5978c87b03e5Sespie{ 5979c87b03e5Sespie output_arg_descriptor (insn); 5980c87b03e5Sespie return output_call (insn, operands[0], 0); 5981c87b03e5Sespie}" 5982c87b03e5Sespie [(set_attr "type" "call") 5983c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) 5984c87b03e5Sespie 5985c87b03e5Sespie(define_insn "call_symref_pic" 5986c87b03e5Sespie [(call (mem:SI (match_operand 0 "call_operand_address" "")) 5987c87b03e5Sespie (match_operand 1 "" "i")) 5988c87b03e5Sespie (clobber (reg:SI 1)) 5989c87b03e5Sespie (clobber (reg:SI 2)) 5990c87b03e5Sespie (clobber (reg:SI 4)) 5991c87b03e5Sespie (use (reg:SI 19)) 5992c87b03e5Sespie (use (const_int 0))] 5993c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" 5994c87b03e5Sespie "* 5995c87b03e5Sespie{ 5996c87b03e5Sespie output_arg_descriptor (insn); 5997c87b03e5Sespie return output_call (insn, operands[0], 0); 5998c87b03e5Sespie}" 5999c87b03e5Sespie [(set_attr "type" "call") 6000c87b03e5Sespie (set (attr "length") 6001c87b03e5Sespie (plus (symbol_ref "attr_length_call (insn, 0)") 6002c87b03e5Sespie (symbol_ref "attr_length_save_restore_dltp (insn)")))]) 6003c87b03e5Sespie 6004c87b03e5Sespie 6005c87b03e5Sespie;; Split out the PIC register save and restore after reload. This is 6006c87b03e5Sespie;; done only if the function returns. As the split is done after reload, 6007c87b03e5Sespie;; there are some situations in which we unnecessarily save and restore 6008c87b03e5Sespie;; %r4. This happens when there is a single call and the PIC register 6009c87b03e5Sespie;; is "dead" after the call. This isn't easy to fix as the usage of 6010c87b03e5Sespie;; the PIC register isn't completely determined until the reload pass. 6011c87b03e5Sespie(define_split 6012c87b03e5Sespie [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" "")) 6013c87b03e5Sespie (match_operand 1 "" "")) 6014c87b03e5Sespie (clobber (reg:SI 1)) 6015c87b03e5Sespie (clobber (reg:SI 2)) 6016c87b03e5Sespie (clobber (reg:SI 4)) 6017c87b03e5Sespie (use (reg:SI 19)) 6018c87b03e5Sespie (use (const_int 0))])] 6019c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT 6020c87b03e5Sespie && reload_completed 6021c87b03e5Sespie && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" 6022c87b03e5Sespie [(set (reg:SI 4) (reg:SI 19)) 6023c87b03e5Sespie (parallel [(call (mem:SI (match_dup 0)) 6024c87b03e5Sespie (match_dup 1)) 6025c87b03e5Sespie (clobber (reg:SI 1)) 6026c87b03e5Sespie (clobber (reg:SI 2)) 6027c87b03e5Sespie (use (reg:SI 19)) 6028c87b03e5Sespie (use (const_int 0))]) 6029c87b03e5Sespie (set (reg:SI 19) (reg:SI 4))] 6030c87b03e5Sespie "") 6031c87b03e5Sespie 6032c87b03e5Sespie;; Remove the clobber of register 4 when optimizing. This has to be 6033c87b03e5Sespie;; done with a peephole optimization rather than a split because the 6034c87b03e5Sespie;; split sequence for a call must be longer than one instruction. 6035c87b03e5Sespie(define_peephole2 6036c87b03e5Sespie [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" "")) 6037c87b03e5Sespie (match_operand 1 "" "")) 6038c87b03e5Sespie (clobber (reg:SI 1)) 6039c87b03e5Sespie (clobber (reg:SI 2)) 6040c87b03e5Sespie (clobber (reg:SI 4)) 6041c87b03e5Sespie (use (reg:SI 19)) 6042c87b03e5Sespie (use (const_int 0))])] 6043c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed" 6044c87b03e5Sespie [(parallel [(call (mem:SI (match_dup 0)) 6045c87b03e5Sespie (match_dup 1)) 6046c87b03e5Sespie (clobber (reg:SI 1)) 6047c87b03e5Sespie (clobber (reg:SI 2)) 6048c87b03e5Sespie (use (reg:SI 19)) 6049c87b03e5Sespie (use (const_int 0))])] 6050c87b03e5Sespie "") 6051c87b03e5Sespie 6052c87b03e5Sespie(define_insn "*call_symref_pic_post_reload" 6053c87b03e5Sespie [(call (mem:SI (match_operand 0 "call_operand_address" "")) 6054c87b03e5Sespie (match_operand 1 "" "i")) 6055c87b03e5Sespie (clobber (reg:SI 1)) 6056c87b03e5Sespie (clobber (reg:SI 2)) 6057c87b03e5Sespie (use (reg:SI 19)) 6058c87b03e5Sespie (use (const_int 0))] 6059c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" 6060c87b03e5Sespie "* 6061c87b03e5Sespie{ 6062c87b03e5Sespie output_arg_descriptor (insn); 6063c87b03e5Sespie return output_call (insn, operands[0], 0); 6064c87b03e5Sespie}" 6065c87b03e5Sespie [(set_attr "type" "call") 6066c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) 6067c87b03e5Sespie 6068c87b03e5Sespie;; This pattern is split if it is necessary to save and restore the 6069c87b03e5Sespie;; PIC register. 6070c87b03e5Sespie(define_insn "call_symref_64bit" 6071c87b03e5Sespie [(call (mem:SI (match_operand 0 "call_operand_address" "")) 6072c87b03e5Sespie (match_operand 1 "" "i")) 6073c87b03e5Sespie (clobber (reg:DI 1)) 6074c87b03e5Sespie (clobber (reg:DI 2)) 6075c87b03e5Sespie (clobber (reg:DI 4)) 6076c87b03e5Sespie (use (reg:DI 27)) 6077c87b03e5Sespie (use (reg:DI 29)) 6078c87b03e5Sespie (use (const_int 0))] 6079c87b03e5Sespie "TARGET_64BIT" 6080c87b03e5Sespie "* 6081c87b03e5Sespie{ 6082c87b03e5Sespie output_arg_descriptor (insn); 6083c87b03e5Sespie return output_call (insn, operands[0], 0); 6084c87b03e5Sespie}" 6085c87b03e5Sespie [(set_attr "type" "call") 6086c87b03e5Sespie (set (attr "length") 6087c87b03e5Sespie (plus (symbol_ref "attr_length_call (insn, 0)") 6088c87b03e5Sespie (symbol_ref "attr_length_save_restore_dltp (insn)")))]) 6089c87b03e5Sespie 6090c87b03e5Sespie;; Split out the PIC register save and restore after reload. This is 6091c87b03e5Sespie;; done only if the function returns. As the split is done after reload, 6092c87b03e5Sespie;; there are some situations in which we unnecessarily save and restore 6093c87b03e5Sespie;; %r4. This happens when there is a single call and the PIC register 6094c87b03e5Sespie;; is "dead" after the call. This isn't easy to fix as the usage of 6095c87b03e5Sespie;; the PIC register isn't completely determined until the reload pass. 6096c87b03e5Sespie(define_split 6097c87b03e5Sespie [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" "")) 6098c87b03e5Sespie (match_operand 1 "" "")) 6099c87b03e5Sespie (clobber (reg:DI 1)) 6100c87b03e5Sespie (clobber (reg:DI 2)) 6101c87b03e5Sespie (clobber (reg:DI 4)) 6102c87b03e5Sespie (use (reg:DI 27)) 6103c87b03e5Sespie (use (reg:DI 29)) 6104c87b03e5Sespie (use (const_int 0))])] 6105c87b03e5Sespie "TARGET_64BIT 6106c87b03e5Sespie && reload_completed 6107c87b03e5Sespie && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" 6108c87b03e5Sespie [(set (reg:DI 4) (reg:DI 27)) 6109c87b03e5Sespie (parallel [(call (mem:SI (match_dup 0)) 6110c87b03e5Sespie (match_dup 1)) 6111c87b03e5Sespie (clobber (reg:DI 1)) 6112c87b03e5Sespie (clobber (reg:DI 2)) 6113c87b03e5Sespie (use (reg:DI 27)) 6114c87b03e5Sespie (use (reg:DI 29)) 6115c87b03e5Sespie (use (const_int 0))]) 6116c87b03e5Sespie (set (reg:DI 27) (reg:DI 4))] 6117c87b03e5Sespie "") 6118c87b03e5Sespie 6119c87b03e5Sespie;; Remove the clobber of register 4 when optimizing. This has to be 6120c87b03e5Sespie;; done with a peephole optimization rather than a split because the 6121c87b03e5Sespie;; split sequence for a call must be longer than one instruction. 6122c87b03e5Sespie(define_peephole2 6123c87b03e5Sespie [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" "")) 6124c87b03e5Sespie (match_operand 1 "" "")) 6125c87b03e5Sespie (clobber (reg:DI 1)) 6126c87b03e5Sespie (clobber (reg:DI 2)) 6127c87b03e5Sespie (clobber (reg:DI 4)) 6128c87b03e5Sespie (use (reg:DI 27)) 6129c87b03e5Sespie (use (reg:DI 29)) 6130c87b03e5Sespie (use (const_int 0))])] 6131c87b03e5Sespie "TARGET_64BIT && reload_completed" 6132c87b03e5Sespie [(parallel [(call (mem:SI (match_dup 0)) 6133c87b03e5Sespie (match_dup 1)) 6134c87b03e5Sespie (clobber (reg:DI 1)) 6135c87b03e5Sespie (clobber (reg:DI 2)) 6136c87b03e5Sespie (use (reg:DI 27)) 6137c87b03e5Sespie (use (reg:DI 29)) 6138c87b03e5Sespie (use (const_int 0))])] 6139c87b03e5Sespie "") 6140c87b03e5Sespie 6141c87b03e5Sespie(define_insn "*call_symref_64bit_post_reload" 6142c87b03e5Sespie [(call (mem:SI (match_operand 0 "call_operand_address" "")) 6143c87b03e5Sespie (match_operand 1 "" "i")) 6144c87b03e5Sespie (clobber (reg:DI 1)) 6145c87b03e5Sespie (clobber (reg:DI 2)) 6146c87b03e5Sespie (use (reg:DI 27)) 6147c87b03e5Sespie (use (reg:DI 29)) 6148c87b03e5Sespie (use (const_int 0))] 6149c87b03e5Sespie "TARGET_64BIT" 6150c87b03e5Sespie "* 6151c87b03e5Sespie{ 6152c87b03e5Sespie output_arg_descriptor (insn); 6153c87b03e5Sespie return output_call (insn, operands[0], 0); 6154c87b03e5Sespie}" 6155c87b03e5Sespie [(set_attr "type" "call") 6156c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) 6157c87b03e5Sespie 6158c87b03e5Sespie(define_insn "call_reg" 6159c87b03e5Sespie [(call (mem:SI (reg:SI 22)) 6160c87b03e5Sespie (match_operand 0 "" "i")) 6161c87b03e5Sespie (clobber (reg:SI 1)) 6162c87b03e5Sespie (clobber (reg:SI 2)) 6163c87b03e5Sespie (use (const_int 1))] 6164c87b03e5Sespie "!TARGET_64BIT" 6165c87b03e5Sespie "* 6166c87b03e5Sespie{ 6167c87b03e5Sespie return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); 6168c87b03e5Sespie}" 6169c87b03e5Sespie [(set_attr "type" "dyncall") 6170c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) 6171c87b03e5Sespie 6172c87b03e5Sespie;; This pattern is split if it is necessary to save and restore the 6173c87b03e5Sespie;; PIC register. 6174c87b03e5Sespie(define_insn "call_reg_pic" 6175c87b03e5Sespie [(call (mem:SI (reg:SI 22)) 6176c87b03e5Sespie (match_operand 0 "" "i")) 6177c87b03e5Sespie (clobber (reg:SI 1)) 6178c87b03e5Sespie (clobber (reg:SI 2)) 6179c87b03e5Sespie (clobber (reg:SI 4)) 6180c87b03e5Sespie (use (reg:SI 19)) 6181c87b03e5Sespie (use (const_int 1))] 6182c87b03e5Sespie "!TARGET_64BIT" 6183c87b03e5Sespie "* 6184c87b03e5Sespie{ 6185c87b03e5Sespie return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); 6186c87b03e5Sespie}" 6187c87b03e5Sespie [(set_attr "type" "dyncall") 6188c87b03e5Sespie (set (attr "length") 6189c87b03e5Sespie (plus (symbol_ref "attr_length_indirect_call (insn)") 6190c87b03e5Sespie (symbol_ref "attr_length_save_restore_dltp (insn)")))]) 6191c87b03e5Sespie 6192c87b03e5Sespie;; Split out the PIC register save and restore after reload. This is 6193c87b03e5Sespie;; done only if the function returns. As the split is done after reload, 6194c87b03e5Sespie;; there are some situations in which we unnecessarily save and restore 6195c87b03e5Sespie;; %r4. This happens when there is a single call and the PIC register 6196c87b03e5Sespie;; is "dead" after the call. This isn't easy to fix as the usage of 6197c87b03e5Sespie;; the PIC register isn't completely determined until the reload pass. 6198c87b03e5Sespie(define_split 6199c87b03e5Sespie [(parallel [(call (mem:SI (reg:SI 22)) 6200c87b03e5Sespie (match_operand 0 "" "")) 6201c87b03e5Sespie (clobber (reg:SI 1)) 6202c87b03e5Sespie (clobber (reg:SI 2)) 6203c87b03e5Sespie (clobber (reg:SI 4)) 6204c87b03e5Sespie (use (reg:SI 19)) 6205c87b03e5Sespie (use (const_int 1))])] 6206c87b03e5Sespie "!TARGET_64BIT 6207c87b03e5Sespie && reload_completed 6208c87b03e5Sespie && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" 6209c87b03e5Sespie [(set (reg:SI 4) (reg:SI 19)) 6210c87b03e5Sespie (parallel [(call (mem:SI (reg:SI 22)) 6211c87b03e5Sespie (match_dup 0)) 6212c87b03e5Sespie (clobber (reg:SI 1)) 6213c87b03e5Sespie (clobber (reg:SI 2)) 6214c87b03e5Sespie (use (reg:SI 19)) 6215c87b03e5Sespie (use (const_int 1))]) 6216c87b03e5Sespie (set (reg:SI 19) (reg:SI 4))] 6217c87b03e5Sespie "") 6218c87b03e5Sespie 6219c87b03e5Sespie;; Remove the clobber of register 4 when optimizing. This has to be 6220c87b03e5Sespie;; done with a peephole optimization rather than a split because the 6221c87b03e5Sespie;; split sequence for a call must be longer than one instruction. 6222c87b03e5Sespie(define_peephole2 6223c87b03e5Sespie [(parallel [(call (mem:SI (reg:SI 22)) 6224c87b03e5Sespie (match_operand 0 "" "")) 6225c87b03e5Sespie (clobber (reg:SI 1)) 6226c87b03e5Sespie (clobber (reg:SI 2)) 6227c87b03e5Sespie (clobber (reg:SI 4)) 6228c87b03e5Sespie (use (reg:SI 19)) 6229c87b03e5Sespie (use (const_int 1))])] 6230c87b03e5Sespie "!TARGET_64BIT && reload_completed" 6231c87b03e5Sespie [(parallel [(call (mem:SI (reg:SI 22)) 6232c87b03e5Sespie (match_dup 0)) 6233c87b03e5Sespie (clobber (reg:SI 1)) 6234c87b03e5Sespie (clobber (reg:SI 2)) 6235c87b03e5Sespie (use (reg:SI 19)) 6236c87b03e5Sespie (use (const_int 1))])] 6237c87b03e5Sespie "") 6238c87b03e5Sespie 6239c87b03e5Sespie(define_insn "*call_reg_pic_post_reload" 6240c87b03e5Sespie [(call (mem:SI (reg:SI 22)) 6241c87b03e5Sespie (match_operand 0 "" "i")) 6242c87b03e5Sespie (clobber (reg:SI 1)) 6243c87b03e5Sespie (clobber (reg:SI 2)) 6244c87b03e5Sespie (use (reg:SI 19)) 6245c87b03e5Sespie (use (const_int 1))] 6246c87b03e5Sespie "!TARGET_64BIT" 6247c87b03e5Sespie "* 6248c87b03e5Sespie{ 6249c87b03e5Sespie return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); 6250c87b03e5Sespie}" 6251c87b03e5Sespie [(set_attr "type" "dyncall") 6252c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) 6253c87b03e5Sespie 6254c87b03e5Sespie;; This pattern is split if it is necessary to save and restore the 6255c87b03e5Sespie;; PIC register. 6256c87b03e5Sespie(define_insn "call_reg_64bit" 6257c87b03e5Sespie [(call (mem:SI (match_operand:DI 0 "register_operand" "r")) 6258c87b03e5Sespie (match_operand 1 "" "i")) 6259c87b03e5Sespie (clobber (reg:DI 2)) 6260c87b03e5Sespie (clobber (reg:DI 4)) 6261c87b03e5Sespie (use (reg:DI 27)) 6262c87b03e5Sespie (use (reg:DI 29)) 6263c87b03e5Sespie (use (const_int 1))] 6264c87b03e5Sespie "TARGET_64BIT" 6265c87b03e5Sespie "* 6266c87b03e5Sespie{ 6267c87b03e5Sespie return output_indirect_call (insn, operands[0]); 6268c87b03e5Sespie}" 6269c87b03e5Sespie [(set_attr "type" "dyncall") 6270c87b03e5Sespie (set (attr "length") 6271c87b03e5Sespie (plus (symbol_ref "attr_length_indirect_call (insn)") 6272c87b03e5Sespie (symbol_ref "attr_length_save_restore_dltp (insn)")))]) 6273c87b03e5Sespie 6274c87b03e5Sespie;; Split out the PIC register save and restore after reload. This is 6275c87b03e5Sespie;; done only if the function returns. As the split is done after reload, 6276c87b03e5Sespie;; there are some situations in which we unnecessarily save and restore 6277c87b03e5Sespie;; %r4. This happens when there is a single call and the PIC register 6278c87b03e5Sespie;; is "dead" after the call. This isn't easy to fix as the usage of 6279c87b03e5Sespie;; the PIC register isn't completely determined until the reload pass. 6280c87b03e5Sespie(define_split 6281c87b03e5Sespie [(parallel [(call (mem:SI (match_operand 0 "register_operand" "")) 6282c87b03e5Sespie (match_operand 1 "" "")) 6283c87b03e5Sespie (clobber (reg:DI 2)) 6284c87b03e5Sespie (clobber (reg:DI 4)) 6285c87b03e5Sespie (use (reg:DI 27)) 6286c87b03e5Sespie (use (reg:DI 29)) 6287c87b03e5Sespie (use (const_int 1))])] 6288c87b03e5Sespie "TARGET_64BIT 6289c87b03e5Sespie && reload_completed 6290c87b03e5Sespie && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" 6291c87b03e5Sespie [(set (reg:DI 4) (reg:DI 27)) 6292c87b03e5Sespie (parallel [(call (mem:SI (match_dup 0)) 6293c87b03e5Sespie (match_dup 1)) 6294c87b03e5Sespie (clobber (reg:DI 2)) 6295c87b03e5Sespie (use (reg:DI 27)) 6296c87b03e5Sespie (use (reg:DI 29)) 6297c87b03e5Sespie (use (const_int 1))]) 6298c87b03e5Sespie (set (reg:DI 27) (reg:DI 4))] 6299c87b03e5Sespie "") 6300c87b03e5Sespie 6301c87b03e5Sespie;; Remove the clobber of register 4 when optimizing. This has to be 6302c87b03e5Sespie;; done with a peephole optimization rather than a split because the 6303c87b03e5Sespie;; split sequence for a call must be longer than one instruction. 6304c87b03e5Sespie(define_peephole2 6305c87b03e5Sespie [(parallel [(call (mem:SI (match_operand 0 "register_operand" "")) 6306c87b03e5Sespie (match_operand 1 "" "")) 6307c87b03e5Sespie (clobber (reg:DI 2)) 6308c87b03e5Sespie (clobber (reg:DI 4)) 6309c87b03e5Sespie (use (reg:DI 27)) 6310c87b03e5Sespie (use (reg:DI 29)) 6311c87b03e5Sespie (use (const_int 1))])] 6312c87b03e5Sespie "TARGET_64BIT && reload_completed" 6313c87b03e5Sespie [(parallel [(call (mem:SI (match_dup 0)) 6314c87b03e5Sespie (match_dup 1)) 6315c87b03e5Sespie (clobber (reg:DI 2)) 6316c87b03e5Sespie (use (reg:DI 27)) 6317c87b03e5Sespie (use (reg:DI 29)) 6318c87b03e5Sespie (use (const_int 1))])] 6319c87b03e5Sespie "") 6320c87b03e5Sespie 6321c87b03e5Sespie(define_insn "*call_reg_64bit_post_reload" 6322c87b03e5Sespie [(call (mem:SI (match_operand:DI 0 "register_operand" "r")) 6323c87b03e5Sespie (match_operand 1 "" "i")) 6324c87b03e5Sespie (clobber (reg:DI 2)) 6325c87b03e5Sespie (use (reg:DI 27)) 6326c87b03e5Sespie (use (reg:DI 29)) 6327c87b03e5Sespie (use (const_int 1))] 6328c87b03e5Sespie "TARGET_64BIT" 6329c87b03e5Sespie "* 6330c87b03e5Sespie{ 6331c87b03e5Sespie return output_indirect_call (insn, operands[0]); 6332c87b03e5Sespie}" 6333c87b03e5Sespie [(set_attr "type" "dyncall") 6334c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) 6335c87b03e5Sespie 6336c87b03e5Sespie(define_expand "call_value" 6337c87b03e5Sespie [(parallel [(set (match_operand 0 "" "") 6338c87b03e5Sespie (call (match_operand:SI 1 "" "") 6339c87b03e5Sespie (match_operand 2 "" ""))) 6340c87b03e5Sespie (clobber (reg:SI 2))])] 6341c87b03e5Sespie "" 6342c87b03e5Sespie " 6343c87b03e5Sespie{ 6344c87b03e5Sespie rtx op, call_insn; 6345c87b03e5Sespie rtx dst = operands[0]; 6346c87b03e5Sespie rtx nb = operands[2]; 6347c87b03e5Sespie 6348c87b03e5Sespie if (TARGET_PORTABLE_RUNTIME) 6349c87b03e5Sespie op = force_reg (SImode, XEXP (operands[1], 0)); 6350c87b03e5Sespie else 6351c87b03e5Sespie op = XEXP (operands[1], 0); 6352c87b03e5Sespie 6353c87b03e5Sespie if (TARGET_64BIT) 6354c87b03e5Sespie { 6355c87b03e5Sespie if (!virtuals_instantiated) 6356c87b03e5Sespie emit_move_insn (arg_pointer_rtx, 6357c87b03e5Sespie gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, 6358c87b03e5Sespie GEN_INT (64))); 6359c87b03e5Sespie else 6360c87b03e5Sespie { 6361c87b03e5Sespie /* The loop pass can generate new libcalls after the virtual 6362c87b03e5Sespie registers are instantiated when fpregs are disabled because 6363c87b03e5Sespie the only method that we have for doing DImode multiplication 6364c87b03e5Sespie is with a libcall. This could be trouble if we haven't 6365c87b03e5Sespie allocated enough space for the outgoing arguments. */ 6366c87b03e5Sespie if (INTVAL (nb) > current_function_outgoing_args_size) 6367c87b03e5Sespie abort (); 6368c87b03e5Sespie 6369c87b03e5Sespie emit_move_insn (arg_pointer_rtx, 6370c87b03e5Sespie gen_rtx_PLUS (word_mode, stack_pointer_rtx, 6371c87b03e5Sespie GEN_INT (STACK_POINTER_OFFSET + 64))); 6372c87b03e5Sespie } 6373c87b03e5Sespie } 6374c87b03e5Sespie 6375c87b03e5Sespie /* Use two different patterns for calls to explicitly named functions 6376c87b03e5Sespie and calls through function pointers. This is necessary as these two 6377c87b03e5Sespie types of calls use different calling conventions, and CSE might try 6378c87b03e5Sespie to change the named call into an indirect call in some cases (using 6379c87b03e5Sespie two patterns keeps CSE from performing this optimization). 6380c87b03e5Sespie 6381c87b03e5Sespie We now use even more call patterns as there was a subtle bug in 6382c87b03e5Sespie attempting to restore the pic register after a call using a simple 6383c87b03e5Sespie move insn. During reload, a instruction involving a pseudo register 6384c87b03e5Sespie with no explicit dependence on the PIC register can be converted 6385c87b03e5Sespie to an equivalent load from memory using the PIC register. If we 6386c87b03e5Sespie emit a simple move to restore the PIC register in the initial rtl 6387c87b03e5Sespie generation, then it can potentially be repositioned during scheduling. 6388c87b03e5Sespie and an instruction that eventually uses the PIC register may end up 6389c87b03e5Sespie between the call and the PIC register restore. 6390c87b03e5Sespie 6391c87b03e5Sespie This only worked because there is a post call group of instructions 6392c87b03e5Sespie that are scheduled with the call. These instructions are included 6393c87b03e5Sespie in the same basic block as the call. However, calls can throw in 6394c87b03e5Sespie C++ code and a basic block has to terminate at the call if the call 6395c87b03e5Sespie can throw. This results in the PIC register restore being scheduled 6396c87b03e5Sespie independently from the call. So, we now hide the save and restore 6397c87b03e5Sespie of the PIC register in the call pattern until after reload. Then, 6398c87b03e5Sespie we split the moves out. A small side benefit is that we now don't 6399c87b03e5Sespie need to have a use of the PIC register in the return pattern and 6400c87b03e5Sespie the final save/restore operation is not needed. 6401c87b03e5Sespie 6402c87b03e5Sespie I elected to just clobber %r4 in the PIC patterns and use it instead 6403c87b03e5Sespie of trying to force hppa_pic_save_rtx () to a callee saved register. 6404c87b03e5Sespie This might have required a new register class and constraint. It 6405c87b03e5Sespie was also simpler to just handle the restore from a register than a 6406c87b03e5Sespie generic pseudo. */ 6407c87b03e5Sespie if (TARGET_64BIT) 6408c87b03e5Sespie { 6409c87b03e5Sespie if (GET_CODE (op) == SYMBOL_REF) 6410c87b03e5Sespie call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb)); 6411c87b03e5Sespie else 6412c87b03e5Sespie { 6413c87b03e5Sespie op = force_reg (word_mode, op); 6414c87b03e5Sespie call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb)); 6415c87b03e5Sespie } 6416c87b03e5Sespie } 6417c87b03e5Sespie else 6418c87b03e5Sespie { 6419c87b03e5Sespie if (GET_CODE (op) == SYMBOL_REF) 6420c87b03e5Sespie { 6421c87b03e5Sespie if (flag_pic) 6422c87b03e5Sespie call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb)); 6423c87b03e5Sespie else 6424c87b03e5Sespie call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb)); 6425c87b03e5Sespie } 6426c87b03e5Sespie else 6427c87b03e5Sespie { 6428c87b03e5Sespie rtx tmpreg = gen_rtx_REG (word_mode, 22); 6429c87b03e5Sespie 6430c87b03e5Sespie emit_move_insn (tmpreg, force_reg (word_mode, op)); 6431c87b03e5Sespie if (flag_pic) 6432c87b03e5Sespie call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb)); 6433c87b03e5Sespie else 6434c87b03e5Sespie call_insn = emit_call_insn (gen_call_val_reg (dst, nb)); 6435c87b03e5Sespie } 6436c87b03e5Sespie } 6437c87b03e5Sespie 6438c87b03e5Sespie DONE; 6439c87b03e5Sespie}") 6440c87b03e5Sespie 6441c87b03e5Sespie(define_insn "call_val_symref" 6442c87b03e5Sespie [(set (match_operand 0 "" "") 6443c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 6444c87b03e5Sespie (match_operand 2 "" "i"))) 6445c87b03e5Sespie (clobber (reg:SI 1)) 6446c87b03e5Sespie (clobber (reg:SI 2)) 6447c87b03e5Sespie (use (const_int 0))] 6448c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" 6449c87b03e5Sespie "* 6450c87b03e5Sespie{ 6451c87b03e5Sespie output_arg_descriptor (insn); 6452c87b03e5Sespie return output_call (insn, operands[1], 0); 6453c87b03e5Sespie}" 6454c87b03e5Sespie [(set_attr "type" "call") 6455c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) 6456c87b03e5Sespie 6457c87b03e5Sespie(define_insn "call_val_symref_pic" 6458c87b03e5Sespie [(set (match_operand 0 "" "") 6459c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 6460c87b03e5Sespie (match_operand 2 "" "i"))) 6461c87b03e5Sespie (clobber (reg:SI 1)) 6462c87b03e5Sespie (clobber (reg:SI 2)) 6463c87b03e5Sespie (clobber (reg:SI 4)) 6464c87b03e5Sespie (use (reg:SI 19)) 6465c87b03e5Sespie (use (const_int 0))] 6466c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" 6467c87b03e5Sespie "* 6468c87b03e5Sespie{ 6469c87b03e5Sespie output_arg_descriptor (insn); 6470c87b03e5Sespie return output_call (insn, operands[1], 0); 6471c87b03e5Sespie}" 6472c87b03e5Sespie [(set_attr "type" "call") 6473c87b03e5Sespie (set (attr "length") 6474c87b03e5Sespie (plus (symbol_ref "attr_length_call (insn, 0)") 6475c87b03e5Sespie (symbol_ref "attr_length_save_restore_dltp (insn)")))]) 6476c87b03e5Sespie 6477c87b03e5Sespie;; Split out the PIC register save and restore after reload. This is 6478c87b03e5Sespie;; done only if the function returns. As the split is done after reload, 6479c87b03e5Sespie;; there are some situations in which we unnecessarily save and restore 6480c87b03e5Sespie;; %r4. This happens when there is a single call and the PIC register 6481c87b03e5Sespie;; is "dead" after the call. This isn't easy to fix as the usage of 6482c87b03e5Sespie;; the PIC register isn't completely determined until the reload pass. 6483c87b03e5Sespie(define_split 6484c87b03e5Sespie [(parallel [(set (match_operand 0 "" "") 6485c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 6486c87b03e5Sespie (match_operand 2 "" ""))) 6487c87b03e5Sespie (clobber (reg:SI 1)) 6488c87b03e5Sespie (clobber (reg:SI 2)) 6489c87b03e5Sespie (clobber (reg:SI 4)) 6490c87b03e5Sespie (use (reg:SI 19)) 6491c87b03e5Sespie (use (const_int 0))])] 6492c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT 6493c87b03e5Sespie && reload_completed 6494c87b03e5Sespie && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" 6495c87b03e5Sespie [(set (reg:SI 4) (reg:SI 19)) 6496c87b03e5Sespie (parallel [(set (match_dup 0) 6497c87b03e5Sespie (call (mem:SI (match_dup 1)) 6498c87b03e5Sespie (match_dup 2))) 6499c87b03e5Sespie (clobber (reg:SI 1)) 6500c87b03e5Sespie (clobber (reg:SI 2)) 6501c87b03e5Sespie (use (reg:SI 19)) 6502c87b03e5Sespie (use (const_int 0))]) 6503c87b03e5Sespie (set (reg:SI 19) (reg:SI 4))] 6504c87b03e5Sespie "") 6505c87b03e5Sespie 6506c87b03e5Sespie;; Remove the clobber of register 4 when optimizing. This has to be 6507c87b03e5Sespie;; done with a peephole optimization rather than a split because the 6508c87b03e5Sespie;; split sequence for a call must be longer than one instruction. 6509c87b03e5Sespie(define_peephole2 6510c87b03e5Sespie [(parallel [(set (match_operand 0 "" "") 6511c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 6512c87b03e5Sespie (match_operand 2 "" ""))) 6513c87b03e5Sespie (clobber (reg:SI 1)) 6514c87b03e5Sespie (clobber (reg:SI 2)) 6515c87b03e5Sespie (clobber (reg:SI 4)) 6516c87b03e5Sespie (use (reg:SI 19)) 6517c87b03e5Sespie (use (const_int 0))])] 6518c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed" 6519c87b03e5Sespie [(parallel [(set (match_dup 0) 6520c87b03e5Sespie (call (mem:SI (match_dup 1)) 6521c87b03e5Sespie (match_dup 2))) 6522c87b03e5Sespie (clobber (reg:SI 1)) 6523c87b03e5Sespie (clobber (reg:SI 2)) 6524c87b03e5Sespie (use (reg:SI 19)) 6525c87b03e5Sespie (use (const_int 0))])] 6526c87b03e5Sespie "") 6527c87b03e5Sespie 6528c87b03e5Sespie(define_insn "*call_val_symref_pic_post_reload" 6529c87b03e5Sespie [(set (match_operand 0 "" "") 6530c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 6531c87b03e5Sespie (match_operand 2 "" "i"))) 6532c87b03e5Sespie (clobber (reg:SI 1)) 6533c87b03e5Sespie (clobber (reg:SI 2)) 6534c87b03e5Sespie (use (reg:SI 19)) 6535c87b03e5Sespie (use (const_int 0))] 6536c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" 6537c87b03e5Sespie "* 6538c87b03e5Sespie{ 6539c87b03e5Sespie output_arg_descriptor (insn); 6540c87b03e5Sespie return output_call (insn, operands[1], 0); 6541c87b03e5Sespie}" 6542c87b03e5Sespie [(set_attr "type" "call") 6543c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) 6544c87b03e5Sespie 6545c87b03e5Sespie;; This pattern is split if it is necessary to save and restore the 6546c87b03e5Sespie;; PIC register. 6547c87b03e5Sespie(define_insn "call_val_symref_64bit" 6548c87b03e5Sespie [(set (match_operand 0 "" "") 6549c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 6550c87b03e5Sespie (match_operand 2 "" "i"))) 6551c87b03e5Sespie (clobber (reg:DI 1)) 6552c87b03e5Sespie (clobber (reg:DI 2)) 6553c87b03e5Sespie (clobber (reg:DI 4)) 6554c87b03e5Sespie (use (reg:DI 27)) 6555c87b03e5Sespie (use (reg:DI 29)) 6556c87b03e5Sespie (use (const_int 0))] 6557c87b03e5Sespie "TARGET_64BIT" 6558c87b03e5Sespie "* 6559c87b03e5Sespie{ 6560c87b03e5Sespie output_arg_descriptor (insn); 6561c87b03e5Sespie return output_call (insn, operands[1], 0); 6562c87b03e5Sespie}" 6563c87b03e5Sespie [(set_attr "type" "call") 6564c87b03e5Sespie (set (attr "length") 6565c87b03e5Sespie (plus (symbol_ref "attr_length_call (insn, 0)") 6566c87b03e5Sespie (symbol_ref "attr_length_save_restore_dltp (insn)")))]) 6567c87b03e5Sespie 6568c87b03e5Sespie;; Split out the PIC register save and restore after reload. This is 6569c87b03e5Sespie;; done only if the function returns. As the split is done after reload, 6570c87b03e5Sespie;; there are some situations in which we unnecessarily save and restore 6571c87b03e5Sespie;; %r4. This happens when there is a single call and the PIC register 6572c87b03e5Sespie;; is "dead" after the call. This isn't easy to fix as the usage of 6573c87b03e5Sespie;; the PIC register isn't completely determined until the reload pass. 6574c87b03e5Sespie(define_split 6575c87b03e5Sespie [(parallel [(set (match_operand 0 "" "") 6576c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 6577c87b03e5Sespie (match_operand 2 "" ""))) 6578c87b03e5Sespie (clobber (reg:DI 1)) 6579c87b03e5Sespie (clobber (reg:DI 2)) 6580c87b03e5Sespie (clobber (reg:DI 4)) 6581c87b03e5Sespie (use (reg:DI 27)) 6582c87b03e5Sespie (use (reg:DI 29)) 6583c87b03e5Sespie (use (const_int 0))])] 6584c87b03e5Sespie "TARGET_64BIT 6585c87b03e5Sespie && reload_completed 6586c87b03e5Sespie && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" 6587c87b03e5Sespie [(set (reg:DI 4) (reg:DI 27)) 6588c87b03e5Sespie (parallel [(set (match_dup 0) 6589c87b03e5Sespie (call (mem:SI (match_dup 1)) 6590c87b03e5Sespie (match_dup 2))) 6591c87b03e5Sespie (clobber (reg:DI 1)) 6592c87b03e5Sespie (clobber (reg:DI 2)) 6593c87b03e5Sespie (use (reg:DI 27)) 6594c87b03e5Sespie (use (reg:DI 29)) 6595c87b03e5Sespie (use (const_int 0))]) 6596c87b03e5Sespie (set (reg:DI 27) (reg:DI 4))] 6597c87b03e5Sespie "") 6598c87b03e5Sespie 6599c87b03e5Sespie;; Remove the clobber of register 4 when optimizing. This has to be 6600c87b03e5Sespie;; done with a peephole optimization rather than a split because the 6601c87b03e5Sespie;; split sequence for a call must be longer than one instruction. 6602c87b03e5Sespie(define_peephole2 6603c87b03e5Sespie [(parallel [(set (match_operand 0 "" "") 6604c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 6605c87b03e5Sespie (match_operand 2 "" ""))) 6606c87b03e5Sespie (clobber (reg:DI 1)) 6607c87b03e5Sespie (clobber (reg:DI 2)) 6608c87b03e5Sespie (clobber (reg:DI 4)) 6609c87b03e5Sespie (use (reg:DI 27)) 6610c87b03e5Sespie (use (reg:DI 29)) 6611c87b03e5Sespie (use (const_int 0))])] 6612c87b03e5Sespie "TARGET_64BIT && reload_completed" 6613c87b03e5Sespie [(parallel [(set (match_dup 0) 6614c87b03e5Sespie (call (mem:SI (match_dup 1)) 6615c87b03e5Sespie (match_dup 2))) 6616c87b03e5Sespie (clobber (reg:DI 1)) 6617c87b03e5Sespie (clobber (reg:DI 2)) 6618c87b03e5Sespie (use (reg:DI 27)) 6619c87b03e5Sespie (use (reg:DI 29)) 6620c87b03e5Sespie (use (const_int 0))])] 6621c87b03e5Sespie "") 6622c87b03e5Sespie 6623c87b03e5Sespie(define_insn "*call_val_symref_64bit_post_reload" 6624c87b03e5Sespie [(set (match_operand 0 "" "") 6625c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 6626c87b03e5Sespie (match_operand 2 "" "i"))) 6627c87b03e5Sespie (clobber (reg:DI 1)) 6628c87b03e5Sespie (clobber (reg:DI 2)) 6629c87b03e5Sespie (use (reg:DI 27)) 6630c87b03e5Sespie (use (reg:DI 29)) 6631c87b03e5Sespie (use (const_int 0))] 6632c87b03e5Sespie "TARGET_64BIT" 6633c87b03e5Sespie "* 6634c87b03e5Sespie{ 6635c87b03e5Sespie output_arg_descriptor (insn); 6636c87b03e5Sespie return output_call (insn, operands[1], 0); 6637c87b03e5Sespie}" 6638c87b03e5Sespie [(set_attr "type" "call") 6639c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) 6640c87b03e5Sespie 6641c87b03e5Sespie(define_insn "call_val_reg" 6642c87b03e5Sespie [(set (match_operand 0 "" "") 6643c87b03e5Sespie (call (mem:SI (reg:SI 22)) 6644c87b03e5Sespie (match_operand 1 "" "i"))) 6645c87b03e5Sespie (clobber (reg:SI 1)) 6646c87b03e5Sespie (clobber (reg:SI 2)) 6647c87b03e5Sespie (use (const_int 1))] 6648c87b03e5Sespie "!TARGET_64BIT" 6649c87b03e5Sespie "* 6650c87b03e5Sespie{ 6651c87b03e5Sespie return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); 6652c87b03e5Sespie}" 6653c87b03e5Sespie [(set_attr "type" "dyncall") 6654c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) 6655c87b03e5Sespie 6656c87b03e5Sespie;; This pattern is split if it is necessary to save and restore the 6657c87b03e5Sespie;; PIC register. 6658c87b03e5Sespie(define_insn "call_val_reg_pic" 6659c87b03e5Sespie [(set (match_operand 0 "" "") 6660c87b03e5Sespie (call (mem:SI (reg:SI 22)) 6661c87b03e5Sespie (match_operand 1 "" "i"))) 6662c87b03e5Sespie (clobber (reg:SI 1)) 6663c87b03e5Sespie (clobber (reg:SI 2)) 6664c87b03e5Sespie (clobber (reg:SI 4)) 6665c87b03e5Sespie (use (reg:SI 19)) 6666c87b03e5Sespie (use (const_int 1))] 6667c87b03e5Sespie "!TARGET_64BIT" 6668c87b03e5Sespie "* 6669c87b03e5Sespie{ 6670c87b03e5Sespie return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); 6671c87b03e5Sespie}" 6672c87b03e5Sespie [(set_attr "type" "dyncall") 6673c87b03e5Sespie (set (attr "length") 6674c87b03e5Sespie (plus (symbol_ref "attr_length_indirect_call (insn)") 6675c87b03e5Sespie (symbol_ref "attr_length_save_restore_dltp (insn)")))]) 6676c87b03e5Sespie 6677c87b03e5Sespie;; Split out the PIC register save and restore after reload. This is 6678c87b03e5Sespie;; done only if the function returns. As the split is done after reload, 6679c87b03e5Sespie;; there are some situations in which we unnecessarily save and restore 6680c87b03e5Sespie;; %r4. This happens when there is a single call and the PIC register 6681c87b03e5Sespie;; is "dead" after the call. This isn't easy to fix as the usage of 6682c87b03e5Sespie;; the PIC register isn't completely determined until the reload pass. 6683c87b03e5Sespie(define_split 6684c87b03e5Sespie [(parallel [(set (match_operand 0 "" "") 6685c87b03e5Sespie (call (mem:SI (reg:SI 22)) 6686c87b03e5Sespie (match_operand 1 "" ""))) 6687c87b03e5Sespie (clobber (reg:SI 1)) 6688c87b03e5Sespie (clobber (reg:SI 2)) 6689c87b03e5Sespie (clobber (reg:SI 4)) 6690c87b03e5Sespie (use (reg:SI 19)) 6691c87b03e5Sespie (use (const_int 1))])] 6692c87b03e5Sespie "!TARGET_64BIT 6693c87b03e5Sespie && reload_completed 6694c87b03e5Sespie && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" 6695c87b03e5Sespie [(set (reg:SI 4) (reg:SI 19)) 6696c87b03e5Sespie (parallel [(set (match_dup 0) 6697c87b03e5Sespie (call (mem:SI (reg:SI 22)) 6698c87b03e5Sespie (match_dup 1))) 6699c87b03e5Sespie (clobber (reg:SI 1)) 6700c87b03e5Sespie (clobber (reg:SI 2)) 6701c87b03e5Sespie (use (reg:SI 19)) 6702c87b03e5Sespie (use (const_int 1))]) 6703c87b03e5Sespie (set (reg:SI 19) (reg:SI 4))] 6704c87b03e5Sespie "") 6705c87b03e5Sespie 6706c87b03e5Sespie;; Remove the clobber of register 4 when optimizing. This has to be 6707c87b03e5Sespie;; done with a peephole optimization rather than a split because the 6708c87b03e5Sespie;; split sequence for a call must be longer than one instruction. 6709c87b03e5Sespie(define_peephole2 6710c87b03e5Sespie [(parallel [(set (match_operand 0 "" "") 6711c87b03e5Sespie (call (mem:SI (reg:SI 22)) 6712c87b03e5Sespie (match_operand 1 "" ""))) 6713c87b03e5Sespie (clobber (reg:SI 1)) 6714c87b03e5Sespie (clobber (reg:SI 2)) 6715c87b03e5Sespie (clobber (reg:SI 4)) 6716c87b03e5Sespie (use (reg:SI 19)) 6717c87b03e5Sespie (use (const_int 1))])] 6718c87b03e5Sespie "!TARGET_64BIT && reload_completed" 6719c87b03e5Sespie [(parallel [(set (match_dup 0) 6720c87b03e5Sespie (call (mem:SI (reg:SI 22)) 6721c87b03e5Sespie (match_dup 1))) 6722c87b03e5Sespie (clobber (reg:SI 1)) 6723c87b03e5Sespie (clobber (reg:SI 2)) 6724c87b03e5Sespie (use (reg:SI 19)) 6725c87b03e5Sespie (use (const_int 1))])] 6726c87b03e5Sespie "") 6727c87b03e5Sespie 6728c87b03e5Sespie(define_insn "*call_val_reg_pic_post_reload" 6729c87b03e5Sespie [(set (match_operand 0 "" "") 6730c87b03e5Sespie (call (mem:SI (reg:SI 22)) 6731c87b03e5Sespie (match_operand 1 "" "i"))) 6732c87b03e5Sespie (clobber (reg:SI 1)) 6733c87b03e5Sespie (clobber (reg:SI 2)) 6734c87b03e5Sespie (use (reg:SI 19)) 6735c87b03e5Sespie (use (const_int 1))] 6736c87b03e5Sespie "!TARGET_64BIT" 6737c87b03e5Sespie "* 6738c87b03e5Sespie{ 6739c87b03e5Sespie return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); 6740c87b03e5Sespie}" 6741c87b03e5Sespie [(set_attr "type" "dyncall") 6742c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) 6743c87b03e5Sespie 6744c87b03e5Sespie;; This pattern is split if it is necessary to save and restore the 6745c87b03e5Sespie;; PIC register. 6746c87b03e5Sespie(define_insn "call_val_reg_64bit" 6747c87b03e5Sespie [(set (match_operand 0 "" "") 6748c87b03e5Sespie (call (mem:SI (match_operand:DI 1 "register_operand" "r")) 6749c87b03e5Sespie (match_operand 2 "" "i"))) 6750c87b03e5Sespie (clobber (reg:DI 2)) 6751c87b03e5Sespie (clobber (reg:DI 4)) 6752c87b03e5Sespie (use (reg:DI 27)) 6753c87b03e5Sespie (use (reg:DI 29)) 6754c87b03e5Sespie (use (const_int 1))] 6755c87b03e5Sespie "TARGET_64BIT" 6756c87b03e5Sespie "* 6757c87b03e5Sespie{ 6758c87b03e5Sespie return output_indirect_call (insn, operands[1]); 6759c87b03e5Sespie}" 6760c87b03e5Sespie [(set_attr "type" "dyncall") 6761c87b03e5Sespie (set (attr "length") 6762c87b03e5Sespie (plus (symbol_ref "attr_length_indirect_call (insn)") 6763c87b03e5Sespie (symbol_ref "attr_length_save_restore_dltp (insn)")))]) 6764c87b03e5Sespie 6765c87b03e5Sespie;; Split out the PIC register save and restore after reload. This is 6766c87b03e5Sespie;; done only if the function returns. As the split is done after reload, 6767c87b03e5Sespie;; there are some situations in which we unnecessarily save and restore 6768c87b03e5Sespie;; %r4. This happens when there is a single call and the PIC register 6769c87b03e5Sespie;; is "dead" after the call. This isn't easy to fix as the usage of 6770c87b03e5Sespie;; the PIC register isn't completely determined until the reload pass. 6771c87b03e5Sespie(define_split 6772c87b03e5Sespie [(parallel [(set (match_operand 0 "" "") 6773c87b03e5Sespie (call (mem:SI (match_operand:DI 1 "register_operand" "")) 6774c87b03e5Sespie (match_operand 2 "" ""))) 6775c87b03e5Sespie (clobber (reg:DI 2)) 6776c87b03e5Sespie (clobber (reg:DI 4)) 6777c87b03e5Sespie (use (reg:DI 27)) 6778c87b03e5Sespie (use (reg:DI 29)) 6779c87b03e5Sespie (use (const_int 1))])] 6780c87b03e5Sespie "TARGET_64BIT 6781c87b03e5Sespie && reload_completed 6782c87b03e5Sespie && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" 6783c87b03e5Sespie [(set (reg:DI 4) (reg:DI 27)) 6784c87b03e5Sespie (parallel [(set (match_dup 0) 6785c87b03e5Sespie (call (mem:SI (match_dup 1)) 6786c87b03e5Sespie (match_dup 2))) 6787c87b03e5Sespie (clobber (reg:DI 2)) 6788c87b03e5Sespie (use (reg:DI 27)) 6789c87b03e5Sespie (use (reg:DI 29)) 6790c87b03e5Sespie (use (const_int 1))]) 6791c87b03e5Sespie (set (reg:DI 27) (reg:DI 4))] 6792c87b03e5Sespie "") 6793c87b03e5Sespie 6794c87b03e5Sespie;; Remove the clobber of register 4 when optimizing. This has to be 6795c87b03e5Sespie;; done with a peephole optimization rather than a split because the 6796c87b03e5Sespie;; split sequence for a call must be longer than one instruction. 6797c87b03e5Sespie(define_peephole2 6798c87b03e5Sespie [(parallel [(set (match_operand 0 "" "") 6799c87b03e5Sespie (call (mem:SI (match_operand:DI 1 "register_operand" "")) 6800c87b03e5Sespie (match_operand 2 "" ""))) 6801c87b03e5Sespie (clobber (reg:DI 2)) 6802c87b03e5Sespie (clobber (reg:DI 4)) 6803c87b03e5Sespie (use (reg:DI 27)) 6804c87b03e5Sespie (use (reg:DI 29)) 6805c87b03e5Sespie (use (const_int 1))])] 6806c87b03e5Sespie "TARGET_64BIT && reload_completed" 6807c87b03e5Sespie [(parallel [(set (match_dup 0) 6808c87b03e5Sespie (call (mem:SI (match_dup 1)) 6809c87b03e5Sespie (match_dup 2))) 6810c87b03e5Sespie (clobber (reg:DI 2)) 6811c87b03e5Sespie (use (reg:DI 27)) 6812c87b03e5Sespie (use (reg:DI 29)) 6813c87b03e5Sespie (use (const_int 1))])] 6814c87b03e5Sespie "") 6815c87b03e5Sespie 6816c87b03e5Sespie(define_insn "*call_val_reg_64bit_post_reload" 6817c87b03e5Sespie [(set (match_operand 0 "" "") 6818c87b03e5Sespie (call (mem:SI (match_operand:DI 1 "register_operand" "r")) 6819c87b03e5Sespie (match_operand 2 "" "i"))) 6820c87b03e5Sespie (clobber (reg:DI 2)) 6821c87b03e5Sespie (use (reg:DI 27)) 6822c87b03e5Sespie (use (reg:DI 29)) 6823c87b03e5Sespie (use (const_int 1))] 6824c87b03e5Sespie "TARGET_64BIT" 6825c87b03e5Sespie "* 6826c87b03e5Sespie{ 6827c87b03e5Sespie return output_indirect_call (insn, operands[1]); 6828c87b03e5Sespie}" 6829c87b03e5Sespie [(set_attr "type" "dyncall") 6830c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) 6831c87b03e5Sespie 6832c87b03e5Sespie;; Call subroutine returning any type. 6833c87b03e5Sespie 6834c87b03e5Sespie(define_expand "untyped_call" 6835c87b03e5Sespie [(parallel [(call (match_operand 0 "" "") 6836c87b03e5Sespie (const_int 0)) 6837c87b03e5Sespie (match_operand 1 "" "") 6838c87b03e5Sespie (match_operand 2 "" "")])] 6839c87b03e5Sespie "" 6840c87b03e5Sespie " 6841c87b03e5Sespie{ 6842c87b03e5Sespie int i; 6843c87b03e5Sespie 6844c87b03e5Sespie emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); 6845c87b03e5Sespie 6846c87b03e5Sespie for (i = 0; i < XVECLEN (operands[2], 0); i++) 6847c87b03e5Sespie { 6848c87b03e5Sespie rtx set = XVECEXP (operands[2], 0, i); 6849c87b03e5Sespie emit_move_insn (SET_DEST (set), SET_SRC (set)); 6850c87b03e5Sespie } 6851c87b03e5Sespie 6852c87b03e5Sespie /* The optimizer does not know that the call sets the function value 6853c87b03e5Sespie registers we stored in the result block. We avoid problems by 6854c87b03e5Sespie claiming that all hard registers are used and clobbered at this 6855c87b03e5Sespie point. */ 6856c87b03e5Sespie emit_insn (gen_blockage ()); 6857c87b03e5Sespie 6858c87b03e5Sespie DONE; 6859c87b03e5Sespie}") 6860c87b03e5Sespie 6861c87b03e5Sespie(define_expand "sibcall" 6862c87b03e5Sespie [(call (match_operand:SI 0 "" "") 6863c87b03e5Sespie (match_operand 1 "" ""))] 6864c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME" 6865c87b03e5Sespie " 6866c87b03e5Sespie{ 6867c87b03e5Sespie rtx op, call_insn; 6868c87b03e5Sespie rtx nb = operands[1]; 6869c87b03e5Sespie 6870c87b03e5Sespie op = XEXP (operands[0], 0); 6871c87b03e5Sespie 6872c87b03e5Sespie if (TARGET_64BIT) 6873c87b03e5Sespie { 6874c87b03e5Sespie if (!virtuals_instantiated) 6875c87b03e5Sespie emit_move_insn (arg_pointer_rtx, 6876c87b03e5Sespie gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, 6877c87b03e5Sespie GEN_INT (64))); 6878c87b03e5Sespie else 6879c87b03e5Sespie { 6880c87b03e5Sespie /* The loop pass can generate new libcalls after the virtual 6881c87b03e5Sespie registers are instantiated when fpregs are disabled because 6882c87b03e5Sespie the only method that we have for doing DImode multiplication 6883c87b03e5Sespie is with a libcall. This could be trouble if we haven't 6884c87b03e5Sespie allocated enough space for the outgoing arguments. */ 6885c87b03e5Sespie if (INTVAL (nb) > current_function_outgoing_args_size) 6886c87b03e5Sespie abort (); 6887c87b03e5Sespie 6888c87b03e5Sespie emit_move_insn (arg_pointer_rtx, 6889c87b03e5Sespie gen_rtx_PLUS (word_mode, stack_pointer_rtx, 6890c87b03e5Sespie GEN_INT (STACK_POINTER_OFFSET + 64))); 6891c87b03e5Sespie } 6892c87b03e5Sespie } 6893c87b03e5Sespie 6894c87b03e5Sespie /* Indirect sibling calls are not allowed. */ 6895c87b03e5Sespie if (TARGET_64BIT) 6896c87b03e5Sespie call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]); 6897c87b03e5Sespie else 6898c87b03e5Sespie call_insn = gen_sibcall_internal_symref (op, operands[1]); 6899c87b03e5Sespie 6900c87b03e5Sespie call_insn = emit_call_insn (call_insn); 6901c87b03e5Sespie 6902c87b03e5Sespie if (TARGET_64BIT) 6903c87b03e5Sespie use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx); 6904c87b03e5Sespie 6905c87b03e5Sespie /* We don't have to restore the PIC register. */ 6906c87b03e5Sespie if (flag_pic) 6907c87b03e5Sespie use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx); 6908c87b03e5Sespie 6909c87b03e5Sespie DONE; 6910c87b03e5Sespie}") 6911c87b03e5Sespie 6912c87b03e5Sespie(define_insn "sibcall_internal_symref" 6913c87b03e5Sespie [(call (mem:SI (match_operand 0 "call_operand_address" "")) 6914c87b03e5Sespie (match_operand 1 "" "i")) 6915c87b03e5Sespie (clobber (reg:SI 1)) 6916c87b03e5Sespie (use (reg:SI 2)) 6917c87b03e5Sespie (use (const_int 0))] 6918c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" 6919c87b03e5Sespie "* 6920c87b03e5Sespie{ 6921c87b03e5Sespie output_arg_descriptor (insn); 6922c87b03e5Sespie return output_call (insn, operands[0], 1); 6923c87b03e5Sespie}" 6924c87b03e5Sespie [(set_attr "type" "call") 6925c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))]) 6926c87b03e5Sespie 6927c87b03e5Sespie(define_insn "sibcall_internal_symref_64bit" 6928c87b03e5Sespie [(call (mem:SI (match_operand 0 "call_operand_address" "")) 6929c87b03e5Sespie (match_operand 1 "" "i")) 6930c87b03e5Sespie (clobber (reg:DI 1)) 6931c87b03e5Sespie (use (reg:DI 2)) 6932c87b03e5Sespie (use (const_int 0))] 6933c87b03e5Sespie "TARGET_64BIT" 6934c87b03e5Sespie "* 6935c87b03e5Sespie{ 6936c87b03e5Sespie output_arg_descriptor (insn); 6937c87b03e5Sespie return output_call (insn, operands[0], 1); 6938c87b03e5Sespie}" 6939c87b03e5Sespie [(set_attr "type" "call") 6940c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))]) 6941c87b03e5Sespie 6942c87b03e5Sespie(define_expand "sibcall_value" 6943c87b03e5Sespie [(set (match_operand 0 "" "") 6944c87b03e5Sespie (call (match_operand:SI 1 "" "") 6945c87b03e5Sespie (match_operand 2 "" "")))] 6946c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME" 6947c87b03e5Sespie " 6948c87b03e5Sespie{ 6949c87b03e5Sespie rtx op, call_insn; 6950c87b03e5Sespie rtx nb = operands[1]; 6951c87b03e5Sespie 6952c87b03e5Sespie op = XEXP (operands[1], 0); 6953c87b03e5Sespie 6954c87b03e5Sespie if (TARGET_64BIT) 6955c87b03e5Sespie { 6956c87b03e5Sespie if (!virtuals_instantiated) 6957c87b03e5Sespie emit_move_insn (arg_pointer_rtx, 6958c87b03e5Sespie gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, 6959c87b03e5Sespie GEN_INT (64))); 6960c87b03e5Sespie else 6961c87b03e5Sespie { 6962c87b03e5Sespie /* The loop pass can generate new libcalls after the virtual 6963c87b03e5Sespie registers are instantiated when fpregs are disabled because 6964c87b03e5Sespie the only method that we have for doing DImode multiplication 6965c87b03e5Sespie is with a libcall. This could be trouble if we haven't 6966c87b03e5Sespie allocated enough space for the outgoing arguments. */ 6967c87b03e5Sespie if (INTVAL (nb) > current_function_outgoing_args_size) 6968c87b03e5Sespie abort (); 6969c87b03e5Sespie 6970c87b03e5Sespie emit_move_insn (arg_pointer_rtx, 6971c87b03e5Sespie gen_rtx_PLUS (word_mode, stack_pointer_rtx, 6972c87b03e5Sespie GEN_INT (STACK_POINTER_OFFSET + 64))); 6973c87b03e5Sespie } 6974c87b03e5Sespie } 6975c87b03e5Sespie 6976c87b03e5Sespie /* Indirect sibling calls are not allowed. */ 6977c87b03e5Sespie if (TARGET_64BIT) 6978c87b03e5Sespie call_insn 6979c87b03e5Sespie = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]); 6980c87b03e5Sespie else 6981c87b03e5Sespie call_insn 6982c87b03e5Sespie = gen_sibcall_value_internal_symref (operands[0], op, operands[2]); 6983c87b03e5Sespie 6984c87b03e5Sespie call_insn = emit_call_insn (call_insn); 6985c87b03e5Sespie 6986c87b03e5Sespie if (TARGET_64BIT) 6987c87b03e5Sespie use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx); 6988c87b03e5Sespie 6989c87b03e5Sespie /* We don't have to restore the PIC register. */ 6990c87b03e5Sespie if (flag_pic) 6991c87b03e5Sespie use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx); 6992c87b03e5Sespie 6993c87b03e5Sespie DONE; 6994c87b03e5Sespie}") 6995c87b03e5Sespie 6996c87b03e5Sespie(define_insn "sibcall_value_internal_symref" 6997c87b03e5Sespie [(set (match_operand 0 "" "") 6998c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 6999c87b03e5Sespie (match_operand 2 "" "i"))) 7000c87b03e5Sespie (clobber (reg:SI 1)) 7001c87b03e5Sespie (use (reg:SI 2)) 7002c87b03e5Sespie (use (const_int 0))] 7003c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" 7004c87b03e5Sespie "* 7005c87b03e5Sespie{ 7006c87b03e5Sespie output_arg_descriptor (insn); 7007c87b03e5Sespie return output_call (insn, operands[1], 1); 7008c87b03e5Sespie}" 7009c87b03e5Sespie [(set_attr "type" "call") 7010c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))]) 7011c87b03e5Sespie 7012c87b03e5Sespie(define_insn "sibcall_value_internal_symref_64bit" 7013c87b03e5Sespie [(set (match_operand 0 "" "") 7014c87b03e5Sespie (call (mem:SI (match_operand 1 "call_operand_address" "")) 7015c87b03e5Sespie (match_operand 2 "" "i"))) 7016c87b03e5Sespie (clobber (reg:DI 1)) 7017c87b03e5Sespie (use (reg:DI 2)) 7018c87b03e5Sespie (use (const_int 0))] 7019c87b03e5Sespie "TARGET_64BIT" 7020c87b03e5Sespie "* 7021c87b03e5Sespie{ 7022c87b03e5Sespie output_arg_descriptor (insn); 7023c87b03e5Sespie return output_call (insn, operands[1], 1); 7024c87b03e5Sespie}" 7025c87b03e5Sespie [(set_attr "type" "call") 7026c87b03e5Sespie (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))]) 7027c87b03e5Sespie 7028c87b03e5Sespie(define_insn "nop" 7029c87b03e5Sespie [(const_int 0)] 7030c87b03e5Sespie "" 7031c87b03e5Sespie "nop" 7032c87b03e5Sespie [(set_attr "type" "move") 7033c87b03e5Sespie (set_attr "length" "4")]) 7034c87b03e5Sespie 7035c87b03e5Sespie;; These are just placeholders so we know where branch tables 7036c87b03e5Sespie;; begin and end. 7037c87b03e5Sespie(define_insn "begin_brtab" 7038c87b03e5Sespie [(const_int 1)] 7039c87b03e5Sespie "" 7040c87b03e5Sespie "* 7041c87b03e5Sespie{ 7042c87b03e5Sespie /* Only GAS actually supports this pseudo-op. */ 7043c87b03e5Sespie if (TARGET_GAS) 7044c87b03e5Sespie return \".begin_brtab\"; 7045c87b03e5Sespie else 7046c87b03e5Sespie return \"\"; 7047c87b03e5Sespie}" 7048c87b03e5Sespie [(set_attr "type" "move") 7049c87b03e5Sespie (set_attr "length" "0")]) 7050c87b03e5Sespie 7051c87b03e5Sespie(define_insn "end_brtab" 7052c87b03e5Sespie [(const_int 2)] 7053c87b03e5Sespie "" 7054c87b03e5Sespie "* 7055c87b03e5Sespie{ 7056c87b03e5Sespie /* Only GAS actually supports this pseudo-op. */ 7057c87b03e5Sespie if (TARGET_GAS) 7058c87b03e5Sespie return \".end_brtab\"; 7059c87b03e5Sespie else 7060c87b03e5Sespie return \"\"; 7061c87b03e5Sespie}" 7062c87b03e5Sespie [(set_attr "type" "move") 7063c87b03e5Sespie (set_attr "length" "0")]) 7064c87b03e5Sespie 7065c87b03e5Sespie;;; EH does longjmp's from and within the data section. Thus, 7066c87b03e5Sespie;;; an interspace branch is required for the longjmp implementation. 7067c87b03e5Sespie;;; Registers r1 and r2 are used as scratch registers for the jump 7068c87b03e5Sespie;;; when necessary. 7069c87b03e5Sespie(define_expand "interspace_jump" 7070c87b03e5Sespie [(parallel 7071c87b03e5Sespie [(set (pc) (match_operand 0 "pmode_register_operand" "a")) 7072c87b03e5Sespie (clobber (match_dup 1))])] 7073c87b03e5Sespie "" 7074c87b03e5Sespie " 7075c87b03e5Sespie{ 7076c87b03e5Sespie operands[1] = gen_rtx_REG (word_mode, 2); 7077c87b03e5Sespie}") 7078c87b03e5Sespie 7079c87b03e5Sespie(define_insn "" 7080c87b03e5Sespie [(set (pc) (match_operand 0 "pmode_register_operand" "a")) 7081c87b03e5Sespie (clobber (reg:SI 2))] 7082c87b03e5Sespie "TARGET_PA_20 && !TARGET_64BIT" 7083c87b03e5Sespie "bve%* (%0)" 7084c87b03e5Sespie [(set_attr "type" "branch") 7085c87b03e5Sespie (set_attr "length" "4")]) 7086c87b03e5Sespie 7087c87b03e5Sespie(define_insn "" 7088c87b03e5Sespie [(set (pc) (match_operand 0 "pmode_register_operand" "a")) 7089c87b03e5Sespie (clobber (reg:SI 2))] 7090c87b03e5Sespie "TARGET_NO_SPACE_REGS && !TARGET_64BIT" 7091c87b03e5Sespie "be%* 0(%%sr4,%0)" 7092c87b03e5Sespie [(set_attr "type" "branch") 7093c87b03e5Sespie (set_attr "length" "4")]) 7094c87b03e5Sespie 7095c87b03e5Sespie(define_insn "" 7096c87b03e5Sespie [(set (pc) (match_operand 0 "pmode_register_operand" "a")) 7097c87b03e5Sespie (clobber (reg:SI 2))] 7098c87b03e5Sespie "!TARGET_64BIT" 7099c87b03e5Sespie "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)" 7100c87b03e5Sespie [(set_attr "type" "branch") 7101c87b03e5Sespie (set_attr "length" "12")]) 7102c87b03e5Sespie 7103c87b03e5Sespie(define_insn "" 7104c87b03e5Sespie [(set (pc) (match_operand 0 "pmode_register_operand" "a")) 7105c87b03e5Sespie (clobber (reg:DI 2))] 7106c87b03e5Sespie "TARGET_64BIT" 7107c87b03e5Sespie "bve%* (%0)" 7108c87b03e5Sespie [(set_attr "type" "branch") 7109c87b03e5Sespie (set_attr "length" "4")]) 7110c87b03e5Sespie 7111c87b03e5Sespie(define_expand "builtin_longjmp" 7112c87b03e5Sespie [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)] 7113c87b03e5Sespie "" 7114c87b03e5Sespie " 7115c87b03e5Sespie{ 7116c87b03e5Sespie /* The elements of the buffer are, in order: */ 7117c87b03e5Sespie rtx fp = gen_rtx_MEM (Pmode, operands[0]); 7118c87b03e5Sespie rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 7119c87b03e5Sespie POINTER_SIZE / BITS_PER_UNIT)); 7120c87b03e5Sespie rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 7121c87b03e5Sespie (POINTER_SIZE * 2) / BITS_PER_UNIT)); 7122c87b03e5Sespie rtx pv = gen_rtx_REG (Pmode, 1); 7123c87b03e5Sespie 7124c87b03e5Sespie /* This bit is the same as expand_builtin_longjmp. */ 7125c87b03e5Sespie emit_move_insn (hard_frame_pointer_rtx, fp); 7126c87b03e5Sespie emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX); 7127c87b03e5Sespie emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx)); 7128c87b03e5Sespie emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); 7129c87b03e5Sespie 7130c87b03e5Sespie /* Load the label we are jumping through into r1 so that we know 7131c87b03e5Sespie where to look for it when we get back to setjmp's function for 7132c87b03e5Sespie restoring the gp. */ 7133c87b03e5Sespie emit_move_insn (pv, lab); 7134c87b03e5Sespie 7135c87b03e5Sespie /* Prevent the insns above from being scheduled into the delay slot 7136c87b03e5Sespie of the interspace jump because the space register could change. */ 7137c87b03e5Sespie emit_insn (gen_blockage ()); 7138c87b03e5Sespie 7139c87b03e5Sespie emit_jump_insn (gen_interspace_jump (pv)); 7140c87b03e5Sespie emit_barrier (); 7141c87b03e5Sespie DONE; 7142c87b03e5Sespie}") 7143c87b03e5Sespie 7144c87b03e5Sespie;;; Hope this is only within a function... 7145c87b03e5Sespie(define_insn "indirect_jump" 7146c87b03e5Sespie [(set (pc) (match_operand 0 "register_operand" "r"))] 7147c87b03e5Sespie "GET_MODE (operands[0]) == word_mode" 7148c87b03e5Sespie "bv%* %%r0(%0)" 7149c87b03e5Sespie [(set_attr "type" "branch") 7150c87b03e5Sespie (set_attr "length" "4")]) 7151c87b03e5Sespie 7152c87b03e5Sespie(define_expand "extzv" 7153c87b03e5Sespie [(set (match_operand 0 "register_operand" "") 7154c87b03e5Sespie (zero_extract (match_operand 1 "register_operand" "") 7155c87b03e5Sespie (match_operand 2 "uint32_operand" "") 7156c87b03e5Sespie (match_operand 3 "uint32_operand" "")))] 7157c87b03e5Sespie "" 7158c87b03e5Sespie " 7159c87b03e5Sespie{ 7160c87b03e5Sespie /* PA extraction insns don't support zero length bitfields. */ 7161c87b03e5Sespie if (INTVAL (operands[2]) == 0) 7162c87b03e5Sespie FAIL; 7163c87b03e5Sespie 7164c87b03e5Sespie if (TARGET_64BIT) 7165c87b03e5Sespie emit_insn (gen_extzv_64 (operands[0], operands[1], 7166c87b03e5Sespie operands[2], operands[3])); 7167c87b03e5Sespie else 7168c87b03e5Sespie { 7169c87b03e5Sespie if (! uint5_operand (operands[2], SImode) 7170c87b03e5Sespie || ! uint5_operand (operands[3], SImode)) 7171c87b03e5Sespie FAIL; 7172c87b03e5Sespie emit_insn (gen_extzv_32 (operands[0], operands[1], 7173c87b03e5Sespie operands[2], operands[3])); 7174c87b03e5Sespie } 7175c87b03e5Sespie DONE; 7176c87b03e5Sespie}") 7177c87b03e5Sespie 7178c87b03e5Sespie(define_insn "extzv_32" 7179c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 7180c87b03e5Sespie (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 7181c87b03e5Sespie (match_operand:SI 2 "uint5_operand" "") 7182c87b03e5Sespie (match_operand:SI 3 "uint5_operand" "")))] 7183c87b03e5Sespie "" 7184c87b03e5Sespie "{extru|extrw,u} %1,%3+%2-1,%2,%0" 7185c87b03e5Sespie [(set_attr "type" "shift") 7186c87b03e5Sespie (set_attr "length" "4")]) 7187c87b03e5Sespie 7188c87b03e5Sespie(define_insn "" 7189c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 7190c87b03e5Sespie (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 7191c87b03e5Sespie (const_int 1) 7192c87b03e5Sespie (match_operand:SI 2 "register_operand" "q")))] 7193c87b03e5Sespie "" 7194c87b03e5Sespie "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}" 7195c87b03e5Sespie [(set_attr "type" "shift") 7196c87b03e5Sespie (set_attr "length" "4")]) 7197c87b03e5Sespie 7198c87b03e5Sespie(define_insn "extzv_64" 7199c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 7200c87b03e5Sespie (zero_extract:DI (match_operand:DI 1 "register_operand" "r") 7201c87b03e5Sespie (match_operand:DI 2 "uint32_operand" "") 7202c87b03e5Sespie (match_operand:DI 3 "uint32_operand" "")))] 7203c87b03e5Sespie "TARGET_64BIT" 7204c87b03e5Sespie "extrd,u %1,%3+%2-1,%2,%0" 7205c87b03e5Sespie [(set_attr "type" "shift") 7206c87b03e5Sespie (set_attr "length" "4")]) 7207c87b03e5Sespie 7208c87b03e5Sespie(define_insn "" 7209c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 7210c87b03e5Sespie (zero_extract:DI (match_operand:DI 1 "register_operand" "r") 7211c87b03e5Sespie (const_int 1) 7212c87b03e5Sespie (match_operand:DI 2 "register_operand" "q")))] 7213c87b03e5Sespie "TARGET_64BIT" 7214c87b03e5Sespie "extrd,u %1,%%sar,1,%0" 7215c87b03e5Sespie [(set_attr "type" "shift") 7216c87b03e5Sespie (set_attr "length" "4")]) 7217c87b03e5Sespie 7218c87b03e5Sespie(define_expand "extv" 7219c87b03e5Sespie [(set (match_operand 0 "register_operand" "") 7220c87b03e5Sespie (sign_extract (match_operand 1 "register_operand" "") 7221c87b03e5Sespie (match_operand 2 "uint32_operand" "") 7222c87b03e5Sespie (match_operand 3 "uint32_operand" "")))] 7223c87b03e5Sespie "" 7224c87b03e5Sespie " 7225c87b03e5Sespie{ 7226c87b03e5Sespie /* PA extraction insns don't support zero length bitfields. */ 7227c87b03e5Sespie if (INTVAL (operands[2]) == 0) 7228c87b03e5Sespie FAIL; 7229c87b03e5Sespie 7230c87b03e5Sespie if (TARGET_64BIT) 7231c87b03e5Sespie emit_insn (gen_extv_64 (operands[0], operands[1], 7232c87b03e5Sespie operands[2], operands[3])); 7233c87b03e5Sespie else 7234c87b03e5Sespie { 7235c87b03e5Sespie if (! uint5_operand (operands[2], SImode) 7236c87b03e5Sespie || ! uint5_operand (operands[3], SImode)) 7237c87b03e5Sespie FAIL; 7238c87b03e5Sespie emit_insn (gen_extv_32 (operands[0], operands[1], 7239c87b03e5Sespie operands[2], operands[3])); 7240c87b03e5Sespie } 7241c87b03e5Sespie DONE; 7242c87b03e5Sespie}") 7243c87b03e5Sespie 7244c87b03e5Sespie(define_insn "extv_32" 7245c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 7246c87b03e5Sespie (sign_extract:SI (match_operand:SI 1 "register_operand" "r") 7247c87b03e5Sespie (match_operand:SI 2 "uint5_operand" "") 7248c87b03e5Sespie (match_operand:SI 3 "uint5_operand" "")))] 7249c87b03e5Sespie "" 7250c87b03e5Sespie "{extrs|extrw,s} %1,%3+%2-1,%2,%0" 7251c87b03e5Sespie [(set_attr "type" "shift") 7252c87b03e5Sespie (set_attr "length" "4")]) 7253c87b03e5Sespie 7254c87b03e5Sespie(define_insn "" 7255c87b03e5Sespie [(set (match_operand:SI 0 "register_operand" "=r") 7256c87b03e5Sespie (sign_extract:SI (match_operand:SI 1 "register_operand" "r") 7257c87b03e5Sespie (const_int 1) 7258c87b03e5Sespie (match_operand:SI 2 "register_operand" "q")))] 7259c87b03e5Sespie "!TARGET_64BIT" 7260c87b03e5Sespie "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}" 7261c87b03e5Sespie [(set_attr "type" "shift") 7262c87b03e5Sespie (set_attr "length" "4")]) 7263c87b03e5Sespie 7264c87b03e5Sespie(define_insn "extv_64" 7265c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 7266c87b03e5Sespie (sign_extract:DI (match_operand:DI 1 "register_operand" "r") 7267c87b03e5Sespie (match_operand:DI 2 "uint32_operand" "") 7268c87b03e5Sespie (match_operand:DI 3 "uint32_operand" "")))] 7269c87b03e5Sespie "TARGET_64BIT" 7270c87b03e5Sespie "extrd,s %1,%3+%2-1,%2,%0" 7271c87b03e5Sespie [(set_attr "type" "shift") 7272c87b03e5Sespie (set_attr "length" "4")]) 7273c87b03e5Sespie 7274c87b03e5Sespie(define_insn "" 7275c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 7276c87b03e5Sespie (sign_extract:DI (match_operand:DI 1 "register_operand" "r") 7277c87b03e5Sespie (const_int 1) 7278c87b03e5Sespie (match_operand:DI 2 "register_operand" "q")))] 7279c87b03e5Sespie "TARGET_64BIT" 7280c87b03e5Sespie "extrd,s %1,%%sar,1,%0" 7281c87b03e5Sespie [(set_attr "type" "shift") 7282c87b03e5Sespie (set_attr "length" "4")]) 7283c87b03e5Sespie 7284c87b03e5Sespie;; Only specify the mode operands 0, the rest are assumed to be word_mode. 7285c87b03e5Sespie(define_expand "insv" 7286c87b03e5Sespie [(set (zero_extract (match_operand 0 "register_operand" "") 7287c87b03e5Sespie (match_operand 1 "uint32_operand" "") 7288c87b03e5Sespie (match_operand 2 "uint32_operand" "")) 7289c87b03e5Sespie (match_operand 3 "arith5_operand" ""))] 7290c87b03e5Sespie "" 7291c87b03e5Sespie " 7292c87b03e5Sespie{ 7293c87b03e5Sespie if (TARGET_64BIT) 7294c87b03e5Sespie emit_insn (gen_insv_64 (operands[0], operands[1], 7295c87b03e5Sespie operands[2], operands[3])); 7296c87b03e5Sespie else 7297c87b03e5Sespie { 7298c87b03e5Sespie if (! uint5_operand (operands[2], SImode) 7299c87b03e5Sespie || ! uint5_operand (operands[3], SImode)) 7300c87b03e5Sespie FAIL; 7301c87b03e5Sespie emit_insn (gen_insv_32 (operands[0], operands[1], 7302c87b03e5Sespie operands[2], operands[3])); 7303c87b03e5Sespie } 7304c87b03e5Sespie DONE; 7305c87b03e5Sespie}") 7306c87b03e5Sespie 7307c87b03e5Sespie(define_insn "insv_32" 7308c87b03e5Sespie [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r") 7309c87b03e5Sespie (match_operand:SI 1 "uint5_operand" "") 7310c87b03e5Sespie (match_operand:SI 2 "uint5_operand" "")) 7311c87b03e5Sespie (match_operand:SI 3 "arith5_operand" "r,L"))] 7312c87b03e5Sespie "" 7313c87b03e5Sespie "@ 7314c87b03e5Sespie {dep|depw} %3,%2+%1-1,%1,%0 7315c87b03e5Sespie {depi|depwi} %3,%2+%1-1,%1,%0" 7316c87b03e5Sespie [(set_attr "type" "shift,shift") 7317c87b03e5Sespie (set_attr "length" "4,4")]) 7318c87b03e5Sespie 7319c87b03e5Sespie;; Optimize insertion of const_int values of type 1...1xxxx. 7320c87b03e5Sespie(define_insn "" 7321c87b03e5Sespie [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 7322c87b03e5Sespie (match_operand:SI 1 "uint5_operand" "") 7323c87b03e5Sespie (match_operand:SI 2 "uint5_operand" "")) 7324c87b03e5Sespie (match_operand:SI 3 "const_int_operand" ""))] 7325c87b03e5Sespie "(INTVAL (operands[3]) & 0x10) != 0 && 7326c87b03e5Sespie (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0" 7327c87b03e5Sespie "* 7328c87b03e5Sespie{ 7329c87b03e5Sespie operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10); 7330c87b03e5Sespie return \"{depi|depwi} %3,%2+%1-1,%1,%0\"; 7331c87b03e5Sespie}" 7332c87b03e5Sespie [(set_attr "type" "shift") 7333c87b03e5Sespie (set_attr "length" "4")]) 7334c87b03e5Sespie 7335c87b03e5Sespie(define_insn "insv_64" 7336c87b03e5Sespie [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r") 7337c87b03e5Sespie (match_operand:DI 1 "uint32_operand" "") 7338c87b03e5Sespie (match_operand:DI 2 "uint32_operand" "")) 7339c87b03e5Sespie (match_operand:DI 3 "arith32_operand" "r,L"))] 7340c87b03e5Sespie "TARGET_64BIT" 7341c87b03e5Sespie "@ 7342c87b03e5Sespie depd %3,%2+%1-1,%1,%0 7343c87b03e5Sespie depdi %3,%2+%1-1,%1,%0" 7344c87b03e5Sespie [(set_attr "type" "shift,shift") 7345c87b03e5Sespie (set_attr "length" "4,4")]) 7346c87b03e5Sespie 7347c87b03e5Sespie;; Optimize insertion of const_int values of type 1...1xxxx. 7348c87b03e5Sespie(define_insn "" 7349c87b03e5Sespie [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r") 7350c87b03e5Sespie (match_operand:DI 1 "uint32_operand" "") 7351c87b03e5Sespie (match_operand:DI 2 "uint32_operand" "")) 7352c87b03e5Sespie (match_operand:DI 3 "const_int_operand" ""))] 7353c87b03e5Sespie "(INTVAL (operands[3]) & 0x10) != 0 7354c87b03e5Sespie && TARGET_64BIT 7355c87b03e5Sespie && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0" 7356c87b03e5Sespie "* 7357c87b03e5Sespie{ 7358c87b03e5Sespie operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10); 7359c87b03e5Sespie return \"depdi %3,%2+%1-1,%1,%0\"; 7360c87b03e5Sespie}" 7361c87b03e5Sespie [(set_attr "type" "shift") 7362c87b03e5Sespie (set_attr "length" "4")]) 7363c87b03e5Sespie 7364c87b03e5Sespie(define_insn "" 7365c87b03e5Sespie [(set (match_operand:DI 0 "register_operand" "=r") 7366c87b03e5Sespie (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) 7367c87b03e5Sespie (const_int 32)))] 7368c87b03e5Sespie "TARGET_64BIT" 7369c87b03e5Sespie "depd,z %1,31,32,%0" 7370c87b03e5Sespie [(set_attr "type" "shift") 7371c87b03e5Sespie (set_attr "length" "4")]) 7372c87b03e5Sespie 7373c87b03e5Sespie;; This insn is used for some loop tests, typically loops reversed when 7374c87b03e5Sespie;; strength reduction is used. It is actually created when the instruction 7375c87b03e5Sespie;; combination phase combines the special loop test. Since this insn 7376c87b03e5Sespie;; is both a jump insn and has an output, it must deal with its own 7377c87b03e5Sespie;; reloads, hence the `m' constraints. The `!' constraints direct reload 7378c87b03e5Sespie;; to not choose the register alternatives in the event a reload is needed. 7379c87b03e5Sespie(define_insn "decrement_and_branch_until_zero" 7380c87b03e5Sespie [(set (pc) 7381c87b03e5Sespie (if_then_else 7382c87b03e5Sespie (match_operator 2 "comparison_operator" 7383c87b03e5Sespie [(plus:SI 7384c87b03e5Sespie (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m") 7385c87b03e5Sespie (match_operand:SI 1 "int5_operand" "L,L,L")) 7386c87b03e5Sespie (const_int 0)]) 7387c87b03e5Sespie (label_ref (match_operand 3 "" "")) 7388c87b03e5Sespie (pc))) 7389c87b03e5Sespie (set (match_dup 0) 7390c87b03e5Sespie (plus:SI (match_dup 0) (match_dup 1))) 7391c87b03e5Sespie (clobber (match_scratch:SI 4 "=X,r,r"))] 7392c87b03e5Sespie "" 7393c87b03e5Sespie "* return output_dbra (operands, insn, which_alternative); " 7394c87b03e5Sespie;; Do not expect to understand this the first time through. 7395c87b03e5Sespie[(set_attr "type" "cbranch,multi,multi") 7396c87b03e5Sespie (set (attr "length") 7397c87b03e5Sespie (if_then_else (eq_attr "alternative" "0") 7398c87b03e5Sespie;; Loop counter in register case 7399c87b03e5Sespie;; Short branch has length of 4 7400c87b03e5Sespie;; Long branch has length of 8 7401c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8)))) 7402c87b03e5Sespie (const_int 8184)) 7403c87b03e5Sespie (const_int 4) 7404c87b03e5Sespie (const_int 8)) 7405c87b03e5Sespie 7406c87b03e5Sespie;; Loop counter in FP reg case. 7407c87b03e5Sespie;; Extra goo to deal with additional reload insns. 7408c87b03e5Sespie (if_then_else (eq_attr "alternative" "1") 7409c87b03e5Sespie (if_then_else (lt (match_dup 3) (pc)) 7410c87b03e5Sespie (if_then_else 7411c87b03e5Sespie (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24)))) 7412c87b03e5Sespie (const_int 8184)) 7413c87b03e5Sespie (const_int 24) 7414c87b03e5Sespie (const_int 28)) 7415c87b03e5Sespie (if_then_else 7416c87b03e5Sespie (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8)))) 7417c87b03e5Sespie (const_int 8184)) 7418c87b03e5Sespie (const_int 24) 7419c87b03e5Sespie (const_int 28))) 7420c87b03e5Sespie;; Loop counter in memory case. 7421c87b03e5Sespie;; Extra goo to deal with additional reload insns. 7422c87b03e5Sespie (if_then_else (lt (match_dup 3) (pc)) 7423c87b03e5Sespie (if_then_else 7424c87b03e5Sespie (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12)))) 7425c87b03e5Sespie (const_int 8184)) 7426c87b03e5Sespie (const_int 12) 7427c87b03e5Sespie (const_int 16)) 7428c87b03e5Sespie (if_then_else 7429c87b03e5Sespie (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8)))) 7430c87b03e5Sespie (const_int 8184)) 7431c87b03e5Sespie (const_int 12) 7432c87b03e5Sespie (const_int 16))))))]) 7433c87b03e5Sespie 7434c87b03e5Sespie(define_insn "" 7435c87b03e5Sespie [(set (pc) 7436c87b03e5Sespie (if_then_else 7437c87b03e5Sespie (match_operator 2 "movb_comparison_operator" 7438c87b03e5Sespie [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)]) 7439c87b03e5Sespie (label_ref (match_operand 3 "" "")) 7440c87b03e5Sespie (pc))) 7441c87b03e5Sespie (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q") 7442c87b03e5Sespie (match_dup 1))] 7443c87b03e5Sespie "" 7444c87b03e5Sespie"* return output_movb (operands, insn, which_alternative, 0); " 7445c87b03e5Sespie;; Do not expect to understand this the first time through. 7446c87b03e5Sespie[(set_attr "type" "cbranch,multi,multi,multi") 7447c87b03e5Sespie (set (attr "length") 7448c87b03e5Sespie (if_then_else (eq_attr "alternative" "0") 7449c87b03e5Sespie;; Loop counter in register case 7450c87b03e5Sespie;; Short branch has length of 4 7451c87b03e5Sespie;; Long branch has length of 8 7452c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8)))) 7453c87b03e5Sespie (const_int 8184)) 7454c87b03e5Sespie (const_int 4) 7455c87b03e5Sespie (const_int 8)) 7456c87b03e5Sespie 7457c87b03e5Sespie;; Loop counter in FP reg case. 7458c87b03e5Sespie;; Extra goo to deal with additional reload insns. 7459c87b03e5Sespie (if_then_else (eq_attr "alternative" "1") 7460c87b03e5Sespie (if_then_else (lt (match_dup 3) (pc)) 7461c87b03e5Sespie (if_then_else 7462c87b03e5Sespie (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12)))) 7463c87b03e5Sespie (const_int 8184)) 7464c87b03e5Sespie (const_int 12) 7465c87b03e5Sespie (const_int 16)) 7466c87b03e5Sespie (if_then_else 7467c87b03e5Sespie (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8)))) 7468c87b03e5Sespie (const_int 8184)) 7469c87b03e5Sespie (const_int 12) 7470c87b03e5Sespie (const_int 16))) 7471c87b03e5Sespie;; Loop counter in memory or sar case. 7472c87b03e5Sespie;; Extra goo to deal with additional reload insns. 7473c87b03e5Sespie (if_then_else 7474c87b03e5Sespie (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8)))) 7475c87b03e5Sespie (const_int 8184)) 7476c87b03e5Sespie (const_int 8) 7477c87b03e5Sespie (const_int 12)))))]) 7478c87b03e5Sespie 7479c87b03e5Sespie;; Handle negated branch. 7480c87b03e5Sespie(define_insn "" 7481c87b03e5Sespie [(set (pc) 7482c87b03e5Sespie (if_then_else 7483c87b03e5Sespie (match_operator 2 "movb_comparison_operator" 7484c87b03e5Sespie [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)]) 7485c87b03e5Sespie (pc) 7486c87b03e5Sespie (label_ref (match_operand 3 "" "")))) 7487c87b03e5Sespie (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q") 7488c87b03e5Sespie (match_dup 1))] 7489c87b03e5Sespie "" 7490c87b03e5Sespie"* return output_movb (operands, insn, which_alternative, 1); " 7491c87b03e5Sespie;; Do not expect to understand this the first time through. 7492c87b03e5Sespie[(set_attr "type" "cbranch,multi,multi,multi") 7493c87b03e5Sespie (set (attr "length") 7494c87b03e5Sespie (if_then_else (eq_attr "alternative" "0") 7495c87b03e5Sespie;; Loop counter in register case 7496c87b03e5Sespie;; Short branch has length of 4 7497c87b03e5Sespie;; Long branch has length of 8 7498c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8)))) 7499c87b03e5Sespie (const_int 8184)) 7500c87b03e5Sespie (const_int 4) 7501c87b03e5Sespie (const_int 8)) 7502c87b03e5Sespie 7503c87b03e5Sespie;; Loop counter in FP reg case. 7504c87b03e5Sespie;; Extra goo to deal with additional reload insns. 7505c87b03e5Sespie (if_then_else (eq_attr "alternative" "1") 7506c87b03e5Sespie (if_then_else (lt (match_dup 3) (pc)) 7507c87b03e5Sespie (if_then_else 7508c87b03e5Sespie (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12)))) 7509c87b03e5Sespie (const_int 8184)) 7510c87b03e5Sespie (const_int 12) 7511c87b03e5Sespie (const_int 16)) 7512c87b03e5Sespie (if_then_else 7513c87b03e5Sespie (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8)))) 7514c87b03e5Sespie (const_int 8184)) 7515c87b03e5Sespie (const_int 12) 7516c87b03e5Sespie (const_int 16))) 7517c87b03e5Sespie;; Loop counter in memory or SAR case. 7518c87b03e5Sespie;; Extra goo to deal with additional reload insns. 7519c87b03e5Sespie (if_then_else 7520c87b03e5Sespie (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8)))) 7521c87b03e5Sespie (const_int 8184)) 7522c87b03e5Sespie (const_int 8) 7523c87b03e5Sespie (const_int 12)))))]) 7524c87b03e5Sespie 7525c87b03e5Sespie(define_insn "" 7526c87b03e5Sespie [(set (pc) (label_ref (match_operand 3 "" "" ))) 7527c87b03e5Sespie (set (match_operand:SI 0 "ireg_operand" "=r") 7528c87b03e5Sespie (plus:SI (match_operand:SI 1 "ireg_operand" "r") 7529c87b03e5Sespie (match_operand:SI 2 "ireg_or_int5_operand" "rL")))] 7530c87b03e5Sespie "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]" 7531c87b03e5Sespie "* 7532c87b03e5Sespie{ 7533c87b03e5Sespie return output_parallel_addb (operands, get_attr_length (insn)); 7534c87b03e5Sespie}" 7535c87b03e5Sespie [(set_attr "type" "parallel_branch") 7536c87b03e5Sespie (set (attr "length") 7537c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8)))) 7538c87b03e5Sespie (const_int 8184)) 7539c87b03e5Sespie (const_int 4) 7540c87b03e5Sespie (const_int 8)))]) 7541c87b03e5Sespie 7542c87b03e5Sespie(define_insn "" 7543c87b03e5Sespie [(set (pc) (label_ref (match_operand 2 "" "" ))) 7544c87b03e5Sespie (set (match_operand:SF 0 "ireg_operand" "=r") 7545c87b03e5Sespie (match_operand:SF 1 "ireg_or_int5_operand" "rL"))] 7546c87b03e5Sespie "reload_completed" 7547c87b03e5Sespie "* 7548c87b03e5Sespie{ 7549c87b03e5Sespie return output_parallel_movb (operands, get_attr_length (insn)); 7550c87b03e5Sespie}" 7551c87b03e5Sespie [(set_attr "type" "parallel_branch") 7552c87b03e5Sespie (set (attr "length") 7553c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 7554c87b03e5Sespie (const_int 8184)) 7555c87b03e5Sespie (const_int 4) 7556c87b03e5Sespie (const_int 8)))]) 7557c87b03e5Sespie 7558c87b03e5Sespie(define_insn "" 7559c87b03e5Sespie [(set (pc) (label_ref (match_operand 2 "" "" ))) 7560c87b03e5Sespie (set (match_operand:SI 0 "ireg_operand" "=r") 7561c87b03e5Sespie (match_operand:SI 1 "ireg_or_int5_operand" "rL"))] 7562c87b03e5Sespie "reload_completed" 7563c87b03e5Sespie "* 7564c87b03e5Sespie{ 7565c87b03e5Sespie return output_parallel_movb (operands, get_attr_length (insn)); 7566c87b03e5Sespie}" 7567c87b03e5Sespie [(set_attr "type" "parallel_branch") 7568c87b03e5Sespie (set (attr "length") 7569c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 7570c87b03e5Sespie (const_int 8184)) 7571c87b03e5Sespie (const_int 4) 7572c87b03e5Sespie (const_int 8)))]) 7573c87b03e5Sespie 7574c87b03e5Sespie(define_insn "" 7575c87b03e5Sespie [(set (pc) (label_ref (match_operand 2 "" "" ))) 7576c87b03e5Sespie (set (match_operand:HI 0 "ireg_operand" "=r") 7577c87b03e5Sespie (match_operand:HI 1 "ireg_or_int5_operand" "rL"))] 7578c87b03e5Sespie "reload_completed" 7579c87b03e5Sespie "* 7580c87b03e5Sespie{ 7581c87b03e5Sespie return output_parallel_movb (operands, get_attr_length (insn)); 7582c87b03e5Sespie}" 7583c87b03e5Sespie [(set_attr "type" "parallel_branch") 7584c87b03e5Sespie (set (attr "length") 7585c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 7586c87b03e5Sespie (const_int 8184)) 7587c87b03e5Sespie (const_int 4) 7588c87b03e5Sespie (const_int 8)))]) 7589c87b03e5Sespie 7590c87b03e5Sespie(define_insn "" 7591c87b03e5Sespie [(set (pc) (label_ref (match_operand 2 "" "" ))) 7592c87b03e5Sespie (set (match_operand:QI 0 "ireg_operand" "=r") 7593c87b03e5Sespie (match_operand:QI 1 "ireg_or_int5_operand" "rL"))] 7594c87b03e5Sespie "reload_completed" 7595c87b03e5Sespie "* 7596c87b03e5Sespie{ 7597c87b03e5Sespie return output_parallel_movb (operands, get_attr_length (insn)); 7598c87b03e5Sespie}" 7599c87b03e5Sespie [(set_attr "type" "parallel_branch") 7600c87b03e5Sespie (set (attr "length") 7601c87b03e5Sespie (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8)))) 7602c87b03e5Sespie (const_int 8184)) 7603c87b03e5Sespie (const_int 4) 7604c87b03e5Sespie (const_int 8)))]) 7605c87b03e5Sespie 7606c87b03e5Sespie(define_insn "" 7607c87b03e5Sespie [(set (match_operand 0 "register_operand" "=f") 7608c87b03e5Sespie (mult (match_operand 1 "register_operand" "f") 7609c87b03e5Sespie (match_operand 2 "register_operand" "f"))) 7610c87b03e5Sespie (set (match_operand 3 "register_operand" "+f") 7611c87b03e5Sespie (plus (match_operand 4 "register_operand" "f") 7612c87b03e5Sespie (match_operand 5 "register_operand" "f")))] 7613c87b03e5Sespie "TARGET_PA_11 && ! TARGET_SOFT_FLOAT 7614c87b03e5Sespie && reload_completed && fmpyaddoperands (operands)" 7615c87b03e5Sespie "* 7616c87b03e5Sespie{ 7617c87b03e5Sespie if (GET_MODE (operands[0]) == DFmode) 7618c87b03e5Sespie { 7619c87b03e5Sespie if (rtx_equal_p (operands[3], operands[5])) 7620c87b03e5Sespie return \"fmpyadd,dbl %1,%2,%0,%4,%3\"; 7621c87b03e5Sespie else 7622c87b03e5Sespie return \"fmpyadd,dbl %1,%2,%0,%5,%3\"; 7623c87b03e5Sespie } 7624c87b03e5Sespie else 7625c87b03e5Sespie { 7626c87b03e5Sespie if (rtx_equal_p (operands[3], operands[5])) 7627c87b03e5Sespie return \"fmpyadd,sgl %1,%2,%0,%4,%3\"; 7628c87b03e5Sespie else 7629c87b03e5Sespie return \"fmpyadd,sgl %1,%2,%0,%5,%3\"; 7630c87b03e5Sespie } 7631c87b03e5Sespie}" 7632c87b03e5Sespie [(set_attr "type" "fpalu") 7633c87b03e5Sespie (set_attr "length" "4")]) 7634c87b03e5Sespie 7635c87b03e5Sespie(define_insn "" 7636c87b03e5Sespie [(set (match_operand 3 "register_operand" "+f") 7637c87b03e5Sespie (plus (match_operand 4 "register_operand" "f") 7638c87b03e5Sespie (match_operand 5 "register_operand" "f"))) 7639c87b03e5Sespie (set (match_operand 0 "register_operand" "=f") 7640c87b03e5Sespie (mult (match_operand 1 "register_operand" "f") 7641c87b03e5Sespie (match_operand 2 "register_operand" "f")))] 7642c87b03e5Sespie "TARGET_PA_11 && ! TARGET_SOFT_FLOAT 7643c87b03e5Sespie && reload_completed && fmpyaddoperands (operands)" 7644c87b03e5Sespie "* 7645c87b03e5Sespie{ 7646c87b03e5Sespie if (GET_MODE (operands[0]) == DFmode) 7647c87b03e5Sespie { 7648c87b03e5Sespie if (rtx_equal_p (operands[3], operands[5])) 7649c87b03e5Sespie return \"fmpyadd,dbl %1,%2,%0,%4,%3\"; 7650c87b03e5Sespie else 7651c87b03e5Sespie return \"fmpyadd,dbl %1,%2,%0,%5,%3\"; 7652c87b03e5Sespie } 7653c87b03e5Sespie else 7654c87b03e5Sespie { 7655c87b03e5Sespie if (rtx_equal_p (operands[3], operands[5])) 7656c87b03e5Sespie return \"fmpyadd,sgl %1,%2,%0,%4,%3\"; 7657c87b03e5Sespie else 7658c87b03e5Sespie return \"fmpyadd,sgl %1,%2,%0,%5,%3\"; 7659c87b03e5Sespie } 7660c87b03e5Sespie}" 7661c87b03e5Sespie [(set_attr "type" "fpalu") 7662c87b03e5Sespie (set_attr "length" "4")]) 7663c87b03e5Sespie 7664c87b03e5Sespie(define_insn "" 7665c87b03e5Sespie [(set (match_operand 0 "register_operand" "=f") 7666c87b03e5Sespie (mult (match_operand 1 "register_operand" "f") 7667c87b03e5Sespie (match_operand 2 "register_operand" "f"))) 7668c87b03e5Sespie (set (match_operand 3 "register_operand" "+f") 7669c87b03e5Sespie (minus (match_operand 4 "register_operand" "f") 7670c87b03e5Sespie (match_operand 5 "register_operand" "f")))] 7671c87b03e5Sespie "TARGET_PA_11 && ! TARGET_SOFT_FLOAT 7672c87b03e5Sespie && reload_completed && fmpysuboperands (operands)" 7673c87b03e5Sespie "* 7674c87b03e5Sespie{ 7675c87b03e5Sespie if (GET_MODE (operands[0]) == DFmode) 7676c87b03e5Sespie return \"fmpysub,dbl %1,%2,%0,%5,%3\"; 7677c87b03e5Sespie else 7678c87b03e5Sespie return \"fmpysub,sgl %1,%2,%0,%5,%3\"; 7679c87b03e5Sespie}" 7680c87b03e5Sespie [(set_attr "type" "fpalu") 7681c87b03e5Sespie (set_attr "length" "4")]) 7682c87b03e5Sespie 7683c87b03e5Sespie(define_insn "" 7684c87b03e5Sespie [(set (match_operand 3 "register_operand" "+f") 7685c87b03e5Sespie (minus (match_operand 4 "register_operand" "f") 7686c87b03e5Sespie (match_operand 5 "register_operand" "f"))) 7687c87b03e5Sespie (set (match_operand 0 "register_operand" "=f") 7688c87b03e5Sespie (mult (match_operand 1 "register_operand" "f") 7689c87b03e5Sespie (match_operand 2 "register_operand" "f")))] 7690c87b03e5Sespie "TARGET_PA_11 && ! TARGET_SOFT_FLOAT 7691c87b03e5Sespie && reload_completed && fmpysuboperands (operands)" 7692c87b03e5Sespie "* 7693c87b03e5Sespie{ 7694c87b03e5Sespie if (GET_MODE (operands[0]) == DFmode) 7695c87b03e5Sespie return \"fmpysub,dbl %1,%2,%0,%5,%3\"; 7696c87b03e5Sespie else 7697c87b03e5Sespie return \"fmpysub,sgl %1,%2,%0,%5,%3\"; 7698c87b03e5Sespie}" 7699c87b03e5Sespie [(set_attr "type" "fpalu") 7700c87b03e5Sespie (set_attr "length" "4")]) 7701c87b03e5Sespie 7702c87b03e5Sespie;; Clean up turds left by reload. 7703c87b03e5Sespie(define_peephole 7704c87b03e5Sespie [(set (match_operand 0 "reg_or_nonsymb_mem_operand" "") 7705c87b03e5Sespie (match_operand 1 "register_operand" "fr")) 7706c87b03e5Sespie (set (match_operand 2 "register_operand" "fr") 7707c87b03e5Sespie (match_dup 0))] 7708c87b03e5Sespie "! TARGET_SOFT_FLOAT 7709c87b03e5Sespie && GET_CODE (operands[0]) == MEM 7710c87b03e5Sespie && ! MEM_VOLATILE_P (operands[0]) 7711c87b03e5Sespie && GET_MODE (operands[0]) == GET_MODE (operands[1]) 7712c87b03e5Sespie && GET_MODE (operands[0]) == GET_MODE (operands[2]) 7713c87b03e5Sespie && GET_MODE (operands[0]) == DFmode 7714c87b03e5Sespie && GET_CODE (operands[1]) == REG 7715c87b03e5Sespie && GET_CODE (operands[2]) == REG 7716c87b03e5Sespie && ! side_effects_p (XEXP (operands[0], 0)) 7717c87b03e5Sespie && REGNO_REG_CLASS (REGNO (operands[1])) 7718c87b03e5Sespie == REGNO_REG_CLASS (REGNO (operands[2]))" 7719c87b03e5Sespie "* 7720c87b03e5Sespie{ 7721c87b03e5Sespie rtx xoperands[2]; 7722c87b03e5Sespie 7723c87b03e5Sespie if (FP_REG_P (operands[1])) 7724c87b03e5Sespie output_asm_insn (output_fp_move_double (operands), operands); 7725c87b03e5Sespie else 7726c87b03e5Sespie output_asm_insn (output_move_double (operands), operands); 7727c87b03e5Sespie 7728c87b03e5Sespie if (rtx_equal_p (operands[1], operands[2])) 7729c87b03e5Sespie return \"\"; 7730c87b03e5Sespie 7731c87b03e5Sespie xoperands[0] = operands[2]; 7732c87b03e5Sespie xoperands[1] = operands[1]; 7733c87b03e5Sespie 7734c87b03e5Sespie if (FP_REG_P (xoperands[1])) 7735c87b03e5Sespie output_asm_insn (output_fp_move_double (xoperands), xoperands); 7736c87b03e5Sespie else 7737c87b03e5Sespie output_asm_insn (output_move_double (xoperands), xoperands); 7738c87b03e5Sespie 7739c87b03e5Sespie return \"\"; 7740c87b03e5Sespie}") 7741c87b03e5Sespie 7742c87b03e5Sespie(define_peephole 7743c87b03e5Sespie [(set (match_operand 0 "register_operand" "fr") 7744c87b03e5Sespie (match_operand 1 "reg_or_nonsymb_mem_operand" "")) 7745c87b03e5Sespie (set (match_operand 2 "register_operand" "fr") 7746c87b03e5Sespie (match_dup 1))] 7747c87b03e5Sespie "! TARGET_SOFT_FLOAT 7748c87b03e5Sespie && GET_CODE (operands[1]) == MEM 7749c87b03e5Sespie && ! MEM_VOLATILE_P (operands[1]) 7750c87b03e5Sespie && GET_MODE (operands[0]) == GET_MODE (operands[1]) 7751c87b03e5Sespie && GET_MODE (operands[0]) == GET_MODE (operands[2]) 7752c87b03e5Sespie && GET_MODE (operands[0]) == DFmode 7753c87b03e5Sespie && GET_CODE (operands[0]) == REG 7754c87b03e5Sespie && GET_CODE (operands[2]) == REG 7755c87b03e5Sespie && ! side_effects_p (XEXP (operands[1], 0)) 7756c87b03e5Sespie && REGNO_REG_CLASS (REGNO (operands[0])) 7757c87b03e5Sespie == REGNO_REG_CLASS (REGNO (operands[2]))" 7758c87b03e5Sespie "* 7759c87b03e5Sespie{ 7760c87b03e5Sespie rtx xoperands[2]; 7761c87b03e5Sespie 7762c87b03e5Sespie if (FP_REG_P (operands[0])) 7763c87b03e5Sespie output_asm_insn (output_fp_move_double (operands), operands); 7764c87b03e5Sespie else 7765c87b03e5Sespie output_asm_insn (output_move_double (operands), operands); 7766c87b03e5Sespie 7767c87b03e5Sespie xoperands[0] = operands[2]; 7768c87b03e5Sespie xoperands[1] = operands[0]; 7769c87b03e5Sespie 7770c87b03e5Sespie if (FP_REG_P (xoperands[1])) 7771c87b03e5Sespie output_asm_insn (output_fp_move_double (xoperands), xoperands); 7772c87b03e5Sespie else 7773c87b03e5Sespie output_asm_insn (output_move_double (xoperands), xoperands); 7774c87b03e5Sespie 7775c87b03e5Sespie return \"\"; 7776c87b03e5Sespie}") 7777c87b03e5Sespie 77784e43c760Sespie;; Flush the I and D cache lines from the start address (operand0) 77794e43c760Sespie;; to the end address (operand1). No lines are flushed if the end 77804e43c760Sespie;; address is less than the start address (unsigned). 77814e43c760Sespie;; 77824e43c760Sespie;; Because the range of memory flushed is variable and the size of 77834e43c760Sespie;; a MEM can only be a CONST_INT, the patterns specify that they 77844e43c760Sespie;; perform an unspecified volatile operation on all memory. 77854e43c760Sespie;; 77864e43c760Sespie;; The address range for an icache flush must lie within a single 77874e43c760Sespie;; space on targets with non-equivalent space registers. 77884e43c760Sespie;; 7789c87b03e5Sespie;; This is used by the trampoline code for nested functions. 77904e43c760Sespie;; 77914e43c760Sespie;; Operand 0 contains the start address. 77924e43c760Sespie;; Operand 1 contains the end address. 77934e43c760Sespie;; Operand 2 contains the line length to use. 77944e43c760Sespie;; Operands 3 and 4 (icacheflush) are clobbered scratch registers. 7795c87b03e5Sespie(define_insn "dcacheflush" 77964e43c760Sespie [(const_int 1) 77974e43c760Sespie (unspec_volatile [(mem:BLK (scratch))] 0) 77984e43c760Sespie (use (match_operand 0 "pmode_register_operand" "r")) 77994e43c760Sespie (use (match_operand 1 "pmode_register_operand" "r")) 78004e43c760Sespie (use (match_operand 2 "pmode_register_operand" "r")) 78014e43c760Sespie (clobber (match_scratch 3 "=&0"))] 7802c87b03e5Sespie "" 78034e43c760Sespie "* 78044e43c760Sespie{ 78054e43c760Sespie if (TARGET_64BIT) 78064e43c760Sespie return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\"; 78074e43c760Sespie else 78084e43c760Sespie return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\"; 78094e43c760Sespie}" 7810c87b03e5Sespie [(set_attr "type" "multi") 7811c87b03e5Sespie (set_attr "length" "12")]) 7812c87b03e5Sespie 7813c87b03e5Sespie(define_insn "icacheflush" 78144e43c760Sespie [(const_int 2) 78154e43c760Sespie (unspec_volatile [(mem:BLK (scratch))] 0) 78164e43c760Sespie (use (match_operand 0 "pmode_register_operand" "r")) 78174e43c760Sespie (use (match_operand 1 "pmode_register_operand" "r")) 7818c87b03e5Sespie (use (match_operand 2 "pmode_register_operand" "r")) 7819c87b03e5Sespie (clobber (match_operand 3 "pmode_register_operand" "=&r")) 78204e43c760Sespie (clobber (match_operand 4 "pmode_register_operand" "=&r")) 78214e43c760Sespie (clobber (match_scratch 5 "=&0"))] 7822c87b03e5Sespie "" 78234e43c760Sespie "* 78244e43c760Sespie{ 78254e43c760Sespie if (TARGET_64BIT) 78264e43c760Sespie return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\"; 78274e43c760Sespie else 78284e43c760Sespie return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\"; 78294e43c760Sespie}" 7830c87b03e5Sespie [(set_attr "type" "multi") 7831c87b03e5Sespie (set_attr "length" "52")]) 7832c87b03e5Sespie 7833c87b03e5Sespie;; An out-of-line prologue. 7834c87b03e5Sespie(define_insn "outline_prologue_call" 7835c87b03e5Sespie [(unspec_volatile [(const_int 0)] 0) 7836c87b03e5Sespie (clobber (reg:SI 31)) 7837c87b03e5Sespie (clobber (reg:SI 22)) 7838c87b03e5Sespie (clobber (reg:SI 21)) 7839c87b03e5Sespie (clobber (reg:SI 20)) 7840c87b03e5Sespie (clobber (reg:SI 19)) 7841c87b03e5Sespie (clobber (reg:SI 1))] 7842c87b03e5Sespie "" 7843c87b03e5Sespie "* 7844c87b03e5Sespie{ 7845c87b03e5Sespie extern int frame_pointer_needed; 7846c87b03e5Sespie 7847c87b03e5Sespie /* We need two different versions depending on whether or not we 7848c87b03e5Sespie need a frame pointer. Also note that we return to the instruction 7849c87b03e5Sespie immediately after the branch rather than two instructions after the 7850c87b03e5Sespie break as normally is the case. */ 7851c87b03e5Sespie if (frame_pointer_needed) 7852c87b03e5Sespie { 7853c87b03e5Sespie /* Must import the magic millicode routine(s). */ 7854c87b03e5Sespie output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL); 7855c87b03e5Sespie 7856c87b03e5Sespie if (TARGET_PORTABLE_RUNTIME) 7857c87b03e5Sespie { 7858c87b03e5Sespie output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL); 7859c87b03e5Sespie output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\", 7860c87b03e5Sespie NULL); 7861c87b03e5Sespie } 7862c87b03e5Sespie else 7863c87b03e5Sespie output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL); 7864c87b03e5Sespie } 7865c87b03e5Sespie else 7866c87b03e5Sespie { 7867c87b03e5Sespie /* Must import the magic millicode routine(s). */ 7868c87b03e5Sespie output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL); 7869c87b03e5Sespie 7870c87b03e5Sespie if (TARGET_PORTABLE_RUNTIME) 7871c87b03e5Sespie { 7872c87b03e5Sespie output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL); 7873c87b03e5Sespie output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL); 7874c87b03e5Sespie } 7875c87b03e5Sespie else 7876c87b03e5Sespie output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL); 7877c87b03e5Sespie } 7878c87b03e5Sespie return \"\"; 7879c87b03e5Sespie}" 7880c87b03e5Sespie [(set_attr "type" "multi") 7881c87b03e5Sespie (set_attr "length" "8")]) 7882c87b03e5Sespie 7883c87b03e5Sespie;; An out-of-line epilogue. 7884c87b03e5Sespie(define_insn "outline_epilogue_call" 7885c87b03e5Sespie [(unspec_volatile [(const_int 1)] 0) 7886c87b03e5Sespie (use (reg:SI 29)) 7887c87b03e5Sespie (use (reg:SI 28)) 7888c87b03e5Sespie (clobber (reg:SI 31)) 7889c87b03e5Sespie (clobber (reg:SI 22)) 7890c87b03e5Sespie (clobber (reg:SI 21)) 7891c87b03e5Sespie (clobber (reg:SI 20)) 7892c87b03e5Sespie (clobber (reg:SI 19)) 7893c87b03e5Sespie (clobber (reg:SI 2)) 7894c87b03e5Sespie (clobber (reg:SI 1))] 7895c87b03e5Sespie "" 7896c87b03e5Sespie "* 7897c87b03e5Sespie{ 7898c87b03e5Sespie extern int frame_pointer_needed; 7899c87b03e5Sespie 7900c87b03e5Sespie /* We need two different versions depending on whether or not we 7901c87b03e5Sespie need a frame pointer. Also note that we return to the instruction 7902c87b03e5Sespie immediately after the branch rather than two instructions after the 7903c87b03e5Sespie break as normally is the case. */ 7904c87b03e5Sespie if (frame_pointer_needed) 7905c87b03e5Sespie { 7906c87b03e5Sespie /* Must import the magic millicode routine. */ 7907c87b03e5Sespie output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL); 7908c87b03e5Sespie 7909c87b03e5Sespie /* The out-of-line prologue will make sure we return to the right 7910c87b03e5Sespie instruction. */ 7911c87b03e5Sespie if (TARGET_PORTABLE_RUNTIME) 7912c87b03e5Sespie { 7913c87b03e5Sespie output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL); 7914c87b03e5Sespie output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\", 7915c87b03e5Sespie NULL); 7916c87b03e5Sespie } 7917c87b03e5Sespie else 7918c87b03e5Sespie output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL); 7919c87b03e5Sespie } 7920c87b03e5Sespie else 7921c87b03e5Sespie { 7922c87b03e5Sespie /* Must import the magic millicode routine. */ 7923c87b03e5Sespie output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL); 7924c87b03e5Sespie 7925c87b03e5Sespie /* The out-of-line prologue will make sure we return to the right 7926c87b03e5Sespie instruction. */ 7927c87b03e5Sespie if (TARGET_PORTABLE_RUNTIME) 7928c87b03e5Sespie { 7929c87b03e5Sespie output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL); 7930c87b03e5Sespie output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL); 7931c87b03e5Sespie } 7932c87b03e5Sespie else 7933c87b03e5Sespie output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL); 7934c87b03e5Sespie } 7935c87b03e5Sespie return \"\"; 7936c87b03e5Sespie}" 7937c87b03e5Sespie [(set_attr "type" "multi") 7938c87b03e5Sespie (set_attr "length" "8")]) 7939c87b03e5Sespie 7940c87b03e5Sespie;; Given a function pointer, canonicalize it so it can be 7941c87b03e5Sespie;; reliably compared to another function pointer. */ 7942c87b03e5Sespie(define_expand "canonicalize_funcptr_for_compare" 7943c87b03e5Sespie [(set (reg:SI 26) (match_operand:SI 1 "register_operand" "")) 7944c87b03e5Sespie (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0)) 7945c87b03e5Sespie (clobber (match_dup 2)) 7946c87b03e5Sespie (clobber (reg:SI 26)) 7947c87b03e5Sespie (clobber (reg:SI 22)) 7948c87b03e5Sespie (clobber (reg:SI 31))]) 7949c87b03e5Sespie (set (match_operand:SI 0 "register_operand" "") 7950c87b03e5Sespie (reg:SI 29))] 7951c87b03e5Sespie "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" 7952c87b03e5Sespie " 7953c87b03e5Sespie{ 7954c87b03e5Sespie if (TARGET_ELF32) 7955c87b03e5Sespie { 7956c87b03e5Sespie rtx canonicalize_funcptr_for_compare_libfunc 7957c87b03e5Sespie = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL); 7958c87b03e5Sespie 7959c87b03e5Sespie emit_library_call_value (canonicalize_funcptr_for_compare_libfunc, 7960c87b03e5Sespie operands[0], LCT_NORMAL, Pmode, 7961c87b03e5Sespie 1, operands[1], Pmode); 7962c87b03e5Sespie DONE; 7963c87b03e5Sespie } 7964c87b03e5Sespie 7965c87b03e5Sespie operands[2] = gen_reg_rtx (SImode); 7966c87b03e5Sespie if (GET_CODE (operands[1]) != REG) 7967c87b03e5Sespie { 7968c87b03e5Sespie rtx tmp = gen_reg_rtx (Pmode); 7969c87b03e5Sespie emit_move_insn (tmp, operands[1]); 7970c87b03e5Sespie operands[1] = tmp; 7971c87b03e5Sespie } 7972c87b03e5Sespie}") 7973c87b03e5Sespie 7974c87b03e5Sespie(define_insn "" 7975c87b03e5Sespie [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0)) 7976c87b03e5Sespie (clobber (match_operand:SI 0 "register_operand" "=a")) 7977c87b03e5Sespie (clobber (reg:SI 26)) 7978c87b03e5Sespie (clobber (reg:SI 22)) 7979c87b03e5Sespie (clobber (reg:SI 31))] 7980c87b03e5Sespie "!TARGET_64BIT" 7981c87b03e5Sespie "* 7982c87b03e5Sespie{ 7983c87b03e5Sespie int length = get_attr_length (insn); 7984c87b03e5Sespie rtx xoperands[2]; 7985c87b03e5Sespie 7986c87b03e5Sespie xoperands[0] = GEN_INT (length - 8); 7987c87b03e5Sespie xoperands[1] = GEN_INT (length - 16); 7988c87b03e5Sespie 7989c87b03e5Sespie /* Must import the magic millicode routine. */ 7990c87b03e5Sespie output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL); 7991c87b03e5Sespie 7992c87b03e5Sespie /* This is absolutely amazing. 7993c87b03e5Sespie 7994c87b03e5Sespie First, copy our input parameter into %r29 just in case we don't 7995c87b03e5Sespie need to call $$sh_func_adrs. */ 7996c87b03e5Sespie output_asm_insn (\"copy %%r26,%%r29\", NULL); 7997c87b03e5Sespie output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL); 7998c87b03e5Sespie 7999c87b03e5Sespie /* Next, examine the low two bits in %r26, if they aren't 0x2, then 8000c87b03e5Sespie we use %r26 unchanged. */ 8001c87b03e5Sespie output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands); 8002c87b03e5Sespie output_asm_insn (\"ldi 4096,%%r31\", NULL); 8003c87b03e5Sespie 8004c87b03e5Sespie /* Next, compare %r26 with 4096, if %r26 is less than or equal to 8005c87b03e5Sespie 4096, then again we use %r26 unchanged. */ 8006c87b03e5Sespie output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands); 8007c87b03e5Sespie 8008c87b03e5Sespie /* Finally, call $$sh_func_adrs to extract the function's real add24. */ 8009c87b03e5Sespie return output_millicode_call (insn, 8010c87b03e5Sespie gen_rtx_SYMBOL_REF (SImode, 8011c87b03e5Sespie \"$$sh_func_adrs\")); 8012c87b03e5Sespie}" 8013c87b03e5Sespie [(set_attr "type" "multi") 8014c87b03e5Sespie (set (attr "length") 8015c87b03e5Sespie (plus (symbol_ref "attr_length_millicode_call (insn)") 8016c87b03e5Sespie (const_int 20)))]) 8017c87b03e5Sespie 8018c87b03e5Sespie;; On the PA, the PIC register is call clobbered, so it must 8019c87b03e5Sespie;; be saved & restored around calls by the caller. If the call 8020c87b03e5Sespie;; doesn't return normally (nonlocal goto, or an exception is 8021c87b03e5Sespie;; thrown), then the code at the exception handler label must 8022c87b03e5Sespie;; restore the PIC register. 8023c87b03e5Sespie(define_expand "exception_receiver" 8024c87b03e5Sespie [(const_int 4)] 8025c87b03e5Sespie "flag_pic" 8026c87b03e5Sespie " 8027c87b03e5Sespie{ 8028c87b03e5Sespie /* On the 64-bit port, we need a blockage because there is 8029c87b03e5Sespie confusion regarding the dependence of the restore on the 8030c87b03e5Sespie frame pointer. As a result, the frame pointer and pic 8031c87b03e5Sespie register restores sometimes are interchanged erroneously. */ 8032c87b03e5Sespie if (TARGET_64BIT) 8033c87b03e5Sespie emit_insn (gen_blockage ()); 8034c87b03e5Sespie /* Restore the PIC register using hppa_pic_save_rtx (). The 8035c87b03e5Sespie PIC register is not saved in the frame in 64-bit ABI. */ 8036c87b03e5Sespie emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ()); 8037c87b03e5Sespie emit_insn (gen_blockage ()); 8038c87b03e5Sespie DONE; 8039c87b03e5Sespie}") 8040c87b03e5Sespie 8041c87b03e5Sespie(define_expand "builtin_setjmp_receiver" 8042c87b03e5Sespie [(label_ref (match_operand 0 "" ""))] 8043c87b03e5Sespie "flag_pic" 8044c87b03e5Sespie " 8045c87b03e5Sespie{ 8046c87b03e5Sespie if (TARGET_64BIT) 8047c87b03e5Sespie emit_insn (gen_blockage ()); 8048c87b03e5Sespie /* Restore the PIC register. Hopefully, this will always be from 8049c87b03e5Sespie a stack slot. The only registers that are valid after a 8050c87b03e5Sespie builtin_longjmp are the stack and frame pointers. */ 8051c87b03e5Sespie emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ()); 8052c87b03e5Sespie emit_insn (gen_blockage ()); 8053c87b03e5Sespie DONE; 8054c87b03e5Sespie}") 8055c87b03e5Sespie 8056c87b03e5Sespie;; Allocate new stack space and update the saved stack pointer in the 8057c87b03e5Sespie;; frame marker. The HP C compilers also copy additional words in the 8058c87b03e5Sespie;; frame marker. The 64-bit compiler copies words at -48, -32 and -24. 8059c87b03e5Sespie;; The 32-bit compiler copies the word at -16 (Static Link). We 8060c87b03e5Sespie;; currently don't copy these values. 8061c87b03e5Sespie;; 8062c87b03e5Sespie;; Since the copy of the frame marker can't be done atomically, I 8063c87b03e5Sespie;; suspect that using it for unwind purposes may be somewhat unreliable. 8064c87b03e5Sespie;; The HP compilers appear to raise the stack and copy the frame 8065c87b03e5Sespie;; marker in a strict instruction sequence. This suggests that the 8066c87b03e5Sespie;; unwind library may check for an alloca sequence when ALLOCA_FRAME 8067c87b03e5Sespie;; is set in the callinfo data. We currently don't set ALLOCA_FRAME 8068c87b03e5Sespie;; as GAS doesn't support it, or try to keep the instructions emitted 8069c87b03e5Sespie;; here in strict sequence. 8070c87b03e5Sespie(define_expand "allocate_stack" 8071c87b03e5Sespie [(match_operand 0 "" "") 8072c87b03e5Sespie (match_operand 1 "" "")] 8073c87b03e5Sespie "" 8074c87b03e5Sespie " 8075c87b03e5Sespie{ 8076c87b03e5Sespie /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx 8077c87b03e5Sespie in operand 0 before adjusting the stack. */ 8078c87b03e5Sespie emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 8079c87b03e5Sespie anti_adjust_stack (operands[1]); 8080c87b03e5Sespie if (TARGET_HPUX_UNWIND_LIBRARY) 8081c87b03e5Sespie { 8082c87b03e5Sespie rtx dst = gen_rtx_MEM (word_mode, 8083c87b03e5Sespie gen_rtx_PLUS (word_mode, stack_pointer_rtx, 8084c87b03e5Sespie GEN_INT (TARGET_64BIT ? -8 : -4))); 8085c87b03e5Sespie 8086c87b03e5Sespie emit_move_insn (dst, frame_pointer_rtx); 8087c87b03e5Sespie } 8088c87b03e5Sespie DONE; 8089c87b03e5Sespie}") 8090