1.\" $OpenBSD: ahc.4,v 1.39 2012/08/14 01:08:19 dlg Exp $ 2.\" $NetBSD: ahc.4,v 1.1.2.1 1996/08/25 17:22:14 thorpej Exp $ 3.\" 4.\" Copyright (c) 1995, 1996 5.\" Justin T. Gibbs. All rights reserved. 6.\" 7.\" Redistribution and use in source and binary forms, with or without 8.\" modification, are permitted provided that the following conditions 9.\" are met: 10.\" 1. Redistributions of source code must retain the above copyright 11.\" notice, this list of conditions and the following disclaimer. 12.\" 2. Redistributions in binary form must reproduce the above copyright 13.\" notice, this list of conditions and the following disclaimer in the 14.\" documentation and/or other materials provided with the distribution. 15.\" 3. The name of the author may not be used to endorse or promote products 16.\" derived from this software without specific prior written permission. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28.\" 29.\" 30.Dd $Mdocdate: August 14 2012 $ 31.Dt AHC 4 32.Os 33.Sh NAME 34.Nm ahc 35.Nd Adaptec VL/EISA/PCI SCSI interface 36.Sh SYNOPSIS 37.Cd "ahc0 at isa? " Pq VL 38.Cd "ahc* at eisa? " Pq EISA 39.Cd "ahc* at pci? " Pq PCI 40.Cd "option AHC_ALLOW_MEMIO" 41.Cd "option AHC_TMODE_ENABLE" 42.Sh DESCRIPTION 43This driver provides access to the 44.Tn SCSI 45bus(es) connected to Adaptec 46.Tn AIC7770 , 47.Tn AIC7850 , 48.Tn AIC7860 , 49.Tn AIC7870 , 50.Tn AIC7880 , 51.Tn AIC7890 , 52.Tn AIC7891 , 53.Tn AIC7892 , 54.Tn AIC7895 , 55.Tn AIC7896 , 56.Tn AIC7897 57and 58.Tn AIC7899 59host adapter chips. 60These chips are found on many motherboards as well as the following 61Adaptec SCSI controller cards: 62.Tn 274X(W) , 63.Tn 274X(T) , 64.Tn 284X , 65.Tn 2910 , 66.Tn 2915 , 67.Tn 2920 , 68.Tn 2930C , 69.Tn 2930U2 , 70.Tn 2940 , 71.Tn 2940J , 72.Tn 2940N , 73.Tn 2940U , 74.Tn 2940AU , 75.Tn 2940UW , 76.Tn 2940UW Dual , 77.Tn 2940UW Pro , 78.Tn 2940U2W , 79.Tn 2940U2B , 80.Tn 2950U2W , 81.Tn 2950U2B , 82.Tn 19160B , 83.Tn 29160B , 84.Tn 29160N , 85.Tn 3940 , 86.Tn 3940U , 87.Tn 3940AU , 88.Tn 3940UW , 89.Tn 3940AUW , 90.Tn 3940U2W , 91.Tn 3950U2 , 92.Tn 3960 , 93.Tn 39160 , 94.Tn 3985 , 95and 96.Tn 4944UW . 97.Pp 98Driver features include support for twin and wide buses, 99fast, ultra, ultra2 and ultra160 synchronous transfers depending on 100controller type, tagged queuing, and SCB paging, and target mode. 101.Pp 102Memory mapped I/O can be enabled for PCI devices with the 103.Dq Dv AHC_ALLOW_MEMIO 104configuration option. 105Memory mapped I/O is more efficient than the alternative, programmed I/O. 106Most PCI BIOSes will map devices so that either technique for communicating 107with the card is available. 108In some cases, 109usually when the PCI device is sitting behind a PCI->PCI bridge, 110the BIOS may fail to properly initialize the chip for memory mapped I/O. 111The typical symptom of this problem is a system hang if memory mapped I/O 112is attempted. 113Most modern motherboards perform the initialization correctly and work fine 114with this option enabled. 115This is the default mode of operation on every architecture except i386. 116.Pp 117Individual controllers may be configured to operate in the target role through 118the 119.Dq Dv AHC_TMODE_ENABLE 120configuration option. 121The value assigned to this option should be a bitmap of all units where target 122mode is desired. 123For example, a value of 0x25, would enable target mode on units 0, 2, and 5. 124A value of 0x8a enables it for units 1, 3, and 7. 125.Pp 126Per target configuration performed in the 127.Tn SCSI-Select 128menu, accessible at boot 129in 130.No non- Ns Tn EISA 131models, 132or through an 133.Tn EISA 134configuration utility for 135.Tn EISA 136models, 137is honored by this driver. 138This includes synchronous/asynchronous transfers, 139maximum synchronous negotiation rate, 140wide transfers, 141disconnection, 142the host adapter's SCSI ID, 143and, 144in the case of 145.Tn EISA 146Twin Channel controllers, 147the primary channel selection. 148For systems that store non-volatile settings in a system specific manner 149rather than a serial eeprom directly connected to the aic7xxx controller, 150the 151.Tn BIOS 152must be enabled for the driver to access this information. 153This restriction applies to all 154.Tn EISA 155and many motherboard configurations. 156.Pp 157Note that I/O addresses are determined automatically by the probe routines, 158but care should be taken when using a 284x 159.Pq Tn VESA No local bus controller 160in an 161.Tn EISA 162system. 163The jumpers setting the I/O area for the 284x should match the 164.Tn EISA 165slot into which the card is inserted to prevent conflicts with other 166.Tn EISA 167cards. 168.Pp 169Performance and feature sets vary throughout the aic7xxx product line. 170The following table provides a comparison of the different chips supported by 171the 172.Nm 173driver. 174Note that wide and twin channel features, although always supported by a 175particular chip, may be disabled in a particular motherboard or card design. 176.Bd -literal 177.Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features" 178aic7770 10 EISA/VL 10MHz 16Bit 4 1 179aic7850 10 PCI/32 10MHz 8Bit 3 180aic7860 10 PCI/32 20MHz 8Bit 3 181aic7870 10 PCI/32 10MHz 16Bit 16 182aic7880 10 PCI/32 20MHz 16Bit 16 183aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8 184aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8 185aic7892 20 PCI/64 80MHz 16Bit 16 3 4 5 6 7 8 186aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5 187aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8 188aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8 189aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8 190aic7899 20 PCI/64 80MHz 16Bit 16 2 3 4 5 6 7 8 191.Ed 192.Pp 193.Bl -enum -compact 194.It 195Multiplexed Twin Channel Device - One controller servicing two buses. 196.It 197Multi-function Twin Channel Device - Two controllers on one chip. 198.It 199Command Channel Secondary DMA Engine - Allows scatter gather list and 200SCB prefetch. 201.It 20264 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA. 203.It 204Block Move Instruction Support - Doubles the speed of certain sequencer 205operations. 206.It 207.Sq Bayonet 208style Scatter Gather Engine - Improves S/G prefetch performance. 209.It 210Queuing Registers - Allows queuing of new transactions without pausing the 211sequencer. 212.It 213Ultra160 support. 214.It 215Multiple Target IDs - Allows the controller to respond to selection as a target 216on multiple SCSI IDs. 217.El 218.Sh SCSI CONTROL BLOCKS (SCBs) 219Every transaction sent to a device on the SCSI bus is assigned a 220.Sq SCSI Control Block 221(SCB). 222The SCB contains all of the information required by the controller to process a 223transaction. 224The chip feature table lists the number of SCBs that can be stored in on-chip 225memory. 226All chips with model numbers greater than or equal to 7870 allow for the 227on-chip SCB space to be augmented with external SRAM up to a maximum of 255 228SCBs. 229Very few Adaptec controller configurations have external SRAM. 230.Pp 231If external SRAM is not available, 232SCBs are a limited resource. 233Using the SCBs in a straight forward manner would only allow the driver to 234handle as many concurrent transactions as there are physical SCBs. 235To fully utilize the SCSI bus and the devices on it, 236requires much more concurrency. 237The solution to this problem is 238.Em SCB Paging , 239a concept similar to memory paging. 240SCB paging takes advantage of the fact that devices usually disconnect from the 241SCSI bus for long periods of time without talking to the controller. 242The SCBs for disconnected transactions are only of use to the controller when 243the transfer is resumed. 244When the host queues another transaction for the controller to execute, 245the controller firmware will use a free SCB if one is available. 246Otherwise, the state of the most recently disconnected (and therefore most 247likely to stay disconnected) SCB is saved, via DMA, to host memory, 248and the local SCB reused to start the new transaction. 249This allows the controller to queue up to 255 transactions regardless of the 250amount of SCB space. 251Since the local SCB space serves as a cache for disconnected transactions, 252the more SCB space available, the less host bus traffic consumed saving and 253restoring SCB data. 254.Sh SEE ALSO 255.Xr ahd 4 , 256.Xr cd 4 , 257.Xr ch 4 , 258.Xr eisa 4 , 259.Xr intro 4 , 260.Xr isa 4 , 261.Xr pci 4 , 262.Xr scsi 4 , 263.Xr sd 4 , 264.Xr st 4 , 265.Xr uk 4 266.Sh AUTHORS 267The core 268.Nm 269driver, the 270.Tn AIC7xxx 271sequencer-code assembler, and the firmware running on the aic7xxx chips 272were written by 273.An Justin T. Gibbs . 274.Pp 275The 276.Ox 277platform dependent code was written by Steve P. Murphree, Jr and Kenneth 278R. Westerback. 279.Sh BUGS 280Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an 281.Tn AIC7870 282Rev B in synchronous mode at 10MHz. 283Controllers with this problem have a 42 MHz clock crystal on them and run 284slightly above 10MHz. 285This confuses the drive and hangs the bus. 286Setting a maximum synchronous negotiation rate of 8MHz in the 287.Tn SCSI-Select 288utility will allow normal operation. 289.Pp 290Although the Ultra2 and Ultra160 products have sufficient instruction RAM space 291to support both the initiator and target roles concurrently, 292this configuration is disabled in favor of allowing the target role to respond 293on multiple target ids. 294A method for configuring dual role mode should be provided. 295.Pp 296Tagged Queuing is not supported in target mode. 297.Pp 298Reselection in target mode fails to function correctly on all high voltage 299differential boards as shipped by Adaptec. 300Information on how to modify HVD board to work correctly in target mode is 301available from Adaptec. 302