1*16f46ab6Sjmc.\" $OpenBSD: zqclock.4,v 1.2 2021/04/30 13:52:12 jmc Exp $ 26fd70764Svisa.\" 36fd70764Svisa.\" Copyright (c) 2021 Visa Hankala 46fd70764Svisa.\" 56fd70764Svisa.\" Permission to use, copy, modify, and distribute this software for any 66fd70764Svisa.\" purpose with or without fee is hereby granted, provided that the above 76fd70764Svisa.\" copyright notice and this permission notice appear in all copies. 86fd70764Svisa.\" 96fd70764Svisa.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 106fd70764Svisa.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 116fd70764Svisa.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 126fd70764Svisa.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 136fd70764Svisa.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 146fd70764Svisa.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 156fd70764Svisa.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 166fd70764Svisa.\" 176fd70764Svisa.Dd $Mdocdate: April 30 2021 $ 18*16f46ab6Sjmc.Dt ZQCLOCK 4 armv7 196fd70764Svisa.Os 206fd70764Svisa.Sh NAME 216fd70764Svisa.Nm zqclock 226fd70764Svisa.Nd Xilinx Zynq-7000 clock controller 236fd70764Svisa.Sh SYNOPSIS 246fd70764Svisa.Cd "zqclock* at fdt?" 256fd70764Svisa.Sh DESCRIPTION 266fd70764SvisaThe 276fd70764Svisa.Nm 286fd70764Svisadriver controls the clock signals for the integrated components 296fd70764Svisaof Zynq-7000 SoCs. 306fd70764Svisa.Sh SEE ALSO 316fd70764Svisa.Xr intro 4 , 326fd70764Svisa.Xr zqreset 4 336fd70764Svisa.Sh HISTORY 346fd70764SvisaThe 356fd70764Svisa.Nm 366fd70764Svisadriver first appeared in 376fd70764Svisa.Ox 7.0 . 38