1.\" $OpenBSD: uperf.4,v 1.14 2007/05/31 19:19:57 jmc Exp $ 2.\" 3.\" Copyright (c) 2002 Jason L. Wright (jason@thought.net) 4.\" All rights reserved. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Redistributions in binary form must reproduce the above copyright 12.\" notice, this list of conditions and the following disclaimer in the 13.\" documentation and/or other materials provided with the distribution. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17.\" WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18.\" DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19.\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20.\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21.\" SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23.\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24.\" ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25.\" POSSIBILITY OF SUCH DAMAGE. 26.\" 27.Dd $Mdocdate: May 31 2007 $ 28.Dt UPERF 4 sparc64 29.Os 30.Sh NAME 31.Nm uperf 32.Nd performance counters driver 33.Sh SYNOPSIS 34.Cd "uperf* at ebus?" 35.Cd "uperf* at sbus?" 36.Sh DESCRIPTION 37Some UltraSPARC host bridges provide performance counters on their host 38bridges. 39The counters are a part of the system controller chip (usc, dsc, or qsc). 40On PCI machines the system controller shows up as a device on the EBus, but 41on SBus machines the system controller exists in SBus space. 42The 43.Nm 44driver provides access to these counters via 45.Xr ioctl 2 . 46.Sh IOCTLS 47All of the ioctl calls supported by the 48.Nm 49driver take the following structure as an argument: 50.Bd -literal -offset indent 51struct uperf_io { 52 int cnt_flags; 53 int cnt_src0; 54 int cnt_src1; 55 u_int32_t cnt_val0; 56 u_int32_t cnt_val1; 57}; 58.Ed 59.Pp 60The 61.Fa cnt_flags 62field specifies which counters are being operated on and is a bit mask 63of 64.Fa UPERF_CNT0 65and/or 66.Fa UPERF_CNT1 . 67.Pp 68The 69.Fa cnt_src0 70and 71.Fa cnt_src1 72fields specify the source for the counter. 73Not all counters support monitoring all sources and specifying an invalid 74source for a counter to monitor will result in an error. 75The sources are specified below: 76.Bl -column "XXXXXXXXXXXXXX" "description" -offset indent 77.It Em UPERFSRC_SYSCK Ta "system clock ticks" 78.It Em UPERFSRC_PRALL Ta "all p-requests" 79.It Em UPERFSRC_PRP0 Ta "p-requests from processor 0" 80.It Em UPERFSRC_PRU2S Ta "p-requests from the U2S" 81.It Em UPERFSRC_UPA128 Ta "cycles UPA 128 bit data is busy" 82.It Em UPERFSRC_UPA64 Ta "cycles UPA 64 bit data is busy" 83.It Em UPERFSRC_PIOS Ta "cycles stalled during PIO" 84.It Em UPERFSRC_MEMRI Ta "memory requests issued" 85.It Em UPERFSRC_MCBUSY Ta "cycles memory controller is busy" 86.It Em UPERFSRC_PXSH Ta "stall cycles due to pending transaction scoreboard hit" 87.It Em UPERFSRC_P0CWMR Ta "coherent write miss requests, processor 0" 88.It Em UPERFSRC_P1CWMR Ta "coherent write miss requests, processor 1" 89.It Em UPERFSRC_CIT Ta "coherent intervention transactions" 90.It Em UPERFSRC_U2SDAT Ta "data transactions on U2S" 91.It Em UPERFSRC_CRXI Ta "coherent read transactions issued" 92.It Em UPERFSRC_RDP0 Ta "read requests, processor 0" 93.It Em UPERFSRC_P0CRMR Ta "coherent read misses, processor 0" 94.It Em UPERFSRC_P0PIO Ta "PIO accesses, processor 0" 95.It Em UPERFSRC_MEMRC Ta "memory requests completed" 96.It Em UPERFSRC_P1RR Ta "read requests, processor 1" 97.It Em UPERFSRC_CRMP1 Ta "coherent read misses, processor 1" 98.It Em UPERFSRC_PIOP1 Ta "PIO accesses, processor 1" 99.It Em UPERFSRC_CWXI Ta "coherent write transactions issued" 100.It Em UPERFSRC_RP0 Ta "read requests, processor 0" 101.It Em UPERFSRC_SDVRA Ta "streaming DVMA read transfers, PCI bus A" 102.It Em UPERFSRC_SDVWA Ta "streaming DVMA write transfers, PCI bus A" 103.It Em UPERFSRC_CDVRA Ta "consistent DVMA read transfers, PCI bus A" 104.It Em UPERFSRC_CDVWA Ta "consistent DVMA write transfers, PCI bus A" 105.It Em UPERFSRC_SBMA Ta "streaming buffer misses, PCI bus A" 106.It Em UPERFSRC_DVA Ta "DVMA cycles, PCI bus A" 107.It Em UPERFSRC_DVWA Ta "words transferred via DVMA, PCI bus A" 108.It Em UPERFSRC_PIOA Ta "cycles consumed by PIO, bus A" 109.It Em UPERFSRC_SDVRB Ta "streaming DVMA read transfers, PCI bus B" 110.It Em UPERFSRC_SDVWB Ta "streaming DVMA write transfers, PCI bus B" 111.It Em UPERFSRC_CDVRB Ta "consistent DVMA read transfers, PCI bus B" 112.It Em UPERFSRC_CDVWB Ta "consistent DVMA write transfers, PCI bus B" 113.It Em UPERFSRC_SBMB Ta "streaming buffer misses, PCI bus B" 114.It Em UPERFSRC_DVB Ta "DVMA cycles, PCI bus B" 115.It Em UPERFSRC_DVWB Ta "words transferred via DVMA, PCI bus B" 116.It Em UPERFSRC_PIOB Ta "cycles consumed by PIO, bus B" 117.It Em UPERFSRC_TLBMISS Ta "TLB misses" 118.It Em UPERFSRC_NINTRS Ta "interrupts" 119.It Em UPERFSRC_INACK Ta "interrupt NACKS on UPA" 120.It Em UPERFSRC_PIOR Ta "PIO read transfers" 121.It Em UPERFSRC_PIOW Ta "PIO write transfers" 122.It Em UPERFSRC_MERGE Ta "merge buffer transactions" 123.It Em UPERFSRC_TBLA Ta "DMA requests retried due to tablewalks, PCI bus A" 124.It Em UPERFSRC_STCA Ta "DMA requests retries due to STC, PCI bus A" 125.It Em UPERFSRC_TBLB Ta "DMA requests retries due to tablewalks, PCI bus B" 126.It Em UPERFSRC_STCB Ta "DMA requests retries due to STC, PCI bus B" 127.El 128.Pp 129The 130.Fa cnt_val0 131and 132.Fa cnt_val1 133contain the values fetched for the counters. 134Software using this interface should be prepared to handle the counters 135rolling over. 136.Pp 137The 138.Nm 139device responds to the following 140.Xr ioctl 2 141calls, which are defined in 142.Aq Pa dev/sun/uperfio.h . 143.Bl -tag -width UPIO_GCNTSRC 144.It Dv UPIO_GCNTSRC 145.Pq Li "struct uperf_io" 146Retrieve the source the counters are monitoring. 147The 148.Fa cnt_flags 149is a bit mask for which of the counters is to be fetched. 150The result is returned in 151.Fa cnt_src0 152and/or 153.Fa cnt_src1 . 154.It Dv UPIO_SCNTSRC 155.Pq Li "struct uperf_io" 156Set the source the counters should monitor. 157This call also clears the current value of the counters that are set. 158The 159.Fa cnt_flags 160is a bit mask for which of the counters is to be set. 161The 162.Fa cnt_src0 163and/or 164.Fa cnt_src1 165fields specify the source to be set for the respective counter. 166.It Dv UPIO_CLRCNT 167.Pq Li "struct uperf_io" 168Clear the counters specified in 169.Fa cnt_flags . 170.It Dv UPIO_GETCNT 171.Pq Li "struct uperf_io" 172Retrieve the value for the counters specified in 173.Fa cnt_flags . 174The values are returned in 175.Fa cnt_val0 176and/or 177.Fa cnt_val1 . 178.El 179.Sh SEE ALSO 180.Xr ioctl 2 , 181.Xr ebus 4 , 182.Xr intro 4 , 183.Xr sbus 4 184.Sh HISTORY 185The 186.Nm 187driver was first supported in 188.Ox 3.1 . 189.Sh AUTHORS 190The driver was written by 191.An Jason Wright Aq jason@thought.net . 192